WO2022104598A1 - 半导体结构及其制作方法、发光器件及其制作方法 - Google Patents

半导体结构及其制作方法、发光器件及其制作方法 Download PDF

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WO2022104598A1
WO2022104598A1 PCT/CN2020/129794 CN2020129794W WO2022104598A1 WO 2022104598 A1 WO2022104598 A1 WO 2022104598A1 CN 2020129794 W CN2020129794 W CN 2020129794W WO 2022104598 A1 WO2022104598 A1 WO 2022104598A1
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layer
semiconductor layer
semiconductor
electrode
holes
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PCT/CN2020/129794
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English (en)
French (fr)
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张丽旸
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苏州晶湛半导体有限公司
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Priority to PCT/CN2020/129794 priority Critical patent/WO2022104598A1/zh
Priority to US18/029,855 priority patent/US20230387346A1/en
Priority to CN202080106630.0A priority patent/CN116420239A/zh
Priority to TW110141635A priority patent/TWI843971B/zh
Publication of WO2022104598A1 publication Critical patent/WO2022104598A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/10—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/24—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0041—Processes relating to semiconductor body packages relating to wavelength conversion elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0058—Processes relating to semiconductor body packages relating to optical field-shaping elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/405—Reflective materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/50—Wavelength conversion elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58—Optical field-shaping elements
    • H01L33/60—Reflective elements

Definitions

  • the present application relates to the field of semiconductors, and in particular, to a semiconductor structure and a manufacturing method thereof, a light-emitting device and a manufacturing method thereof.
  • an LED light-emitting device is usually prepared by using a gallium nitride-based material, and the epitaxial sidewall of the prepared LED light-emitting device is a vertical structure.
  • this vertical structure and the high refractive index of gallium nitride most of the light is reflected when it reaches the surface of the LED light-emitting device, so that a large amount of light is confined inside the LED chip, resulting in low light extraction efficiency.
  • the present application provides a semiconductor structure and a manufacturing method thereof, a light emitting device and a manufacturing method thereof, which can improve the luminous efficiency of the light emitting device.
  • a semiconductor structure includes: a substrate, a first semiconductor layer, an isolation layer, an active layer, a second semiconductor layer, a first electrode and a second electrode; the conductivity types of the first semiconductor layer and the second semiconductor layer
  • the second semiconductor layer is a conductive DBR structure
  • the first semiconductor layer includes a flat portion, a first protruding portion and a second protruding portion sequentially stacked in a vertical direction, the flat portion is formed on the substrate, and the isolation layer is formed on the flat portion
  • a plurality of first through holes are opened on the part and along the vertical direction, the first raised part is formed in the first through hole, and the second raised part is formed on the first raised part
  • the second protruding parts correspond to the first through holes one-to-one, and the second protruding parts are arranged at intervals, and the side surfaces of the second protruding parts are inclined surfaces;
  • the active layer, the second semiconductor layer, and the first electrode are sequentially stacked on the second protrusion of the first semiconductor layer;
  • the isolation layer is further provided with a second through hole along the vertical direction, and the second electrode is formed in the second through hole and connected to the first semiconductor layer.
  • the conductive DBR structure is a porous conductive DBR structure
  • the porous conductive DBR structure includes a first porous conductive layer and a second porous conductive layer alternately stacked after electrochemical corrosion, wherein the first porous conductive layer and the second porous conductive layer are alternately stacked.
  • a plurality of first holes are formed in the porous conductive layer, and a plurality of second holes are formed in the second porous conductive layer, and the diameters of the first holes are different from the diameters of the second holes.
  • the materials of the first porous conductive layer and the second porous conductive layer are gallium nitride based materials.
  • the included angle between the side surface of the second raised portion and the horizontal plane is a first included angle, and the degree range of the first included angle is 40 degrees to 70 degrees.
  • the side wall of the first through hole is an inclined surface, and the inclination direction of the side wall of the first through hole is the same as the inclination direction of the side surface of the second protrusion.
  • the shape of the second protruding portion is a cone, a truncated cone, a pyramid or a pyramid.
  • a transparent electrode is further provided between the second semiconductor layer and the first electrode.
  • the material of the first semiconductor layer is a gallium nitride-based material.
  • a light emitting device including the semiconductor structure as described above.
  • the light-emitting device further includes a circuit board and a wavelength conversion medium layer;
  • the circuit board is provided with a first pad and a second pad, the first electrode of the semiconductor structure is connected to the first pad on the circuit board, and the second electrode of the semiconductor structure is connected to the circuit board the second pad on the connection;
  • a plurality of third through holes are opened on the side of the substrate away from the first semiconductor layer, and the third through holes correspond to the first through holes one-to-one, and the wavelength conversion medium layer is disposed on at least one of the first through holes. in the third through hole.
  • the sidewall of the third through hole is an inclined plane.
  • the light emitting device further includes a reflection layer, and the reflection layer is covered on the sidewall of the third through hole.
  • a method for fabricating a semiconductor structure for fabricating the above-mentioned semiconductor structure.
  • the fabrication method of the semiconductor structure includes the following steps:
  • S1 forming a flat portion of the first semiconductor layer on the substrate; forming the isolation layer on the flat portion of the first semiconductor layer, and forming a plurality of the first pass-through layers on the isolation layer a hole; forming a first protruding portion of the first semiconductor layer in the first through hole of the isolation layer, and forming a second protruding portion of the first semiconductor layer on the first protruding portion;
  • S4 forming the first electrode on the second semiconductor layer; forming the second through hole on the isolation layer, and forming the second through hole connected to the first semiconductor layer in the second through hole the second electrode to form the semiconductor structure.
  • step S2 an active layer is formed on the second raised portion of the first semiconductor layer by selective growth
  • step S3 by selective growth, the second semiconductor layer having the opposite conductivity type to that of the first semiconductor layer is formed on the active layer;
  • step S4 the first electrode is formed on the second semiconductor layer by selective growth.
  • a method for fabricating a light emitting device includes the above-mentioned manufacturing method of the semiconductor structure, and the manufacturing method of the light-emitting device further includes:
  • S5 Mount the semiconductor structure on the front surface of a circuit board, the circuit board is provided with a first solder pad and a second solder pad, and connect the first electrode of the semiconductor structure to the first solder pad on the circuit board pad connection, the second electrode of the semiconductor structure is connected to the second pad on the circuit board;
  • the sidewall of the third through hole is an inclined plane.
  • step S6 and before step S7 it further includes:
  • a reflective layer is formed on the sidewall of the third through hole.
  • the semiconductor structure and its manufacturing method, the light-emitting device and its manufacturing method of the present application by setting the second semiconductor layer as a conductive DBR structure, on the one hand, the conductive DBR structure is used as a part of the indispensable P-N junction in the light-emitting device , on the other hand, the conductive DBR structure can resonate light of a suitable wavelength, thereby improving the luminous efficiency; at the same time, by setting the sidewall of the epitaxial structure as a slope, it can not only provide a certain reflection angle, but also can increase the luminous efficiency.
  • the area of the reflective surface can reflect more light to the light-emitting surface, thereby improving the light-emitting efficiency.
  • the sidewalls of the active layer, the second semiconductor layer and the first electrode formed on the outer surface thereof are all slopes, thereby The effect that the sidewalls of the final epitaxial structure are inclined planes is achieved; and since the sidewalls of the active layer are inclined planes, the light emitting area of the light emitting device can be increased without increasing the size of the light emitting device.
  • FIG. 1 is a schematic cross-sectional structure diagram of the semiconductor structure according to the first embodiment of the present application.
  • FIG. 2 is a partial enlarged view of part A of FIG. 1 .
  • Example 3 is a schematic cross-sectional structure diagram of a second semiconductor layer of the semiconductor structure of Example 1 of the present application.
  • FIG. 4( g ) are process flow diagrams of the method for fabricating the semiconductor structure of Embodiment 1 of the present application.
  • FIG. 5 is a schematic cross-sectional structure diagram of the light-emitting component of Example 2 of the present application.
  • 6(a) to 6(d) are process flow diagrams of the method for manufacturing the light-emitting component of Example 2 of the present application.
  • this embodiment provides a semiconductor structure 100 .
  • the semiconductor structure 100 includes: a substrate 110 , a first semiconductor layer 120 , an isolation layer 130 , an active layer 140 , a second semiconductor layer 150 , a first electrode 160 and a second electrode 170 .
  • the conductivity types of the first semiconductor layer 120 and the second semiconductor layer 150 are opposite, that is, when the first semiconductor layer 120 is a P-type semiconductor layer, the second semiconductor layer 150 is an N-type semiconductor layer; or, when the first semiconductor layer 120 When it is an N-type semiconductor layer, the second semiconductor layer 150 is a P-type semiconductor layer.
  • the second semiconductor layer 150 is a conductive DBR structure
  • the conductive DBR structure is a porous conductive DBR structure.
  • the porous conductive DBR structure includes alternately stacked first porous conductive layers 151 and second porous conductive layers 152 formed by electrochemical etching, wherein the first porous conductive layer 151 is formed with a plurality of A plurality of second holes 1521 are formed in the first hole 1511 and the second porous conductive layer 152 , and the diameters of the first holes 1511 and the second holes 1521 are different.
  • the materials of the first porous conductive layer 151 and the second porous conductive layer 152 are gallium nitride based materials, such as GaN, AlGaN, GaInN, AlGaInN and other materials.
  • the doping concentrations of the first porous conductive layer 151 and the second porous conductive layer 152 are different.
  • the conductive DBR structure is used as a part of the indispensable P-N junction in the light-emitting device, and on the other hand, the conductive DBR structure can be used for suitable The light of the wavelength forms resonance, thereby improving the luminous efficiency.
  • the first semiconductor layer 120 includes a flat portion 121 , a first raised portion 122 and a second raised portion 123 stacked in sequence along the vertical direction Y.
  • the flat portion 121 is formed on the substrate 110
  • the isolation layer 130 is formed on the flat portion 121 and has a plurality of first through holes 131 opened along the vertical direction Y
  • the first raised portion 122 is formed in the first through hole 131
  • the second raised portion 123 is formed in the first raised portion
  • the second raised parts 123 correspond to the first through holes 131 one-to-one
  • the second raised parts 123 are arranged at intervals.
  • the direction of its center is inclined.
  • the active layer 140 , the second semiconductor layer 150 , and the first electrode 160 are sequentially stacked on the second protrusion 123 of the first semiconductor layer 120 .
  • the sidewalls 1231 of the second protrusions of the first semiconductor layer 120 are inclined planes, so as to achieve the effect that the sidewalls of the final epitaxial structure are inclined planes.
  • the sidewall of the epitaxial structure By setting the sidewall of the epitaxial structure to be inclined, not only a certain reflection angle can be provided, but also the area of the reflection surface can be increased, so that more light can be reflected to the light exit surface, thereby improving the light extraction efficiency.
  • the sidewall of the second convex portion of the first semiconductor layer is a slope
  • the sidewalls of the active layer 140 , the second semiconductor layer 150 , and the first electrode 160 formed on the outer surface thereof are all
  • the sidewall of the active layer 140 is inclined, it can increase the light emission of the light emitting device without increasing the size of the light emitting device. area.
  • the active layer 140 , the second semiconductor layer 150 , and the first electrode 160 are all formed corresponding to the second protrusions 123 of the first semiconductor layer 120 , a plurality of the second protrusions 123 corresponding to the number of the second protrusions 123 are finally formed.
  • Spaced epitaxial structures. The width w of the second semiconductor layer 150 in each epitaxial structure is less than or equal to 200um, preferably, less than or equal to 100um.
  • the shape of the second protruding portion 123 is a cone, a truncated cone, a pyramid or a pyramid, for example, a hexagonal pyramid or a hexagonal pyramid.
  • the included angle between the side surface 1231 of the second protruding portion and the horizontal plane is the first included angle ⁇
  • the degree range of the first included angle ⁇ is 40°-70°.
  • each second raised portion 123 may not only be formed on its corresponding first raised portion 122 , but also may be simultaneously formed on a portion of the isolation layer 130 located on the outer periphery of the first raised portion 122 . .
  • the sidewall 1311 of the first through hole is an inclined plane, the angle between the sidewall 1311 of the first through hole and the horizontal plane is a second angle ⁇ , and the range of the second angle ⁇ is 0°-90°.
  • the inclination direction of the side wall 1311 of the first through hole is the same as the inclination direction of the side surface 1231 of the second protrusion, so as to avoid blocking the light path of the light reflected from the side wall of the epitaxial structure to the light exit surface, thereby further improving the light extraction efficiency.
  • a transparent electrode is further provided between the second semiconductor layer 150 and the first electrode 160 to increase the contact between the second semiconductor layer 150 and the first electrode 160 .
  • the material of the transparent electrode is ITO.
  • the material of the first semiconductor layer 120 is a gallium nitride based material, such as GaN, AlGaN, GaInN, AlGaInN and other materials.
  • the isolation layer 130 is further provided with a second through hole 132 along the vertical direction, and the second electrode 170 is formed in the second through hole 132 and connected to the first semiconductor layer 120 .
  • the material of the first electrode 160 and the second electrode 170 may be Cr, or Al, or Ti, or Pt.
  • FIG. 4( a )- FIG. 4( g ) are process flow diagrams of the method for fabricating the semiconductor structure of Embodiment 1 of the present application.
  • the fabrication method is used to fabricate the semiconductor structure as described above.
  • the fabrication method of the semiconductor structure includes the following steps:
  • S10 forming a flat portion of the first semiconductor layer on the substrate; forming the isolation layer on the flat portion of the first semiconductor layer, and forming a plurality of the first pass-through layers on the isolation layer a hole; forming a first protruding portion of the first semiconductor layer in the first through hole of the isolation layer, and forming a second protruding portion of the first semiconductor layer on the first protruding portion;
  • S40 forming the first electrode on the second semiconductor layer; forming the second through hole on the isolation layer, and forming the second through hole connected to the first semiconductor layer in the second through hole the second electrode to form the semiconductor structure.
  • step S10 it includes:
  • Step S11 as shown in FIG. 4( a ), through the first epitaxial growth, a flat portion 121 of the first semiconductor layer 120 is formed on the substrate 110 , and the side of the flat portion 121 away from the substrate 110 is a plane;
  • Step S12 as shown in FIG. 4( b ), an isolation layer 130 is formed on the flat portion 121 of the first semiconductor layer 120 , and a plurality of first through holes 131 are formed on the isolation layer 130 ;
  • Step S13 as shown in FIG. 4( c ), through the second epitaxial growth, continue to grow the first semiconductor layer 120 in the first through hole 131 of the isolation layer 130 and on the isolation layer 130 until the first semiconductor layer 120 is far away
  • One side of the substrate 110 is grown into a plane, and the part of the first semiconductor layer 120 located in the first through hole 131 of the isolation layer 130 is the first protrusion 122 of the first semiconductor layer 120;
  • Step S14 as shown in FIG. 4( d ), etching the side of the first semiconductor layer 120 away from the substrate 110 until the isolation layer 130 is exposed to form the second protrusion 123 of the first semiconductor layer 120 .
  • the first protrusions 122 of the first semiconductor layer 120 can be formed only in the first through holes 131 of the isolation layer 130 by using a mask. and a second raised portion 123 with a sidewall that is beveled directly on the first raised portion 122 without an etching step.
  • step S20 as shown in FIG. 4(e), the active layer 140 is formed on the second protrusion 123 of the first semiconductor layer 120 by selective growth, so that the active layer 140 is only formed on the second
  • the surface of the raised portion 123 achieves the effect that the side surface of the active layer 140 is also inclined.
  • the non-radiative recombination of sidewalls caused by ICP etching in conventional processes can be effectively avoided.
  • step S30 as shown in FIG. 4( f ), a second semiconductor layer 150 having an opposite conductivity type to that of the first semiconductor layer 120 is formed on the active layer 140 by selective growth, so that the second semiconductor layer 150 is only It is formed on the surface of the active layer 140 to achieve the effect that the side surface of the second semiconductor layer 150 is also inclined.
  • step S40 as shown in FIG. 4(g), the first electrode 160 is formed on the second semiconductor layer 150 by selective growth, so that the first electrode 160 is only formed on the surface of the second semiconductor layer 150, so that the The side surface reaching the first electrode 160 also has the effect of an inclined surface.
  • this embodiment provides a light-emitting component including the semiconductor structure 100 in Embodiment 1.
  • the light-emitting component in this embodiment further includes a circuit board 200 , a reflective layer 500 and a wavelength conversion medium layer 300 .
  • the circuit board 200 is provided with a first bonding pad 210 and a second bonding pad 220 , the first electrode 160 of the semiconductor structure 100 is connected to the first bonding pad 210 on the circuit board 200 , and the second electrode 170 of the semiconductor structure 100 is connected to the circuit board 200 the second pad 220 on the connection.
  • a plurality of third through holes 111 are opened on the side of the substrate 110 away from the first semiconductor layer 120 , and the third through holes 111 correspond to the first through holes 131 one-to-one.
  • the sidewall 1111 of the third through hole is inclined to further improve the light extraction efficiency.
  • the reflective layer 500 is covered on the sidewall 1111 of the third through hole to further improve the light extraction efficiency.
  • the wavelength conversion medium layer 300 is disposed in the at least one third through hole 111 .
  • the wavelength conversion medium layer 300 includes a first wavelength conversion medium layer 300 and a second wavelength conversion medium layer 300, and the wavelengths converted by the first wavelength conversion medium layer 300 and the second wavelength conversion medium layer 300 are different. Specifically, it is set according to the design requirements. For example, when the light emitted by the active layer 140 is blue light, a first wavelength conversion medium layer 300 capable of converting blue light into red light can be arranged in a part of the third through holes 111 .
  • a second wavelength conversion medium layer 300 capable of converting blue light into green light is disposed in the third through holes 111 of the first, and a wavelength conversion medium layer 300 is not disposed in part of the third through holes 111, so that blue light is still emitted.
  • the reflective layer 500 may not be provided, and the wavelength conversion medium layer 300 may be directly provided in the third through hole 111 .
  • another aspect of this embodiment further provides a method for manufacturing a light-emitting component, which is used to manufacture the above-mentioned light-emitting component.
  • the preparation method of this light-emitting component includes the preparation method of the semiconductor structure of embodiment 1, also includes:
  • the semiconductor structure 100 is mounted on the front surface of the circuit board 200 .
  • the circuit board 200 is provided with a first pad 210 and a second pad 220 , and the first electrode 160 of the semiconductor structure 100 is mounted on the circuit board 200 .
  • the second electrode 170 of the semiconductor structure 100 is connected to the second pad 220 on the circuit board 200 .
  • the first electrode 160 of the semiconductor structure 100 can be connected to the first pad 210 on the circuit board 200 through the conductive adhesive 400 .
  • the substrate 110 may be thinned to reduce the thickness of the overall device.
  • a plurality of third through holes 111 are opened on the side of the substrate 110 away from the first semiconductor layer 120, and the third through holes 111 and the first through holes 131 are in one-to-one correspondence;
  • the sidewalls 1111 of the three through holes are set as inclined planes to further improve the light extraction efficiency.
  • a reflective layer 500 may be formed on the sidewall 1111 of the third through hole to further improve the light extraction efficiency.
  • a wavelength conversion medium layer 300 is formed in at least one third through hole 111 .
  • the second semiconductor layer 150 is configured as a conductive DBR structure. , through the conductive DBR structure, it can form resonance with the light of the appropriate wavelength, thereby improving the luminous efficiency; at the same time, by setting the sidewall of the epitaxial structure as a slope, it can not only provide a certain reflection angle, but also can increase the area of the reflective surface , so that more light can be reflected to the light emitting surface, thereby improving the light emitting efficiency.
  • the sidewalls 1231 of the second protrusions of the first semiconductor layer 120 are inclined planes, so as to achieve the effect that the sidewalls of the final epitaxial structure are inclined planes.

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Abstract

本申请提供一种半导体结构及其制作方法、发光器件及其制作方法。该半导体结构包括：衬底、第一半导体层、隔离层、有源层、第二半导体层、第一电极和第二电极；第二半导体层为导电DBR结构；第一半导体层包括沿竖直方向依次层叠的平坦部、第一凸起部和第二凸起部，第二凸起部与第一通孔一一对应，且第二凸起部间隔设置，第二凸起部的侧面为斜面；有源层、第二半导体层、第一电极依次层叠设置于第一半导体层的第二凸起部上；隔离层开设有第二通孔，第二电极形成于第二通孔中。该发光器件包括该半导体结构。本申请通过设置将第二半导体层设置为可导电的DBR结构，同时，将外延结构的侧壁设置为斜面，能够提高半导体器件发光效率。

Description

半导体结构及其制作方法、发光器件及其制作方法 技术领域
本申请涉及半导体领域，尤其涉及一种半导体结构及其制作方法、发光器件及其制作方法。
背景技术
目前，通常采用氮化镓基材料制备LED发光器件，而且制备的LED发光器件的外延侧壁是垂直的结构。但是，由于这种垂直的结构以及氮化镓的高折射率，大部分的光到达LED发光器件的表面时被反射，使大量光线被局限于LED芯片内部，导致出光效率低。
因此，如何进一步提高LED发光器件的发光效率，仍然是目前亟待解决的难题。
发明内容
本申请提供一种半导体结构及其制作方法、发光器件及其制作方法，能够提高发光器件的发光效率。
为实现上述目的，根据本申请实施例的第一方面，提供一种半导体结构。所述半导体结构包括：衬底、第一半导体层、隔离层、有源层、第二半导体层、第一电极和第二电极；所述第一半导体层与所述第二半导体层的导电类型相反，所述第二半导体层为导电DBR结构；
所述第一半导体层包括沿竖直方向依次层叠的平坦部、第一凸起部和第二凸起部，所述平坦部形成于所述衬底上，所述隔离层形成于所述平坦部上并沿竖直方向开设有多个第一通孔，所述第一凸起部形成于所述第 一通孔内，所述第二凸起部形成于所述第一凸起部上，所述第二凸起部与所述第一通孔一一对应，且所述第二凸起部间隔设置，所述第二凸起部的侧面为斜面；
所述有源层、所述第二半导体层、所述第一电极依次层叠设置于所述第一半导体层的第二凸起部上；
所述隔离层还沿竖直方向开设有第二通孔，所述第二电极形成于所述第二通孔中，且与所述第一半导体层连接。
可选的，所述导电DBR结构为多孔导电DBR结构，所述多孔导电DBR结构包括经过电化学腐蚀后形成的交替堆叠的第一多孔导电层与第二多孔导电层，其中，第一多孔导电层中形成有多个第一孔洞，第二多孔导电层中形成有多个第二孔洞，所述第一孔洞的直径与第二孔洞的直径不同。
可选的，所述第一多孔导电层和所述第二多孔导电层的材料为氮化镓基材料。
可选的，所述第二凸起部的侧面和水平面的夹角为第一夹角，所述第一夹角的度数范围均为40度-70度。
可选的，所述第一通孔的侧壁为斜面，所述第一通孔的侧壁的倾斜方向与所述第二凸起部的侧面的倾斜方向相同。
可选的，所述第二凸起部的形状为圆锥状、圆台状、棱锥或者棱台。
可选的，所述第二半导体层与所述第一电极之间还设有透明电极。
可选的，所述第一半导体层的材料为氮化镓基材料。
根据本申请实施例的第二方面，提供一种发光器件，所述发光器件包括如上所述的半导体结构。所述发光器件还包括电路板和波长转换介质层；
所述电路板设有第一焊垫和第二焊垫，所述半导体结构的第一电极与所述电路板上的第一焊垫连接，所述半导体结构的第二电极与所述电路板上的第二焊垫连接；
在所述衬底远离所述第一半导体层的一面开设有多个第三通孔，所述第三通孔和所述第一通孔一一对应，所述波长转换介质层设置于至少一个所述第三通孔内。
可选的，所述第三通孔的侧壁为斜面。
可选的，所述发光器件还包括反射层，所述反射层覆设于所述第三通孔的侧壁上。
根据本申请实施例的第三方面，提供一种半导体结构的制作方法，用于制作如上所述的半导体结构。所述半导体结构的制作方法包括以下步骤：
S1：在所述衬底上形成所述第一半导体层的平坦部；在所述第一半导体层的平坦部上形成所述隔离层，在所述隔离层上形成多个所述第一通孔；在所述隔离层的第一通孔内形成所述第一半导体层的第一凸起部、所述第一凸起部上形成所述第一半导体层的第二凸起部；
S2：在所述第一半导体层的所述第二凸起部上形成有源层；
S3：在所述有源层上形成与第一半导体层导电类型相反的所述第二半导体层；
S4：在所述第二半导体层上形成所述第一电极；在所述隔离层上形成所述第二通孔，在所述第二通孔内形成于所述第一半导体层连接的所述第二电极，形成所述半导体结构。
可选的，在步骤S2中，通过选择性生长，在所述第一半导体层的所述第二凸起部上形成有源层；
在步骤S3中，通过选择性生长，在所述有源层上形成与第一半导体层导电类型相反的所述第二半导体层；
在步骤S4中，通过选择性生长，在所述第二半导体层上形成所述第一电极。
根据本申请实施例的第四方面，提供一种发光器件的制作方法。所述发光器件的制作方法包括如上所述的半导体结构的制作方法，所述发光器件的制作方法还包括：
S5：将所述半导体结构安装至电路板的正面上，所述电路板设有第一焊垫和第二焊垫，将所述半导体结构的第一电极与所述电路板上的第一焊垫连接，所述半导体结构的第二电极与所述电路板上的第二焊垫连接；
S6：在所述衬底远离所述第一半导体层的一面开设多个第三通孔，所述第三通孔和所述第一通孔一一对应；
S7：在至少一个所述第三通孔中形成波长转换介质层。
可选的，所述第三通孔的侧壁为斜面。
可选的，在步骤S6之后，步骤S7之前，还包括：
在所述第三通孔的侧壁上形成反射层。
本申请的半导体结构及其制作方法、发光器件及其制作方法，通过将第二半导体层设置为可导电的DBR结构，一方面可导电的DBR结构作为发光器件中必不可少的P-N结的一部分，另一方面，通过可导电的DBR结构能够对合适的波长的光形成共振，从而提高发光效率；同时，通过将外延结构的侧壁设置为斜面，不仅能够提供一定的反射角度，而且能够增加反射面的面积，从而能够将更多的光反射至出光面，从而提高出光效率。需要说明的是，通过设置第一半导体层的第二凸起部的侧面为斜面，从而使形成在其外表面的有源层、第二半导体层、第一电极的侧壁均为斜面，从而达到最终的外延结构的侧壁为斜面的效果；并且，由于有源层的侧壁 为斜面的设置，可以在发光器件的尺寸不增大的情况下，增大发光器件的发光面积。
附图说明
图1是本申请的实施例1的半导体结构的截面结构示意图。
图2是图1的A部分的局部放大图。
图3是本申请的实施例1的半导体结构的第二半导体层的截面结构示意图。
图4(a)-图4(g)是本申请的实施例1的半导体结构的制备方法的工艺流程图。
图5是本申请的实施例2的发光部件的截面结构示意图。
图6(a)-图6(d)是本申请的实施例2的发光部件的制备方法的工艺流程图。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本申请相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置和方法的例子。
实施例1
如图1和图2所示，本实施例提供一种半导体结构100。半导体结构100包括：衬底110、第一半导体层120、隔离层130、有源层140、第 二半导体层150、第一电极160和第二电极170。第一半导体层120与第二半导体层150的导电类型相反，即，当第一半导体层120为P型半导体层时，第二半导体层150为N型半导体层；或者，当第一半导体层120为N型半导体层时，第二半导体层150为P型半导体层。
如图3所示，第二半导体层150为导电DBR结构，所述导电DBR结构为多孔导电DBR结构。具体的，所述多孔导电DBR结构包括经过电化学腐蚀后形成的交替堆叠的第一多孔导电层151与第二多孔导电层152，其中，第一多孔导电层151中形成有多个第一孔洞1511，第二多孔导电层152中形成有多个第二孔洞1521，第一孔洞1511的直径与第二孔洞1521的直径不同。
第一多孔导电层151和第二多孔导电层152的材料为氮化镓基材料，如GaN、AlGaN、GaInN、AlGaInN等材料。第一多孔导电层151和第二多孔导电层152的掺杂浓度不同。
这样，通过将第二半导体层150设置为可导电的DBR结构，一方面可导电的DBR结构作为发光器件中必不可少的P-N结的一部分，另一方面，通过可导电的DBR结构能够对合适的波长的光形成共振，从而提高发光效率。
请复参阅图2，第一半导体层120包括沿竖直方向Y依次层叠的平坦部121、第一凸起部122和第二凸起部123，平坦部121形成于衬底110上，隔离层130形成于平坦部121上并沿竖直方向Y开设有多个第一通孔131，第一凸起部122形成于第一通孔131内，第二凸起部123形成于第一凸起部122上，第二凸起部123与第一通孔131一一对应，且第二凸起部123间隔设置，第二凸起部的侧面1231为斜面，即第二凸部的侧面向靠近其中心的方向倾斜。有源层140、第二半导体层150、第一电极160依次层叠设置于第一半导体层120的第二凸起部123上。
这样，通过设置第一半导体层120的第二凸起部的侧面1231为斜面，从而使形成在其外表面的有源层140、第二半导体层150、第一电极160的侧壁均为斜面，从而达到最终的外延结构的侧壁为斜面的效果。通过将外延结构的侧壁设置为斜面，不仅能够提供一定的反射角度，而且能够增加反射面的面积，从而能够将更多的光反射至出光面，从而提高出光效率。需要说明的是，通过设置第一半导体层的第二凸起部的侧面为斜面，从而使形成在其外表面的有源层140、第二半导体层150、第一电极160的侧壁均为斜面，从而达到最终的外延结构的侧壁为斜面的效果；并且，由于有源层140的侧壁为斜面的设置，可以在发光器件的尺寸不增大的情况下，增大发光器件的发光面积。
而且，由于有源层140、第二半导体层150、第一电极160均对应于第一半导体层120的第二凸起部123形成，从而最终形成与第二凸起部123数量对应的多个间隔设置的外延结构。在每个外延结构中的第二半导体层150的宽度w小于或等于200um，优选地，小于或等于100um。
可选的，第二凸起部123的形状为圆锥状、圆台状、棱锥或者棱台，例如，六边棱台或者六边棱锥。
在本实施例中，第二凸起部的侧面1231和水平面的夹角为第一夹角α，第一夹角α的度数范围均为40度-70度。
需要说明的是，每个第二凸起部123不仅可以形成在其所对应的第一凸起部122上，也可以同时形成在位于该第一凸起部122外周缘的部分隔离层130上。
第一通孔的侧壁1311为斜面，第一通孔的侧壁1311与水平面的夹角为第二夹角β，第二夹角β的度数范围为0度-90度。第一通孔的侧壁1311的倾斜方向与第二凸起部的侧面1231的倾斜方向相同，从而避免阻挡光线由外延结构的侧壁反射至出光面的光路，从而进一步提高出光效率。
在本实施例中，第二半导体层150与第一电极160之间还设有透明电极，以增加第二半导体层150与第一电极160之间的接触。所述透明电极的材料为ITO。
第一半导体层120的材料为氮化镓基材料，如GaN、AlGaN、GaInN、AlGaInN等材料。
隔离层130还沿竖直方向开设有第二通孔132，第二电极170形成于第二通孔132中，且与第一半导体层120连接。第一电极160和第二电极170的材料可以为Cr、或Al、或Ti、或Pt。
图4(a)-图4(g)是本申请的实施例1的半导体结构的制作方法的工艺流程图。该制作方法用于制作如上所述的半导体结构。所述半导体结构的制作方法包括以下步骤：
S10：在所述衬底上形成所述第一半导体层的平坦部；在所述第一半导体层的平坦部上形成所述隔离层，在所述隔离层上形成多个所述第一通孔；在所述隔离层的第一通孔内形成所述第一半导体层的第一凸起部、所述第一凸起部上形成所述第一半导体层的第二凸起部；
S20：在所述第一半导体层的所述第二凸起部上形成有源层；
S30：在所述有源层上形成与第一半导体层导电类型相反的所述第二半导体层；
S40：在所述第二半导体层上形成所述第一电极；在所述隔离层上形成所述第二通孔，在所述第二通孔内形成于所述第一半导体层连接的所述第二电极，形成所述半导体结构。
具体的，在步骤S10中，包括：
步骤S11：如图4(a)所示，通过第一次外延生长，在衬底110上形成第一半导体层120的平坦部121，平坦部121远离衬底110的一面为一平面；
步骤S12：如图4(b)所示，在第一半导体层120的平坦部121上形成隔离层130，在隔离层130上形成多个第一通孔131；
步骤S13：如图4(c)所示，通过第二次外延生长，在隔离层130的第一通孔131内以及隔离层130上继续生长第一半导体层120，至第一半导体层120远离衬底110的一面生长成一平面，位于隔离层130的第一通孔131内的第一半导体层120的部分为第一半导体层120的第一凸起部122；
步骤S14：如图4(d)所示，对第一半导体层120远离衬底110的一面刻蚀，刻蚀至露出隔离层130，形成第一半导体层120的第二凸起部123。
但不限于此，通过调整第一半导体层120的生长参数，也可以通过掩膜的作用，仅在隔离层130的第一通孔131内形成第一半导体层120的第一凸起部122，以及在第一凸起部122上直接生长处侧壁为斜面的第二凸起部123，而无需刻蚀步骤。
在步骤S20中，如图4(e)所示，通过选择性生长，在第一半导体层120的第二凸起部123上形成有源层140，以使有源层140仅形成在第二凸起部123的表面，以达到有源层140的侧面也为斜面的效果。另外，通过选择性生长，能够有效避免常规工艺中ICP刻蚀导致的侧壁非辐射复合。
在步骤S30中，如图4(f)所示，通过选择性生长，在有源层140上形成与第一半导体层120导电类型相反的第二半导体层150，以使第二半导体层150仅形成在有源层140的表面，以达到第二半导体层150的侧面也为斜面的效果。
在步骤S40中，如图4(g)所示，通过选择性生长，在第二半导体层150上形成第一电极160，以使第一电极160仅形成在第二半导体层150 的表面，以达到第一电极160的侧面也为斜面的效果。
实施例2
如图5所示，本实施例提供一种发光部件，该发光部件包括实施例1中的半导体结构100，本实施例中发光部件还包括电路板200、反射层500和波长转换介质层300。
电路板200设有第一焊垫210和第二焊垫220，半导体结构100的第一电极160与电路板200上的第一焊垫210连接，半导体结构100的第二电极170与电路板200上的第二焊垫220连接。
在衬底110远离第一半导体层120的一面开设有多个第三通孔111，第三通孔111和第一通孔131一一对应。较佳的，第三通孔的侧壁1111为斜面，以进一步提高出光效率。
反射层500覆设于第三通孔的侧壁1111上，以进一步提高出光效率。
波长转换介质层300设置于至少一个第三通孔111内。波长转换介质层300包括第一波长转换介质层300和第二波长转换介质层300，第一波长转换介质层300和第二波长转换介质层300转换的波长不同。具体根据设计要求进行设置，如当有源层140发出的光是蓝光，可以在部分数量的第三通孔111内设置能将蓝光转换为红光的第一波长转换介质层300，在部分数量的第三通孔111内设置能将蓝光转换为绿光的第二波长转换介质层300，部分数量的第三通孔111内不设置波长转换介质层300，从而仍旧发出蓝光。
在其他实施例中，也可以不设置反射层500，直接在第三通孔111内设置波长转换介质层300。
如图6(a)-图6(d)所示，本实施例的另一个方面还提供一种发光部件的制作方法，用于制备上述发光部件。该发光部件的制备方法包括 实施例1的半导体结构的制作方法，还包括：
S50：如图6(a)所示，将半导体结构100安装至电路板200的正面上，电路板200设有第一焊垫210和第二焊垫220，将半导体结构100的第一电极160与电路板200上的第一焊垫210连接，半导体结构100的第二电极170与电路板200上的第二焊垫220连接。具体地，由于第一电极160的面积较大，可以通过导电胶400将半导体结构100的第一电极160与电路板200上的第一焊垫210连接。
在进入下一步骤之前，可以先对衬底110进行减薄，以减薄整体器件的厚度。
S60：如图6(b)所示，在衬底110远离第一半导体层120的一面开设多个第三通孔111，第三通孔111和第一通孔131一一对应；可以将第三通孔的侧壁1111设置为斜面，以进一步提高出光效率。
在进入下一步骤之前，如图6(c)所示，可以在第三通孔的侧壁1111上形成反射层500，以进一步提高出光效率。
S70：如图6(d)所示，在至少一个第三通孔111中形成波长转换介质层300。
本申请的发光器件1及其制作方法，通过将第二半导体层150设置为可导电的DBR结构，一方面可导电的DBR结构作为发光器件1中必不可少的P-N结的一部分，另一方面，通过可导电的DBR结构能够对合适的波长的光形成共振，从而提高发光效率；同时，通过将外延结构的侧壁设置为斜面，不仅能够提供一定的反射角度，而且能够增加反射面的面积，从而能够将更多的光反射至出光面，从而提高出光效率。需要说明的是，通过设置第一半导体层120的第二凸起部的侧面1231为斜面，从而使形成在其外表面的有源层140、第二半导体层150、第一电极160的侧壁均为斜面，从而达到最终的外延结构的侧壁为斜面的效果。
以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本申请保护的范围之内。

Claims (16)

  1. 一种半导体结构，其特征在于，所述半导体结构包括：衬底、第一半导体层、隔离层、有源层、第二半导体层、第一电极和第二电极；所述第一半导体层与所述第二半导体层的导电类型相反，所述第二半导体层为导电DBR结构；
    所述第一半导体层包括沿竖直方向依次层叠的平坦部、第一凸起部和第二凸起部，所述平坦部形成于所述衬底上，所述隔离层形成于所述平坦部上并沿竖直方向开设有多个第一通孔，所述第一凸起部形成于所述第一通孔内，所述第二凸起部形成于所述第一凸起部上，所述第二凸起部与所述第一通孔一一对应，且所述第二凸起部间隔设置，所述第二凸起部的侧面为斜面；
    所述有源层、所述第二半导体层、所述第一电极依次层叠设置于所述第一半导体层的第二凸起部上；
    所述隔离层还沿竖直方向开设有第二通孔，所述第二电极形成于所述第二通孔中，且与所述第一半导体层连接。
  2. 如权利要求1所述的半导体结构，其特征在于，所述导电DBR结构为多孔导电DBR结构，所述多孔导电DBR结构包括经过电化学腐蚀后形成的交替堆叠的第一多孔导电层与第二多孔导电层，其中，第一多孔导电层中形成有多个第一孔洞，第二多孔导电层中形成有多个第二孔洞，所述第一孔洞的直径与第二孔洞的直径不同。
  3. 如权利要求2所述的半导体结构，其特征在于，所述第一多孔导电层和所述第二多孔导电层的材料为氮化镓基材料。
  4. 如权利要求1所述的半导体结构，其特征在于，所述第二凸起部的侧面和水平面的夹角为第一夹角，所述第一夹角的度数范围均为20度-70度。
  5. 如权利要求4所述的半导体结构，其特征在于，所述第一通孔的侧 壁为斜面，所述第一通孔的侧壁的倾斜方向与所述第二凸起部的侧面的倾斜方向相同。
  6. 如权利要求1所述的半导体结构，其特征在于，所述第二凸起部的形状为圆锥状、圆台状、棱锥或者棱台。
  7. 如权利要求1所述的半导体结构，其特征在于，所述第二半导体层与所述第一电极之间还设有透明电极。
  8. 如权利要求1所述的半导体结构，其特征在于，所述第一半导体层的材料为氮化镓基材料。
  9. 一种发光器件，其特征在于，所述发光器件包括如权利要求1～8中的任意一项所述的半导体结构，所述发光器件还包括电路板和波长转换介质层；
    所述电路板设有第一焊垫和第二焊垫，所述半导体结构的第一电极与所述电路板上的第一焊垫连接，所述半导体结构的第二电极与所述电路板上的第二焊垫连接；
    在所述衬底远离所述第一半导体层的一面开设有多个第三通孔，所述第三通孔和所述第一通孔一一对应，所述波长转换介质层设置于至少一个所述第三通孔内。
  10. 如权利要求9所述的发光器件，其特征在于，所述第三通孔的侧壁为斜面。
  11. 如权利要求9所述的发光器件，其特征在于，所述发光器件还包括反射层，所述反射层覆设于所述第三通孔的侧壁上。
  12. 一种半导体结构的制作方法，其特征在于，用于制作如权利要求1～8中任意一项所述的半导体结构，所述半导体结构的制作方法包括以下步骤：
    S1：在所述衬底上形成所述第一半导体层的平坦部；在所述第一半导体层的平坦部上形成所述隔离层，在所述隔离层上形成多个所述第一通孔；在所述隔离层的第一通孔内形成所述第一半导体层的第一凸起部、所述第一凸起部上形成所述第一半导体层的第二凸起部；
    S2：在所述第一半导体层的所述第二凸起部上形成有源层；
    S3：在所述有源层上形成与第一半导体层导电类型相反的所述第二半导体层；
    S4：在所述第二半导体层上形成所述第一电极；在所述隔离层上形成所述第二通孔，在所述第二通孔内形成于所述第一半导体层连接的所述第二电极，形成所述半导体结构。
  13. 如权利要求12所述的半导体结构的制作方法，其特征在于，
    在步骤S2中，通过选择性生长，在所述第一半导体层的所述第二凸起部上形成有源层；
    在步骤S3中，通过选择性生长，在所述有源层上形成与第一半导体层导电类型相反的所述第二半导体层；
    在步骤S4中，通过选择性生长，在所述第二半导体层上形成所述第一电极。
  14. 一种发光器件的制作方法，其特征在于，所述发光器件的制作方法包括如权利要求12或13所述的半导体结构的制作方法，所述发光器件的制作方法还包括：
    S5：将所述半导体结构安装至电路板的正面上，所述电路板设有第一焊垫和第二焊垫，将所述半导体结构的第一电极与所述电路板上的第一焊垫连接，所述半导体结构的第二电极与所述电路板上的第二焊垫连接；
    S6：在所述衬底远离所述第一半导体层的一面开设多个第三通孔，所述第三通孔和所述第一通孔一一对应；
    S7：在至少一个所述第三通孔中形成波长转换介质层。
  15. 如权利要求14所述的发光器件的制作方法，其特征在于，所述第三通孔的侧壁为斜面。
  16. 如权利要求15所述的发光器件的制作方法，其特征在于，在步骤S6之后，步骤S7之前，还包括：
    在所述第三通孔的侧壁上形成反射层。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220352238A1 (en) * 2021-04-30 2022-11-03 Samsung Display Co., Ltd. Display device and manufacturing method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0677522A (ja) * 1992-08-24 1994-03-18 Oki Electric Ind Co Ltd 発光・受光素子及びそれらの製造方法
CN1698213A (zh) * 2003-03-20 2005-11-16 索尼株式会社 半导体发光元件及其制法,集成半导体发光元件及其制法,图像显示装置及其制法,照明装置及其制法
US20060054902A1 (en) * 2004-09-14 2006-03-16 Finisar Corporation Band offset in AlInGaP based light emitters to improve temperature performance
CN105336826A (zh) * 2015-11-11 2016-02-17 厦门乾照光电股份有限公司 一种集成多孔状反射层的发光二极管制作方法
CN110098295A (zh) * 2019-04-26 2019-08-06 山东大学 一种具有导电DBR的GaN基LED及其制备方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0677522A (ja) * 1992-08-24 1994-03-18 Oki Electric Ind Co Ltd 発光・受光素子及びそれらの製造方法
CN1698213A (zh) * 2003-03-20 2005-11-16 索尼株式会社 半导体发光元件及其制法,集成半导体发光元件及其制法,图像显示装置及其制法,照明装置及其制法
US20060054902A1 (en) * 2004-09-14 2006-03-16 Finisar Corporation Band offset in AlInGaP based light emitters to improve temperature performance
CN105336826A (zh) * 2015-11-11 2016-02-17 厦门乾照光电股份有限公司 一种集成多孔状反射层的发光二极管制作方法
CN110098295A (zh) * 2019-04-26 2019-08-06 山东大学 一种具有导电DBR的GaN基LED及其制备方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220352238A1 (en) * 2021-04-30 2022-11-03 Samsung Display Co., Ltd. Display device and manufacturing method thereof

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