WO2022102475A1 - 基板処理装置及び基板処理方法 - Google Patents
基板処理装置及び基板処理方法 Download PDFInfo
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- WO2022102475A1 WO2022102475A1 PCT/JP2021/040428 JP2021040428W WO2022102475A1 WO 2022102475 A1 WO2022102475 A1 WO 2022102475A1 JP 2021040428 W JP2021040428 W JP 2021040428W WO 2022102475 A1 WO2022102475 A1 WO 2022102475A1
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- H01L21/6773—Conveying cassettes, containers or carriers
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- H01L21/67739—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
- H01L21/67745—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber characterized by movements or sequence of movements of transfer devices
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- H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
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- H01L21/67763—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading
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Definitions
- This disclosure relates to a substrate processing apparatus and a substrate processing method.
- a semiconductor wafer (hereinafter referred to as a wafer) which is a substrate by a substrate processing device. Wafers are transported between devices while being housed in a carrier, which is a transport container.
- Patent Document 1 describes a coating and developing apparatus.
- the carrier In the coating / developing device, the carrier is transported by a carrier mounting section on which the carrier is mounted for loading / unloading the wafer into the device and a ceiling transport mechanism that transports the carrier between the substrate processing devices. It is equipped with a carrier temporary storage part. Then, the carrier is transferred between the carrier mounting portion and the carrier temporary placing portion by the carrier moving mechanism provided in the coating / developing apparatus.
- the present disclosure provides a technique capable of preventing a delay in loading or unloading a substrate to a substrate processing device and improving the throughput of the device.
- the substrate processing apparatus of the present disclosure includes a carrier block in which a carrier, which is a transport container for accommodating a substrate, is arranged.
- a substrate processing apparatus including a processing block in which the substrate is delivered to and from the carrier block and a processing module for processing the substrate is provided.
- a board unloading port and a board receiving port provided on the carrier block on which the carrier is mounted for carrying out the board from the carrier to the processing block and carrying the board from the processing block to the carrier.
- a first carrier temporary placement portion and a second carrier temporary placement portion for temporarily placing the carriers respectively, The carrier is placed between the carrier carry-in port, the carrier carry-out port, the board receiving port, the board carry-out port, the first carrier temporary placing portion, and the second carrier temporary placing portion.
- a carrier transfer mechanism that can be transferred, and From the transfer source to the next transfer destination among the carrier carry-in port, the board carry-out port, the board accept port, and the carrier carry-out port, the first carrier temporary placement section or the second carrier temporary placement section is provided.
- the transfer time via the first carrier temporary storage section is compared with the transfer time via the second carrier temporary storage section, and the first carrier is transferred.
- a control signal for controlling the operation of the carrier transfer mechanism so that the carrier is transferred to the carrier temporary placement portion having the shorter transfer time among the carrier temporary placement portion and the second carrier temporary placement portion of the above.
- the control unit to output and To prepare for.
- This disclosure can prevent a delay in loading or unloading a substrate to a substrate processing device and improve the throughput of the device.
- the coating and developing apparatus 1 which is an embodiment of the substrate processing apparatus of the present disclosure, will be described with reference to the plan view of FIG. 1 and the vertical sectional side view of FIG. 2, respectively.
- the coating / developing device 1 is configured by connecting the carrier block D1, the processing block D2, and the interface block D3 in a row in the horizontal direction. The direction along this row is the front-back direction, and the carrier block D1 side is the front side. These blocks D1 to D3 are partitioned from each other.
- An exposure machine D4 is connected to the interface block D3 on the rear side.
- the carrier block D1 is a block for loading and unloading the wafer W to and from the coating and developing apparatus 1.
- the wafer W is carried in and out of the carrier block D1 in a state of being housed in a carrier C called, for example, FOUP (Front Opening Unify Pod). That is, the carrier C is a transport container for transporting the wafer W, and the carrier C is placed on the carrier block D1.
- FOUP Front Opening Unify Pod
- FIG. 3 shows a schematic perspective view of the carrier block D1.
- 11 is a housing of the carrier block D1, and four wafer W transport ports 12 that form a load port and can be opened and closed are arranged side by side on the lower side of the front surface of the housing 11.
- a carrier stage is provided on the front side below each transport port 12. These carrier stages on which the carrier C is placed move between the front unload position and the rear load position. At the unload position, the carrier C is handed over to the carrier stage.
- the load position is a position where the wafer W is transferred between the carrier C and the carrier block D1, and at the load position, the opening / closing mechanism 13 for opening / closing the transport port 12 also opens / closes the lid of the carrier C. ..
- the carrier C in which the wafer W is housed is placed on the two carrier stages on the left side, and the wafer W is dispensed (delivered) from the carrier C to the apparatus. Will be done. Therefore, these carrier stages are referred to as sender stages 14. Further, of these two sender stages 14 which are board carry-out ports, the left side may be designated as 14-1 and the right side may be designated as 14-2.
- the carrier C having the wafer W dispensed to the apparatus is placed on the two carrier stages on the right side, and the wafer W is carried into the carrier C from the apparatus. Therefore, these carrier stages are referred to as receiver stages 15. Further, of the two receiver stages 15 that are the board receiving ports, the left side may be designated as 15-1 and the right side may be designated as 15-2. Further, the carrier C mounted on the sender stage 14 may be described as a sender carrier, and the carrier C mounted on the receiver stage 15 may be described as a receiver carrier.
- a transport mechanism 20 is provided in the housing 11 of the carrier block D1.
- the transport mechanism 20 transports the wafer W from the carrier C mounted on the sender stage 14 to the processing block D2 and transports the wafer W from the processing block D2 to the carrier C mounted on the receiver stage 15. conduct.
- shelves 26 are provided in two stages. Further, on the front side of each shelf 26, shelves 27 are provided in two stages. For each of the two shelves 26 and the lower shelf 27, each region divided into four on the left and right is configured as a stocker 16, and the carrier C can be temporarily placed on each stocker 16.
- the stocker 16 which is the temporary storage portion may be numbered and distinguished from each other. 16-1, 16-2, 16-3, 16-4 from the left side of the lower shelf 26, 16-5, 16-6, 16-7, 16-8, lower from the left side of the upper shelf 26.
- the numbers are 16-9, 16-10, 16-11, and 16-12 in order from the left side of the side shelf 27.
- the upper shelf 27 is provided with two load stages 18 and two unload stages 19.
- OHT Overhead Hoist Transfer
- OHT Overhead Hoist Transfer
- the carrier C in which the wafer W before processing in the coating / developing device 1 is stored is placed on the load stage 18, and the wafer W processed in the coating / developing device 1 is stored in the unload stage 19.
- the carrier C is placed. Therefore, the load stage 18 and the unload stage 19 are configured as a carrier carry-in port and a carrier carry-out port, respectively.
- the two load stages 18 may be described as 18-1, 18-2, and the two unload stages may be described as 19-1, 19-2, respectively, and 18-1, 18-2, 19 from the left side to the right side. They are arranged in the order of -1, 19-2.
- a carrier transfer mechanism 21 is provided between the shelves 26 and the shelves 27 (see FIGS. 1 and 2).
- the carrier transfer mechanism 21 is provided with an elevating shaft 23 that can move along a moving shaft 22 extending to the left and right, a joint arm 24 that can move up and down along the elevating shaft 23, and a tip side of the joint arm 24. It is provided with two claw portions 25. The distance between the two claw portions 25 can be freely changed so that the holding portion C0 provided on the upper side of the carrier C can be gripped.
- the carrier transfer mechanism 21 allows the carrier C to be transferred between the sender stage 14, the receiver stage 15, the stocker 16, the load stage 18, and the unload stage 19.
- the processing block D2 is configured by stacking six unit blocks E1 to E6 partitioned from each other from the bottom in numerical order.
- each unit block E (E1 to E6), the wafer W is conveyed and processed in parallel with each other.
- the unit blocks E1 to E3 have the same configuration as each other, and the unit blocks E4 to E6 have the same configuration as each other.
- the unit block E6 shown in FIG. 1 will be described as a representative of the unit blocks E1 to E6.
- a wafer W transport path 31 extending in the front-rear direction is formed at the center of the left and right sides of the unit block E6.
- a plurality of developing modules 32 are provided on one of the left and right sides of the transport path 31.
- a large number of heating modules 33 for performing PEB (Post Exposure Bake), which is a heat treatment after exposure and before development, are provided side by side.
- the transport path 31 is provided with a transport arm F6 which is a transport mechanism for transporting the wafer W by the unit block E6.
- the unit blocks E1 to E3 include a resist film forming module instead of the developing module 32.
- the resist film forming module forms a resist film by applying a resist as a chemical solution to the wafer W.
- a heating module for heating the wafer W after forming the resist film is provided instead of the heating module 33 for PEB.
- the transfer arms of the unit blocks E1 to E5 corresponding to the transfer arm F6 are shown as F1 to F5.
- a tower T1 extending vertically so as to straddle the unit blocks E1 to E6 is provided.
- the tower T1 is provided with a transfer module TRS and a temperature control module SCPL at heights corresponding to the unit blocks E1 to E6, respectively. Wafer W can be transferred between modules.
- the TRS and SCPL of the tower T1 are shown as TRS1 to TRS6 and SCPL1 to SCPL6 with the same numbers as the corresponding unit blocks E1 to E6.
- the TRS1 to TRS6 and the TRS in various places described later are modules for temporarily placing the wafer W for transferring the wafer W between the transfer mechanisms, and are accessed by the transfer arms F1 to F6.
- the tower T1 is also provided with TRS7 and TRS8 for transferring the wafer W between the transfer mechanism 30 and the transfer mechanism 20 of the carrier block D1.
- the SCPL1 to SCPL6 are modules in which the temperature of the wafer W can be adjusted.
- the place where the wafer W is placed is described as a module.
- modules that process the wafer W such as the temperature control module SCPL, the developing module 32, and the resist film forming module, are described as processing modules.
- the processing block D2 is actually provided with a module other than the module described above, but it is omitted in order to prevent the explanation from being complicated.
- the interface block D3 includes towers T2 to T4 extending up and down so as to straddle the unit blocks E1 to E6. Further, the interface block D3 is provided with transfer mechanisms 41 to 43, and the wafer W is transferred between various modules provided in the towers T2 to T4 by these transfer mechanisms 41 to 43, which will be described here. In order to avoid complication, the display of modules other than the modules provided in the tower T2 is omitted. Accordingly, it will be described below that the wafer W is conveyed only by 41, 42 of the transfer mechanisms 41 to 43.
- the tower T2 is provided with TRS at each height of the unit blocks E1 to E6, and the TRS located at the same height as the unit block is attached with the same number and the letter A as the unit block to TRS1A to TRS1A. Shown as TRS6A. Further, the tower T2 is provided with ICPL and TRS7A, which are modules for transferring the wafer W to and from the exposure machine D4. The ICPL adjusts the temperature of the wafer W in the same manner as the SCPL.
- the wafer W is transported by a transport path specified by PJ described later.
- the first transport path H1 and the second transport path H2 among the transport routes will be described with reference to FIG. 4, which outlines these transport routes.
- the first transfer path H1 is a transfer path through which the wafer W passes through any one of the unit blocks E1 to E3 and any one of the unit blocks E4 to E6, and a resist pattern is formed on the wafer W.
- the wafer W discharged from the sender carrier C of the sender stage 14 by the transfer mechanism 20 is transferred to the transfer module TRS7 of the tower T1 and distributed to the transfer modules TRS1 to TRS3 of the tower T1 by the transfer mechanism 30.
- the wafer W is received by the transfer arms F1 to F3, and is conveyed in the order of temperature adjusting modules SCPL1 to SCPL3 ⁇ resist film forming module ⁇ heating module.
- the wafer W on which the resist film is formed by being conveyed in this way is conveyed to the transfer modules TRS1A to TRS3A, and is conveyed in the order of transfer mechanism 42 ⁇ ICPL ⁇ transfer mechanism 41 ⁇ exposure machine D4, and the resist film is exposed. ..
- the exposed wafer W is conveyed in the order of the transfer mechanism 41 ⁇ TRS7A, and then distributed to the transfer modules TRS4A to TRS6A by the transfer mechanism 42.
- the wafers W thus transferred to the TRS4A to TRS6A are conveyed in the order of the heating module 33 ⁇ the temperature control modules SCPL4 to SCPL6 ⁇ the developing module 32 by the transfer arms F4 to F6.
- the resist film is developed and a resist pattern is formed on the wafer W.
- the developed wafer W is conveyed to the transfer modules TRS4 to TRS6, conveyed in the order of the transfer mechanism 30 ⁇ the transfer module TRS8, and is carried into the receiver carrier C of the receiver stage 15 by the transfer mechanism 20.
- the second transfer path H2 is a transfer path through which the wafer W passes through only one of the unit blocks E1 to E6 among the unit blocks E1 to E6, and the wafer W is subjected to a resist film forming process and a developing process. Of these, only the resist film formation process is performed.
- the wafer W is transferred from the sender carrier C to the transfer modules TRS1 to TRS3 via the transfer module TRS7. Then, the wafer W is conveyed in the order of temperature adjusting modules SCPL1 to SCPL3 ⁇ resist film forming module ⁇ heating module.
- the processed wafer W is conveyed to the transfer modules TRS1 to TRS3, transferred to the transfer module TRS8 by the transfer mechanism 30, and returned to the carrier C of the receiver stage 15.
- a plurality of TRS1 to TRS3 are provided, but different ones are used for carrying in from TRS7 and carrying out to TRS8.
- the wafer W in the carrier C is set for the process job (PJ).
- the PJ is information for designating a processing recipe for the wafer W (including a transfer recipe for transporting and processing to which type of module) and the wafer W to be transported. Since wafers W of the same PJ receive the same processing, they are wafers W of the same lot.
- each transfer mechanism is controlled by the control unit 51 described later. That is, after the wafer W of the preceding PJ is collectively carried into the apparatus, the wafer W of the succeeding PJ is collectively conveyed to the apparatus. Then, each wafer W is conveyed by the transfer path specified by each PJ, and is processed by each processing module in the transfer path according to the processing recipe specified by each PJ.
- the processing recipe includes parameters such as the rotation speed of the wafer W during the liquid treatment and the temperature of the wafer W during the heat treatment.
- each PJ is distinguished by adding alphabetic characters as PJ-A, PJ-B, PJ-C ..., and PJs are carried out in the order of the attached alphabetic characters. That is, it is assumed that the wafer W of PJ-A, the wafer W of PJ-B, the wafer W of PJ-C, and so on are carried into the apparatus in this order, and each wafer W is processed.
- the coating / developing device 1 includes a control unit 51 configured by a computer.
- the control unit 51 includes a wafer processing program 52 and a carrier transfer program 53.
- the wafer processing program 52 a group of steps is set up so that the above-mentioned wafer W transfer and wafer W processing in each module are performed, and each module and wafer are subjected to such transfer and processing.
- a control signal is output to each transport mechanism of W.
- the carrier transfer program 53 has a set of steps so that the carrier C, which will be described later, can be transferred, and outputs a control signal to the carrier transfer mechanism 21 so that the transfer can be performed.
- the wafer processing program 52 and the carrier transfer program 53 cooperate with each other to operate so that the wafer W can be conveyed and processed and the carrier C, which will be described later, can be transferred.
- the carrier transfer program 53 performs selection of the stocker 16 on which the carrier C is placed, which will be described in detail later, and various operations for that purpose.
- the wafer processing program 52 and the carrier transfer program 53 are stored in a storage medium such as a compact disk, a hard disk, or a DVD, and installed in the control unit 51.
- the memory 54 included in the control unit 51 stores the time required for each transfer mechanism of the wafer W to transfer one step, that is, the time required to transfer the wafer W from one module to the next module. There is. Further, the memory 54 stores parameters related to the speed of the carrier transfer mechanism 21 of the carrier C.
- the carrier transfer program 53 is configured so that the transfer time can be calculated based on the parameter once the carrier C is transferred from which stage or stocker 16 to which stage or stocker 16. ing.
- the wafer processing program 52 can calculate the processing time of the wafer W in each processing module based on the above processing recipe, and further, from this processing time, the staying time of the wafer W in each processing module (MUT: Module Using Time). ) Can be calculated.
- MUT Module Using Time
- the time required from the time when the wafer W is carried into the processing module to the start of processing and the time required from the end of processing until the wafer W can be carried out from the processing module are added to the processing time. It was done.
- the transfer time of one step by the transfer mechanism of the MUT and the wafer W described above is used to select the stocker 16 to which the carrier C is transferred, which will be described in detail later.
- the control unit 51 is connected to the upper control unit 56.
- the upper control unit 56 controls the operation of the OHT described above. Further, the upper control unit 56 transmits a carrier out instruction to the control unit 51.
- This carrier out instruction is an instruction that allows the carrier C to be transferred to the unload stage 19, and is issued for each carrier C. That is, among the carriers C for which the discharged wafer W has been collected, the carrier C for which the carrier out instruction has been output can be transferred to the unload stage 19, but the carrier C for which the carrier out instruction has not been output can be transferred to the unload stage 19. , It is not possible to transfer to the unload stage 19.
- the carrier block D1 can transfer the carrier C from which the wafer W has been discharged from the sender stage 14 to another place by the carrier transfer mechanism 21 described above. As a result, it is possible to prevent the sender stage 14 from being occupied by the same carrier C for a long time, to sequentially transfer the subsequent carrier C to the sender stage 14, and to dispense the wafer W into the apparatus. Further, the carrier C whose wafer W has been discharged is sequentially transferred to the receiver stage 15 by the carrier transfer mechanism 21, and the carrier C whose wafer W has been stored is transferred from the receiver stage 15 to another place. .. As a result, it is possible to prevent the receiver stage 15 from being occupied by the same carrier C for a long time, and to sequentially collect the wafer W from the inside of the apparatus to each carrier C.
- FIG. 6 is a schematic diagram showing an outline of the transfer route for the carrier C.
- the carrier C conveyed from the OHT to the load stage 18 is transferred in the order of the load stage 18 ⁇ the sender stage 14 ⁇ the receiver stage 15 ⁇ the unload stage 19 as indicated by the solid arrow.
- the transfer destination stage is not available (when all of the transfer destination stages are occupied by other carrier C)
- the carrier C is transferred from the stocker 16 to the transfer destination.
- the carrier out instruction described above is not output for the carrier C for which the wafer W has been carried in at the receiver stage 15, the carrier C is transferred to the stocker 16 regardless of whether the unload stage 19 is available or not. Will be posted. Unless the transfer destination stage is not available or the carrier out instruction is not issued for the transfer to the unload stage 19, the transfer source stage does not go through the stocker 16. Carrier C is transferred directly to the transfer destination stage.
- FIG. 7 schematically shows the stocker 16.
- the stage and stocker 16 on the rear side of the carrier block D1 are shown as one table on the upper side of the figure, and the stage and stocker 16 on the front side are shown on the lower side of the figure. It is shown to form one table.
- each stage and each stocker 16 are schematically shown by separating them from each other as shown as squares in the table.
- each of the vertically arranged squares and the horizontally arranged squares will be described as columns, and the vertical direction will be the Z-axis direction and the horizontal direction will be the Y-axis direction.
- FIG. 7 schematically shows the stocker 16.
- stage and the stocker 16 located on the front side and the stage and the stocker 16 located on the rear side described in FIG. 3 are shown so as to be displaced vertically in the figure. There is. Therefore, the arrangements of the stages and stockers 16 shown in the table correspond to those described in FIG. Further, among the many carriers C shown in the figure, the carrier C to be transferred is indicated by dots.
- the carrier C of the sender stage 14-1 is subject to transfer after the wafer W has been dispensed to the apparatus, and the receiver stage 15 is occupied by the carrier C. Therefore, the carrier C of the sender stage 14-1 is transferred to the stocker 16, but the carrier C is mounted on the stockers 16-1 to 16-4. Therefore, according to the above-mentioned rule, the carrier C of the sender stage 14-1 is transferred to the stocker 16-5 having the youngest number among the vacant ones (see the left of FIG. 7 and the center of FIG. 7). Therefore, the carrier C moves two steps in the Z-axis direction.
- the carrier C of 15-2 is transferred to the unload stage 19-1, so that 15-2 becomes vacant. Therefore, the carrier C of the stocker 16-5 is transferred to the 15-2. As a result of this transfer, the carrier C moves three steps in the Y-axis direction and two steps in the Z-axis direction, so that the transfer distance is relatively long (see the right side of FIG. 7). Therefore, the time required to transfer the carrier C from the sender stage 14-1 to the receiver stage 15-2 is relatively long.
- the carrier transfer mechanism 21 cannot transfer another carrier C. Therefore, even if the carrier C in the carrier block D1 can be transferred during the transfer of the carrier C from the stocker 16-5 to the receiver stage 15-2, the other carrier C can be transferred. There is a risk that the transfer of the other carrier C cannot be performed and the timing of starting the transfer of the other carrier C will be delayed. That is, the selection of the stocker 16 according to the number in this comparative example may delay the transfer of the carrier C, which may cause a delay in the loading and unloading of the wafer W to the coating and developing apparatus 1. Therefore, there is a concern that a sufficiently high throughput cannot be obtained for the coating / developing device 1.
- the transfer is performed under the same conditions as in the comparative example, that is, under the condition that the receiver stage 15 and the stockers 16-1 to 16-4 are not vacant when the carrier C of the sender stage 14-1 is transferred. Is shown as an example of doing.
- the total of the transfer time from the transfer source sender stage 14-1 and the transfer time to the transfer destination receiver stage 15-2 among the vacant stockers 16 is calculated.
- the minimum stocker 16 is selected as the evacuation destination and reprinted.
- the stocker 16-12 is selected, and the carrier C is transferred from the sender stage 14-1 to the stocker 16-12 (FIG. 8 left, FIG. 8 center). .. Therefore, the carrier C is transferred in three stages in the Y-axis direction and one stage in the Z-axis direction. After that, when the receiver stage 15-2 becomes empty, the carrier C of the stocker 16-12 is transferred to the receiver stage 15-2 (Fig. 8, right). Therefore, the carrier C moves only one step in the Z-axis direction.
- the carrier C has a total of three stages in the Y-axis direction and the Z-axis before the transfer from the sender stage 14-1 to the receiver stage 15-2 via the stocker 16 of the evacuation destination. Move a total of 4 steps in the direction.
- the carrier C moves only by a total of 3 steps in the Y-axis direction and a total of 2 steps in the Z-axis direction, so that the distance required for transferring the carrier C is shorter than that of the comparative example. Therefore, the time required for transfer is also shortened.
- the transfer from the sender stage 14 to the receiver stage 15 has been described as an outline of the embodiment, but the same applies to the case where the carrier C is transferred between other transfer source and transfer destination stages. That is, when transferring from the transfer source stage to the transfer destination stage via the stocker 16, the total of the transfer time from the transfer source stage and the transfer time to the transfer destination stage. The stocker 16 having the minimum value is selected as the evacuation destination, and the carrier C is transferred to the selected stocker 16.
- the method of selecting the stocker 16 at the time of transfer of each section of the load stage 18 ⁇ the sender stage 14, the sender stage 14 ⁇ the receiver stage 15, the receiver stage 15 ⁇ the unload stage 19 will be described in Examples 1 and 2, respectively. It will be described as Example 3. Further, in the outline of the above embodiment, it has been described that the receiver stage 15-2 is predetermined as the transfer destination of the carrier C. However, when selecting the stocker 16, the transfer destination is selected from a plurality of candidates for the transfer destination. The selection of the transfer destination will also be described in each of the following examples.
- Example 1 The first embodiment will be described with reference to FIG. FIG. 9 shows a state in which the carrier C can be transferred from the load stage 18-1 but the sender stages 14-1 and 14-2 are not vacant. Therefore, the load stage 18-1 ⁇ stocker 16 ⁇ sender stage 14 is transferred.
- the availability of the stocker 16 is determined, and the vacant stocker 16 is set as a candidate for the evacuation destination (temporary storage destination) of the carrier C.
- the stockers 16-5 to 16-12 are candidates for the evacuation destination.
- each transfer time (first transfer) from the load stage 18-1 which is the transfer source as the second stage to the stockers 16-5 to 16-12 specified as candidates for the evacuation destination in the first stage. Time) is calculated. That is, the first transfer time is calculated for each stocker 16-5 to 16-12, for example, 10 seconds to 16-5, 15 seconds to 16-6 ... 20 seconds to 16-12.
- the third step it is determined which of the sender stages 14-1 and 14-2, which are candidates for the transfer destination, is to be the transfer destination. This is done so that, of the sender stages 14-1 and 14-2, the one that can be vacated by transferring the carrier C to another place earlier is determined as the transfer destination.
- the wafer W is dispensed from each carrier C of the sender stage 14 to the apparatus in the order of PJ. Therefore, the wafer W remaining on the carrier C of the sender stage 14-1 and the wafer W remaining on the carrier C of the sender stage 14-2 are compared at the timing of transferring the carrier C from the load stage 18-1. Then, the sender stage on which the carrier C having the earliest PJ order of the wafer W to be discharged last is placed is determined as the transfer destination.
- the PJs of the wafer W remaining in the carrier C of the sender stage 14-1 are PJ-A and PJ-B
- the PJs of the wafer W remaining in the carrier C of the sender stage 14-2 are PJ-A and PJ-B. It is assumed that it is PJ-C. Therefore, the PJ of the wafer W finally discharged by the carrier C of 14-1 is PJ-B, and the PJ of the wafer W finally discharged by the carrier C of 14-2 is PJ-C. Since the wafer W of PJ-B is discharged before the wafer W of PJ-C, the carrier C of the sender stage 14-1 can be transferred to another place earlier. Is decided as the transfer destination. That is, which sender stage 14 is the transfer destination is determined according to the order of processing the lots of the wafers W of the sender stages 14-1 and 14-2.
- the transfer destination is the one on which the carrier C having a smaller number of wafers W remaining without being discharged in the carrier C is placed.
- the number of wafers W of the carrier C of 14-1 is 13. It is assumed that the number of wafers W of the carrier C of 14-2 is 14.
- the carrier C of 14-1 completes the ejection of the wafer W first and can be transferred to another place, so that 14-1 is determined as the transfer destination.
- the transfer destination is based on the remaining number of wafers W of the carrier C of each sender stage 14. It can be decided.
- each transfer time (second transfer) from the stockers 16-5 to 16-12 specified in the first stage to the sender stage 14-1 which is the transfer destination determined in the third stage. (As time) is calculated. That is, the second transfer time is calculated for each stocker 16-5 to 16-12, for example, 10 seconds from 16-5, 15 seconds from 16-6 ... 20 seconds from 16-12. Will be done.
- the stocker 16 having the minimum total time is selected as the stocker 16 as the save destination. That is, the control unit 51 described above makes a comparison about the total time, and the stocker 16 is selected based on the comparison result.
- the carrier C is transferred from the load stage 18-1 to the stocker 16 selected in this way and is made to stand by, and when the sender stage 14-1 determined as the transfer destination becomes available, the sender stage 14 is transferred from the stocker 16.
- the stockers 16-5 to 16-12 for which the above total time is calculated, and the other stockers are the first carrier temporary storage unit and the second carrier temporary storage unit, respectively.
- the above comparison of the total time is based on the transfer time when the transfer is performed via the first carrier temporary storage section and the transfer when the transfer is performed via the second carrier temporary storage section. It is a comparison with the loading time.
- FIG. 10 shows a state in which the carrier C can be transferred from the sender stage 14-1 but the receiver stages 15-1 and 15-2 are not vacant. Therefore, the sender stage 14-1 ⁇ stocker 16 ⁇ receiver stage 15 is transferred.
- the availability of the stocker 16 is determined as in the first embodiment, and the vacant stocker 16 is set as a candidate for the evacuation destination of the carrier C.
- the stockers 16-5 to 16-12 will be described as candidates for the evacuation destination.
- the first transfer time of each of the stockers 16-5 to 16-12 specified in the first stage is calculated from the sender stage 14-1 which is the transfer source.
- the third step it is determined which of the receiver stages 15-1 and 15-2, which are candidates for the transfer destination, is to be the transfer destination. This is done so that, of the receiver stages 15-1 and 15-2, the one that can be vacated by transferring the carrier C to another place earlier is determined as the transfer destination. More specifically, among the wafers W carried in 15-1 and 15-2, the carrier C having the earlier arrival time of the wafer W scheduled to be carried in last to the carrier C is mounted. The stage 15 on the other side is determined as the transfer destination.
- the wafer W of PJ-A is scheduled to be finally carried into the carrier C of the receiver stage 15-1, and the wafer W is hereinafter referred to as the last wafer W of PJ-A.
- the PJ-B wafer W is scheduled to be finally carried into the carrier C of the receiver stage 15-2, and the wafer W is hereinafter referred to as the last PJ-B carry-in wafer W.
- Each of these PJ-A and PJ-B wafers W is conveyed by the transfer path H1 described with reference to FIG. 4, and the last carry-in wafer W of PJ-A is located in the heating module 33 of the unit block E6 and is PJ.
- the last carry-in wafer W of ⁇ B will be described as being located in the heating module of the unit block E3.
- the estimated arrival time to the carrier C is acquired by the same calculation. Specifically, the MUT of each processing module on the downstream side of the transfer path after the heating module of the unit block E3 in which the wafer W is located, and the transfer mechanism required for the wafer W to reach the transfer time of one process ⁇ carrier C.
- the estimated arrival time can be obtained by adding the number of steps of.
- the exposure machine D4 may also be treated as a processing module, and for example, the carry-out interval of the wafer W from the exposure machine D4 may be set to the MUT of the exposure machine D4.
- the wafers W of PJ-A and PJ-B are both conveyed by the transfer path H1, but when the wafers are conveyed by the transfer path H2, the calculation according to the transfer path H2 is performed.
- the arrival time at the carrier C may be acquired.
- PJ-B is transported by the transport path H2, and the last carry-in wafer W of PJ-B is located in the heating module of the unit block E3 as described above.
- the MUT of the heating module + the transport time of one step (the transport time between the heating module and TRS3) + the transport time of one step (the transport time between TRS3 and TRS8) + the transport time of one process (TRS8-carrier C).
- Transport time between is calculated. From the calculation result, the arrival time of the last wafer W of the PJ-B to the carrier C can be obtained.
- the receiver stage 15 on which the carrier C having the earliest delivery timing of the wafer W to be carried in last is placed is determined as the transfer destination. Will be. It is assumed that the arrival time of the last carry-in wafer W of the PJ-A to the carrier C is earlier, and the receiver stage 15-1 on which the carrier C for storing the PJ-A is mounted is determined as the transfer destination. , The following steps will be explained.
- the total time of the first transfer time and the second transfer time is calculated for each stocker 16-5 to 16-12, and this total time is the minimum stocker.
- 16 is selected as the stocker 16 as the evacuation destination. That is, the control unit 51 described above makes a comparison about the total time, and the stocker 16 is selected based on the comparison result. Then, the carrier C is transferred from the sender stage 14-1 to the stocker 16 selected in this way, and when the receiver stage 15-1 determined as the transfer destination becomes available, the stocker 16 is transferred to the receiver stage 15-1. Transfer carrier C.
- FIG. 11 shows a state in which the carrier C can be transferred from the receiver stage 15-2, but the unload stages 19-1 and 19-2 are not vacant. Therefore, the receiver stage 15-2 ⁇ stocker 16 ⁇ unload stage 19 is transferred. It is assumed that the carrier out instruction of the carrier C has been issued.
- the availability of the stocker 16 is determined as in the first and second embodiments, and the vacant stocker 16 is set as a candidate for the evacuation destination of the carrier C.
- the stockers 16-5 to 16-12 will be described as candidates for the evacuation destination.
- the first transfer time of each of the stockers 16-5 to 16-12 specified in the first step is calculated from the receiver stage 15-2 which is the transfer source.
- the second transfer time for transferring between the unload stages 19-1 and 19-2 and the stockers 16-5 to 16-12 specified in the first stage is acquired. That is, each transfer time between the stockers 16-5 to 16-12 and the unload stage 19-1, and each transfer time between the stockers 16-5 to 16-12 and the unload stage 19-2. , Obtained as the second transfer time, respectively.
- the total time of the first transfer time and the second transfer time is calculated for each stocker 16-5 to 16-12, and the total time is further compared to obtain the total time. It is decided to transfer the carrier C to the stocker 16 which minimizes. Then, when either unload stage 19-1 or 19-2 becomes vacant, the carrier C is transferred to the vacant unload stage 19.
- the stocker 16 is selected and transferred to the unload stage 19. Therefore, in this Example 3, among the transfer destinations 19-1 and 19-2, the unload stage 19 which is the acquisition source of the second transfer time used for calculating the minimum total time described above is used. May have carrier C transferred to another unload stage 19. That is, for this third embodiment, the transfer destination is determined from the unload stages 19-1 and 19-2 with the expectation that the transfer time will be the shortest. This is because OHT is transferred to the carrier C of the unload stages 19-1 and 19-2, so that the control unit 51 can obtain information on the vacant timing for each of these 19-1 and 19-2 in advance. Because there is no such thing.
- one of the unload stages 19-1 and 19-2 is set as a temporary transfer destination with arbitrary regularity, and the temporary transfer destinations are set from the stockers 16-5 to 16-12.
- the calculation may be performed with the transfer time to the transfer destination as the second transfer time.
- 19-1 and 19-2 may be alternately determined to be temporary transfer destinations.
- the transfer time from the transfer source stage to the stocker 16 and the transfer destination stage from the stocker 16 to the carrier C transfer via the stocker 16 between the stages.
- the stocker 16 is selected so that the total time with the transfer time to is shortened. Therefore, since the loading / unloading of the wafer W from the carrier C to the coating / developing device 1 is prevented from being delayed, the coating / developing device 1 can obtain a high throughput. Further, the load (stress) of the carrier transfer mechanism 21 can be reduced, the consumption of parts can be suppressed, and the frequency of maintenance can be reduced.
- the carrier C is not transferred to the stocker 16 when the transfer destination stage is vacant. Therefore, since the carrier C is transferred between the stages more quickly, it is possible to obtain a higher throughput for the coating and developing apparatus 1 more reliably.
- the carrier C is set to another place (the stage in the latter stage) earlier than the sender stage 14 and the receiver stages 15 provided in a plurality of stages as described above. Or, the person who can be transferred to the stocker 16) is specified. Then, the stocker 16 is selected based on the identification. Therefore, a more suitable stocker 16 is selected so that the transfer time of the carrier C between the stages is further suppressed. Only one of the sender stage 14, the receiver stage 15, and the unload stage 19 which are the transfer destinations is provided, and the coating and developing apparatus 1 is configured so that the transfer destination does not need to be selected. May be good. Only one load stage 18 may be provided.
- the above layout is an example, and it is sufficient if the carrier transfer mechanism 21 can access the above layout. Not limited. Further, the number of arrangements of each stage and each stocker is not limited to the above example. Further, the receiver stage and the sender stage are separate bodies in the above configuration example, but are not limited to such separate bodies. That is, when the carrier C containing the wafer W is placed, it functions as a sender stage, and when the carrier C from which the wafer W is discharged is placed, it functions as a receiver stage to provide a carrier stage that can be used properly. May be.
- the wafer transport mechanism that transports the wafer W to the processing block D2 and the wafer transport mechanism that transports the wafer W to the carrier C are integrated. However, it may be a separate body. Further, the wafer W is not limited to be returned to the same carrier C as the carrier C paid out in the sender stage 14.
- the first transfer path H1 and the second transfer path H2 for the wafer W in the above-mentioned processing block D2 are examples, and for example, any of the unit blocks E4 to E6 among the unit blocks E1 to E6 for performing development processing.
- the wafer W may be transported by a transport path that passes through only one of them.
- the processing block D2 may be configured to include only one unit block.
- the processing performed in the processing block D2 is not limited to the formation and development of the resist film. Treatments such as formation of an antireflection film and an insulating film by liquid treatment, cleaning of the wafer W by supplying a cleaning liquid, and application of an adhesive for adhering the wafer W may be performed.
- the process also includes imaging the wafer W and inspecting the surface condition. Therefore, the substrate processing device is not limited to the coating / developing device 1.
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Abstract
Description
前記キャリアブロックとの間で前記基板が受け渡され、当該基板を処理する処理モジュールが設けられる処理ブロックと、を備える基板処理装置において、
前記基板処理装置に対して前記キャリアの搬入出を行うために当該キャリアが載置されるキャリア搬入ポート及びキャリア搬出ポートと、
前記キャリアブロックに設けられ、前記キャリアから前記処理ブロックへの前記基板の搬出及び前記処理ブロックから前記キャリアへの前記基板の搬入を行うために当該キャリアが載置される基板搬出ポート及び基板受入ポートと、
前記キャリアを各々仮置きするための第1のキャリア仮置き部及び第2のキャリア仮置き部と、
前記キャリア搬入ポートと、前記キャリア搬出ポートと、前記基板受入ポートと、前記基板搬出ポートと、前記第1のキャリア仮置き部と、前記第2のキャリア仮置き部と、の間で前記キャリアを移載可能なキャリア移載機構と、
前記キャリア搬入ポート、前記基板搬出ポート、前記基板受入ポート、前記キャリア搬出ポートのうちの移載元から次の移載先へ、前記第1のキャリア仮置き部または第2のキャリア仮置き部を経由して前記キャリアを移載するために、前記第1のキャリア仮置き部を経由する移載時間と、前記第2のキャリア仮置き部を経由する移載時間とを比較し、前記第1のキャリア仮置き部及び第2のキャリア仮置き部のうち当該移載時間が短い方のキャリア仮置き部へ前記キャリアを移載するように、前記キャリア移載機構の動作を制御する制御信号を出力する制御部と、
を備える。
後述する本技術の実施例におけるキャリアCの移載方法の効果を明確にするために、先ず比較例におけるキャリアCの移載について説明する。この比較例では、図6で説明したようにストッカ16への移載が必要になったときに、ストッカ16-1~16-12のうちの空いているストッカの中で、番号がより若いものへと移載が行われる。
続いて実施例について、図8を参照してその概要を説明する。当該図8では、比較例と同様の条件、即ち、センダーステージ14-1のキャリアCを移載するにあたり、レシーバーステージ15及びストッカ16-1~16-4が空いていないという条件で、移載を行う例を示している。この実施例では、空いているストッカ16のうち、移載元であるセンダーステージ14-1からの移載時間と、移載先であるレシーバーステージ15-2への移載時間との合計が、最小となるストッカ16を待避先として選択して移載する。この選択方法についての詳細は後述するが、このケースではストッカ16-12が選択され、センダーステージ14-1から当該ストッカ16-12へキャリアCが移載される(図8左、図8中央)。従ってキャリアCは、Y軸方向に3段、Z軸方向に1段移載する。その後、レシーバーステージ15-2が空くと、ストッカ16-12のキャリアCは当該レシーバーステージ15-2へ移載される(図8右)。従って、当該キャリアCは、Z軸方向に1段のみ移動する。
実施例1として、図9を参照して説明する。この図9では、ロードステージ18-1からキャリアCが移載可能であるが、センダーステージ14-1、14-2が空いていない状態を示している。従って、ロードステージ18-1→ストッカ16→センダーステージ14の移載を行う。
以下、実施例2について図10を参照して、実施例1との差異点を中心に説明する。この図10では、センダーステージ14-1からキャリアCが移載可能であるが、レシーバーステージ15-1、15-2が空いていない状態を示している。従って、センダーステージ14-1→ストッカ16→レシーバーステージ15の移載を行う。
以下、実施例3について図11を参照して、実施例1、2との差異点を中心に説明する。この図11では、レシーバーステージ15-2からキャリアCが移載可能であるが、アンロードステージ19-1、19-2が空いていない状態を示している。従って、レシーバーステージ15-2→ストッカ16→アンロードステージ19の移載を行う。なお、当該キャリアCのキャリアアウト指示は出されているものとする。
D1 キャリアブロック
D2 処理ブロック
W ウエハ
1 塗布、現像装置
14 センダーステージ
15 レシーバーステージ
16 ストッカ
18 ロードポート
19 アンロードポート
21 キャリア移載機構
Claims (7)
- 基板を収納する搬送容器であるキャリアが配置されるキャリアブロックと、
前記キャリアブロックとの間で前記基板が受け渡され、当該基板を処理する処理モジュールが設けられる処理ブロックと、を備える基板処理装置において、
前記基板処理装置に対して前記キャリアの搬入出を行うために当該キャリアが載置されるキャリア搬入ポート及びキャリア搬出ポートと、
前記キャリアブロックに設けられ、前記キャリアから前記処理ブロックへの前記基板の搬出及び前記処理ブロックから前記キャリアへの前記基板の搬入を行うために当該キャリアが載置される基板搬出ポート及び基板受入ポートと、
前記キャリアを各々仮置きするための第1のキャリア仮置き部及び第2のキャリア仮置き部と、
前記キャリア搬入ポートと、前記キャリア搬出ポートと、前記基板受入ポートと、前記基板搬出ポートと、前記第1のキャリア仮置き部と、前記第2のキャリア仮置き部と、の間で前記キャリアを移載可能なキャリア移載機構と、
前記キャリア搬入ポート、前記基板搬出ポート、前記基板受入ポート、前記キャリア搬出ポートのうちの移載元から次の移載先へ、前記第1のキャリア仮置き部または第2のキャリア仮置き部を経由して前記キャリアを移載するために、前記第1のキャリア仮置き部を経由する移載時間と、前記第2のキャリア仮置き部を経由する移載時間とを比較し、前記第1のキャリア仮置き部及び第2のキャリア仮置き部のうち当該移載時間が短い方のキャリア仮置き部へ前記キャリアを移載するように、前記キャリア移載機構の動作を制御する制御信号を出力する制御部と、
を備える基板処理装置。 - 前記第1のキャリア仮置き部を経由する移載時間は、前記移載元から前記第1のキャリア仮置き部への移載時間と、前記第1のキャリア仮置き部から前記移載先への移載時間との合計時間であり、
前記第2のキャリア仮置き部を経由する移載時間は、前記移載元から前記第2のキャリア仮置き部への移載時間と、前記第2のキャリア仮置き部から前記移載先への移載時間との合計時間である請求項1記載の基板処理装置。 - 前記移載先へ前記キャリアを移載可能であるときには、前記第1のキャリア仮置き部及び第2のキャリア仮置き部を経由せずに前記移載元から前記移載先への移載が行われるように前記制御部は制御信号を出力する請求項1記載の基板処理装置。
- 前記基板搬出ポートは複数設けられ、
前記移載元、前記移載先が夫々前記キャリア搬入ポート、前記基板搬出ポートであり、当該複数の基板搬出ポートに前記キャリアが各々載置された状態で、
前記制御部は、前記複数の基板搬出ポートの各々のキャリア内に収納された前記基板のロットについての処理の順番に応じて、当該複数の基板搬出ポートのうちのいずれの基板搬出ポートを前記移載先とするかを決定して、前記移載時間の比較を行う請求項1記載の基板処理装置。 - 前記制御部は、前記基板のロットの処理の順番と、前記複数の基板搬出ポートにおける各キャリア内の前記基板の数と、に基づいて、当該複数の基板搬出ポートのうちのいずれの基板搬出ポートを移載先にするかを決定する請求項4記載の基板処理装置。
- 前記基板受入ポートは複数設けられ、
前記移載元が前記基板搬出ポートで前記移載先が前記基板受入ポートであり、当該各基板受入ポートに前記キャリアが載置された状態で、
前記制御部は、前記複数の基板受入ポートにおける各キャリアについて、各々最後に搬入される前記基板の搬入のタイミングが最も早いキャリアが載置される基板受入ポートを前記移載先として決定して、前記移載時間の比較を行う請求項1記載の基板処理装置。 - 基板を収納する搬送容器であるキャリアが配置されるキャリアブロックと、前記キャリアブロックとの間で前記基板が受け渡され、当該基板を処理する処理モジュールが設けられる処理ブロックと、を備える基板処理装置を用いた基板処理方法において、
前記基板処理装置に対して前記キャリアの搬入出を行うために、キャリア搬入ポート及びキャリア搬出ポートに各々前記キャリアを載置する工程と、
前記キャリアから前記処理ブロックへの前記基板の搬出及び前記処理ブロックから前記キャリアへの前記基板の搬入を行うために、前記キャリアブロックに設けられる基板搬出ポート及び基板受入ポートに各々前記キャリアを載置する工程と、
第1のキャリア仮置き部及び第2のキャリア仮置き部に前記キャリアを仮置きする工程と、
前記キャリア搬入ポートと、前記キャリア搬出ポートと、前記基板受入ポートと、前記基板搬出ポートと、前記第1のキャリア仮置き部及び第2のキャリア仮置き部のうちの一方との間で、キャリア移載機構により前記キャリアを移載する工程と、
キャリア移載機構により、前記キャリア搬入ポートと、前記キャリア搬出ポートと、前記基板受入ポートと、前記基板搬出ポートと、前記第1のキャリア仮置き部と、前記第2のキャリア仮置き部と、の間で前記キャリアを移載する工程と、
前記キャリア搬入ポート、前記基板搬出ポート、前記基板受入ポート、前記キャリア搬出ポートのうちの移載元から次の移載先へ、前記第1のキャリア仮置き部または第2のキャリア仮置き部を経由して前記キャリアを移載するにあたり、前記第1のキャリア仮置き部を経由する移載時間と、前記第2のキャリア仮置き部を経由する移載時間とを比較し、前記第1のキャリア仮置き部及び第2のキャリア仮置き部のうち当該移載時間が短い方のキャリア仮置き部へ前記キャリアを移載する工程と、
を備える基板処理方法。
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JPH11330197A (ja) * | 1998-05-15 | 1999-11-30 | Hitachi Ltd | 搬送制御方法とその装置 |
JP2000236008A (ja) * | 1999-02-15 | 2000-08-29 | Mitsubishi Electric Corp | ウエハ自動搬送システムにおける搬送制御方法 |
JP2006041074A (ja) * | 2004-07-26 | 2006-02-09 | Hitachi Kokusai Electric Inc | 半導体製造装置 |
JP2010171276A (ja) * | 2009-01-23 | 2010-08-05 | Tokyo Electron Ltd | 塗布、現像装置 |
JP2020053429A (ja) * | 2018-09-21 | 2020-04-02 | 株式会社Screenホールディングス | インデクサ装置、基板処理装置、インデクサ装置の制御方法および基板処理装置の制御方法 |
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JPH11330197A (ja) * | 1998-05-15 | 1999-11-30 | Hitachi Ltd | 搬送制御方法とその装置 |
JP2000236008A (ja) * | 1999-02-15 | 2000-08-29 | Mitsubishi Electric Corp | ウエハ自動搬送システムにおける搬送制御方法 |
JP2006041074A (ja) * | 2004-07-26 | 2006-02-09 | Hitachi Kokusai Electric Inc | 半導体製造装置 |
JP2010171276A (ja) * | 2009-01-23 | 2010-08-05 | Tokyo Electron Ltd | 塗布、現像装置 |
JP2020053429A (ja) * | 2018-09-21 | 2020-04-02 | 株式会社Screenホールディングス | インデクサ装置、基板処理装置、インデクサ装置の制御方法および基板処理装置の制御方法 |
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