WO2022100081A1 - 一种高效太阳能电池及其制备方法 - Google Patents

一种高效太阳能电池及其制备方法 Download PDF

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WO2022100081A1
WO2022100081A1 PCT/CN2021/098440 CN2021098440W WO2022100081A1 WO 2022100081 A1 WO2022100081 A1 WO 2022100081A1 CN 2021098440 W CN2021098440 W CN 2021098440W WO 2022100081 A1 WO2022100081 A1 WO 2022100081A1
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layer
doped
silicon
region
silicon substrate
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PCT/CN2021/098440
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French (fr)
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杨新强
高礼强
陈刚
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浙江爱旭太阳能科技有限公司
广东爱旭科技有限公司
天津爱旭太阳能科技有限公司
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Publication of WO2022100081A1 publication Critical patent/WO2022100081A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/02168—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells the coatings being antireflective or having enhancing optical properties for the solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H01L31/0682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • H01L31/1868—Passivation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the invention relates to the technical field of solar cells, in particular to a high-efficiency solar cell and a preparation method thereof.
  • the back-contact heterojunction (HBC) cell combines the advantages of the back-contact cell with full light reception and the high-quality passivation of the HJT cell. Its experimental efficiency reaches 26.63%, and the cell efficiency is greatly improved. , on the other hand, it is beneficial to reduce the LCOE of the entire industry chain.
  • Chinese Patent Publication No. CN107210331A discloses an HBC battery, which needs to deposit an insulating layer and a base low protective layer between the P-type semiconductor layer and the N-type semiconductor layer to realize the isolation between P/N, and the structure is complex , the process is more.
  • the technical problem to be solved by the present invention is to provide a high-efficiency solar cell with a simple structure, low series resistance, good passivation effect and high conversion efficiency through the texture design of the back surface area and the multi-layer passivation structure design.
  • the present invention also provides a method for preparing a high-efficiency solar cell, which has few steps, controllable quality and low cost.
  • the present invention provides a high-efficiency solar cell, comprising a silicon substrate, the silicon substrate is provided with a front surface and a back surface, a first passivation layer is provided on the front surface of the silicon substrate, and the first passivation layer is provided on the front surface of the silicon substrate.
  • the backside of the silicon substrate is provided with a first doping region, a second doping region and a second passivation layer, and the first doping region and the second doping region are alternately arranged;
  • a tunnel layer is arranged on the first doped region, a first doped layer is arranged on the tunnel layer, a first electrode is arranged on the first doped layer, and a first electrode is arranged on the second doped region is provided with a second electrode;
  • the second passivation layer covers the exposed second doping region and extends to the first doping layer to insulate the first electrode and the second electrode.
  • the tunneling layer extends from the first doping region to the second doping region, and the second passivation layer covers the exposed tunneling layer and extends to the first doping region layer to insulate the first electrode and the second electrode;
  • the tunnel layer covering the first doped region and the second passivation layer form a composite layer
  • the second electrode is disposed on the silicon substrate and passes through the composite layer of the second doped region.
  • the second doped region is provided with a textured region, the surface of the textured region has a rough structure formed by a textured process, and the second electrode is disposed on the textured region.
  • the width of the texturing region is 25% to 75% of the width of the first doping region
  • the texturing width of the texturing area is less than or equal to the width of the second electrode.
  • a mask layer and a tunneling layer are further provided between the second passivation layer provided on the second doped region and the silicon substrate, and the mask layer is provided between the silicon substrate and the tunneling layer , wherein the tunneling layers on the first doped region and the second doped region are separated;
  • the materials of the mask layer and the tunnel layer are both silicon dioxide, and the mask layer and the tunnel layer form a double-layer passivation tunnel structure.
  • the material of the first passivation layer is selected from silicon dioxide, silicon nitride, nickel oxide, cuprous iodide, copper oxide, cuprous oxide, copper sulfide, intrinsic silicon carbide, intrinsic One or more of amorphous silicon, the thickness of which is 1 to 10 nm;
  • the material of the antireflection layer is selected from one or more of silicon nitride, silicon oxide, silicon oxynitride and magnesium fluoride, and the thickness thereof is 20-150 nm.
  • the first doped layer is a B-doped polysilicon layer or a B-doped amorphous silicon layer or a doped silicon carbide layer;
  • the material of the tunneling layer is selected from SiO 2 , Al 2 O 3 , this One or more of intrinsic amorphous silicon and intrinsic silicon carbide;
  • the material of the second passivation layer is silicon nitride.
  • the second doped region is provided with a diffusion layer.
  • the materials of the tunneling layer are SiO2 and intrinsic silicon carbide.
  • the intrinsic silicon carbide includes intrinsic hydrogenated silicon carbide.
  • the present invention also provides a method for preparing a high-efficiency solar cell, comprising:
  • Pretreating the silicon substrate includes cleaning the single crystal silicon wafer and removing the damaged layer;
  • the silicon substrate is provided with a front surface and a back surface, and the back surface of the silicon substrate is provided with a first doping region and a second doping region, wherein the first doping region and the second doping region are alternately arranged;
  • a mask layer is formed on the second doped region on the back of the silicon substrate, and the material of the mask layer is selected from one or more of silicon dioxide, silicon carbide, silicon nitride and ink;
  • first electrode is conductively connected to the first doped layer
  • second electrode is conductively connected to the silicon base of the second doped region
  • step (3) when the pretreatment in step (1) also includes a texturing process, after step (3) is completed, the following step is also included: polishing the silicon substrate, so that the first dopant on the back of the silicon substrate The surface of the impurity region is a planar structure.
  • step (5) only the first doping layer on the second doping region is removed, the mask layer and the tunneling layer on the second doping region are retained, and the first doping layer is The region is separated from the tunneling layer on the second doped region.
  • first doped regions and second doped regions are arranged on the backside of the silicon substrate, and a tunnel layer and a first doped layer are sequentially arranged on the first doped regions.
  • the back of the substrate is covered with a second passivation layer, thereby forming a regional texture design and a multi-layer passivation structure design on the back of the battery, reducing the series resistance of the back electrode, improving the passivation effect, and further improving the conversion efficiency of the battery.
  • the tunneling layer of the present invention covers the entire backside of the silicon substrate, wherein the tunneling layer covering the first doped region and the second passivation layer form a composite layer, which effectively reduces surface recombination and improves conversion efficiency.
  • the present invention forms a textured region with a rough structure on the second doped region, increases the contact area between the second electrode and the silicon substrate, and further reduces the series resistance.
  • the masking layer and the tunneling layer on the second doping region are retained, which can reduce the second masking process of the conventional process. and de-masking process to reduce production costs.
  • the battery of the present invention has a simple structure, few manufacturing processes, controllable quality and low cost.
  • FIG. 1 is a schematic diagram of a solar cell structure according to Embodiment 1 of the present invention.
  • FIG. 2 is a schematic diagram of a solar cell structure according to Embodiment 2 of the present invention.
  • FIG. 3 is a schematic diagram of a solar cell structure according to Embodiment 3 of the present invention.
  • FIG. 4 is a schematic diagram of the structure of the solar cell according to Embodiment 4 of the present invention.
  • a high-efficiency solar cell provided by the present invention includes a silicon substrate 10, and the silicon substrate 10 is provided with a front surface and a back surface; a first passivation layer 20 is arranged on the front surface of the silicon substrate 10, and the first passivation layer A passivation layer 20 is provided with an antireflection layer 30; the backside of the silicon substrate is provided with a first doped region, a second doped region and a second passivation layer 40, the first doped region and the second The doped regions are alternately arranged; a tunnel layer 50 is arranged on the first doped region, a first doped layer 60 is arranged on the tunnel layer 50, and a first doped layer is arranged on the first doped layer 60 The electrode 70 is provided with a second electrode 80 on the second doping region; the second passivation layer 30 covers the exposed second doping region and extends to the first doping layer 60 to The first electrode 70 and the second electrode 80 are insulated.
  • the silicon substrate 10 is an N-type silicon wafer or a P-type silicon wafer.
  • the material of the first passivation layer 20 is selected from silicon dioxide, silicon nitride, nickel oxide, cuprous iodide, copper oxide, cuprous oxide, copper sulfide, intrinsic silicon carbide, and intrinsic amorphous silicon. One or more, the thickness of which is 1-10 nm.
  • the material of the anti-reflection layer 30 is selected from one or more of silicon nitride, silicon oxide, silicon oxynitride and magnesium fluoride.
  • the thickness of the antireflection layer 30 is 20-150 nm.
  • the material of the tunneling layer 50 is selected from one or more of SiO 2 , Al 2 O 3 , intrinsic amorphous silicon, and intrinsic silicon carbide.
  • the materials of the tunneling layer are SiO 2 and intrinsic silicon carbide.
  • the intrinsic silicon carbide includes intrinsic hydrogenated silicon carbide.
  • the thickness of the tunneling layer 50 is 1-20 nm. More preferably, the thickness of the tunneling layer 50 is 1 ⁇ 5 nm. Preferably, the thickness of the tunneling layer 50 is 1.4-2 nm.
  • the first doped layer 60 is a B-doped polysilicon layer, a B-doped amorphous silicon layer or a doped silicon carbide layer.
  • the first doped layer 60 is a B-doped amorphous silicon layer.
  • the doped silicon carbide layer includes doped hydrogenated silicon carbide.
  • the material of the second passivation layer 30 is silicon nitride. Since the second passivation layer 30 covers the back of the battery, it can reduce the reflection of external light on the back of the battery, increase the incidence of light on the back of the battery, and improve the short circuit current.
  • the second doped region is a second doped region formed by methods such as diffusion/ion implantation/selective deposition.
  • the second doped region is provided with a diffusion layer, and the diffusion layer is a P-type diffusion layer or an N-type diffusion layer, wherein the P-type diffusion layer is a diffusion region formed by diffusion of boron, aluminum, gallium, etc., and N
  • the type diffusion layer is a diffusion region formed by the diffusion of nitrogen, phosphorus, arsenic, etc.
  • the preparation method of the high-efficiency solar cell in this embodiment includes the following steps:
  • the pretreatment includes cleaning the single crystal silicon wafer and removing the damaged layer. Specifically, including:
  • the silicon wafer is cleaned with HF solution to remove the silicon dioxide layer on the surface of the silicon wafer and form Si-H passivation bonds with the dangling bonds on the surface of the silicon wafer, and finally dried in nitrogen for use.
  • the silicon base is provided with a front surface and a back surface, and the back surface of the silicon base is provided with a first doped region and a second doped region, wherein the first doped region and the second doped region are alternately arranged .
  • the specific preparation process includes: Method 1: Pass in a source gas (such as borane) containing elements such as boron, aluminum, gallium, etc.
  • a source gas such as borane
  • Method 2 Gas or carrier gas carrying boron trichloride or boron tribromide) for thermal diffusion to form a P-type diffusion layer;
  • Method 2 Depositing dopant sources (such as borosilicate glass) containing boron, aluminum, gallium, etc., and forming by thermal diffusion P-type diffusion layer;
  • Method 3 Prepare an aluminum electrode above the diffusion layer, and then form a P-type diffusion layer doped with aluminum through a high-temperature process;
  • Method 4 Spin coating containing doping sources such as boron, aluminum, and gallium (such as tribromide Boron) is thermally diffused to form a P-type diffusion layer;
  • Method 5 Implant ions containing elements such as boron, aluminum, and gallium, and diffuse at high temperature to form a P-type diffusion layer.
  • Method 1 Pass in a source gas containing nitrogen, phosphorus, arsenic and other elements (such as phosphine gas or a carrier gas carrying phosphorus oxychloride) for thermal diffusion to form N
  • Method 2 Deposit doping sources containing nitrogen, phosphorus, arsenic, etc. (such as phosphosilicate glass) and form an N-type diffusion layer by thermal diffusion
  • Method 3 Spin coating doping sources containing nitrogen, phosphorus, arsenic, etc.
  • N-type diffusion layer (for example, phosphorus oxychloride) is thermally diffused to form an N-type diffusion layer; method 4: ions containing nitrogen, phosphorus, arsenic and other elements are injected, and the N-type diffusion layer is formed by high-temperature diffusion.
  • a first passivation layer is deposited on the front surface of the silicon substrate by using a PECVD deposition method, and an antireflection layer is deposited on the first passivation layer.
  • a mask layer is formed on the second doped region on the backside of the silicon substrate by using a photolithography mask method or a laser ablation method, and the mask layer has an interdigitated shape.
  • a SiO 2 layer is deposited on the backside of the silicon substrate by a laser ablation method, and then the SiO 2 on the first doped region is removed by a laser ablation method to form an interdigitated mask layer.
  • the material of the mask layer can also be silicon carbide, silicon nitride or ink.
  • the thickness of the mask layer is 20-300 nm. More preferably, the thickness of the mask layer is 20 nm, 50 nm, 150 nm or 300 nm.
  • the present invention uses an ultraviolet picosecond laser with a wavelength of 260-270 nm to remove SiO 2 on the first doped region.
  • the laser spot is circular with a diameter of 10-20 ⁇ m , the spot overlap is 5% to 15%.
  • the wavelength of the ultraviolet picosecond laser is 263-267 nm
  • the spot diameter is 13-17 ⁇ m
  • the spot overlap is 5%-10%.
  • the invention adopts ultraviolet picosecond laser to etch the SiO 2 layer, so that the SiO 2 on the first doped region can be removed in a very short time, so as to reduce the thermal damage to the battery caused by the laser heat.
  • the technical difficulty of using the ultraviolet picosecond laser to etch the SiO 2 layer in the present invention lies in that the laser energy, scanning speed, frequency and spot overlap need to be reasonably matched. Laser damage can be minimized only when laser energy, scanning speed, frequency, and spot overlap are effectively coordinated.
  • the overlapping degree of the light spots and the diameter of the light spots play the most important role in forming the interdigitated mask layer, especially the width and precision of the first doped region. If the overlap of the light spots is too small, the SiO 2 layer between the light spots will not be removed cleanly, and the surface of the silicon substrate cannot be etched, or the pattern formed is incomplete; if the overlap of the light spots is too large, the energy of the overlapping area of the light spots will be too high , the loss increases, affecting the battery performance.
  • the present invention performs boron ion implantation on the amorphous silicon layer to form a first doped layer. After the ion implantation treatment, there will be ion bombardment to slow down the etching effect, that is, a layer of anti-organic alkali etching will be formed on the surface. Amorphous silicon layer.
  • the tunneling layer covers the entire back surface of the silicon substrate, that is, the tunneling layer covers the mask layer and the first doped region, and the first doped layer covers the tunneling layer.
  • an etching solution is used to etch and remove the mask layer and the tunneling layer and the first doping layer on the mask layer, wherein the etching solution is a TMAH solution with a concentration of 1% to 2%.
  • the temperature of the liquid is 20 to 80°C. In order to speed up the etching speed, preferably, the temperature of the etching solution is 40-60°C.
  • a thermal oxidation method, a PECVD method or a hot wire CVD method is used to deposit and form the second passivation layer on the backside of the silicon substrate.
  • the second passivation layer covers all structures on the backside of the silicon substrate.
  • first electrode is conductively connected to the first doping layer
  • second electrode is conductively connected to the silicon substrate of the second doping region
  • the second passivation layer on the first doped region is etched, the first doped layer is etched to form a first hole, and the second passivation layer on the second doped region is etched, The surface of the silicon substrate is etched to form a second hole; a first electrode is formed in the first hole, and a second electrode is formed in the second hole.
  • the cell is annealed to achieve better ohmic contact.
  • N 2 and/or O 2 gas is introduced for annealing, the annealing temperature is 750-1000° C., and the annealing time is 10-60 min.
  • the tunneling layer 50 extends from the first doped region to the second doped region, and the second passivation
  • the doped layer 40 covers the exposed tunneling layer 50 and extends to the first doped layer 60 to insulate the first electrode 70 and the second electrode 80 .
  • the tunneling layer 50 covers the entire backside of the silicon substrate, wherein the tunneling layer 50 covering the first doped region and the second passivation layer 40 form a composite layer, which effectively reduces surface recombination and improves conversion efficiency .
  • the second electrode 80 is disposed on the silicon substrate and passes through the composite layer of the second doped region.
  • the preparation method of the high-efficiency solar cell in this embodiment includes the following steps:
  • the pretreatment includes cleaning the single crystal silicon wafer and removing the damaged layer. Specifically, including:
  • the silicon wafer is cleaned with HF solution to remove the silicon dioxide layer on the surface of the silicon wafer and form Si-H passivation bonds with the dangling bonds on the surface of the silicon wafer, and finally dried in nitrogen for use.
  • the silicon base is provided with a front surface and a back surface, and the back surface of the silicon base is provided with a first doped region and a second doped region, wherein the first doped region and the second doped region are alternately arranged .
  • a first passivation layer is deposited on the front surface of the silicon substrate by using a PECVD deposition method, and an antireflection layer is deposited on the first passivation layer.
  • a tunneling layer is formed on the backside of the silicon substrate
  • the tunneling layer covers the entire back surface of the silicon substrate, that is, the tunneling layer covers the first doped region and the second doped region.
  • a photolithography mask method or a laser ablation method is used to form a mask layer on the tunnel layer of the second doped region on the backside of the silicon substrate, and the mask layer has an interdigitated shape.
  • a SiO 2 layer is deposited on the backside of the silicon substrate by a laser ablation method, and then the SiO 2 on the first doped region is removed by a laser ablation method to form an interdigitated mask layer.
  • the material of the mask layer can also be silicon carbide, silicon nitride or ink.
  • the thickness of the mask layer is 20-300 nm. More preferably, the thickness of the mask layer is 20 nm, 50 nm, 150 nm or 300 nm.
  • the present invention uses an ultraviolet picosecond laser with a wavelength of 260-270 nm to remove SiO 2 on the first doped region.
  • the laser spot is circular with a diameter of 10-20 ⁇ m , the spot overlap is 5% to 15%.
  • the wavelength of the ultraviolet picosecond laser is 263-267 nm
  • the spot diameter is 13-17 ⁇ m
  • the spot overlap is 5%-10%.
  • the invention adopts ultraviolet picosecond laser to etch the SiO 2 layer, so that the SiO 2 on the first doped region can be removed in a very short time, so as to reduce the thermal damage to the battery caused by the laser heat.
  • the technical difficulty of using the ultraviolet picosecond laser to etch the SiO 2 layer in the present invention lies in that the laser energy, scanning speed, frequency and spot overlap need to be reasonably matched. Laser damage can be minimized only when laser energy, scanning speed, frequency, and spot overlap are effectively coordinated.
  • the overlapping degree of the light spots and the diameter of the light spots play the most important role in forming the interdigitated mask layer, especially the width and precision of the first doped region. If the overlap of the light spots is too small, the SiO 2 layer between the light spots cannot be removed cleanly, and the surface of the silicon substrate cannot be etched, or the pattern formed is incomplete; if the overlap of the light spots is too large, the energy of the overlapping area of the light spots is too high , the loss increases and affects the battery performance.
  • the present invention performs boron ion implantation on the amorphous silicon layer to form a first doped layer. After the ion implantation treatment, there will be ion bombardment to slow down the etching effect, that is, a layer of anti-organic alkali etching will be formed on the surface. Amorphous silicon layer.
  • the first doped layer covers the entire back surface of the silicon substrate, that is, the first doped layer covers the mask layer and the tunneling layer.
  • an etching solution is used to etch and remove the mask layer and the tunneling layer and the first doping layer on the mask layer, wherein the etching solution is a TMAH solution with a concentration of 1% to 2%.
  • the temperature of the liquid is 20 to 80°C. In order to speed up the etching speed, preferably, the temperature of the etching solution is 40-60°C.
  • a thermal oxidation method, a PECVD method or a hot wire CVD method is used to deposit and form the second passivation layer on the backside of the silicon substrate.
  • the second passivation layer covers all structures on the backside of the silicon substrate.
  • first electrode is conductively connected to the first doped layer
  • second electrode is conductively connected to the silicon substrate of the second doped region
  • the second passivation layer on the first doped region is etched, the first doped layer is etched to form a first hole, and the second passivation layer on the second doped region is etched, The surface of the silicon substrate is etched to form a second hole; a first electrode is formed in the first hole, and a second electrode is formed in the second hole.
  • the cell is annealed to reduce ohmic contact.
  • N 2 and/or O 2 gas is introduced for annealing, the annealing temperature is 750-1000° C., and the annealing time is 10-60 min.
  • the second doped region is provided with a textured region 11 , and the surface of the textured region 11 has a rough structure, It is formed by a texturing process, and the second electrode 80 is disposed on the texturing area 11 .
  • the texturing region 11 is formed on the second doped region to increase the contact area between the region and the second electrode 80 , thereby reducing the contact resistance.
  • the width of the texturing region 11 is 25% to 75% of the width of the first doping region.
  • the width of the texturing area 11 can be adjusted to maximize the untextured area, thereby reducing the contact resistance and improving the passivation effect and reflection effect, thereby maximizing the conversion efficiency.
  • the texturing width of the texturing area 11 is less than or equal to the width of the second electrode 80 . More preferably, the texturing width of the texturing area 11 is 25% to 100% of the width of the second electrode 80 .
  • the texturing width of the texturing zone refers to the particle size of the rough structure.
  • the preparation method of the high-efficiency solar cell in this embodiment includes the following steps:
  • the pretreatment includes cleaning the single crystal silicon wafer, removing the damaged layer, and texturing. Specifically, including:
  • the silicon wafer is cleaned with HF solution to remove the silicon dioxide layer on the surface of the silicon wafer and form Si-H passivation bonds with the dangling bonds on the surface of the silicon wafer, and finally, nitrogen is dried for use.
  • the silicon substrate is provided with a front surface and a back surface, and the back surface of the silicon substrate is provided with a first doping region and a second doping region, wherein the first doping region and the second doping region are alternately arranged .
  • a first passivation layer is deposited on the front surface of the silicon substrate by thermal oxidation, PECVD or hot wire CVD, and an antireflection layer is deposited on the first passivation layer by PECVD.
  • a mask layer is formed on the second doped region on the backside of the silicon substrate by using a photolithography mask method or a laser ablation method, and the mask layer has an interdigitated shape.
  • a SiO 2 layer is deposited on the backside of the silicon substrate by a laser ablation method, and then the SiO 2 on the first doped region is removed by a laser ablation method to form an interdigitated mask layer.
  • the material of the mask layer can also be silicon carbide, silicon nitride or ink.
  • the thickness of the mask layer is 20-300 nm. More preferably, the thickness of the mask layer is 20 nm, 50 nm, 150 nm or 300 nm.
  • the present invention uses an ultraviolet picosecond laser with a wavelength of 260-270 nm to remove SiO 2 on the first doped region.
  • the laser spot is circular with a diameter of 10-20 ⁇ m , the spot overlap is 5% to 15%.
  • the wavelength of the ultraviolet picosecond laser is 263-267 nm
  • the spot diameter is 13-17 ⁇ m
  • the spot overlap is 5%-10%.
  • the invention adopts ultraviolet picosecond laser to etch the SiO 2 layer, so that the SiO 2 on the first doped region can be removed in a very short time, so as to reduce the thermal damage to the battery caused by the laser heat.
  • the technical difficulty of using the ultraviolet picosecond laser to etch the SiO 2 layer in the present invention lies in that the laser energy, scanning speed, frequency and spot overlap need to be reasonably matched. Laser damage can be minimized only when laser energy, scanning speed, frequency, and spot overlap are effectively coordinated.
  • the overlapping degree of the light spots and the diameter of the light spots play the most important role in forming the interdigitated mask layer, especially the width and precision of the first doped region. If the overlap of the light spots is too small, the SiO 2 layer between the light spots cannot be removed cleanly, and the surface of the silicon substrate cannot be etched, or the pattern formed is incomplete; if the overlap of the light spots is too large, the energy of the overlapping area of the light spots is too high , the loss increases and affects the battery performance.
  • polishing the silicon substrate so that the surface of the first doped region on the backside of the silicon substrate is a planar structure
  • the present invention uses a polishing liquid to polish the first doped region of the silicon substrate, so that the surface of the first doped region on the backside of the silicon substrate has a planar structure.
  • the polishing liquid is KOH solution.
  • the above-mentioned polishing liquid cannot etch through the mask layer, thereby obtaining a solar cell backside structure with selective texture.
  • the present invention performs boron ion implantation on the amorphous silicon layer to form a first doped layer. After the ion implantation treatment, there will be ion bombardment to slow down the etching effect, that is, a layer of anti-organic alkali etching will be formed on the surface. Amorphous silicon layer.
  • the tunneling layer covers the entire back surface of the silicon substrate, that is, the tunneling layer covers the mask layer and the first doped region, and the first doped layer covers the tunneling layer.
  • an etching solution is used to etch and remove the mask layer and the tunneling layer and the first doping layer on the mask layer, wherein the etching solution is a TMAH solution with a concentration of 1% to 2%.
  • the temperature of the liquid is 20 to 80°C. In order to speed up the etching speed, preferably, the temperature of the etching solution is 40-60°C.
  • a thermal oxidation method, a PECVD method or a hot wire CVD method is used to deposit and form the second passivation layer on the backside of the silicon substrate.
  • the second passivation layer covers all structures on the backside of the silicon substrate.
  • first electrode is conductively connected to the first doped layer
  • second electrode is conductively connected to the silicon substrate of the second doped region
  • the second passivation layer on the first doped region is etched, the first doped layer is etched to form a first hole, and the second passivation layer on the second doped region is etched, The surface of the silicon substrate is etched to form a second hole; a first electrode is formed in the first hole, and a second electrode is formed in the second hole.
  • the cell is annealed to reduce ohmic contact.
  • N 2 and/or O 2 gas is introduced for annealing, the annealing temperature is 750-1000° C., and the annealing time is 10-60 min.
  • the second passivation layer disposed on the second doped region and the silicon substrate further includes a mask layer and a tunnel A through layer, the mask layer is arranged between the silicon base and the tunnel layer, wherein the first doped region and the tunnel layer on the second doped region are separated.
  • the mask layer and the tunnel layer on the second doped region are retained, which can reduce the second mask process and removal of the conventional process.
  • Masking process reduces production costs.
  • the material of the mask layer is selected from one or more of silicon dioxide, silicon carbide, silicon nitride and ink.
  • the mask layer and the tunnel layer are made of silicon dioxide, so that the mask layer and the tunnel layer can form a good double-layer passivation tunnel structure, improve the passivation effect of the texturing area, reduce compound to improve conversion efficiency.
  • the preparation method of the high-efficiency solar cell in this embodiment includes the following steps:
  • the pretreatment includes cleaning the single crystal silicon wafer, removing the damaged layer, and texturing. Specifically, including:
  • the silicon wafer is cleaned with HF solution to remove the silicon dioxide layer on the surface of the silicon wafer and form Si-H passivation bonds with the dangling bonds on the surface of the silicon wafer, and finally, nitrogen is dried for use.
  • the silicon base is provided with a front surface and a back surface, and the back surface of the silicon base is provided with a first doped region and a second doped region, wherein the first doped region and the second doped region are alternately arranged .
  • a first passivation layer is deposited on the front surface of the silicon substrate by thermal oxidation, PECVD or hot wire CVD, and an antireflection layer is deposited on the first passivation layer by PECVD.
  • a mask layer is formed on the second doped region on the backside of the silicon substrate by using a photolithography mask method or a laser ablation method, and the mask layer has an interdigitated shape.
  • a SiO 2 layer is deposited on the backside of the silicon substrate by a laser ablation method, and then the SiO 2 on the first doped region is removed by a laser ablation method to form an interdigitated mask layer.
  • the material of the mask layer can also be silicon carbide, silicon nitride or ink.
  • the thickness of the mask layer is 20-300 nm. More preferably, the thickness of the mask layer is 20 nm, 50 nm, 150 nm or 300 nm.
  • the present invention uses an ultraviolet picosecond laser with a wavelength of 260-270 nm to remove SiO 2 on the first doped region.
  • the laser spot is circular with a diameter of 10-20 ⁇ m , the spot overlap is 5% to 15%.
  • the wavelength of the ultraviolet picosecond laser is 263-267 nm
  • the spot diameter is 13-17 ⁇ m
  • the spot overlap is 5%-10%.
  • the invention adopts ultraviolet picosecond laser to etch the SiO 2 layer, so that the SiO 2 on the first doped region can be removed in a very short time, so as to reduce the thermal damage to the battery caused by the laser heat.
  • the technical difficulty of using the ultraviolet picosecond laser to etch the SiO 2 layer in the present invention lies in that the laser energy, scanning speed, frequency and spot overlap need to be reasonably matched. Laser damage can be minimized only when laser energy, scanning speed, frequency, and spot overlap are effectively coordinated.
  • the overlapping degree of the light spots and the diameter of the light spots play the most important role in forming the interdigitated mask layer, especially the width and precision of the first doped region. If the overlap of the light spots is too small, the SiO 2 layer between the light spots cannot be removed cleanly, and the surface of the silicon substrate cannot be etched, or the pattern formed is incomplete; if the overlap of the light spots is too large, the energy of the overlapping area of the light spots is too high , the loss increases and affects the battery performance.
  • polishing the silicon substrate so that the surface of the first doped region on the backside of the silicon substrate is a planar structure
  • the present invention uses a polishing liquid to polish the first doped region of the silicon substrate, so that the surface of the first doped region on the backside of the silicon substrate has a planar structure.
  • the polishing liquid is KOH solution.
  • the above-mentioned polishing liquid cannot etch through the mask layer, thereby obtaining a solar cell backside structure with selective texture.
  • the present invention performs boron ion implantation on the amorphous silicon layer to form a first doped layer. After the ion implantation treatment, there will be ion bombardment to slow down the etching effect, that is, a layer of anti-organic alkali etching will be formed on the surface.
  • the amorphous silicon layer as a mask structure, blocks the corrosion of the subsequent etching solution.
  • the tunneling layer covers the entire back surface of the silicon substrate, that is, the tunneling layer covers the mask layer and the first doped region, and the first doped layer covers the tunneling layer.
  • the first doped layer is annealed to make the doping uniform, so as to form a PN junction region.
  • N 2 and/or O 2 gas is introduced for annealing, the annealing temperature is 750-1000° C., and the annealing time is 10-60 min.
  • an etching solution is used to etch and remove the first doping layer on the second doping region, wherein the etching solution only etches the first doping layer, but does not etch the tunneling layer and the mask layer.
  • laser etching is used to remove the first doped layer on the second doped region.
  • a laser or photolithography process is used to etch the tunneling layer, and an isolation trench is formed between the first doped region and the second doped region, so as to separate the first doped region and the second doped region. separated by the tunneling layer.
  • a transparent conductive layer is deposited on the backside of the silicon substrate to enhance the current spreadability of the battery.
  • PVD or RPD method is used to deposit a transparent conductive layer on the back of the silicon substrate, wherein the material of the transparent conductive layer is selected from indium tin oxide, indium oxide, titanium-doped indium oxide, aluminum-doped zinc oxide, and tungsten-doped indium oxide One or more of them, and its thickness is 40-150nm.
  • a thermal oxidation method, a PECVD method or a hot wire CVD method is used to deposit and form the second passivation layer on the backside of the silicon substrate.
  • the second passivation layer covers all structures on the backside of the silicon substrate.
  • first electrode is conductively connected to the first doped layer
  • second electrode is conductively connected to the silicon substrate of the second doped region
  • the second passivation layer on the first doped region is etched, the first doped layer is etched to form a first hole, and the second passivation layer on the second doped region is etched, The surface of the silicon substrate is etched to form a second hole; a first electrode is formed in the first hole, and a second electrode is formed in the second hole.

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Abstract

本发明公开了一种高效太阳能电池及其制备方法，所述电池包括硅基体，所述硅基体设有正面和背面，所述硅基体的正面上设有第一钝化层，所述第一钝化层上设有减反层；所述硅基体的背面设有第一掺杂区、第二掺杂区和第二钝化层，所述第一掺杂区和第二掺杂区交替设置；所述第一掺杂区上设有隧穿层，所述隧穿层上设有第一掺杂层，所述第一掺杂层上设有第一电极，所述第二掺杂区上设有第二电极；所述第二钝化层覆盖在裸露出来的第二掺杂区上，并延伸到第一掺杂层上，以使第一电极和第二电极绝缘。本发明的电池结构简单，通过背面区域织构化设计及多层钝化结构设计，串联电阻低，钝化效果好，转化效率高。

Description

一种高效太阳能电池及其制备方法 技术领域
本发明涉及太阳能电池技术领域，尤其涉及一种高效太阳能电池及其制备方法。
 背景技术
晶体硅太阳能电池发展至今，在钝化结构上经历了背面无钝化(Al-BSF)、非接触钝化(PERC、PERT、PERL)和接触钝化(TOPCon、HJT)的演进，晶硅太阳能电池的光电转换效率逐渐接近其理论极限，目前以HBC电池结构及POLO-IBC结构转化效率最高。
背接触异质结(HBC)电池其结合背接触电池全面受光和HJT电池高质量钝化的优势，其实验效率达到26.63％，电池片效率的大幅度提高，一方面电池本身单瓦发电量提高，另一方面有利于降低整个产业链的LCOE。
中国专利公开号为CN107210331A的专利公开的一种HBC电池，其需要在P型半导体层与N型半导体层之间沉积绝缘层及基低保护层，以实现P/N之间的隔离，结构复杂，工序较多。
 技术问题
本发明所要解决的技术问题在于，提供一种高效太阳能电池，结构简单，通过背面区域织构化设计及多层钝化结构设计，串联电阻低，钝化效果好，转化效率高。
相应地，本发明还提供了一种高效太阳能电池的制备方法，工序少，质量可控，成本低。
 技术解决方案
为了解决上述技术问题，本发明提供了一种高效太阳能电池，包括硅基体，所述硅基体设有正面和背面，所述硅基体的正面上设有第一钝化层，所述第一钝化层上设有减反层；
所述硅基体的背面设有第一掺杂区、第二掺杂区和第二钝化层，所述第一掺杂区和第二掺杂区交替设置；
所述第一掺杂区上设有隧穿层，所述隧穿层上设有第一掺杂层，所述第一掺杂层上设有第一电极，所述第二掺杂区上设有第二电极；
所述第二钝化层覆盖在裸露出来的第二掺杂区上，并延伸到第一掺杂层上，以使第一电极和第二电极绝缘。
作为上述方案的改进，所述隧穿层从第一掺杂区延伸到第二掺杂区上，所述第二钝化层覆盖在裸露出来的隧穿层上，并延伸到第一掺杂层上，以使第一电极和第二电极绝缘；
其中，覆盖在第一掺杂区的隧穿层与第二钝化层形成复合层，所述第二电极设置在硅基体上并穿过第二掺杂区的复合层。
作为上述方案的改进，所述第二掺杂区设有制绒区，所述制绒区的表面具有粗糙结构，其通过制绒工艺形成，所述第二电极设置在制绒区上。
作为上述方案的改进，所述制绒区的宽度为第一掺杂区宽度的25％～75％；
作为上述方案的改进，所述制绒区的制绒宽度小于等于第二电极的宽度。
作为上述方案的改进，设于第二掺杂区上的第二钝化层与硅基体之间还具有掩膜层和隧穿层，所述掩膜层设于硅基体和隧穿层之间，其中，第一掺杂区和第二掺杂区上的隧穿层隔开；
所述掩膜层和隧穿层的材料均为二氧化硅，所述掩膜层和隧穿层形成双层钝化隧穿结构。
作为上述方案的改进，所述第一钝化层的材料选自二氧化硅、氮化硅、氧化镍、碘化亚铜、氧化铜、氧化亚铜、硫化铜、本征碳化硅、本征非晶硅中的一种或多种，其厚度为1～10nm；
所述减反层的材料选自氮化硅、氧化硅、氮氧化硅和氟化镁中的一种或几种，其厚度为20～150nm。
作为上述方案的改进，所述第一掺杂层为掺B多晶硅层或掺B非晶硅层或掺杂碳化硅层；所述隧穿层的材料选自SiO 2、Al 2O 3、本征非晶硅、本征碳化硅中的一种或多种；所述第二钝化层的材料为氮化硅。
作为上述方案的改进，所述第二掺杂区设有扩散层。
作为上述方案的改进，所述隧穿层的材料为SiO2和本征碳化硅。
作为上述方案的改进，所述本征碳化硅包括本征氢化碳化硅。
相应地，本发明还提供了一种高效太阳能电池的制备方法，包括：
一、对硅基体进行预处理，所述预处理包括对单晶硅片进行清洗、去除损伤层；
所述硅基体设有正面和背面，所述硅基体的背面设有第一掺杂区和第二掺杂区，其中，所述第一掺杂区和第二掺杂区交替设置；
二、在硅基体的正面依次形成第一钝化层和减反层；
三、在硅基体背面的第二掺杂区上形成掩膜层，所述掩膜层的材料选自二氧化硅、碳化硅、氮化硅和油墨中的一种或几种；
四、在硅基体背面的依次形成隧穿层和第一掺杂层；
五、除去掩膜层及掩膜层上的隧穿层和第一掺杂层，以将第二掺杂区裸露出来；
六、在硅基体背面沉积形成第二钝化层；
七、形成第一电极和第二电极，其中，第一电极与第一掺杂层导电连接，第二电极与第二掺杂区的硅基体导电连接。
作为上述方案的改进，当步骤(一)中的预处理还包括制绒工艺，则完成步骤(三)之后，还包括以下步骤：对硅基体进行抛光处理，以使硅基体背面的第一掺杂区的表面为平面结构。
作为上述方案的改进，步骤(五)中，只除第二掺杂区上的第一掺杂层，第二掺杂区上的掩膜层和隧穿层保留下来，并将第一掺杂区和第二掺杂区上的隧穿层隔开。
 有益效果
实施本发明，具有如下有益效果：
本发明的高效太阳能电池在硅基体的背面设置相互交替的第一掺杂区和第二掺杂区，并在第一掺杂区上依次设置隧穿层和第一掺杂层，最后在硅基体的背面覆盖一层第二钝化层，从而在电池的背面形成区域织构化设计及多层钝化结构设计，降低背面电极串联电阻，提升钝化效果，进一步提升电池的转化效率。
此外，本发明的隧穿层覆盖在硅基体的整个背面，其中，覆盖在第一掺杂区的隧穿层与第二钝化层形成复合层，有效减少表面复合，提升转化效率。
其次，本发明在第二掺杂区上形成具有粗糙结构的制绒区，增加第二电极与硅基体的接触面积，进一步降低串联电阻。
进一步地，本发明在硅基体背面形成隧穿层和第一掺杂层后，第二掺杂区上的掩膜层和隧穿层被保留下来，可以减少常规工艺的第二次掩膜工序及去掩膜工序，降低生产成本。
最后，本发明的电池结构简单，制作工艺少，质量可控，成本低。
 附图说明
图1是本发明实施例1的太阳能电池结构的示意图；
图2是本发明实施例2的太阳能电池结构的示意图；
图3是本发明实施例3的太阳能电池结构的示意图；
图4是本发明实施例4的太阳能电池结构的示意图。
 本发明的最佳实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明作进一步地详细描述。
实施例1
参见图1，本发明提供的一种高效太阳能电池，包括硅基体10，所述硅基体10设有正面和背面；所述硅基体10的正面上设有第一钝化层20，所述第一钝化层20上设有减反层30；所述硅基体的背面设有第一掺杂区、第二掺杂区和第二钝化层40，所述第一掺杂区和第二掺杂区交替设置；所述第一掺杂区上设有隧穿层50，所述隧穿层50上设有第一掺杂层60，所述第一掺杂层60上设有第一电极70，所述第二掺杂区上设有第二电极80；所述第二钝化层30覆盖在裸露出来的第二掺杂区上，并延伸到第一掺杂层60上，以使第一电极70和第二电极80绝缘。
所述硅基体10为N型硅片或P型硅片。
所述第一钝化层20的材料选自二氧化硅、氮化硅、氧化镍、碘化亚铜、氧化铜、氧化亚铜、硫化铜、本征碳化硅、本征非晶硅中的一种或多种，其厚度为1～10nm。
所述减反层30的材料选自氮化硅、氧化硅、氮氧化硅和氟化镁中的一种或几种。优选的，所述减反层30的厚度为20～150nm。
当所述硅基体10为N型硅片时，则所述隧穿层50的材料选自SiO 2、Al2O 3、本征非晶硅、本征碳化硅中的一种或多种。优选的，所述隧穿层的材料为SiO 2和本征碳化硅。优选的，所述本征碳化硅包括本征氢化碳化硅。
优选的，所述隧穿层50的厚度为1～20nm。更优的，所述隧穿层50的厚度为1～5nm。最优的，所述隧穿层50的厚度为1.4～2nm。
优选的，所述第一掺杂层60为掺B多晶硅层或掺B非晶硅层或掺杂碳化硅层。其中，当所述隧穿层50的材料选用本征非晶硅时，所述第一掺杂层60为掺B非晶硅层。优选的，所述掺杂碳化硅层包括掺杂氢化碳化硅。
优选的，所述第二钝化层30的材料为氮化硅，由于第二钝化层30覆盖在电池的背面，因此可减少外界光对电池背面的反射，增加电池背面光的入射，提升短路电流。
其中，所述第二掺杂区为通过扩散/离子注入/选择性沉积等方法形成的第二掺杂区。优选的，所述第二掺杂区设有扩散层，所述扩散层为P型扩散层或N型扩散层，其中P型扩散层为掺硼、铝、镓等扩散形成的扩散区域，N型扩散层为掺氮、磷、砷等扩散形成的扩散区域。
相应地，本实施例高效太阳能电池的制备方法，包括以下步骤：
一、对硅基体进行预处理；
所述预处理包括对单晶硅片进行清洗、去除损伤层。具体的，包括：
(1)RCA标准清洗，清除硅片表面的颗粒及有机物等；
(2)硅片清洗后再放入20％的NaOH碱溶液中，去除切片工艺中造成的表面损伤层；
(3)使用HCl对硅片表面进行酸洗，以中和残留在硅片表面的碱液、去除硅片表面残留的金属杂质；
(4)采用HF溶液清洗硅片，以去除硅片表面的二氧化硅层并与硅片表面的悬挂键形成Si-H钝化键，最后氮气烘干备用。
具体的，所述硅基体设有正面和背面，所述硅基体的背面设有第一掺杂区和第二掺杂区，其中，所述第一掺杂区和第二掺杂区交替设置。
具体的，当第二掺杂区设有扩散层时，当扩散层为P型扩散层，其具体制备工艺包括：方式一：通入含有硼、铝、镓等元素的源气体（如硼烷气体或携带三氯化硼或三溴化硼的运载气体）进行热扩散形成P型扩散层；方式二：沉积含硼、铝、镓等掺杂源（如硼硅玻璃）以及经热扩散形成P型扩散层；方式三：在扩散层上方制备铝电极，再经高温工艺形成掺杂铝的P型扩散层；方式四：旋涂含有硼、铝、镓等掺杂源（如三溴化硼）进行热扩散形成P型扩散层；方式五：注入含有硼、铝、镓等元素的离子，并经高温扩散形成P型扩散层。
当扩散层为N型扩散层，其具体制备工艺：方式一：通入含有氮、磷、砷等元素的源气体（如磷烷气体或携带三氯氧磷的运载气体）进行热扩散形成N型扩散层；方式二：沉积含氮、磷、砷等掺杂源（如磷硅玻璃）以及经热扩散形成N型扩散层；方式三：旋涂含有氮、磷、砷等掺杂源（如三氯氧磷）进行热扩散形成N型扩散层；方式四：注入含有氮、磷、砷等元素的离子，并经高温扩散形成N型扩散层。
二、在硅基体的正面依次形成第一钝化层和减反层；
具体的，采用PECVD沉积法在硅基体的正面沉积形成第一钝化层，在第一钝化层上沉积形成减反层。
三、在硅基体背面的第二掺杂区上形成掩膜层；
具体的，采用光刻掩膜方式或激光消融法在硅基体背面的第二掺杂区上形成掩膜层，所述掩膜层的形状为叉指状。
其中，采用激光消融法在硅基体背面沉积形成SiO 2层，再通过激光消融法去除第一掺杂区上的SiO 2，以形成叉指状的掩膜层。除了SiO 2外，所述掩膜层的材料还可以为碳化硅、氮化硅或油墨。
优选的，掩膜层的厚度为20～300nm。更优的，所述掩膜层的厚度为20nm、50nm、150nm或300nm。
为了能够形成叉指状的掩膜层，本发明采用波长为260～270nm的紫外皮秒激光来去除第一掺杂区上的SiO 2，优选的，激光光斑为圆形，直径为10～20μm，光斑重叠度为5％～15％。
更优的，所述紫外皮秒激光的波长为263～267nm，光斑直径为13～17μm，光斑重叠度为5％～10％。
本发明采用紫外皮秒激光来刻蚀SiO 2层，这样可以在很短的时间内将第一掺杂区上的SiO 2去除，以减少激光热量对电池的热损伤。
本发明采用紫外皮秒激光来刻蚀SiO 2层的技术难点在于：需要合理匹配激光能量、扫描速度、频率和光斑重叠度。只有激光能量、扫描速度、频率和光斑重叠度相互有效配合，才能让激光损伤减少到最低。其中，激光能量是通过激光功率来调节的，激光重合度＝(单个激光光斑直径-扫描速度/频率)/单个激光光斑直径；速度越快，激光光斑间重合度越小，硅片单位面积接收到激光能量越低，反之则相反；频率越高，激光光斑重合度越高，硅片单位面积接收到激光能量越低，反之则相反。因此，光斑的重叠度和光斑的直径对形成叉指状的掩膜层起着最重要的作用，尤其是对第一掺杂区的宽度和精度。若光斑的重叠度过小，则光斑间的SiO 2层去除不干净，不能刻蚀到硅基体的表面，或形成的图案不完整；若光斑的重叠度过大，光斑的重叠区域能量过高，损失增大，影响电池性能。
四、在硅基体背面的依次形成隧穿层和第一掺杂层；
具体的，本发明在非晶硅层进行硼离子注入，形成第一掺杂层，经过离子注入处理后，会有产生离子轰击减缓刻蚀效应，即在表面形成一层抗有机碱刻蚀的非晶硅层。
其中，所述隧穿层覆盖在硅基体的整个背面上，即所述隧穿层覆盖在掩膜层和第一掺杂区上，所述第一掺杂层覆盖在隧穿层上。
五、除去掩膜层及掩膜层上的隧穿层和第一掺杂层，以将第二掺杂区裸露出来；
具体的，采用刻蚀液来刻蚀除去掩膜层及掩膜层上的隧穿层和第一掺杂层，其中，所述刻蚀液为1％～2％浓度的TMAH溶液，刻蚀液的温度为20～80℃。为了加快刻蚀速度，优选的，所述刻蚀液的温度为40～60℃。
六、在硅基体背面沉积形成第二钝化层；
具体的，采用热氧化法、PECVD法或热丝CVD在硅基体背面沉积形成第二钝化层。其中，所述第二钝化层覆盖在硅基体背面的所有结构上。
七、形成第一电极和第二电极，其中，第一电极与第一掺杂层导电连接，第二电极与第二掺杂区的硅基体导电连接；
具体的，对第一掺杂区上的第二钝化层进行刻蚀，刻蚀至第一掺杂层形成第一孔洞，对第二掺杂区上的第二钝化层进行刻蚀，刻蚀至硅基体的表面，形成第二孔洞；在第一孔洞内形成第一电极，在第二孔洞内形成第二电极。
优选的，在形成第一电极和第二电极后，对电池进行退火，以实现更好的欧姆接触。优选的，通入N 2和/或O 2气体进行退火，退火温度为750～1000℃，退火时间10～60min。
实施例2
作为本发明的另一优选实施例，如图2所示，与实施例1不同的是，所述隧穿层50从第一掺杂区延伸到第二掺杂区上，所述第二钝化层40覆盖在裸露出来的隧穿层50上，并延伸到第一掺杂层60上，以使第一电极70和第二电极80绝缘。
本实施例中，隧穿层50覆盖在硅基体的整个背面，其中，覆盖在第一掺杂区的隧穿层50与第二钝化层40形成复合层，有效减少表面复合，提升转化效率。其中所述第二电极80设置在硅基体上并穿过第二掺杂区的复合层。
相应地，本实施例高效太阳能电池的制备方法，包括以下步骤：
一、对硅基体进行预处理；
所述预处理包括对单晶硅片进行清洗、去除损伤层。具体的，包括：
(1)RCA标准清洗，清除硅片表面的颗粒及有机物等；
(2)硅片清洗后再放入20％的NaOH碱溶液中，去除切片工艺中造成的表面损伤层；
(3)使用HCl对硅片表面进行酸洗，以中和残留在硅片表面的碱液、去除硅片表面残留的金属杂质；
(4)采用HF溶液清洗硅片，以去除硅片表面的二氧化硅层并与硅片表面的悬挂键形成Si-H钝化键，最后氮气烘干备用。
具体的，所述硅基体设有正面和背面，所述硅基体的背面设有第一掺杂区和第二掺杂区，其中，所述第一掺杂区和第二掺杂区交替设置。
二、在硅基体的正面依次形成第一钝化层和减反层；
具体的，采用PECVD沉积法在硅基体的正面沉积形成第一钝化层，在第一钝化层上沉积形成减反层。
三、在硅基体的背面形成隧穿层；
其中，所述隧穿层覆盖在硅基体的整个背面上，即所述隧穿层覆盖在第一掺杂区和第二掺杂区上。
四、在硅基体背面第二掺杂区的隧穿层上形成掩膜层；
具体的，采用光刻掩膜方式或激光消融法在硅基体背面第二掺杂区的隧穿层上形成掩膜层，所述掩膜层的形状为叉指状。
其中，采用激光消融法在硅基体背面沉积形成SiO 2层，再通过激光消融法去除第一掺杂区上的SiO 2，以形成叉指状的掩膜层。除了SiO 2外，所述掩膜层的材料还可以为碳化硅、氮化硅或油墨。
优选的，掩膜层的厚度为20～300nm。更优的，所述掩膜层的厚度为20nm、50nm、150nm或300nm。
为了能够形成叉指状的掩膜层，本发明采用波长为260～270nm的紫外皮秒激光来去除第一掺杂区上的SiO 2，优选的，激光光斑为圆形，直径为10～20μm，光斑重叠度为5％～15％。
更优的，所述紫外皮秒激光的波长为263～267nm，光斑直径为13～17μm，光斑重叠度为5％～10％。
本发明采用紫外皮秒激光来刻蚀SiO 2层，这样可以在很短的时间内将第一掺杂区上的SiO 2去除，以减少激光热量对电池的热损伤。
本发明采用紫外皮秒激光来刻蚀SiO 2层的技术难点在于：需要合理匹配激光能量、扫描速度、频率和光斑重叠度。只有激光能量、扫描速度、频率和光斑重叠度相互有效配合，才能让激光损伤减少到最低。其中，激光能量是通过激光功率来调节的，激光重合度＝(单个激光光斑直径-扫描速度/频率)/单个激光光斑直径；速度越快，激光光斑间重合度越小，硅片单位面积接收到激光能量越低，反之则相反；频率越高，激光光斑重合度越高，硅片单位面积接收到激光能量越低，反之则相反。因此，光斑的重叠度和光斑的直径对形成叉指状的掩膜层起着最重要的作用，尤其是对第一掺杂区的宽度和精度。若光斑的重叠度过小，则光斑间的SiO 2层去除不干净，不能刻蚀到硅基体的表面，或形成的图案不完整；若光斑的重叠度过大，光斑的重叠区域能量过高，损失增大，影响电池性能。
五、在硅基体的背面形成第一掺杂层；
具体的，本发明在非晶硅层进行硼离子注入，形成第一掺杂层，经过离子注入处理后，会有产生离子轰击减缓刻蚀效应，即在表面形成一层抗有机碱刻蚀的非晶硅层。
其中，所述第一掺杂层覆盖在硅基体的整个背面上，即所述第一掺杂层覆盖在掩膜层和隧穿层上。
六、除去掩膜层及掩膜层上的第一掺杂层，以将第二掺杂区裸露出来；
具体的，采用刻蚀液来刻蚀除去掩膜层及掩膜层上的隧穿层和第一掺杂层，其中，所述刻蚀液为1％～2％浓度的TMAH溶液，刻蚀液的温度为20～80℃。为了加快刻蚀速度，优选的，所述刻蚀液的温度为40～60℃。
七、在硅基体背面沉积形成第二钝化层；
具体的，采用热氧化法、PECVD法或热丝CVD在硅基体背面沉积形成第二钝化层。其中，所述第二钝化层覆盖在硅基体背面的所有结构上。
八、形成第一电极和第二电极，其中，第一电极与第一掺杂层导电连接，第二电极与第二掺杂区的硅基体导电连接；
具体的，对第一掺杂区上的第二钝化层进行刻蚀，刻蚀至第一掺杂层形成第一孔洞，对第二掺杂区上的第二钝化层进行刻蚀，刻蚀至硅基体的表面，形成第二孔洞；在第一孔洞内形成第一电极，在第二孔洞内形成第二电极。
优选的，在形成第一电极和第二电极后，对电池进行退火，以减少欧姆接触。优选的，通入N 2和/或O 2气体进行退火，退火温度为750～1000℃，退火时间10～60min。
实施例3
作为本发明的另一优选实施例，如图3所示，与实施例1不同的是，所述第二掺杂区设有制绒区11，所述制绒区11的表面具有粗糙结构，其通过制绒工艺形成，所述第二电极80设置在制绒区11上。本实施例通过在第二掺杂区上形成制绒区11以增加该区域与第二电极80的接触面积，从而减小接触电阻。
优选的，所述制绒区11的宽度为第一掺杂区宽度的25％～75％。本实施例可通过调整制绒区11的宽度，以使未制绒的区域尽量多，在减少接触电阻的同时，提升钝化效果及反射效果，从而最大程度提升转化效率。
优选的，所述制绒区11的制绒宽度小于等于第二电极80的宽度。更优的，所述制绒区11的制绒宽度为第二电极80宽度的25％～100％。其中，制绒区的制绒宽度是指粗糙结构的粒径大小。
相应地，本实施例高效太阳能电池的制备方法，包括以下步骤：
一、对硅基体进行预处理；
所述预处理包括对单晶硅片进行清洗、去除损伤层、制绒。具体的，包括：
(1)RCA标准清洗，清除硅片表面的颗粒及有机物等；
(2)硅片清洗后再放入20％的NaOH碱溶液中，去除切片工艺中造成的表面损伤层；
(3)浸入NaOH、NaSiO、IPA混合溶液中进行制绒；
(4)使用HCl对制绒后的硅片表面进行酸洗，以中和残留在硅片表面的碱液、去除硅片表面残留的金属杂质；
(5)采用HF溶液清洗硅片，以去除硅片表面的二氧化硅层并与硅片表面的悬挂键形成Si-H钝化键，最后氮气烘干备用。
具体的，所述硅基体设有正面和背面，所述硅基体的背面设有第一掺杂区和第二掺杂区，其中，所述第一掺杂区和第二掺杂区交替设置。
二、在硅基体的正面依次形成第一钝化层和减反层；
具体的，采用热氧化法、PECVD法或热丝CVD在硅基体的正面沉积形成第一钝化层，采用PECVD法在第一钝化层上沉积形成减反层。
三、在硅基体背面的第二掺杂区上形成掩膜层；
具体的，采用光刻掩膜方式或激光消融法在硅基体背面的第二掺杂区上形成掩膜层，所述掩膜层的形状为叉指状。
其中，采用激光消融法在硅基体背面沉积形成SiO 2层，再通过激光消融法去除第一掺杂区上的SiO 2，以形成叉指状的掩膜层。除了SiO 2外，所述掩膜层的材料还可以为碳化硅、氮化硅或油墨。
优选的，掩膜层的厚度为20～300nm。更优的，所述掩膜层的厚度为20nm、50nm、150nm或300nm。
为了能够形成叉指状的掩膜层，本发明采用波长为260～270nm的紫外皮秒激光来去除第一掺杂区上的SiO 2，优选的，激光光斑为圆形，直径为10～20μm，光斑重叠度为5％～15％。
更优的，所述紫外皮秒激光的波长为263～267nm，光斑直径为13～17μm，光斑重叠度为5％～10％。
本发明采用紫外皮秒激光来刻蚀SiO 2层，这样可以在很短的时间内将第一掺杂区上的SiO2去除，以减少激光热量对电池的热损伤。
本发明采用紫外皮秒激光来刻蚀SiO 2层的技术难点在于：需要合理匹配激光能量、扫描速度、频率和光斑重叠度。只有激光能量、扫描速度、频率和光斑重叠度相互有效配合，才能让激光损伤减少到最低。其中，激光能量是通过激光功率来调节的，激光重合度＝(单个激光光斑直径-扫描速度/频率)/单个激光光斑直径；速度越快，激光光斑间重合度越小，硅片单位面积接收到激光能量越低，反之则相反；频率越高，激光光斑重合度越高，硅片单位面积接收到激光能量越低，反之则相反。因此，光斑的重叠度和光斑的直径对形成叉指状的掩膜层起着最重要的作用，尤其是对第一掺杂区的宽度和精度。若光斑的重叠度过小，则光斑间的SiO 2层去除不干净，不能刻蚀到硅基体的表面，或形成的图案不完整；若光斑的重叠度过大，光斑的重叠区域能量过高，损失增大，影响电池性能。
四、对硅基体进行抛光处理，以使硅基体背面的第一掺杂区的表面为平面结构；
具体的，本发明采用抛光液来对硅基体的第一掺杂区进行抛光，以使硅基体背面的第一掺杂区的表面为平面结构。
优选的，所述抛光液为KOH溶液。在抛光过程中，上述抛光液不能蚀穿掩膜层，从而得到具有选择性织构化的太阳能电池背面结构。
五、在硅基体背面上依次形成隧穿层和第一掺杂层；
具体的，本发明在非晶硅层进行硼离子注入，形成第一掺杂层，经过离子注入处理后，会有产生离子轰击减缓刻蚀效应，即在表面形成一层抗有机碱刻蚀的非晶硅层。
其中，所述隧穿层覆盖在硅基体的整个背面上，即所述隧穿层覆盖在掩膜层和第一掺杂区上，所述第一掺杂层覆盖在隧穿层上。
六、除去掩膜层及掩膜层上的隧穿层和第一掺杂层，以将第二掺杂区裸露出来；
具体的，采用刻蚀液来刻蚀除去掩膜层及掩膜层上的隧穿层和第一掺杂层，其中，所述刻蚀液为1％～2％浓度的TMAH溶液，刻蚀液的温度为20～80℃。为了加快刻蚀速度，优选的，所述刻蚀液的温度为40～60℃。
七、在硅基体背面沉积形成第二钝化层；
具体的，采用热氧化法、PECVD法或热丝CVD在硅基体背面沉积形成第二钝化层。其中，所述第二钝化层覆盖在硅基体背面的所有结构上。
八、形成第一电极和第二电极，其中，第一电极与第一掺杂层导电连接，第二电极与第二掺杂区的硅基体导电连接；
具体的，对第一掺杂区上的第二钝化层进行刻蚀，刻蚀至第一掺杂层形成第一孔洞，对第二掺杂区上的第二钝化层进行刻蚀，刻蚀至硅基体的表面，形成第二孔洞；在第一孔洞内形成第一电极，在第二孔洞内形成第二电极。
优选的，在形成第一电极和第二电极后，对电池进行退火，以减少欧姆接触。优选的，通入N 2和/或O 2气体进行退火，退火温度为750～1000℃，退火时间10～60min。
实施例4
作为本发明的另一优选实施例，如图4所示，与实施例3不同的是，设于第二掺杂区上的第二钝化层与硅基体之间还具有掩膜层和隧穿层，所述掩膜层设于硅基体和隧穿层之间，其中，第一掺杂区和第二掺杂区上的隧穿层隔开。
本实施例在硅基体背面形成隧穿层和第一掺杂层后，第二掺杂区上的掩膜层和隧穿层被保留下来，可以减少常规工艺的第二次掩膜工序及去掩膜工序，降低生产成本。
所述掩膜层的材料选自二氧化硅、碳化硅、氮化硅和油墨中的一种或几种。
优选的，所述掩膜层和隧穿层的材料均为二氧化硅，这样掩膜层和隧穿层可以形成良好的双层钝化隧穿结构，提升制绒区的钝化效果，减少复合，提升转化效率。
相应地，本实施例高效太阳能电池的制备方法，包括以下步骤：
一、对硅基体进行预处理；
所述预处理包括对单晶硅片进行清洗、去除损伤层、制绒。具体的，包括：
(1)RCA标准清洗，清除硅片表面的颗粒及有机物等；
(2)硅片清洗后再放入20％的NaOH碱溶液中，去除切片工艺中造成的表面损伤层；
(3)浸入NaOH、NaSiO、IPA混合溶液中进行制绒；
(4)使用HCl对制绒后的硅片表面进行酸洗，以中和残留在硅片表面的碱液、去除硅片表面残留的金属杂质；
(5)采用HF溶液清洗硅片，以去除硅片表面的二氧化硅层并与硅片表面的悬挂键形成Si-H钝化键，最后氮气烘干备用。
具体的，所述硅基体设有正面和背面，所述硅基体的背面设有第一掺杂区和第二掺杂区，其中，所述第一掺杂区和第二掺杂区交替设置。
二、在硅基体的正面依次形成第一钝化层和减反层；
具体的，采用热氧化法、PECVD法或热丝CVD在硅基体的正面沉积形成第一钝化层，采用PECVD法在第一钝化层上沉积形成减反层。
三、在硅基体背面的第二掺杂区上形成掩膜层；
具体的，采用光刻掩膜方式或激光消融法在硅基体背面的第二掺杂区上形成掩膜层，所述掩膜层的形状为叉指状。
其中，采用激光消融法在硅基体背面沉积形成SiO 2层，再通过激光消融法去除第一掺杂区上的SiO 2，以形成叉指状的掩膜层。除了SiO 2外，所述掩膜层的材料还可以为碳化硅、氮化硅或油墨。
优选的，掩膜层的厚度为20～300nm。更优的，所述掩膜层的厚度为20nm、50nm、150nm或300nm。
为了能够形成叉指状的掩膜层，本发明采用波长为260～270nm的紫外皮秒激光来去除第一掺杂区上的SiO 2，优选的，激光光斑为圆形，直径为10～20μm，光斑重叠度为5％～15％。
更优的，所述紫外皮秒激光的波长为263～267nm，光斑直径为13～17μm，光斑重叠度为5％～10％。
本发明采用紫外皮秒激光来刻蚀SiO 2层，这样可以在很短的时间内将第一掺杂区上的SiO 2去除，以减少激光热量对电池的热损伤。
本发明采用紫外皮秒激光来刻蚀SiO 2层的技术难点在于：需要合理匹配激光能量、扫描速度、频率和光斑重叠度。只有激光能量、扫描速度、频率和光斑重叠度相互有效配合，才能让激光损伤减少到最低。其中，激光能量是通过激光功率来调节的，激光重合度＝(单个激光光斑直径-扫描速度/频率)/单个激光光斑直径；速度越快，激光光斑间重合度越小，硅片单位面积接收到激光能量越低，反之则相反；频率越高，激光光斑重合度越高，硅片单位面积接收到激光能量越低，反之则相反。因此，光斑的重叠度和光斑的直径对形成叉指状的掩膜层起着最重要的作用，尤其是对第一掺杂区的宽度和精度。若光斑的重叠度过小，则光斑间的SiO 2层去除不干净，不能刻蚀到硅基体的表面，或形成的图案不完整；若光斑的重叠度过大，光斑的重叠区域能量过高，损失增大，影响电池性能。
四、对硅基体进行抛光处理，以使硅基体背面的第一掺杂区的表面为平面结构；
具体的，本发明采用抛光液来对硅基体的第一掺杂区进行抛光，以使硅基体背面的第一掺杂区的表面为平面结构。
优选的，所述抛光液为KOH溶液。在抛光过程中，上述抛光液不能蚀穿掩膜层，从而得到具有选择性织构化的太阳能电池背面结构。
五、在硅基体背面依次形成隧穿层和第一掺杂层；
具体的，本发明在非晶硅层进行硼离子注入，形成第一掺杂层，经过离子注入处理后，会有产生离子轰击减缓刻蚀效应，即在表面形成一层抗有机碱刻蚀的非晶硅层，作为掩膜结构，阻挡后续腐蚀液的腐蚀。
其中，所述隧穿层覆盖在硅基体的整个背面上，即所述隧穿层覆盖在掩膜层和第一掺杂区上，所述第一掺杂层覆盖在隧穿层上。
优选的，在形成第一掺杂层后，对第一掺杂层进行退火，使得掺杂均匀，以形成PN结区。优选的，通入N 2和/或O 2气体进行退火，退火温度为750～1000℃，退火时间10～60min。
六、除去第二掺杂区上的第一掺杂层，并将第一掺杂区和第二掺杂区上的隧穿层隔开；
具体的，采用刻蚀液来刻蚀除去第二掺杂区上的第一掺杂层，其中，所述刻蚀液只腐蚀第一掺杂层，并不腐蚀隧穿层和掩膜层。
或者，采用激光刻蚀除去第二掺杂区上的第一掺杂层。
具体的，采用激光或光刻工艺，对隧穿层进行刻蚀，在第一掺杂区和第二掺杂区之间形成隔离槽，以将第一掺杂区和第二掺杂区上的隧穿层隔开。
需要说明的是，在隔开第一掺杂区和第二掺杂区上的隧穿层之前，在硅基体的背面沉积形成透明导电层，以增强电池的电流扩展性。
具体的，采用PVD或RPD法在硅基体背面沉积形成透明导电层，其中，所述透明导电层的材料选自氧化铟锡、氧化铟、掺钛氧化铟、掺铝氧化锌、掺钨氧化铟中的一种或几种，其厚度为40～150nm。
七、在硅基体背面沉积形成第二钝化层；
具体的，采用热氧化法、PECVD法或热丝CVD在硅基体背面沉积形成第二钝化层。其中，所述第二钝化层覆盖在硅基体背面的所有结构上。
八、形成第一电极和第二电极，其中，第一电极与第一掺杂层导电连接，第二电极与第二掺杂区的硅基体导电连接；
具体的，对第一掺杂区上的第二钝化层进行刻蚀，刻蚀至第一掺杂层形成第一孔洞，对第二掺杂区上的第二钝化层进行刻蚀，刻蚀至硅基体的表面，形成第二孔洞；在第一孔洞内形成第一电极，在第二孔洞内形成第二电极。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，因此依本发明权利要求所作的等同变化，仍属本发明所涵盖的范围。

Claims (15)

  1. 一种高效太阳能电池，其特征在于，包括硅基体，所述硅基体设有正面和背面，所述硅基体的正面上设有第一钝化层，所述第一钝化层上设有减反层；
    所述硅基体的背面设有第一掺杂区、第二掺杂区和第二钝化层，所述第一掺杂区和第二掺杂区交替设置；
    所述第一掺杂区上设有隧穿层，所述隧穿层上设有第一掺杂层，所述第一掺杂层上设有第一电极，所述第二掺杂区上设有第二电极；
    所述第二钝化层覆盖在裸露出来的第二掺杂区上，并延伸到第一掺杂层上，以使第一电极和第二电极绝缘。
  2. 如权利要求1所述的高效太阳能电池，其特征在于，所述隧穿层从第一掺杂区延伸到第二掺杂区上，所述第二钝化层覆盖在裸露出来的隧穿层上，并延伸到第一掺杂层上，以使第一电极和第二电极绝缘；
    其中，覆盖在第一掺杂区的隧穿层与第二钝化层形成复合层，所述第二电极设置在硅基体上并穿过第二掺杂区的复合层。
  3. 如权利要求1所述的高效太阳能电池，其特征在于，所述第二掺杂区设有制绒区，所述制绒区的表面具有粗糙结构，其通过制绒工艺形成，所述第二电极设置在制绒区上。
  4. 如权利要求3所述的高效太阳能电池，其特征在于，所述制绒区的宽度为第一掺杂区宽度的25％～75％。
  5. 如权利要求3所述的高效太阳能电池，其特征在于，所述制绒区的制绒宽度小于等于第二电极的宽度。
  6. 如权利要求3所述的高效太阳能电池，其特征在于，设于第二掺杂区上的第二钝化层与硅基体之间还具有掩膜层和隧穿层，所述掩膜层设于硅基体和隧穿层之间，其中，第一掺杂区和第二掺杂区上的隧穿层隔开；
    所述掩膜层和隧穿层的材料均为二氧化硅，所述掩膜层和隧穿层形成双层钝化隧穿结构。
  7. 如权利要求1所述的高效太阳能电池，其特征在于，所述第一钝化层的材料选自二氧化硅、氮化硅、氧化镍、碘化亚铜、氧化铜、氧化亚铜、硫化铜、本征碳化硅、本征非晶硅中的一种或多种，其厚度为1～10nm；
    所述减反层的材料选自氮化硅、氧化硅、氮氧化硅和氟化镁中的一种或几种，其厚度为20～150nm。
  8. 如权利要求7所述的高效太阳能电池，其特征在于，所述第一掺杂层为掺B多晶硅层或掺B非晶硅层或掺杂碳化硅层；所述隧穿层的材料选自SiO 2、Al 2O 3、本征非晶硅、本征碳化硅中的一种或多种；所述第二钝化层的材料为氮化硅。
  9. 如权利要求1所述的高效太阳能电池，其特征在于，所述第二掺杂区设有扩散层。
  10. 如权利要求8所述的高效太阳能电池，其特征在于，所述掺杂碳化硅层包括掺杂氢化碳化硅。
  11. 如权利要求8所述的高效太阳能电池，其特征在于，所述隧穿层的材料为SiO 2和本征碳化硅。
  12. 如权利要求8所述的高效太阳能电池，其特征在于，所述本征碳化硅包括本征氢化碳化硅。
  13. 一种高效太阳能电池的制备方法，其特征在于，包括：
    一、对硅基体进行预处理，所述预处理包括对单晶硅片进行清洗、去除损伤层；
    所述硅基体设有正面和背面，所述硅基体的背面设有第一掺杂区和第二掺杂区，其中，所述第一掺杂区和第二掺杂区交替设置；
    二、在硅基体的正面依次形成第一钝化层和减反层；
    三、在硅基体背面的第二掺杂区上形成掩膜层，所述掩膜层的材料选自二氧化硅、碳化硅、氮化硅和油墨中的一种或几种；
    四、在硅基体背面的依次形成隧穿层和第一掺杂层；
    五、除去掩膜层及掩膜层上的隧穿层和第一掺杂层，以将第二掺杂区裸露出来；
    六、在硅基体背面沉积形成第二钝化层；
    七、形成第一电极和第二电极，其中，第一电极与第一掺杂层导电连接，第二电极与第二掺杂区的硅基体导电连接。
  14. 如权利要求13所述的高效太阳能电池的制备方法，其特征在于，当步骤(一)中的预处理还包括制绒工艺，则完成步骤(三)之后，还包括以下步骤：对硅基体进行抛光处理，以使硅基体背面的第一掺杂区的表面为平面结构。
  15. 如权利要求14所述的高效太阳能电池的制备方法，其特征在于，步骤(五)中，只除第二掺杂区上的第一掺杂层，第二掺杂区上的掩膜层和隧穿层保留下来，并将第一掺杂区和第二掺杂区上的隧穿层隔开。
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