WO2022099599A1 - Led器件、led结构及其制备方法 - Google Patents

Led器件、led结构及其制备方法 Download PDF

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WO2022099599A1
WO2022099599A1 PCT/CN2020/128629 CN2020128629W WO2022099599A1 WO 2022099599 A1 WO2022099599 A1 WO 2022099599A1 CN 2020128629 W CN2020128629 W CN 2020128629W WO 2022099599 A1 WO2022099599 A1 WO 2022099599A1
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layer
insertion layer
source
led structure
potential well
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PCT/CN2020/128629
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English (en)
French (fr)
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刘慰华
程凯
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苏州晶湛半导体有限公司
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Priority to CN202080106669.2A priority Critical patent/CN116420238A/zh
Priority to US18/250,531 priority patent/US20240014344A1/en
Priority to PCT/CN2020/128629 priority patent/WO2022099599A1/zh
Publication of WO2022099599A1 publication Critical patent/WO2022099599A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H01L33/325—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen characterised by the doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer

Definitions

  • the present disclosure relates to the technical field of semiconductors, and in particular, to an LED device, an LED structure, and a preparation method of the LED structure.
  • LED Light Emitting Diode
  • a light-emitting diode includes a P-type semiconductor layer, an active layer, and an N-type semiconductor layer that are stacked.
  • the N-type semiconductor is used for supplying electrons
  • the P-type semiconductor is used for supplying holes.
  • the electrons provided by the N-type semiconductor and the holes provided by the P-type semiconductor can recombine in the active layer, thereby generating light.
  • the photoelectric performance of the light emitting diode is easily degraded.
  • the purpose of the present disclosure is to provide an LED device, an LED structure and a preparation method of the LED structure, which can prevent the photoelectric performance of the light emitting diode from being reduced.
  • a method for fabricating an LED structure comprising:
  • An active layer is grown on the first conductive type semiconductor layer, the active layer includes a potential well layer, an insertion layer, and a barrier layer that are stacked in layers, and the insertion layer includes a first insertion layer and a second insertion layer that are stacked in layers An insertion layer, a quantum confinement Stark effect is generated between the first insertion layer and the potential well layer;
  • the materials of the potential well layer, the first insertion layer and the potential barrier layer are all III-V group semiconductor materials,
  • the material of the second insertion layer includes Si-N bonds for repairing the V-shaped defects of the first insertion layer;
  • a second conductivity type semiconductor layer is grown on the active layer, and the first conductivity type semiconductor layer is opposite in conductivity type to the second conductivity type semiconductor layer.
  • the material of the potential well layer is InGaN
  • the material of the barrier layer is GaN
  • the material of the first insertion layer is AlGaN or AlInGaN
  • the material of the second insertion layer is selected from SiN, Si-doped At least one of doped AlGaN, Si-doped GaN, and Si-doped AlN.
  • the Si-N bond in the second intercalation layer is achieved by feeding a silicon source into the reaction chamber, the silicon source including silane and/or disilane.
  • the growth method of the insertion layer includes:
  • Al source, Ga source, Si source, ammonia gas and carrier gas are passed into the reaction chamber to grow the second insertion layer, and the material of the second insertion layer is Si-doped AlGaN.
  • the method for growing the insertion layer includes:
  • the Al source and Ga source are turned off, and Si source, ammonia gas and carrier gas are passed into the reaction chamber at the same time, and the second insertion layer is grown, and the material of the second insertion layer is SiN.
  • the growth method of the insertion layer includes:
  • the Al source is turned off, while Ga source, Si source, ammonia gas and carrier gas are passed into the reaction chamber to grow the second insertion layer, and the material of the second insertion layer is Si-doped GaN.
  • the growth method of the insertion layer includes:
  • the Ga source is turned off, while Al source, Si source, ammonia gas and carrier gas are passed into the reaction chamber to grow the second insertion layer, and the material of the second insertion layer is Si-doped AlN.
  • the ratio of the molar rate of the Si source to the molar rate of the Ga source is 1/10 7 -1/10 5 .
  • a ratio of a growth time of the second insertion layer to a growth time of the insertion layer is 1/100-1/5.
  • an LED structure comprising:
  • the active layer includes a stacked potential well layer, an insertion layer and a potential barrier layer, the insertion layer includes a stacked first insertion layer and a second insertion layer, the first insertion layer and the potential well layer are The quantum confinement Stark effect is generated between the two layers; the materials of the potential well layer, the first insertion layer and the barrier layer are all III-V semiconductor materials, and the material of the second insertion layer contains Si-N bonds, which are used for Repair the V-shaped defect of the first insertion layer.
  • the material of the potential well layer is InGaN
  • the material of the barrier layer is GaN
  • the material of the first insertion layer is AlGaN or AlInGaN
  • the material of the second insertion layer is selected from SiN, Si-doped At least one of doped AlGaN, Si-doped GaN, and Si-doped AlN.
  • the insertion layers include a plurality of the first insertion layers and a plurality of the second insertion layers, and the first insertion layers and the second insertion layers are alternately distributed.
  • an LED device including the above-mentioned LED structure.
  • the active layer includes a potential well layer, an insertion layer and a potential barrier layer arranged in a stack
  • the insertion layer includes a first insertion layer and a second insertion layer arranged in a stack
  • the first insertion layer is arranged in layers.
  • the quantum confinement Stark effect is generated between the first insertion layer and the potential well layer, and the Si-N bond in the second insertion layer material can repair the first insertion layer material and the potential well layer.
  • a V-shaped defect in the insertion layer can solve the problem of reducing the photoelectric performance of the light emitting diode caused by the lattice mismatch between the first insertion layer and the potential well layer, and prevent the photoelectric performance of the light emitting diode from being reduced.
  • FIG. 1 is a schematic diagram of a light-emitting diode in the related art
  • FIG. 2 is a flowchart of a method for fabricating an LED structure according to Embodiment 1 of the present disclosure
  • FIG. 3 is a schematic diagram of an LED structure according to Embodiment 1 of the present disclosure.
  • FIG. 4 is another schematic diagram of the LED structure according to the first embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of an insertion layer in the LED structure according to Embodiment 1 of the present disclosure.
  • FIG. 6 is a schematic diagram of an insertion layer in the LED structure according to the fifth embodiment of the present disclosure.
  • Substrate 1. Buffer layer; 3. First conductivity type semiconductor layer; 4. Active layer; 401, Potential well layer; 402, Insertion layer; 4021, First insertion layer; The second insertion layer; 403, the barrier layer; 5, the second conductive type semiconductor layer.
  • a light emitting diode includes a first conductive type semiconductor layer 3 , an active layer 4 and a second conductive type semiconductor layer 5 that are stacked.
  • the active layer 4 includes a well layer 401 and a barrier layer 403 .
  • the material of the well layer 401 is InGaN
  • the material of the barrier layer 403 is GaN.
  • the content of the In composition in the well layer 401 is often increased, and AlGaN is used to form the insertion layer 402 between the well layer 401 and the barrier layer 403 .
  • a quantum confinement Stark effect is generated between the insertion layer 402 and the potential well layer 401 to narrow the forbidden band width of the potential well, so as to increase the emission wavelength.
  • the lattice constant of the 100 crystallographic direction of the material of the potential well layer 401 is larger, the lattice constant of the 100 crystallographic direction of the material of the insertion layer 402 is smaller, and there is a larger crystallinity between the material of the insertion layer 402 and the material of the potential well layer 401
  • the lattice mismatch problem results in poor lattice quality of the epitaxially grown insertion layer 402 material and V-shaped defects.
  • the V-type defects in the material of the insertion layer 402 will enlarge and form pits or holes, causing the In component in the material of the potential well layer 401 to decompose and escape during the subsequent high temperature epitaxial growth process , which affects the uniformity of the In composition, and at the same time reduces the content of the In composition in the material of the potential well layer 401, thereby reducing the photoelectric performance of the light emitting diode (LED).
  • LED light emitting diode
  • FIG. 2 is a flowchart of a method for fabricating an LED structure according to Embodiment 1 of the present disclosure.
  • 3 and 4 are schematic diagrams of an LED structure according to Embodiment 1 of the present disclosure.
  • FIG. 5 is a schematic diagram of an insertion layer in the LED structure according to the first embodiment of the present disclosure.
  • the manufacturing method of the LED structure of the first embodiment may include steps S100 to S120, wherein:
  • Step S100 growing a first conductive type semiconductor layer on a substrate.
  • Step S110 growing an active layer on the first conductive type semiconductor layer, the active layer includes a potential well layer, an insertion layer and a potential barrier layer arranged in a stack, and the insertion layer includes a first insertion layer and a second insertion layer arranged in a stack, A quantum confinement Stark effect is generated between the first insertion layer and the potential well layer; the materials of the potential well layer, the first insertion layer and the potential barrier layer are all III-V group semiconductor materials, and the material of the second insertion layer contains Si- N-bond for repairing V-shaped defects in the first insertion layer.
  • Step S120 growing a second conductive type semiconductor layer on the active layer, where the conductivity types of the first conductive type semiconductor layer and the second conductive type semiconductor layer are opposite.
  • the active layer 4 includes a potential well layer 401 , an insertion layer 402 and a barrier layer 403 arranged in layers, and the insertion layer 402 includes a first layer arranged in layers.
  • the insertion layer 4021 and the second insertion layer 4022, the quantum confinement Stark effect is generated between the first insertion layer 4021 and the potential well layer 401, and the Si-N bond in the material of the second insertion layer 4022 can be repaired due to the first insertion layer 4021.
  • the V-type defect in the first insertion layer 4021 formed by the lattice mismatch between the material and the material of the potential well layer 401 can solve the problem caused by the lattice mismatch between the first insertion layer 4021 and the potential well layer 401 in the related art
  • the photoelectric performance of the light-emitting diode is reduced, and the photoelectric performance of the light-emitting diode is prevented from being reduced.
  • step S100 a first conductive type semiconductor layer is grown on a substrate.
  • the substrate 1 may be one of a sapphire substrate 1 , a silicon carbide substrate 1 and a silicon substrate 1 , which is not limited in this embodiment.
  • the buffer layer 2 may also be formed on the substrate 1 in this embodiment.
  • the first conductive type semiconductor layer 3 may be grown on the buffer layer 2 .
  • the first conductive type semiconductor layer 3 can be formed in a reaction chamber, and its forming process can include: atomic layer deposition (ALD, Atomic layer deposition), or chemical vapor deposition (CVD, Chemical Vapor Deposition), or molecular Beam Epitaxy (MBE, Molecular Beam Epitaxy), or Plasma Enhanced Chemical Vapor Deposition (PECVD, Plasma Enhanced Chemical Vapor Deposition), or Low Pressure Chemical Vapor Deposition (LPCVD, Low Pressure Chemical Vapor Deposition), or Metal Organic Compounds chemical vapor deposition, or a combination thereof.
  • ALD Atomic layer deposition
  • CVD chemical vapor deposition
  • MBE molecular Beam Epitaxy
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • LPCVD Low Pressure Chemical Vapor Deposition
  • Metal Organic Compounds chemical vapor deposition or a combination thereof.
  • Both the buffer layer 2 and the first conductive type semiconductor layer 3 can be made of III-V group semiconductor materials, such as GaN or the like
  • an active layer is grown on the first conductive type semiconductor layer, the active layer includes a stacked potential well layer, an insertion layer and a potential barrier layer, and the insertion layer includes a stacked first insertion layer and a second insertion layer layer, the quantum confinement Stark effect is generated between the first insertion layer and the potential well layer; the materials of the potential well layer, the first insertion layer and the potential barrier layer are all III-V semiconductor materials, and the material of the second insertion layer contains Si-N bonds for repairing V-type defects in the first insertion layer.
  • the active layer 4 may be a single quantum well structure, which includes a potential well layer 401 , an insertion layer 402 and a potential barrier layer 403 .
  • the active layer 4 can also be a multi-quantum well structure, the potential well layers 401 and the barrier layers 403 are alternately arranged, and any adjacent potential well layers 401 and the barrier layers 403 have a space between them.
  • An intervening layer 402 is provided.
  • the material of the potential well layer 401 may be InGaN, and the material of the barrier layer 403 may be GaN, but the embodiments of the present disclosure do not specifically limit this.
  • the formation process of the potential well layer 401 and the potential barrier layer 403 can be referred to the formation process of the first conductive type semiconductor layer 3 .
  • the insertion layer 402 includes a first insertion layer 4021 and a second insertion layer 4022 arranged in layers.
  • the top and bottom of the insertion layer 402 are both the first insertion layer 4021 .
  • a quantum confinement Stark effect (QCSE) is generated between the first insertion layer 4021 and the potential well layer 401, so that the forbidden band width of the potential well is narrowed to increase the emission wavelength.
  • the material of the first insertion layer 4021 may be AlGaN or AlInGaN.
  • the material of the second insertion layer 4022 may be Si-doped AlGaN.
  • the Si-N bond in the material of the second insertion layer 4022 can repair the first insertion layer formed by the lattice mismatch between the material of the first insertion layer 4021 and the material of the potential well layer 401
  • the V-shaped defects in 4021 avoid the formation of pits or holes by the above-mentioned V-shaped defects, and prevent the In components in the material of the potential well layer 401 from being resolved during the subsequent high temperature epitaxial growth process.
  • the formation process of the first insertion layer 4021 and the second insertion layer 4022 may refer to the formation process of the first conductive type semiconductor layer 3 .
  • the Si-N bond in the second insertion layer 4022 is realized by feeding a silicon source into the reaction chamber.
  • the silicon source may include silane and/or disilane, which is not particularly limited in the embodiment of the present disclosure.
  • the growth method of the insertion layer 402 may include: simultaneously feeding Al source, Ga source, ammonia gas and carrier gas into the reaction chamber to grow the first insertion layer Layer 4021; at the same time, Al source, Ga source, Si source, ammonia gas and carrier gas are passed into the reaction chamber to grow the second insertion layer 4022.
  • the ratio of the molar rate of the Si source to the molar rate of the Ga source may be 1/10 7 -1/10 5 , for example, 1/10 7 , 1/10 6 , 1/10 5 and the like.
  • the ratio of the growth time of a second insertion layer 4022 to the growth time of the insertion layer 402 may be 1/100-1/5, such as 1/100, 1/60, 1/20, 1/5, and the like.
  • the ratio of the molar rate of feeding the Si source to the molar rate of feeding the Ga source during the growth of the first insertion layer 4021 may be 1/10 7 -1/10 5 .
  • the molar rate of feeding the Ga source during the growth of the first insertion layer 4021 may be the same as the molar rate of feeding the Ga source during the growth of the second insertion layer 4022 .
  • step S120 a second conductivity type semiconductor layer is grown on the active layer, and the conductivity types of the first conductivity type semiconductor layer and the second conductivity type semiconductor layer are opposite.
  • the second conductive type semiconductor layer 5 may be a group III-V semiconductor material, such as GaN or the like. Taking the material of the first conductive type semiconductor layer 3 as N-type GaN as an example, the material of the second conductive type semiconductor layer 5 may be P-type GaN.
  • the formation process of the second conductive type semiconductor layer 5 may refer to the formation process of the first conductive type semiconductor layer 3 .
  • the LED structure prepared in this embodiment may include an active layer 4 .
  • the active layer 4 may include a well layer 401, an insertion layer 402, and a barrier layer 403 that are stacked.
  • the insertion layer 402 includes a first insertion layer 4021 and a second insertion layer 4022 arranged in layers, and a quantum confinement Stark effect is generated between the first insertion layer 4021 and the potential well layer 401 .
  • the materials of the well layer 401 , the first insertion layer 4021 and the barrier layer 403 are all III-V group semiconductor materials.
  • the material of the second insertion layer 4022 contains Si-N bonds, and is used to repair the V-shaped defects of the first insertion layer 4021 .
  • the LED structure and the manufacturing method of the LED structure in the second embodiment of the present disclosure are substantially the same as the LED structure and the manufacturing method of the LED structure in the first embodiment of the present disclosure, and the difference only lies in the growth method of the insertion layer and the material of the second insertion layer in the insertion layer.
  • the material of the second insertion layer in the LED structure of the second embodiment of the present disclosure may be Si-doped GaN
  • the growth method of the insertion layer may be: simultaneously feeding Al source, Ga source, ammonia gas and carrier into the reaction chamber gas, the first insertion layer is grown; the Al source is turned off, and Ga source, Si source, ammonia gas and carrier gas are fed into the reaction chamber at the same time, and the second insertion layer is grown.
  • the LED structure and the preparation method of the LED structure in the third embodiment of the present disclosure are substantially the same as the LED structure and the preparation method of the LED structure in the first embodiment of the present disclosure, and the difference only lies in the growth method of the insertion layer and the material of the second insertion layer in the insertion layer.
  • the material of the second insertion layer in the LED structure of the third embodiment of the present disclosure may be Si-doped AlN
  • the growth method of the insertion layer may be: simultaneously feeding Al source, Ga source, ammonia gas and carrier into the reaction chamber gas to grow the first insertion layer; turn off the Ga source, and at the same time pass the Al source, the Si source, the ammonia gas and the carrier gas into the reaction chamber to grow the second insertion layer.
  • the LED structure and the preparation method of the LED structure in the fourth embodiment of the present disclosure are substantially the same as the LED structure and the preparation method of the LED structure in the first embodiment of the present disclosure, and the difference only lies in the growth method of the insertion layer and the material of the second insertion layer in the insertion layer.
  • the material of the second insertion layer in the LED structure of the fourth embodiment of the present disclosure may be SiN
  • the growth method of the insertion layer may be: simultaneously feeding Al source, Ga source, ammonia gas and carrier gas into the reaction chamber, and growing the second insertion layer. an insertion layer; the Al source and the Ga source are turned off, and the Si source, ammonia gas and carrier gas are fed into the reaction chamber at the same time to grow the second insertion layer.
  • FIG. 6 is a schematic diagram of an insertion layer in the LED structure according to the fifth embodiment of the present disclosure.
  • the LED structure and the manufacturing method of the LED structure in Embodiment 5 of the present disclosure are substantially the same as the LED structure and the manufacturing method of the LED structure in any one of Embodiments 1 to 4 of the present disclosure, and the difference only lies in the structure of the insertion layer.
  • the insertion layer 402 of Embodiment 5 of the present disclosure may include a plurality of first insertion layers 4021 and a plurality of second insertion layers 4022 , and the first insertion layers 4021 and the second insertion layers 4022 are alternately arranged.
  • the number of the second insertion layers 4022 may be 2-20, such as 2, 4, 6, 9, 17, 20, and the like.
  • the materials of the plurality of second insertion layers 4022 are all the same.
  • the LED structure and the preparation method of the LED structure in the sixth embodiment of the present disclosure are substantially the same as the LED structure and the preparation method of the LED structure in the fifth embodiment of the present disclosure, and the difference is only that: the plurality of second insertion layers in the sixth embodiment of the present disclosure have two The materials of the second insertion layers are different, and the material of any second insertion layer is selected from one of SiN, Si-doped AlGaN, Si-doped GaN, and Si-doped AlN.
  • the seventh embodiment of the present disclosure provides an LED device.
  • the LED device may include the LED structure in any one of Embodiments 1 to 6.
  • the LED device may further include a first electrode electrically connected to the first conductive type semiconductor layer and a second electrode electrically connected to the second conductive type semiconductor layer. Since the LED structure included in the LED device according to the seventh embodiment of the present disclosure is the same as the LED structure in the above-mentioned embodiments, it has the same beneficial effects, which will not be repeated in the present disclosure.

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Abstract

一种LED器件、LED结构及LED结构的制备方法。LED结构的制备方法包括：在一衬底（1）上生长第一导电类型半导体层（3）；在第一导电类型半导体层（3）上生长有源层（4），有源层（4）包括层叠设置的势阱层（401）、插入层（402）以及势垒层（403），插入层（402）包括层叠设置的第一插入层（4021）和第二插入层（4022），第一插入层（4021）与势阱层（401）之间产生量子限制斯塔克效应；势阱层（401）、第一插入层（4021）以及势垒层（403）的材料均为Ⅲ-Ⅴ族半导体材料，第二插入层（4022）的材料包含Si-N键，用于修复第一插入层（4021）的V型缺陷；在有源层（4）上生长第二导电类型半导体层（5），第一导电类型半导体层（3）与第二导电类型半导体层（5）的导电类型相反。能够防止发光二极管（LED）的光电性能降低。

Description

LED器件、LED结构及其制备方法 技术领域
本公开涉及半导体技术领域，尤其涉及一种LED器件、LED结构及LED结构的制备方法。
背景技术
近年来，发光二极管(Light Emitting Diode，简称LED)作为新一代绿色光源，广泛应用于照明、背光、显示等领域。
目前，发光二极管包括层叠设置的P型半导体层、有源层以及N型半导体层。该N型半导体用于提供电子，该P型半导体用于提供空穴。N型半导体提供的电子与P型半导体提供的空穴能够在有源层中复合，从而产生光。然而，该发光二极管的光电性能容易降低。
发明内容
本公开的目的在于提供一种LED器件、LED结构及LED结构的制备方法，能够防止发光二极管的光电性能降低。
根据本公开的一个方面，提供一种LED结构的制备方法，包括：
在一衬底上生长第一导电类型半导体层；
在所述第一导电类型半导体层上生长有源层，所述有源层包括层叠设置的势阱层、插入层以及势垒层，所述插入层包括层叠设置的第一插入层和第二插入层，所述第一插入层与所述势阱层之间产生量子限制斯塔克效应；所述势阱层、第一插入层以及势垒层的材料均为Ⅲ-Ⅴ族半导体材料，所述第 二插入层的材料包含Si-N键，用于修复所述第一插入层的V型缺陷；
在所述有源层上生长第二导电类型半导体层，所述第一导电类型半导体层与所述第二导电类型半导体层的导电类型相反。
进一步地，所述势阱层的材料为InGaN，所述势垒层的材料为GaN，所述第一插入层的材料为AlGaN或AlInGaN，所述第二插入层的材料选自SiN、Si掺杂的AlGaN、Si掺杂的GaN以及Si掺杂的AlN中的至少一种。
进一步地，所述第二插入层中的Si-N键通过向反应室中通入硅源实现，所述硅源包括硅烷和/或乙硅烷。
进一步地，所述插入层的生长方法包括：
同时向反应室中通入Al源、Ga源、氨气和载气，生长所述第一插入层；
同时向所述反应室中通入Al源、Ga源、Si源、氨气和载气，生长所述第二插入层，所述第二插入层的材料为Si掺杂的AlGaN。
进一步地，所述插入层的生长方法包括：
同时向反应室中通入Al源、Ga源、氨气和载气，生长所述第一插入层；
关闭Al源、Ga源，同时向所述反应室中通入Si源、氨气和载气，生长所述第二插入层，所述第二插入层的材料为SiN。
进一步地，所述插入层的生长方法包括：
同时向反应室中通入Al源、Ga源、氨气和载气，生长所述第一插入层；
关闭Al源，同时向所述反应室中通入Ga源、Si源、氨气和载气，生长所述第二插入层，所述第二插入层的材料为Si掺杂的GaN。
进一步地，所述插入层的生长方法包括：
同时向反应室中通入Al源、Ga源、氨气和载气，生长所述第一插入层；
关闭Ga源，同时向所述反应室中通入Al源、Si源、氨气和载气，生长所述第二插入层，所述第二插入层的材料为Si掺杂的AlN。
进一步地，所述Si源的摩尔速率与所述Ga源的摩尔速率的比值为1/10 7-1/10 5。
进一步地，一个所述第二插入层的生长时间与所述插入层的生长时间的比值为1/100-1/5。
根据本公开的一个方面，提供一种LED结构，包括：
有源层，包括层叠设置的势阱层、插入层以及势垒层，所述插入层包括层叠设置的第一插入层和第二插入层，所述第一插入层与所述势阱层之间产生量子限制斯塔克效应；所述势阱层、第一插入层以及势垒层的材料均为Ⅲ-Ⅴ族半导体材料，所述第二插入层的材料包含Si-N键，用于修复所述第一插入层的V型缺陷。
进一步地，所述势阱层的材料为InGaN，所述势垒层的材料为GaN，所述第一插入层的材料为AlGaN或AlInGaN，所述第二插入层的材料选自SiN、Si掺杂的AlGaN、Si掺杂的GaN以及Si掺杂的AlN中的至少一种。
进一步地，所述插入层包括多个所述第一插入层和多个所述第二插入层，所述第一插入层和所述第二插入层交替分布。
根据本公开的一个方面，提供一种LED器件，包括上述的LED结构。
本公开的LED器件、LED结构及LED结构的制备方法，有源层包括层叠设置的势阱层、插入层以及势垒层，插入层包括层叠设置的第一插入层和第二插入层，第一插入层与势阱层之间产生量子限制斯塔克效应，第二插入层材料中的Si-N键可以修复由于第一插入层材料与势阱层材料的晶格失配所形成的第一插入层中的V型缺陷，从而能够解决由于第一插入层与势阱层 的晶格失配所导致的发光二极管的光电性能降低的问题，防止发光二极管的光电性能降低。
附图说明
图1是相关技术中发光二极管的示意图；
图2是本公开的实施例一的LED结构的制备方法的流程图；
图3是本公开实施例一的LED结构的示意图；
图4是本公开实施例一的LED结构的另一示意图；
图5是本公开实施例一的LED结构中插入层的示意图；
图6是本公开实施例五的LED结构中插入层的示意图。
附图标记说明：1、衬底；2、缓冲层；3、第一导电类型半导体层；4、有源层；401、势阱层；402、插入层；4021、第一插入层；4022、第二插入层；403、势垒层；5、第二导电类型半导体层。
具体实施方式
这里将详细地对示例性实施方式进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施方式中所描述的实施方式并不代表与本公开相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本公开的一些方面相一致的装置的例子。
在本公开使用的术语是仅仅出于描述特定实施方式的目的，而非旨在限制本公开。除非另作定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开说明书以及 权利要求书中使用的“第一”“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“多个”或者“若干”表示两个及两个以上。除非另行指出，“前部”、“后部”、“下部”和/或“上部”等类似词语只是为了便于说明，而并非限于一个位置或者一种空间定向。“包括”或者“包含”等类似词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而且可以包括电性的连接，不管是直接的还是间接的。在本公开说明书和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
相关技术中，如图1所示，发光二极管(LED)包括层叠设置的第一导电类型半导体层3、有源层4以及第二导电类型半导体层5。该有源层4包括势阱层401和势垒层403。该势阱层401的材料为InGaN，该势垒层403的材料为GaN。为了使发光二极管能够产生具有较长波长的光，常常提高势阱层401中的In组分的含量，同时采用AlGaN在势阱层401和势垒层403之间形成插入层402。该插入层402与势阱层401之间产生量子限制斯塔克效应(QCSE)，使势阱禁带宽度变窄，以提高发光波长。然而，势阱层401材料的100晶向的晶格常数较大，插入层402材料的100晶向的晶格常数较小，插入层402材料与势阱层401材料之间存在较大的晶格失配问题，导致外延生长的插入层402材料的晶格品质较差，并产生V型缺陷。随着插入层402的厚度增加，插入层402材料中的V型缺陷会放大并形成凹坑或孔洞，导致势阱层401材料中的In组分在后续的高温外延生长过程中分解并析出逃逸，对In组分的均匀性造成影响，同时减少了势阱层401材料中In组分的含量，进而降低了发光二极管(LED)的光电性能。
实施例一
图2是本公开实施例一的LED结构的制备方法的流程图。图3和图4是本公开实施例一的LED结构的示意图。图5是本公开实施例一的LED结构中插入层的示意图。
如图2所示，实施例一的LED结构的制备方法可以包括步骤S100至步骤S120，其中：
步骤S100、在一衬底上生长第一导电类型半导体层。
步骤S110、在第一导电类型半导体层上生长有源层，有源层包括层叠设置的势阱层、插入层以及势垒层，插入层包括层叠设置的第一插入层和第二插入层，第一插入层与势阱层之间产生量子限制斯塔克效应；势阱层、第一插入层以及势垒层的材料均为Ⅲ-Ⅴ族半导体材料，第二插入层的材料包含Si-N键，用于修复第一插入层的V型缺陷。
步骤S120、在有源层上生长第二导电类型半导体层，第一导电类型半导体层与第二导电类型半导体层的导电类型相反。
本实施例的LED结构的制备方法，如图3至图5所示，有源层4包括层叠设置的势阱层401、插入层402以及势垒层403，插入层402包括层叠设置的第一插入层4021和第二插入层4022，第一插入层4021与势阱层401之间产生量子限制斯塔克效应，第二插入层4022材料中的Si-N键可以修复由于第一插入层4021材料与势阱层401材料的晶格失配所形成的第一插入层4021中的V型缺陷，从而能够解决相关技术中由于第一插入层4021与势阱层401的晶格失配所导致的发光二极管的光电性能降低的问题，防止发光二极管的光电性能降低。
下面对本实施例的各步骤进行详细说明：
在步骤S100中，在一衬底上生长第一导电类型半导体层。
如图3所示，该衬底1可以为蓝宝石衬底1、碳化硅衬底1和硅衬底1 中的一种，本实施例对此不加以限制。此外，在形成第一导电类型半导体层3之间，本实施例还可以在衬底1上形成缓冲层2。该第一导电类型半导体层3可以生长于缓冲层2上。其中，该第一导电类型半导体层3可以在反应室中形成，其形成工艺可以包括：原子层沉积法(ALD，Atomic layer deposition)、或化学气相沉积法(CVD，Chemical Vapor Deposition)、或分子束外延生长法(MBE，Molecular Beam Epitaxy)、或等离子体增强化学气相沉积法(PECVD，Plasma Enhanced Chemical Vapor Deposition)、或低压化学蒸发沉积法(LPCVD，Low Pressure Chemical Vapor Deposition)，或金属有机化合物化学气相沉积法、或其组合方式。该缓冲层2、第一导电类型半导体层3均可以为Ⅲ-Ⅴ族半导体材料，例如GaN等。其中，该第一导电类型半导体层3的材料可以为N型GaN。
在步骤S110中，在第一导电类型半导体层上生长有源层，有源层包括层叠设置的势阱层、插入层以及势垒层，插入层包括层叠设置的第一插入层和第二插入层，第一插入层与势阱层之间产生量子限制斯塔克效应；势阱层、第一插入层以及势垒层的材料均为Ⅲ-Ⅴ族半导体材料，第二插入层的材料包含Si-N键，用于修复第一插入层的V型缺陷。
如图3所示，该有源层4可以为单量子阱结构，其包括一个势阱层401、一个插入层402以及一个势垒层403。当然，如图4所示，该有源层4也可以为多量子阱结构，势阱层401和势垒层403交替设置，且任意相邻的势阱层401和势垒层403之间具设有插入层402。该势阱层401的材料可以为InGaN，该势垒层403的材料可以为GaN，但本公开实施方式对此不做特殊限定。该势阱层401、和势垒层403的形成工艺可以参照第一导电类型半导体层3的形成工艺。
如图5所示，该插入层402包括层叠设置的第一插入层4021和第二插入层4022。其中，该插入层402的顶部和底部均为第一插入层4021。该第一插入层4021与势阱层401之间产生量子限制斯塔克效应(QCSE)，使势阱禁带 宽度变窄，以提高发光波长。该第一插入层4021的材料可以为AlGaN或AlInGaN。该第二插入层4022的材料可以为Si掺杂的AlGaN。以势阱层401材料为InGaN为例，第二插入层4022材料中的Si-N键可以修复由于第一插入层4021材料与势阱层401材料的晶格失配所形成的第一插入层4021中的V型缺陷，避免上述的V型缺陷形成凹坑或孔洞，防止势阱层401材料中的In组分在后续的高温外延生长过程中分解析出。
如图5所示，该第一插入层4021和第二插入层4022的形成工艺可以参照第一导电类型半导体层3的形成工艺。其中，该第二插入层4022中的Si-N键通过向反应室中通入硅源实现。该硅源可以包括硅烷和/或乙硅烷，但本公开实施例对此不做特殊限定。举例而言，以第一插入层4021的材料为AlGaN为例，该插入层402的生长方法可以包括：同时向反应室中通入Al源、Ga源、氨气和载气，生长第一插入层4021；同时向反应室中通入Al源、Ga源、Si源、氨气和载气，生长第二插入层4022。其中，通入Si源的摩尔速率与通入Ga源的摩尔速率的比值可以为1/10 7-1/10 5，例如1/10 7、1/10 6、1/10 5等。一个第二插入层4022的生长时间与插入层402的生长时间的比值可以为1/100-1/5，例如1/100、1/60、1/20、1/5等。可选地，通入Si源的摩尔速率与生长第一插入层4021的过程中通入Ga源的摩尔速率的比值可以为1/10 7-1/10 5。生长第一插入层4021的过程中通入Ga源的摩尔速率可以与生长第二插入层4022的过程中通入Ga源的摩尔速率相同。
在步骤S120中，在有源层上生长第二导电类型半导体层，第一导电类型半导体层与第二导电类型半导体层的导电类型相反。
如图3和图4所示，该第二导电类型半导体层5可以为Ⅲ-Ⅴ族半导体材料，例如GaN等。以第一导电类型半导体层3的材料为N型GaN为例，该第二导电类型半导体层5的材料可以为P型GaN。该第二导电类型半导体层5的形成工艺可以参照第一导电类型半导体层3的形成工艺。
如图3至图5所示，本实施例制备的LED结构可以包括有源层4。该 有源层4可以包括层叠设置的势阱层401、插入层402以及势垒层403。该插入层402包括层叠设置的第一插入层4021和第二插入层4022，第一插入层4021与势阱层401之间产生量子限制斯塔克效应。该势阱层401、第一插入层4021以及势垒层403的材料均为Ⅲ-Ⅴ族半导体材料。该第二插入层4022的材料包含Si-N键，用于修复第一插入层4021的V型缺陷。
实施例二
本公开实施例二的LED结构及LED结构的制备方法与本公开实施例一的LED结构及LED结构的制备方法大致相同，区别仅在于插入层的生长方法以及插入层中第二插入层的材料。其中，本公开实施例二的LED结构中第二插入层的材料可以为Si掺杂的GaN，插入层的生长方法可以为：同时向反应室中通入Al源、Ga源、氨气和载气，生长第一插入层；关闭Al源，同时向反应室中通入Ga源、Si源、氨气和载气，生长第二插入层。
实施例三
本公开实施例三的LED结构及LED结构的制备方法与本公开实施例一的LED结构及LED结构的制备方法大致相同，区别仅在于插入层的生长方法以及插入层中第二插入层的材料。其中，本公开实施例三的LED结构中第二插入层的材料可以为Si掺杂的AlN，插入层的生长方法可以为：同时向反应室中通入Al源、Ga源、氨气和载气，生长第一插入层；关闭Ga源，同时向反应室中通入Al源、Si源、氨气和载气，生长第二插入层。
实施例四
本公开实施例四的LED结构及LED结构的制备方法与本公开实施例一的LED结构及LED结构的制备方法大致相同，区别仅在于插入层的生长方法以及插入层中第二插入层的材料。其中，本公开实施例四的LED结构中第二插入层的材料可以为SiN，插入层的生长方法可以为：同时向反应室中通入Al源、Ga源、氨气和载气，生长第一插入层；关闭Al源、Ga源，同时向所 述反应室中通入Si源、氨气和载气，生长第二插入层。
实施例五
图6是本公开实施例五的LED结构中插入层的示意图。本公开实施例五的LED结构及LED结构的制备方法与本公开实施例一至实施例四中任一实施例的LED结构及LED结构的制备方法大致相同，区别仅在于插入层的结构。如图6所示，本公开实施例五的插入层402可以包括多个第一插入层4021和多个第二插入层4022，且第一插入层4021和第二插入层4022交替设置。其中，该第二插入层4022的数量可以为2-20，例如2、4、6、9、17、20等。多个第二插入层4022的材料均相同。
实施例六
本公开实施例六的LED结构及LED结构的制备方法与本公开实施例五的LED结构及LED结构的制备方法大致相同，区别仅在于：本公开实施例六的多个第二插入层存在两个第二插入层的材料不同，且任一第二插入层的材料选自SiN、Si掺杂的AlGaN、Si掺杂的GaN以及Si掺杂的AlN中的一种。
实施例七
本公开实施例七提供一种LED器件。该LED器件可以包括实施例一至实施例六中任一实施例中的LED结构。当然，该LED器件还可以包括电连接于第一导电类型半导体层的第一电极以及电连接于第二导电类型半导体层的第二电极。由于本公开实施例七的LED器件所包含的LED结构同上述实施例中的LED结构相同，因此，其具有相同的有益效果，本公开在此不再赘述。
以上所述仅是本公开的较佳实施方式而已，并非对本公开做任何形式上的限制，虽然本公开已以较佳实施方式揭露如上，然而并非用以限定本公开，任何熟悉本专业的技术人员，在不脱离本公开技术方案的范围内，当可利用上述揭示的技术内容做出些许更动或修饰为等同变化的等效实施方式，但凡是未脱离本公开技术方案的内容，依据本公开的技术实质对以上实施方 式所作的任何简单修改、等同变化与修饰，均仍属于本公开技术方案的范围内。

Claims (13)

  1. 一种LED结构的制备方法，其特征在于，包括：
    在一衬底(1)上生长第一导电类型半导体层(3)；
    在所述第一导电类型半导体层(3)上生长有源层(4)，所述有源层(4)包括层叠设置的势阱层(401)、插入层(402)以及势垒层(403)，所述插入层(402)包括层叠设置的第一插入层(4021)和第二插入层(4022)，所述第一插入层(4021)与所述势阱层(401)之间产生量子限制斯塔克效应；所述势阱层(401)、第一插入层(4021)以及势垒层(403)的材料均为Ⅲ-Ⅴ族半导体材料，所述第二插入层(4022)的材料包含Si-N键，用于修复所述第一插入层(4021)的V型缺陷；
    在所述有源层(4)上生长第二导电类型半导体层(5)，所述第一导电类型半导体层(3)与所述第二导电类型半导体层(5)的导电类型相反。
  2. 根据权利要求1所述的LED结构的制备方法，其特征在于，所述势阱层(401)的材料为InGaN，所述势垒层(403)的材料为GaN，所述第一插入层(4021)的材料为AlGaN或AlInGaN，所述第二插入层(4022)的材料选自SiN、Si掺杂的AlGaN、Si掺杂的GaN以及Si掺杂的AlN中的至少一种。
  3. 根据权利要求1或2所述的LED结构的制备方法，其特征在于，所述第二插入层(4022)中的Si-N键通过向反应室中通入硅源实现，所述硅源包括硅烷和/或乙硅烷。
  4. 根据权利要求2所述的LED结构的制备方法，其特征在于，所述插入层(402)的生长方法包括：
    同时向反应室中通入Al源、Ga源、氨气和载气，生长所述第一插入层(4021)；
    同时向所述反应室中通入Al源、Ga源、Si源、氨气和载气，生长所述第二插入层(4022)，所述第二插入层(4022)的材料为Si掺杂的AlGaN。
  5. 根据权利要求2所述的LED结构的制备方法，其特征在于，所述插入层(402)的生长方法包括：
    同时向反应室中通入Al源、Ga源、氨气和载气，生长所述第一插入层(4021)；
    关闭Al源、Ga源，同时向所述反应室中通入Si源、氨气和载气，生长所述第二插入层(4022)，所述第二插入层(4022)的材料为SiN。
  6. 根据权利要求2所述的LED结构的制备方法，其特征在于，所述插入层(402)的生长方法包括：
    同时向反应室中通入Al源、Ga源、氨气和载气，生长所述第一插入层(4021)；
    关闭Al源，同时向所述反应室中通入Ga源、Si源、氨气和载气，生长所述第二插入层(4022)，所述第二插入层(4022)的材料为Si掺杂的GaN。
  7. 根据权利要求2所述的LED结构的制备方法，其特征在于，所述插入层(402)的生长方法包括：
    同时向反应室中通入Al源、Ga源、氨气和载气，生长所述第一插入层(4021)；
    关闭Ga源，同时向所述反应室中通入Al源、Si源、氨气和载气，生长所述第二插入层(4022)，所述第二插入层(4022)的材料为Si掺杂的AlN。
  8. 根据权利要求4-7任一项所述的LED结构的制备方法，其特征在于，所述Si源的摩尔速率与所述Ga源的摩尔速率的比值为1/10 7-1/10 5。
  9. 根据权利要求4-7任一项所述的LED结构的制备方法，其特征在于，一个所述第二插入层(4022)的生长时间与所述插入层(402)的生长时间的比值为1/100-1/5。
  10. 一种LED结构，其特征在于，包括：
    有源层(4)，包括层叠设置的势阱层(401)、插入层(402)以及势垒层(403)，所述插入层(402)包括层叠设置的第一插入层(4021)和第二插入层(4022)，所述第一插入层(4021)与所述势阱层(401)之间产生量子限制斯塔克效应；所述势阱层(401)、第一插入层(4021)以及势垒层(403)的材料均为Ⅲ-Ⅴ族半导体材料，所述第二插入层(4022)的材料包含Si-N键，用于修复所述第一插入层(4021) 的V型缺陷。
  11. 根据权利要求10所述的LED结构，其特征在于，所述势阱层(401)的材料为InGaN，所述势垒层(403)的材料为GaN，所述第一插入层(4021)的材料为AlGaN或AlInGaN，所述第二插入层(4022)的材料选自SiN、Si掺杂的AlGaN、Si掺杂的GaN以及Si掺杂的AlN中的至少一种。
  12. 根据权利要求10所述的LED结构，其特征在于，所述插入层(402)包括多个所述第一插入层(4021)和多个所述第二插入层(4022)，所述第一插入层(4021)和所述第二插入层(4022)交替分布。
  13. 一种LED器件，其特征在于，包括权利要求10-12任一项所述的LED结构。
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