WO2022095419A1 - 半导体器件的制备方法 - Google Patents

半导体器件的制备方法 Download PDF

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Publication number
WO2022095419A1
WO2022095419A1 PCT/CN2021/095835 CN2021095835W WO2022095419A1 WO 2022095419 A1 WO2022095419 A1 WO 2022095419A1 CN 2021095835 W CN2021095835 W CN 2021095835W WO 2022095419 A1 WO2022095419 A1 WO 2022095419A1
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Prior art keywords
layer
photoresist
substrate
semiconductor device
mask
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PCT/CN2021/095835
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English (en)
French (fr)
Inventor
夏军
白世杰
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长鑫存储技术有限公司
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Priority to US17/455,493 priority Critical patent/US20220148878A1/en
Publication of WO2022095419A1 publication Critical patent/WO2022095419A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices

Definitions

  • the present application relates to the field of semiconductor manufacturing, and in particular, to a method for preparing a semiconductor device.
  • SADP Self-aligned Double Patterning
  • SAQP Self-aligned Quadruple Patterning
  • SAQP Self-aligned Quadruple Patterning
  • Reverse Self-aligned Quadruple Patterning process etc.
  • a substrate 100 is provided, and a mask layer 110 having a pattern is disposed on the substrate 100 , and the mask layer 110 has openings 111 to expose the substrate 100 .
  • a dielectric layer 120 is deposited on the mask layer 110 , and the dielectric layer 120 covers the upper surface of the mask layer 110 , the sidewalls of the opening 111 and the surface of the substrate 100 .
  • the dielectric layer 120 is covered with a spin-on hard mask layer (SOH) 130 .
  • SOH spin-on hard mask layer
  • the spin-on hard mask layer 130 fills the opening 111, and its upper surface is higher than the upper surfaces of the dielectric layer 120 and the mask layer 110.
  • part of the spin-on hard mask layer 130 is removed by an etching process, and the top surface of the dielectric layer 120 located on the sidewall of the opening 111 and the dielectric layer 120 located on the upper surface of the mask layer 110 are removed. exposed.
  • the dielectric layer 120 and its corresponding substrate 100 are etched, and a desired pattern 140 is formed in the substrate 100 .
  • the ideal state of the spin-coating hard mask layer 130 is that the upper surface of the spin-coating hard mask layer 130 is kept flush, that is, the spin-coating hard mask layer 130 is formed in an ideal state.
  • the surfaces of layer 130 at various locations are in one plane.
  • the heights of the spin-on hard mask layers 130 are different, that is, The upper surfaces of the spin-on hard mask layer 130 are not in the same plane.
  • the higher the distribution density of the openings 111 of the mask layer 110 (that is, the smaller the opening ratio), the higher the height of the spin-coated hard mask layer 130, and at the edge of the semiconductor device, the openings 111 of the mask layer 110
  • the distribution density is the smallest (ie the opening ratio is the largest).
  • the distribution density of the openings 111 of the mask layer 110 is high (ie, the aperture ratio is small) in some areas (such as the area A shown in FIG. 1C ), while in some areas (such as the area B shown in FIG.
  • the mask layer If the distribution density of the openings 111 of 110 is low (ie, the aperture ratio is large), the height of the spin-on hard mask layer 130 in the A region is higher than the height of the spin-on hard mask layer 130 in the B region.
  • the low-height regions of the hard mask layer 130 may be exposed to the substrate 100, eg, at the edge of the semiconductor device, where the substrate 100 is most likely to be exposed. Then the etching gas will act on the substrate 100, so that the substrate 100 is etched, resulting in damage to the substrate 100, which affects the yield of the semiconductor device.
  • the purpose of the present application is to provide a method for manufacturing a semiconductor device, which can avoid damage to the substrate and improve the yield of the semiconductor device.
  • the present application provides a method for fabricating a semiconductor device, which includes the following steps: providing a substrate on which a mask layer is provided, and the mask layer is provided with a plurality of first windows forming a dielectric layer covering at least the sidewall of the first window; forming a first photoresist material layer covering the dielectric layer and the mask layer, and filling the first window; patterning the first photoresist material layer to form a patterned first photoresist layer, the first photoresist layer exposing the top surface of the dielectric layer; using the first photoresist layer
  • the resist layer and the mask layer are masks, and the dielectric layer is removed to form a second window; part of the substrate is removed along the second window to form a patterned substrate.
  • the method for forming a plurality of first windows on the mask layer includes the following steps: sequentially forming a mask layer and a second photoresist material layer on the substrate; patterning the second photoresist material layer to form a second photoresist layer with a pattern; using the second photoresist layer as a mask, transferring the pattern of the second photoresist layer to the mask layer to form a plurality of first photoresist layers window mask.
  • the first photoresist material layer and the second photoresist material layer are of different shapes from each other.
  • the first photoresist material layer is a positive type photoresist
  • the second photoresist material layer is a negative type photoresist
  • the first photoresist material layer is a negative type photoresist
  • the first photoresist material layer is a negative type photoresist.
  • the two photoresist material layers are positive photoresist.
  • the step of patterning the first photoresist material layer and the step of patterning the second photoresist material layer use the same mask.
  • the step of patterning the first photoresist material layer to form a patterned first photoresist layer further comprises: patterning the first photoresist material layer to form a patterned primary photoresist layer, the The primary photoresist layer fills the first window and covers part of the top surface of the dielectric layer; the primary photoresist layer is modified to form the first photoresist layer, and the first photoresist layer is exposed out of the top surface of the dielectric layer.
  • the top surface of the first photoresist material layer is higher than the top surface of the dielectric layer and the top surface of the mask layer.
  • an etching process is used to remove the dielectric layer, and the etchant has an effect on the dielectric layer.
  • the etching rate is higher than the etching rate of the first photoresist layer and the mask layer.
  • the aperture ratios of the first windows are different.
  • the method further includes the following step: removing the mask layer and the first mask layer on the surface of the substrate photoresist layer.
  • the method for forming the dielectric layer is atomic layer deposition.
  • the semiconductor substrate is composed of stacked layers of semiconductors of different elements or semiconductors of different compounds.
  • patterning the second photoresist layer to form a patterned second photoresist layer further includes: using the mask as a shield, exposing and developing the second photoresist layer to form the second photoresist layer; the mask has a plurality of openings through which light is irradiated on the second photoresist material layer.
  • the dielectric layer covers the sidewall of the first window, and covers the upper surface of the mask layer and the exposed surface of the substrate.
  • the dielectric layer and the oxide layer of the substrate are layers of the same material.
  • removing part of the substrate along the second window to form a patterned substrate further comprises: using the first photoresist layer and the mask layer as masks, along the second window The oxide layer is etched to remove portions of the oxide layer to form a patterned substrate.
  • the thickness of the dielectric layer covering the sidewall of the first window is the same as the width of the pattern formed on the substrate.
  • the method for modifying the primary photoresist layer includes: performing ashing treatment on the primary photoresist layer by using oxygen plasma to expose the dielectric layer to be removed.
  • the first photoresist material layer and the second photoresist material layer are of the same type.
  • both the first photoresist material layer and the second photoresist material layer are positive type photoresists or both are negative type photoresists.
  • the advantage of the present application is that the material properties of the first photoresist material layer make the part of the first photoresist material layer that needs to be preserved not damaged during the patterning process of the first photoresist material layer, and the surface of the substrate is not damaged. If the substrate is exposed, the substrate will not be damaged in the subsequent process of forming the patterned substrate, which greatly improves the yield of the semiconductor device.
  • 1A-1E are the flowcharts of the reverse self-aligned dual pattern process in the prior art
  • FIG. 2 is a schematic diagram of steps of a method for fabricating a semiconductor device according to an embodiment of the present application
  • 3A-3H are process flow diagrams of a method for fabricating a semiconductor device according to an embodiment of the present application.
  • 4A-4B are process flow diagrams of forming a mask layer having a plurality of first windows on the substrate according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of steps of a method for fabricating a semiconductor device according to an embodiment of the present application.
  • the preparation method of the semiconductor device of the present application includes the following steps: step S20 , providing a substrate, and forming a mask layer with a plurality of first windows on the substrate; step S21 , forming a dielectric layer, so The dielectric layer covers at least the sidewall of the first window; step S22, a first photoresist material layer is formed, the first photoresist material layer covers the dielectric layer and the mask layer, and fills the first photoresist layer.
  • step S23 patterning the first photoresist material layer to form a patterned first photoresist layer, the first photoresist layer exposing the top surface of the dielectric layer; step S24, using the The first photoresist layer and the mask layer are masks, and the dielectric layer is removed to form a second window; in step S25, part of the substrate is removed along the second window to form a patterned substrate.
  • 3A-3H are process flow diagrams of a method for fabricating a semiconductor device according to an embodiment of the present application.
  • a substrate 300 is provided, and a mask layer 310 having a plurality of first windows 311 is formed on the substrate 300 .
  • the semiconductor substrate 300 may include a silicon substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, an SOI substrate or a GOI (Germanium-on-Insulator, germanium-on-insulator) substrate, etc.;
  • the semiconductor substrate 300 can also be a substrate including other element semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide or silicon carbide, etc.
  • the semiconductor substrate 300 can also be a stacked structure, such as silicon/germanium silicon
  • the semiconductor substrate 300 can be an ion-doped substrate, which can be P-type doped or N-type doped; the semiconductor substrate 300 can also be formed with multiple peripheral devices such as field effect transistors, capacitors, inductors and/or pn junction diodes.
  • the semiconductor substrate 300 includes a nitride layer 301 and an oxide layer 302 located above the nitride layer 301 , and other substrate structures, such as a bit line structure and a transistor structure, are further included under the nitride layer 301 etc., but are not shown because they are irrelevant to this application.
  • the mask layer 310 is disposed on the upper surface of the substrate 300 , and the first window 311 penetrates the mask layer 310 and exposes the upper surface of the substrate 300 . Specifically, in this embodiment, the first window 311 penetrates through the mask layer 310 and exposes the upper surface of the oxide layer 302 .
  • the mask layer 310 may be a single-layer structure or a multi-layer structure.
  • the mask layer 310 is a multi-layer structure composed of an SOH layer and a nitride layer. In other embodiments, the mask layer 310 may only be a single-layer nitride layer or an SOH layer.
  • the aperture ratios of the first windows 311 are different.
  • the aperture ratio refers to the ratio of the area of the first window 311 to the overall area of the mask layer 310 .
  • the aperture ratio of the first window 311 is smaller, and in the B region, the opening of the first window 311 is smaller. high rate.
  • the aperture ratio of the first window 311 is the largest.
  • the aperture ratios of the first windows 311 may also be the same, that is, in the mask layer 310 , regions A and B have the same area. Compared with the regions, the aperture ratios of the first windows 311 are the same.
  • this embodiment also provides a method for forming a mask layer 310 having a plurality of first windows 311 on the substrate 300 .
  • the method includes the following steps:
  • a mask layer 310 and a second photoresist material layer 400 are sequentially formed on the substrate 300 .
  • the mask layer 310 is formed on the substrate 300 by chemical vapor deposition or physical vapor deposition
  • the second photoresist material layer 400 is formed on the mask layer 310 by a spin coating process.
  • the second photoresist layer 400 is patterned to form a patterned second photoresist layer 410 .
  • the mask 500 may be used as a shield, and the second photoresist layer 400 may be exposed and developed to form the second photoresist layer 410 .
  • the mask 500 has a plurality of openings 501 through which light is irradiated on the second photoresist layer 400 .
  • the second photoresist material layer 400 is a positive type photoresist, the area irradiated by light is removed, and the area not irradiated by light is reserved, that is, the area corresponding to the opening 501 is removed, and the area not corresponding to the opening 501 is retained.
  • the second photoresist material layer 400 is an inversion photoresist, so the area irradiated by light is retained, and the area not irradiated by light is removed, that is, the area corresponding to the opening 501 is removed. Regions are retained, and regions that do not correspond to the openings 501 are removed.
  • the pattern of the second photoresist layer 410 is transferred to the mask layer 310 , and then a plurality of the first photoresist layers are formed on the mask layer 310
  • the window 311, the structure formed in this step is shown in FIG. 3A.
  • the mask layer 310 is etched to form a plurality of the first windows 311 on the mask layer 310 .
  • a dielectric layer 320 is formed, and the dielectric layer 320 covers at least the sidewall of the first window 311 .
  • the dielectric layer 320 not only covers the sidewall of the first window 311 , but also covers the upper surface of the mask layer 310 and the exposed surface of the substrate 300 .
  • the dielectric layer 320 may only cover the sidewall of the first window 311 .
  • the dielectric layer 320 is an oxide layer, which is the same material layer as the oxide layer 302 of the substrate 300. In other embodiments of the present application, the dielectric layer 320 is also Other material layers may be used, and the dielectric layer 320 and the mask layer 310 , the first photoresist layer 410 and the second photoresist layer 340 formed subsequently have a higher etching selectivity ratio.
  • the thickness of the dielectric layer 320 covering the sidewall of the first window 311 is the same as the width of the pattern that needs to be formed on the substrate 300 later, so the thickness of the dielectric layer 320 can be used to define the thickness of the dielectric layer 320 to be formed on the substrate subsequently The width of the pattern on 300.
  • the dielectric layer 320 may be formed by atomic layer deposition, so that the critical dimension of the dielectric layer 320 is controllable, so as to ensure that the formed dielectric layer 320 has good uniformity in each region, thereby ensuring the second window 350 formed subsequently. (Please refer to FIG. 3F ) the openings have good uniformity, so that the subsequent patterns formed in the substrate 300 have good uniformity.
  • a first photoresist material layer 330 is formed, the first photoresist material layer 330 covers the dielectric layer 320 and the mask layer 310 , and fills the first window 311 .
  • the first photoresist material layer 330 may be formed by a spin coating process.
  • the top surface of the first photoresist layer 330 is higher than the top surface of the dielectric layer 320 and the top surface of the mask layer 310 to further ensure that the surface of the substrate 300 is not exposed.
  • the ideal state of the first photoresist layer 330 is that the upper surface of the first photoresist layer 330 is kept flush, that is, the surfaces of the first photoresist layer 330 at various positions are all within one plane.
  • the height of the first photoresist material layer 330 is different due to the different aperture ratios of the first windows 311 .
  • the aperture ratio of the first window 311 is the largest, and the height of the first photoresist material layer 330 is the smallest.
  • the first photoresist material layer 330 is patterned to form a patterned first photoresist layer 340 , and the first photoresist layer 340 exposes the surface of the dielectric layer 320 top.
  • first photoresist material layer 330 and the second photoresist material layer 400 are of different shapes. Specifically, if the first photoresist layer 330 is a positive photoresist, the second photoresist layer 400 is a negative photoresist; if the first photoresist layer 330 is a negative photoresist resistance, the second photoresist material layer 400 is a positive type photoresist. In this step, the same mask used for forming the second photoresist layer 410 can be used as a shield, and the first photoresist material layer 330 can be exposed and developed without additional mask, saving The process is improved and the cost is saved.
  • the first photoresist material layer 330 is a negative type photoresist
  • the second photoresist material layer 400 is a positive type photoresist.
  • the same mask as the photoresist layer 410 is used as a shield, and the first photoresist material layer 330 is exposed and developed to form the first photoresist layer 340, and the first photoresist layer 340 only shields the first photoresist layer 340.
  • the window 311 and the dielectric layer 320 located on the sidewall of the first window 311 .
  • the mask 500 is also used as a shield, and the first photoresist material layer 330 is exposed and developed, the area irradiated by light is retained, and the area not irradiated by light is removed.
  • the area corresponding to the opening 501 is reserved, and the area not corresponding to the opening 501 is removed.
  • the first photoresist material layer 330 is a positive type photoresist
  • the second photoresist material layer 400 is a negative type photoresist.
  • the same mask as the second photoresist layer 410 is used as a shield, and the first photoresist material layer 330 is exposed and developed to form the first photoresist layer 340.
  • the first photoresist layer 340 only shields the The first window 311 and the dielectric layer 320 located on the sidewall of the first window 311 .
  • the mask 500 is also used as a shield, and the first photoresist material layer 330 is exposed and developed, the area irradiated by light is removed, and the area not irradiated by light is retained, that is, the same as the above The area corresponding to the opening 501 is removed, and the area not corresponding to the opening 501 is retained.
  • the step of patterning the first photoresist material layer 330 and forming the patterned first photoresist layer 340 further includes the following steps:
  • the first photoresist layer 330 is patterned to form a patterned primary photoresist layer 331 , the primary photoresist layer 331 fills the first window 311 and covers part of the dielectric layer 320 the top surface.
  • the primary photoresist layer 331 is modified to form the first photoresist layer 340 , and the first photoresist layer 340 exposes the top surface of the dielectric layer 320 .
  • the dielectric layer 320 to be removed is exposed, so that subsequent processes can be smoothly performed.
  • the method for modifying the primary photoresist layer 331 is to perform ashing treatment on the primary photoresist layer 331 by using oxygen plasma to expose the dielectric layer 320 to be removed.
  • the first photoresist layer 330 and the second photoresist layer 400 are of the same type, for example, the first photoresist layer 330 and the second photoresist If the material layers 400 are both positive-type photoresists or both are negative-type photoresists, different masks may be used in the steps of patterning the first photoresist material layer 330 and the second photoresist material layer 400 The plate is shielded to obtain the first photoresist layer 340 and the second photoresist layer 410 .
  • step S23 in the process of patterning the first photoresist material layer 330, the height of the remaining portion of the first photoresist material layer 330 is not changed, that is, in the process of patterning the first photoresist material layer 330 During the patterning process of the first photoresist material layer 330, the substrate in the prior art (refer to FIG. 1D) is not exposed, so that damage to the substrate can be avoided in subsequent steps.
  • the dielectric layer 320 is removed to form a second window 350 .
  • the dielectric layer 320 since the dielectric layer 320 not only covers the sidewall of the first window 311, but also covers the upper surface of the mask layer 310 and the exposed surface of the substrate 300, in this step , the dielectric layer 320 on the upper surface of the mask layer 310 is first removed, and then the mask layer 310 below it is exposed. During the continuous etching process, the mask layer 310 and the first The photoresist layer 340 is used as a mask, and the dielectric layer 320 on the sidewall of the first window 311 is removed to form the second window 350 . It can be understood that, in this step, the dielectric layer 320 on the surface of the substrate 300 is retained due to being blocked by the first photoresist layer 340 .
  • the dielectric layer 320 is etched by a dry etching process to remove the dielectric layer 320 on the sidewall of the first window 311 .
  • the etching rate of the etching gas to the dielectric layer 320 is greater than the etching rate of the first photoresist layer 340 and the mask layer 310 to avoid the first photoresist layer 340 and the mask layer 310
  • the photoresist layer 340 and the mask layer 310 are removed.
  • the width of the second window 350 is substantially the same as the thickness of the dielectric layer 320 , that is, the width of the second window 350 depends on the thickness of the dielectric layer 320 . Therefore, the critical dimension of the dielectric layer 320 The more uniform, the more uniform the width of the second window 350 is formed, thereby ensuring the more uniform the critical dimension of the pattern subsequently formed on the substrate.
  • step S25 and FIG. 3G part of the substrate 300 is removed along the second window 350 to form a patterned substrate.
  • the oxide layer 302 is etched along the second window 350 to remove part of the oxide layer 302, A patterned substrate is formed.
  • the etching method may be dry etching or wet etching. In this embodiment, the etching method is dry etching.
  • step S25 since the surface of the substrate 300 is shielded by the mask layer 310, the dielectric layer 320 and the first photoresist layer 340 located above the dielectric layer 320, and the substrate 300 has no exposed part, then During the etching process, the substrate 300 is not damaged, which greatly improves the performance of the semiconductor device.
  • step S25 the mask layer 310, the first photoresist layer 340 and the dielectric layer 320 covered by the first photoresist layer 340 on the surface of the substrate 300 are removed to form a pattern substrate.
  • the preparation method of the semiconductor device of the present application utilizes the material properties of the first photoresist material layer as a transition structure, so that in the process of patterning the first photoresist material layer, the part of the first photoresist material layer that needs to be retained The parts of the substrate that do not need to be etched are not exposed, so in the subsequent process of forming the patterned substrate, the parts of the substrate that do not need to be etched are not damaged, which greatly improves the quality of the semiconductor device. Rate.

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Abstract

本申请提供一种半导体器件的制备方法，如下步骤：提供衬底，于所述衬底上形成具有多个第一窗口的掩膜层；形成介质层，介质层至少覆盖第一窗口的侧壁；形成第一光阻材料层，第一光阻材料层覆盖介质层及掩膜层，且填充第一窗口；图形化第一光阻材料层，形成具有图案的第一光阻层，暴露出介质层的顶面；以第一光阻层及掩膜层为掩膜，去除介质层，形成第二窗口；沿第二窗口去除所述衬底，形成图形化的衬底。本申请优点是，第一光阻材料层的材料特性使得在第一光阻材料层被图形化的过程中，第一光阻材料层需要被保留的部分并未破坏，衬底表面并未被暴露，则在后续形成图形化的衬底的过程中，衬底并未被损坏，大大提高了半导体器件的良率。

Description

半导体器件的制备方法
交叉引用
本申请基于申请号为202011229183.6、申请日为2020年11月06日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及半导体制造领域，尤其涉及一种半导体器件的制备方法。
背景技术
为了增加半导体器件的集成密度，现有技术中采用了许多不同的方法，如，自对准双图形(Self-aligned Double Patterning，SADP)工艺、自对准四次图形(Self-aligned Quadruple Patterning，SAQP)工艺和反向自对准双图形(Reverse Self-aligned Quadruple Patterning)工艺等。
现有的反向自对准双图形工艺的具体流程如下：
请参阅图1A，提供一衬底100，所述衬底100上设置有具有图案的掩膜层110，所述掩膜层110具有开口111，暴露出所述衬底100。
请参阅图1B，在所述掩膜层110上沉积介质层120，所述介质层120覆盖所述掩膜层110的上表面、开口111侧壁及所述衬底100的表面。
请参阅图1C，采用旋涂硬掩膜层(SOH)130覆盖所述介质层120。所述旋涂硬掩膜层130填充所述开口111，且其上表面高于所述介质 层120及所述掩膜层110的上表面。
请参阅图1D，利用刻蚀工艺去除部分所述旋涂硬掩膜层130，位于所述开口111侧壁的介质层120的顶面及位于所述掩膜层110上表面的介质层120被暴露。
请参阅图1E，以所述旋涂硬掩膜层130为掩膜，刻蚀所述介质层120及其对应的所述衬底100，进而在所述衬底100中形成需要的图形140。
其中，在采用旋涂硬掩膜层130覆盖所述介质层120的步骤中，形成的所述旋涂硬掩膜层130的理想状态是，其上表面保持平齐，即旋涂硬掩膜层130各个位置处的表面均在一个平面内。而在实际工艺中，请继续参阅图1C，由于掩膜层110的开口111的分布密度不同，即掩膜层110各处的开口率不同，导致旋涂硬掩膜层130的高度不同，即旋涂硬掩膜层130的上表面并不在同一平面内。具体地说，掩膜层110的开口111的分布密度越高(即开口率越小)，旋涂硬掩膜层130的高度越高，在半导体器件的边缘，掩膜层110的开口111的分布密度最小(即开口率最大)。例如，在某些区域(例如图1C所示A区域)掩膜层110的开口111的分布密度高(即开口率小)，而在某些区域(例如图1C所示B区域)掩膜层110的开口111的分布密度低(即开口率大)，则A区域的旋涂硬掩膜层130的高度高于B区域的旋涂硬掩膜层130的高度。在该种情况下，在利用刻蚀工艺去除部分所述旋涂硬掩膜层130的步骤中，随着刻蚀的进行，涂硬掩膜层130的高度低的区域可能会暴露出衬底100，例如，在半导体器件的边缘，衬 底100最可能会被暴露。则刻蚀气体会作用于所述衬底100，使得衬底100被刻蚀，导致衬底100被损坏，影响半导体器件的良率。
因此，亟需一种新的半导体器件的制造方法，避免出现上述问题。
发明内容
本申请的目的是提供一种半导体器件的制备方法，其能够避免衬底被损坏，提高半导体器件的良率。
为了解决上述问题，本申请提供了一种半导体器件的制备方法，其包括如下步骤：提供一衬底，所述衬底上设置有掩膜层，所述掩膜层开设有多个第一窗口；形成介质层，所述介质层至少覆盖所述第一窗口的侧壁；形成第一光阻材料层，所述第一光阻材料层覆盖所述介质层及所述掩膜层，且填充所述第一窗口；图形化所述第一光阻材料层，形成具有图案的第一光阻层，所述第一光阻层暴露出所述介质层的顶面；以所述第一光阻层及所述掩膜层为掩膜，去除所述介质层，形成第二窗口；沿所述第二窗口去除部分所述衬底，形成图形化的衬底。
可选地，在所述掩膜层上形成多个第一窗口的方法包括如下步骤：于所述衬底上依次形成掩膜层和第二光阻材料层；图形化所述第二光阻材料层，形成具有图案的第二光阻层；以所述第二光阻层为掩膜，将所述第二光阻层的图案转移到所述掩膜层上，形成具有多个第一窗口的掩膜层。
可选地，所述第一光阻材料层与所述第二光阻材料层互为异型。
可选地，所述第一光阻材料层为正型光阻，所述第二光阻材料层 为负型光阻，或者所述第一光阻材料层为负型光阻，所述第二光阻材料层为正型光阻。
可选地，图形化所述第一光阻材料层的步骤与图形化所述第二光阻材料层的步骤采用同一掩膜版。
可选地，图形化所述第一光阻材料层，形成具有图案的第一光阻层的步骤进一步包括：图形化所述第一光阻材料层，形成具有图案的初级光阻层，所述初级光阻层填充所述第一窗口，并覆盖部分所述介质层的顶面；对所述初级光阻层进行修正，形成所述第一光阻层，所述第一光阻层暴露出所述介质层的顶面。
可选地，所述第一光阻材料层的上表面高于所述介质层的顶面及所述掩膜层的上表面。
可选地，以所述第一光阻层及所述掩膜层为掩膜，去除所述介质层的步骤中，采用刻蚀工艺去除所述介质层，刻蚀物对所述介质层的刻蚀速率大于对所述第一光阻层及所述掩膜层的刻蚀速率。
可选地，在所述掩膜层的不同区域，所述第一窗口的开口率不同。
可选地，在沿所述第二窗口去除部分所述衬底，形成图形化的衬底的步骤之后，还包括如下步骤：去除所述衬底表面的所述掩膜层及所述第一光阻层。
可选地，形成所述介质层的方法为原子层沉积法。
可选地，所述半导体衬底为不同元素半导体或不同化合物半导体叠层组成。
可选地，图形化所述第二光阻材料层，形成具有图案的第二光阻 层进一步包括：采用所述掩膜版作为遮挡，对所述第二光阻材料层进行曝光显影，形成所述第二光阻层；所述掩膜版具有多个开口，光穿过所述开口照射在所述第二光阻材料层上。
可选地，所述介质层覆盖所述第一窗口的侧壁，且覆盖所述掩膜层的上表面及所述衬底暴露的表面。
可选地，所述介质层与所述衬底的氧化物层为同种材料层。
可选地，沿所述第二窗口去除部分所述衬底，形成图形化的衬底进一步包括：以所述第一光阻层及所述掩膜层为掩膜，沿所述第二窗口刻蚀所述氧化物层，以去除部分所述氧化物层，形成图形化的衬底。
可选地，覆盖所述第一窗口的侧壁的所述介质层的厚度与在所述衬底上形成的图形的宽度相同。
可选地，对所述初级光阻层进行修正的方法包括：采用氧气等离子体对所述初级光阻层进行灰化处理，以暴露出需要被去除的所述介质层。
可选地，所述第一光阻材料层与所述第二光阻材料层为同型。
可选地，所述第一光阻材料层与所述第二光阻材料层均为正型光阻或者均为负型光阻。
本申请的优点在于，第一光阻材料层的材料特性使得在第一光阻材料层被图形化的过程中，第一光阻材料层需要被保留的部分并未破坏，衬底表面并未被暴露，则在后续形成图形化的衬底的过程中，衬底并未被损坏，大大提高了半导体器件的良率。
附图说明
图1A-图1E是现有技术中的反向自对准双图形工艺的流程图；
图2是本申请一实施例的半导体器件的制备方法的步骤示意图；
图3A-图3H是本申请一实施例的半导体器件的制备方法的工艺流程图；
图4A-图4B是本申请一实施例的于所述衬底上形成具有多个第一窗口的掩膜层的工艺流程图。
具体实施方式
下面结合附图对本申请提供的半导体器件的制备方法的具体实施方式做详细说明。
图2是本申请一实施例的半导体器件的制备方法的步骤示意图。请参阅图2，本申请半导体器件的制备方法包括如下步骤：步骤S20，提供一衬底，于所述衬底上形成具有多个第一窗口的掩膜层；步骤S21，形成介质层，所述介质层至少覆盖所述第一窗口的侧壁；步骤S22，形成第一光阻材料层，所述第一光阻材料层覆盖所述介质层及所述掩膜层，且填充所述第一窗口；步骤S23，图形化所述第一光阻材料层，形成具有图案的第一光阻层，所述第一光阻层暴露出所述介质层的顶面；步骤S24，以所述第一光阻层及所述掩膜层为掩膜，去除所述介质层，形成第二窗口；步骤S25，沿所述第二窗口去除部分所述衬底，形成图形化的衬底。
图3A-图3H是本申请一实施例的半导体器件的制备方法的工艺流程图。
请参阅步骤S20及图3A，提供一衬底300，于所述衬底300上形 成具有多个第一窗口311的掩膜层310。
所述半导体衬底300可以包括硅衬底、锗(Ge)衬底、锗化硅(SiGe)衬底、SOI衬底或GOI(Germanium-on-Insulator，绝缘体上锗)衬底等等；所述半导体衬底300还可以为包括其他元素半导体或化合物半导体的衬底，例如砷化镓、磷化铟或碳化硅等，所述半导体衬底300还可以为叠层结构，例如硅/锗硅叠层等；另外，所述半导体衬底300可以为进行离子掺杂后的衬底，可以进行P型掺杂，也可以进行N型掺杂；所述半导体衬底300中还可以形成有多个外围器件，如场效应晶体管、电容、电感和/或pn结二极管等。本实施例中，所述半导体衬底300包括氮化物层301及位于所述氮化物层301上方的氧化物层302，氮化物层301下方还含有其他衬底结构，比如位线结构，晶体管结构等，但由于与本申请无关，所以不绘示。
所述掩膜层310设置在所述衬底300上表面，所述第一窗口311贯穿所述掩膜层310，并暴露出所述衬底300的上表面。具体地说，在本实施例中，所述第一窗口311贯穿所述掩膜层310，并暴露出所述氧化物层302的上表面。所述掩膜层310可为单层结构，也可为多层结构，例如，在本实施例中，所述掩膜层310为由SOH层与氮化物层构成的多层结构，在本申请其他实施例中，所述掩膜层310可仅为单层氮化物层或者SOH层。
进一步，在本实施例中，在所述掩膜层310的不同区域，所述第一窗口311的开口率不同。所述开口率是指，所述第一窗口311的面积与所述掩膜层310整体面积的比值。例如，在所述掩膜层310中， 具有相同面积的A区域及B区域相比，在A区域，所述第一窗口311的开口率小，在B区域，所述第一窗口311的开口率大。其中，在所述半导体器件的边缘，所述第一窗口311的开口率最大。在本申请其他实施例中，在所述掩膜层310的不同区域，所述第一窗口311的开口率也可相同，即在所述掩膜层310中，具有相同面积的A区域及B区域相比，所述第一窗口311的开口率相同。
进一步，本实施例还提供一种于所述衬底300上形成具有多个第一窗口311的掩膜层310的方法。所述方法包括如下步骤：
请参阅图4A，于所述衬底300上依次形成掩膜层310和第二光阻材料层400。例如，采用化学气相沉积或者物理气相沉积等方法在所述衬底300上形成所述掩膜层310，在所述掩膜层310上采用旋涂工艺形成所述第二光阻材料层400。
请参阅图4B，图形化所述第二光阻材料层400，形成具有图案的第二光阻层410。
在该步骤中，可采用掩膜版500作为遮挡，对所述第二光阻材料层400进行曝光显影，形成所述第二光阻层410。所述掩膜版500具有多个开口501，光穿过所述开口501照射在所述第二光阻材料层400上。其中，在本实施例中，所述第二光阻材料层400为正型光阻，被光照射的区域被去除，未被光照射的区域被保留，即与所述开口501对应的区域被去除，未与所述开口501对应的区域被保留。而在本申请其他实施例中，所述第二光阻材料层400为反型光阻，则被光照射的区域被保留，未被光照射的区域被去除，即与所述开口501对应的 区域被保留，未与所述开口501对应的区域被去除。
以所述第二光阻层410为掩膜，将所述第二光阻层410的图案转移到所述掩膜层310上，进而在所述掩膜层310上形成多个所述第一窗口311，该步骤形成的结构如图3A所示。在该步骤中，以所述第二光阻层410为掩膜，刻蚀所述掩膜层310，以在所述掩膜层310上形成多个所述第一窗口311。
请参阅步骤S21及图3B，形成介质层320，所述介质层320至少覆盖所述第一窗口311的侧壁。在本实施例中，所述介质层320不仅覆盖所述第一窗口311的侧壁，还覆盖所述掩膜层310的上表面及所述衬底300暴露的表面。在本申请其他实施例中，所述介质层320也可仅覆盖所述第一窗口311的侧壁。
其中，在本实施例中，所述介质层320为氧化物层，其与所述衬底300的氧化物层302为同种材料层，在本申请其他实施例中，所述介质层320也可为其他材料层，所述介质层320与掩膜层310、第一光阻层410及后续形成的第二光阻层340具有较高的刻蚀选择比。
进一步，覆盖所述第一窗口311的侧壁的介质层320的厚度与后续需要在衬底300上形成的图案的宽度相同，因此可通过所述介质层320的厚度来界定后续形成在衬底300上的图案的宽度。其中，可采用原子层沉积法形成所述介质层320，使得所述介质层320的关键尺寸可控，保证形成的介质层320在各区域的均匀性好，从而保证后续形成的第二窗口350(请参阅图3F)的开口均一性好，使得后续在衬底300中形成的图案的均一性好。
请参阅步骤S22及图3C，形成第一光阻材料层330，所述第一光阻材料层330覆盖所述介质层320及所述掩膜层310，且填充所述第一窗口311。在该步骤中，可采用旋涂工艺形成所述第一光阻材料层330。所述第一光阻材料层330的上表面高于所述介质层320的顶面及所述掩膜层310的上表面，以进一步确保衬底300表面不被暴露。
在步骤S22中，所述第一光阻材料层330的理想状态是，其上表面保持平齐，即第一光阻材料层330各个位置处的表面均在一个平面而内。而在实际工艺中，由于所述第一窗口311的开口率不同，使得第一光阻材料层330的高度不同。具体地说，第一窗口311的开口率越小，第一光阻材料层330的高度越高。例如，在本实施例中，在半导体器件的边缘，第一窗口311的开口率最大，第一光阻材料层330的高度最小。
请参阅步骤S23、图3D及图3E，图形化所述第一光阻材料层330，形成具有图案的第一光阻层340，所述第一光阻层340暴露出所述介质层320的顶面。
进一步，所述第一光阻材料层330与所述第二光阻材料层400为异型。具体地说，若所述第一光阻材料层330为正型光阻，则所述第二光阻材料层400为负型光阻；若所述第一光阻材料层330为负型光阻，则所述第二光阻材料层400为正型光阻。在该步骤中，可采用与形成所述第二光阻层410相同的掩膜版作为遮挡，对所述第一光阻材料层330进行曝光显影，而不需要额外在提供掩膜版，节省了工艺制程，节约了成本。
在本实施例中，所述第一光阻材料层330为负型光阻，所述第二光阻材料层400为正型光阻，则在该步骤中，可采用与形成所述第二光阻层410相同的掩膜版作为遮挡，对所述第一光阻材料层330进行曝光显影，形成所述第一光阻层340，所述第一光阻层340仅遮挡所述第一窗口311及位于所述第一窗口311侧壁的介质层320。即在该步骤中，也采用掩膜版500作为遮挡，对所述第一光阻材料层330进行曝光显影，被光照射的区域被保留，未被光照射的区域被去除，即与所述开口501对应的区域被保留，未与所述开口501对应的区域被去除。
在本申请其他实施例中，所述第一光阻材料层330为正型光阻，所述第二光阻材料层400为负型光阻，则在该步骤中，可采用与形成所述第二光阻层410相同的掩膜版作为遮挡，对所述第一光阻材料层330进行曝光显影，形成所述第一光阻层340，所述第一光阻层340仅遮挡所述第一窗口311及位于所述第一窗口311侧壁的介质层320。即在该步骤中，也采用掩膜版500作为遮挡，对所述第一光阻材料层330进行曝光显影，被光照射的区域被去除，未被光照射的区域被保留，即与所述开口501对应的区域被去除，未与所述开口501对应的区域被保留。
进一步，若采用与形成所述第二光阻层410相同的掩膜版作为遮挡图形化所述第一光阻材料层330，由于掩膜版500的开口501的尺寸与第一窗口311的尺寸匹配，所述第一光阻层340(即被保留的第一光阻材料层330)的尺寸与第一窗口311的尺寸相同，则位于第一 窗口311侧壁的介质层320被所述第一光阻层340覆盖，而并未被暴露，导致后续工艺无法进行。因此，图形化所述第一光阻材料层330，形成具有图案的第一光阻层340的步骤进一步包括如下步骤：
请参阅图3D，图形化所述第一光阻材料层330，形成具有图案的初级光阻层331，所述初级光阻层331填充所述第一窗口311，并覆盖部分所述介质层320的顶面。
请参阅图3E，对所述初级光阻层331进行修正，形成所述第一光阻层340，所述第一光阻层340暴露出所述介质层320的顶面。对所述初级光阻层331进行修正后，需要被去除的介质层320暴露，使得后续工艺可以顺利进行。
在该步骤中，对所述初级光阻层331进行修正的方法是，采用氧气等离子体对初级光阻层331进行灰化处理，以暴露出需要被去除的介质层320。
进一步，在本申请其他实施例中，所述第一光阻材料层330与所述第二光阻材料层400为同型，例如，所述第一光阻材料层330与所述第二光阻材料层400均为正型光阻或者均为负型光阻，则在图形化所述第一光阻材料层330与所述第二光阻材料层400的步骤中，可采用不同的掩膜版进行遮挡，以获得第一光阻层340及第二光阻层410。
在步骤S23中，在对所述第一光阻材料层330进行图形化的过程中，并不会改变所述第一光阻材料层330的保留部分的高度，也就是说，在对所述第一光阻材料层330进行图形化的过程中，并不会出现现有技术中(请参阅图1D)衬底被暴露的情况，从而能够避免在后 续步骤中衬底被损坏。
请参阅步骤S24及图3F，以所述第一光阻层340及所述掩膜层310为掩膜，去除所述介质层320，形成第二窗口350。
在该实施例中，由于所述介质层320不仅覆盖所述第一窗口311的侧壁，还覆盖所述掩膜层310的上表面及所述衬底300暴露的表面，则在该步骤中，所述掩膜层310的上表面的介质层320首先被去除，然后暴露出其下方的所述掩膜层310，在继续刻蚀的过程中，所述掩膜层310及所述第一光阻层340作为掩膜，所述第一窗口311侧壁的介质层320被去除，形成所述第二窗口350。可以理解的是，在该步骤中，所述衬底300表面的介质层320由于被所述第一光阻层340遮挡而被保留。在本实施例中，采用干法刻蚀工艺刻蚀所述介质层320，以去除所述第一窗口311侧壁的介质层320。其中，刻蚀气体对所述介质层320的刻蚀速率大于对所述第一光阻层340及所述掩膜层310的刻蚀速率，以避免在去除介质层320时，所述第一光阻层340及所述掩膜层310被去除。
其中，所述第二窗口350的宽度与所述介质层320的厚度基本相同，即所述第二窗口350的宽度取决于所述介质层320的厚度，因此，所述介质层320的关键尺寸越均匀，形成的所述第二窗口350的宽度越均一，进而保证后续在衬底上形成的图案的关键尺寸越均一。
请参阅步骤S25及图3G，沿所述第二窗口350去除部分所述衬底300，形成图形化的衬底。
在本实施例中，以所述第一光阻层340及掩膜层310为掩膜，沿 所述第二窗口350刻蚀所述氧化物层302，以去除部分所述氧化物层302，形成具有图案的衬底。其中，所述刻蚀方法可以为干法刻蚀或者湿法刻蚀，在本实施例中，所述刻蚀方法为干法刻蚀。
在步骤S25中，由于所述衬底300的表面被掩膜层310、介质层320及位于所述介质层320上方的第一光阻层340遮挡，所述衬底300没有暴露的部分，则在进行刻蚀工艺时，所述衬底300未被损坏，大大提高了半导体器件的性能。
进一步，请参阅图3H，在步骤S25之后，去除所述衬底300表面的掩膜层310、第一光阻层340及被所述第一光阻层340覆盖的介质层320，形成具有图案的衬底。
本申请半导体器件的制备方法利用第一光阻材料层的材料特性，将其作为过渡结构，使得在第一光阻材料层被图形化的过程中，第一光阻材料层需要被保留的部分并未破坏，衬底不需要刻蚀的部分并未被暴露，则在后续形成图形化的衬底的过程中，衬底不需要刻蚀的部分并未被损坏，大大提高了半导体器件的良率。
以上所述仅是本申请的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (20)

  1. 一种半导体器件的制备方法，其特征在于，包括如下步骤：
    提供衬底，于所述衬底上形成具有多个第一窗口的掩膜层；
    形成介质层，所述介质层至少覆盖所述第一窗口的侧壁；
    形成第一光阻材料层，所述第一光阻材料层覆盖所述介质层及所述掩膜层，且填充所述第一窗口；
    图形化所述第一光阻材料层，形成具有图案的第一光阻层，所述第一光阻层暴露出所述介质层的顶面；
    以所述第一光阻层及所述掩膜层为掩膜，去除所述介质层，形成第二窗口；
    沿所述第二窗口去除部分所述衬底，形成图形化的衬底。
  2. 根据权利要求1所述的半导体器件的制备方法，其特征在于，于所述衬底上形成具有多个第一窗口的掩膜层方法包括如下步骤：
    于所述衬底上依次形成掩膜层和第二光阻材料层；
    图形化所述第二光阻材料层，形成具有图案的第二光阻层；
    以所述第二光阻层为掩膜，将所述第二光阻层的图案转移到所述掩膜层上，形成具有多个第一窗口的掩膜层。
  3. 根据权利要求2所述的半导体器件的制备方法，其特征在于，所述第一光阻材料层与所述第二光阻材料层互为异型。
  4. 根据权利要求3所述的半导体器件的制备方法，其特征在于，所述第一光阻材料层为正型光阻，所述第二光阻材料层为负型光阻，或者所述第一光阻材料层为负型光阻，所述第二光阻材料层为正型光 阻。
  5. 根据权利要求3所述的半导体器件的制备方法，其特征在于，图形化所述第一光阻材料层的步骤与图形化所述第二光阻材料层的步骤采用同一掩膜版。
  6. 根据权利要求5所述的半导体器件的制备方法，其特征在于，图形化所述第一光阻材料层，形成具有图案的第一光阻层的步骤进一步包括：
    图形化所述第一光阻材料层，形成具有图案的初级光阻层，所述初级光阻层填充所述第一窗口，并覆盖部分所述介质层的顶面；
    对所述初级光阻层进行修正，形成所述第一光阻层，所述第一光阻层暴露出所述介质层的顶面。
  7. 根据权利要求1所述的半导体器件的制备方法，其特征在于，所述第一光阻材料层的上表面高于所述介质层的顶面及所述掩膜层的上表面。
  8. 根据权利要求1所述的半导体器件的制备方法，其特征在于，以所述第一光阻层及所述掩膜层为掩膜，去除所述介质层的步骤中，采用刻蚀工艺去除所述介质层，刻蚀物对所述介质层的刻蚀速率大于对所述第一光阻层及所述掩膜层的刻蚀速率。
  9. 根据权利要求1所述的半导体器件的制备方法，其特征在于，在所述掩膜层的不同区域，所述第一窗口的开口率不同。
  10. 根据权利要求1所述的半导体器件的制备方法，其特征在于，在沿所述第二窗口去除部分所述衬底，形成图形化的衬底的步骤之 后，还包括如下步骤：
    去除所述衬底表面的所述掩膜层及所述第一光阻层。
  11. 根据权利要求1所述的半导体器件的制备方法，其特征在于，形成所述介质层方法为原子层沉积法。
  12. 根据权利要求1所述的半导体器件的制备方法，其特征在于，所述半导体衬底为不同元素半导体或不同化合物半导体叠层组成。
  13. 根据权利要求5所述的半导体器件的制备方法，其特征在于，图形化所述第二光阻材料层，形成具有图案的第二光阻层进一步包括：
    采用所述掩膜版作为遮挡，对所述第二光阻材料层进行曝光显影，形成所述第二光阻层；
    所述掩膜版具有多个开口，光穿过所述开口照射在所述第二光阻材料层上。
  14. 根据权利要求1所述的半导体器件的制备方法，其特征在于，所述介质层覆盖所述第一窗口的侧壁，且覆盖所述掩膜层的上表面及所述衬底暴露的表面。
  15. 根据权利要求1所述的半导体器件的制备方法，其特征在于，所述介质层与所述衬底的氧化物层为同种材料层。
  16. 根据权利要求15所述的半导体器件的制备方法，其特征在于，沿所述第二窗口去除部分所述衬底，形成图形化的衬底进一步包括：
    以所述第一光阻层及所述掩膜层为掩膜，沿所述第二窗口刻蚀所 述氧化物层，以去除部分所述氧化物层，形成图形化的衬底。
  17. 根据权利要求1所述的半导体器件的制备方法，其特征在于，覆盖所述第一窗口的侧壁的所述介质层的厚度与在所述衬底上形成的图形的宽度相同。
  18. 根据权利要求6所述的半导体器件的制备方法，其特征在于，对所述初级光阻层进行修正的方法包括：
    采用氧气等离子体对所述初级光阻层进行灰化处理，以暴露出需要被去除的所述介质层。
  19. 根据权利要求2所述的半导体器件的制备方法，其特征在于，所述第一光阻材料层与所述第二光阻材料层为同型。
  20. 根据权利要求19所述的半导体器件的制备方法，其特征在于，所述第一光阻材料层与所述第二光阻材料层均为正型光阻或者均为负型光阻。
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