WO2022087789A1 - 显示基板、显示面板及显示装置 - Google Patents

显示基板、显示面板及显示装置 Download PDF

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Publication number
WO2022087789A1
WO2022087789A1 PCT/CN2020/123743 CN2020123743W WO2022087789A1 WO 2022087789 A1 WO2022087789 A1 WO 2022087789A1 CN 2020123743 W CN2020123743 W CN 2020123743W WO 2022087789 A1 WO2022087789 A1 WO 2022087789A1
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Prior art keywords
display area
display
pixel driving
light
emitting devices
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Application number
PCT/CN2020/123743
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English (en)
French (fr)
Inventor
黄耀
邱远游
顾品超
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2020/123743 priority Critical patent/WO2022087789A1/zh
Priority to CN202080002471.XA priority patent/CN114788009A/zh
Priority to US17/426,172 priority patent/US20220320243A1/en
Publication of WO2022087789A1 publication Critical patent/WO2022087789A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0876—Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate, a display panel and a display device.
  • an embodiment of the present disclosure provides a display substrate, including:
  • a base substrate, the display area of the base substrate includes: a first display area and a second display area, wherein the light transmittance of the first display area is greater than the light transmittance of the second display area;
  • a plurality of light-emitting devices are arranged in an array on the base substrate; the plurality of light-emitting devices include: a plurality of first light-emitting devices located in the first display area, and a plurality of light-emitting devices located in the second display area a second light-emitting device;
  • the plurality of pixel driving circuits include: a plurality of first pixel driving circuits and a plurality of second pixel driving circuits; wherein , the plurality of first pixel driving circuits and the plurality of first light-emitting devices are correspondingly electrically connected, the plurality of second pixel driving circuits and the plurality of second light-emitting devices at least partially overlap each other and are correspondingly electrically connected ; At least one of the plurality of pixel drive circuits has a drive transistor;
  • the gate electrode is connected to the gate electrode of the driving transistor
  • each of the wirings respectively spans at least one of the first pixel driving circuits from at least one of the first pixel driving circuits one of the gate connection electrodes is electrically connected to at least one of the first light emitting devices;
  • the shielding layer includes a plurality of isolation parts, and the orthographic projection of at least one of the isolation parts on the base substrate at least partially overlaps with the orthographic projection of at least one of the gate connection electrodes on the base substrate.
  • the shielding layer is located between the layer where the at least part of the wiring is located and the layer where the gate connecting electrode is located.
  • each of the gate connection electrodes is arranged in a first direction and extends in a second direction
  • each of the isolation portions is arranged in the first direction and extends in the second direction.
  • the shielding layer further includes a plurality of connection parts, and each of the connection parts connects the two isolation parts in the first direction.
  • the width of the isolation portion is greater than the width of the connection portion.
  • the shielding layer is located between the source-drain metal layer and the layer where the plurality of traces are located, and the shielding layer further includes and is connected to the plurality of wires.
  • a plurality of conductive portions having a plurality of connection portions and a plurality of isolation portions independent of each other; wherein each of the conductive portions is connected to one of the wirings and one of the first pixel driving circuits.
  • the shielding layer is provided in the same layer as the other traces except for the at least part of the traces, and the shielding layer further includes a a plurality of conductive parts where the plurality of connection parts and the plurality of isolation parts are independent of each other, wherein each of the conductive parts is connected to one of the at least part of the traces and one of the first pixel driving circuits .
  • the isolation portion is set floating or loaded with a DC signal.
  • the display substrate further comprises: a power supply signal line located in the source-drain metal layer and adjacent to the gate connection electrode, the power supply signal line is close to the gate connection electrode.
  • a power supply signal line located in the source-drain metal layer and adjacent to the gate connection electrode, the power supply signal line is close to the gate connection electrode.
  • One side of the gate connecting electrode has a concave structure;
  • the isolation portion is the same as the signal loaded on the power signal line, and the orthographic projection of the isolation portion on the base substrate covers the orthographic projection of the concave structure and intersects with the orthographic projection of the power signal line. stack.
  • the display substrate further comprises: a power supply signal line located in the source-drain metal layer and adjacent to the gate connection electrode, the power supply signal line is close to the gate connection electrode.
  • a power supply signal line located in the source-drain metal layer and adjacent to the gate connection electrode, the power supply signal line is close to the gate connection electrode.
  • One side of the gate connecting electrode has a concave structure;
  • the orthographic projection of the isolation portion on the base substrate overlaps with the orthographic projection of the concave structure and does not overlap with the orthographic projection of the power signal line.
  • the density of the plurality of first light-emitting devices in the first display area is smaller than the density of the plurality of second light-emitting devices in the second display area density
  • the plurality of pixel driving circuits are located in the second display area, and each of the first pixel driving circuits is located at a gap between each of the second pixel driving circuits.
  • the density of the plurality of first light-emitting devices in the first display area is equal to the density of the plurality of second light-emitting devices in the second display area density
  • the plurality of first pixel circuits are located in a border area adjacent to the first display area, and the plurality of second pixel driving circuits are located in the second display area.
  • the first display area is configured to install a light extraction module.
  • the material of the plurality of traces is a transparent conductive material.
  • the pixel driving circuit further includes a threshold compensation transistor, and the gate connection electrode is further electrically connected to the drain of the threshold compensation transistor.
  • an embodiment of the present disclosure provides a display panel including the above-mentioned display substrate.
  • an embodiment of the present disclosure provides a display device, comprising: a light extraction module, and the above-mentioned display panel; wherein, the light extraction module is disposed in a first display area of the display panel.
  • FIG. 1 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure
  • Fig. 2 is the enlarged structural schematic diagram of a region in Fig. 1;
  • FIG. 3 is a schematic diagram of uneven brightness in the related art
  • Fig. 4 is the actual arrangement diagram of a pixel drive circuit in Fig. 3;
  • FIG. 5 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 6 is another schematic structural diagram of a display substrate provided by an embodiment of the present disclosure.
  • Fig. 7 is a schematic cross-sectional structure along line I-II in Fig. 5 and line III-IV in Fig. 6;
  • Fig. 8 is another kind of cross-sectional structure schematic diagram along line I-II in Fig. 5 and line III-IV in Fig. 6;
  • FIG. 9 is another schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • FIG. 10 is an enlarged schematic structural diagram of region b in FIG. 9 .
  • a display device with an under-screen camera structure includes: a first display area AA1 and a second display area AA2, and the camera can be arranged at the position of the first display area AA1.
  • a plurality of pixels P and a plurality of pixel driving circuits D are arranged in the second display area AA2, wherein each pixel P includes a light-emitting device EL and a corresponding pixel driving circuit D; while in the second display area AA2
  • the pixel driving circuit D provided separately is used to control the light emitting device EL of the first display area AA1 to emit light.
  • a light emitting device EL in the first display area AA1 is electrically connected to a pixel driving circuit D in the second display area AA2 through a wire L.
  • the pixel driving circuit D has a driving transistor Td.
  • the gate voltage of the driving transistor Td will be affected, thereby causing the light-emitting device EL to be electrically connected to the pixel driving circuit D.
  • brightness changes a detailed description is given by taking the pixel driving circuit D as the structure of 7T1C shown in FIG. 3 and FIG. 4 as an example.
  • T1 to T6 and Td represent different transistors
  • Cst represents the storage capacitor
  • N1 to N8 represent different nodes
  • D1 to D4 represent different switching parts.
  • the light-emitting process of driving the light-emitting device EL by the pixel driving circuit D of the 7T1C structure shown in FIG. 3 and FIG. 4 can be divided into the following three stages: In the first stage, under the control of the reset signal terminal Re1, the first transistor T1 is turned on , so that the first initialization signal terminal Vin1 resets the gate (ie, the N1 node) of the driving transistor Td, and the remaining transistors are in an off state. In the second stage, the second transistor T2 and the third transistor T3 are turned on under the control of the scanning signal terminal Gn, the signal of the data signal terminal Dm is written into the N2 node through the third transistor T3, and the second transistor T2 is used to realize the pairing of the driving transistor Td.
  • the sixth transistor T6 is turned on, so that the second initialization signal terminal Vin2 resets the anode (ie, the N4 node) of the light-emitting device EL, and the remaining transistors are in an off state.
  • the fourth transistor T4 and the fifth transistor T5 are turned on.
  • the driving transistor Td is also turned on at this stage, so as to be the light-emitting device EL provide drive current.
  • the line L crosses the gate (ie, the N1 node) of the driving transistor Td in the pixel driving circuit D or the pixel driving circuit D included in the pixel P, a relatively small gap is formed between the line L and the N1 node.
  • the large capacitor C_L_N1 the voltage of the N1 node jumps after the signal of the light-emitting control signal terminal EM is turned on, and because the capacitance of the N1 node contained in the trace L and the multiple pixel drive circuits D is not exactly the same, the brightness is not uniform. all.
  • an embodiment of the present disclosure provides a display substrate, as shown in FIG. 1 , FIG. 2 , FIG. 5 to FIG. 8 , including:
  • the base substrate 101, the display area AA of the base substrate 101 includes: a first display area AA1 and a second display area AA2, wherein the light transmittance of the first display area AA1 is greater than the light transmittance of the second display area AA2;
  • the plurality of light emitting devices EL are arranged in an array on the base substrate 101; the plurality of light emitting devices EL include: a plurality of first light emitting devices 102 located in the first display area AA1, and a plurality of first light emitting devices 102 located in the second display area AA2 two light-emitting devices 103;
  • a plurality of pixel driving circuits D are located between the base substrate 101 and the layers where the plurality of light-emitting devices EL are located; the plurality of pixel driving circuits D include: a plurality of first pixel driving circuits 104 and a plurality of second pixel driving circuits 105; wherein , a plurality of first pixel driving circuits 104 are electrically connected to a plurality of first light emitting devices 102, a plurality of second pixel driving circuits 105 and a plurality of second light emitting devices 103 at least partially overlap each other and are correspondingly electrically connected; at least one of the drive circuits D has a drive transistor Td;
  • the gate is connected to the electrode 106 (ie, the N1 node), which is connected to the gate of the driving transistor;
  • a plurality of wirings 107 are located between the layers where the plurality of pixel driving circuits D are located and the layers where the plurality of light-emitting devices EL are located; at least part of each of the wirings 107 respectively crosses at least one gate from at least one first pixel driving circuit 104 the connection electrode 106 is electrically connected to the at least one first light emitting device 102;
  • the shielding layer 108 includes a plurality of isolation parts 1081, and the orthographic projection of at least one isolation part 1081 on the base substrate 101 at least partially intersects with the orthographic projection of at least one gate connection electrode 106 (ie, the N1 node) on the base substrate 101 stack.
  • the isolation portion 1081 can effectively shield the signals on the traces 107 from the driving transistor Td. Including the interference of the voltage on the gate connecting electrode 106 , the driving current provided by the pixel driving circuit D where the gate connecting electrode 106 (ie, the N1 node) is located will not jump, thereby improving the uniformity of luminous brightness.
  • the shape of the first display area AA1 may be a square as shown in FIG. 1 , or may be other shapes such as a circle, which may be designed according to actual needs, which is not limited herein.
  • the second display area AA2 may surround the periphery of the first display area AA1, or may surround part of the first display area AA1 as shown in FIG.
  • the upper boundary of the first display area AA1 coincides with the upper boundary of the second display area AA2.
  • the shielding layer 108 including a plurality of isolation parts 1081 may be located on at least part of the above-mentioned traces Between the layer where 107 is located and the layer where the gate connecting electrode 106 is located.
  • each gate connection electrode 106 (ie, the N1 node) may be arranged in the first direction X and in the second direction Y
  • each isolation portion 1081 is also arranged in the first direction X and extends in the second direction Y, so as to better shield the signal on the trace 107 from the gate connection electrode 106 (ie the N1 node). interference.
  • the material of the shielding layer 108 may be metal materials such as copper, molybdenum, and aluminum, or indium tin oxide, etc., which have shielding properties themselves. Transparent conductive material.
  • the isolation portion 1081 can be set to float (ie, no signal is applied) or a DC signal can be applied.
  • the DC signal may be a high-level (VDD) signal, a low-level (VSS) signal, an initialization (Vin) signal, and the like.
  • the shielding layer 108 may further include a plurality of connection parts 1082 , and each connection part 1082 connects two isolation parts in the first direction X 1081.
  • the isolation parts 1081 in the same row can be connected into an integrated structure through the connection parts 1082 , so that it is convenient to load a DC signal to each isolation part 1081 .
  • each isolation portion 1081 can also be wired separately to correspond to loading a DC signal, which is not limited here.
  • connection portion 1082 may overlap with other conductive film layers to generate parasitic capacitance, in order to reduce the parasitic capacitance as much as possible, as shown in FIG. 5 , in the second direction Y, the width of the connection part 1082 may be smaller than the width of the isolation part 1081 .
  • the plurality of wirings 107 may be arranged in the same layer, or may be arranged in different layers. And as shown in FIG. 2 , since each trace 107 extending in the row direction has a certain width in the column direction, and the size of the pixels in the column direction is also certain, therefore, the pixel size of each row in the first display area AA1 has a certain width. The number is limited; however, when multiple traces 107 are arranged in different layers, more traces 107 can be provided within a certain size range in the column direction to drive more first light-emitting devices 102, thereby satisfying the first The display area AA1 and the second display area AA2 have the same resolution, thereby improving the overall display effect.
  • the shielding layer 108 may be located between the source-drain metal layer and the layer where the plurality of wirings 107 are located.
  • each conductive part 1083 is connected to a trace 107 and a first pixel driving circuit 104 (specifically, the N4 node of the first pixel driving circuit 104 ), and the wiring 107 extends to be electrically connected to the first light emitting device 102 in the first display area AA.
  • the shielding layer 108 may be connected to at least part of the traces 107 (that is, the traces 107 crossing the gate connection electrode 106 ) other than the remaining traces 107 (that is, not The traces 107) spanning the gate connection electrode 106 are disposed in the same layer, and the shielding layer 108 may further include a plurality of conductive parts 1083 independent of the plurality of connection parts 1082 and the plurality of isolation parts 1081, wherein each conductive part 1083 At least one of the traces 107 is connected to a first pixel driving circuit (specifically, the N4 node of the first pixel driving circuit 104 ), and the trace 107 is extended to electrically connect with the first light emitting device 102 in the first display area AA. connect.
  • a first pixel driving circuit specifically, the N4 node of the first pixel driving circuit 104
  • the display substrate may further include: a power supply signal line 109 disposed adjacent to the source-drain metal layer and the gate connection electrode 106 , the power supply signal line 109 has a concave structure H on the side close to the gate connection electrode 106;
  • the isolation portion 108 and the power signal line 109 are loaded with the same signal (eg, VDD signal).
  • the orthographic projection of the isolation portion 108 on the base substrate 101 can cover the orthographic projection of the concave structure H and is consistent with the positive projection of the power signal line 109 .
  • the projections partially overlap.
  • the concave structure H on the power signal line 109 is mainly used to avoid the gate connection electrode 106 (ie, the N1 node), and to avoid the signal on the power signal line 109 and the gate connection electrode 106 (ie, the N1 node). interfere with each other.
  • the display substrate may further include: a power supply signal line 109 disposed adjacent to the source-drain metal layer and the gate connection electrode 106 , the power supply signal line 109 has a concave structure H on the side close to the gate connection electrode 106; the orthographic projection of the isolation portion 108 on the base substrate 101 and the orthographic projection of the concave structure H overlap each other and overlap with the orthographic projection of the power signal line 109. Do not overlap.
  • the power signal line 109 is provided with a concave structure H that avoids the isolation portion 108, so as to avoid mutual interference between the power signal line 109, the signal of the gate connecting electrode 106 (ie, the N1 node) and the signal of the isolation portion 108.
  • the source-drain metal layer may specifically refer to the metal layer where the source electrode and the drain electrode of the driving transistor are located.
  • the gate connection electrode 106 may be located in the source-drain metal layer.
  • the density of the plurality of first light-emitting devices 102 in the first display area AA1 may be smaller than that of the plurality of second light-emitting devices 103 in the second display area the density of the area AA2; correspondingly, a plurality of first pixel driving circuits 104 electrically connected to the plurality of first light emitting devices 102 and a plurality of second pixel driving circuits 105 corresponding to the plurality of second light emitting devices 103 They are all located in the second display area AA2 , and each of the first pixel driving circuits 104 is specifically located at a gap between each of the second pixel driving circuits 105 .
  • the density of the plurality of first light-emitting devices 102 in the first display area AA1 may also be equal to the density of the plurality of second light-emitting devices 103 in the second display area AA2;
  • the plurality of first pixel driving circuits 104 electrically connected to the first light emitting devices 102 are located in the border area BB adjacent to the first display area AA1, and the plurality of second pixel driving circuits 105 corresponding to the plurality of second light emitting devices 103 are electrically connected Located in the second display area AA2.
  • the middle area of the first display area AA1 may be the area where the camera is located, and only the first light-emitting device EL is arranged in the middle area, and the first pixel driving circuit may be arranged at the edge area of the first display area AA1 104, a second pixel driving circuit 105, and a second light-emitting device 103 at least partially overlapping with the second pixel driving circuit 105;
  • the second display area AA2 is a normal display area, and is provided with the second pixel driving circuit 105,
  • the second light-emitting device 103 at least partially overlapped by the two pixel driving circuits 105; and the density of the second light-emitting device 103 in the edge area of the first display area AA1 is greater than that of the first light-emitting device 102 in the middle area of the first display area AA1
  • the density is lower than the density of the second light emitting device 103 in the second display area AA2.
  • the display substrate may further include: data lines 110 located on the source-drain metal layer, and multiple anodes 111 located on the multiple traces 107 .
  • the first insulating layer 112 located between the source-drain metal layer and the shielding layer 108
  • the second insulating layer 113 located between the shielding layer 108 and the layer where at least part of the traces 107 are located
  • the layer where at least part of the traces 107 are located.
  • the planar layer 114 between the layers where the anodes 111 are located, and the pixel defining layer 115 defining the positions of the anodes 111 are other essential components should be understood by those of ordinary skill in the art, and will not be repeated here, nor should it be used as a limitation to the present disclosure.
  • the first display area AA1 is configured to install a light extraction module, such as a camera module, an optical fingerprint identification module, an ambient light sensor, and the like.
  • a light extraction module such as a camera module, an optical fingerprint identification module, an ambient light sensor, and the like.
  • the material of the plurality of traces 107 may be a transparent conductive material, so as to improve the light transmittance of the first display area AA1.
  • the pixel driving circuit D further includes a threshold compensation transistor, and the gate connection electrode 106 may also be electrically connected to the drain of the threshold compensation transistor.
  • the threshold compensation transistor can be made to compensate the threshold of the driving transistor, thereby effectively avoiding the different thresholds of the driving transistors included in different pixel driving circuits D.
  • the resulting drive currents are different, thereby ensuring the uniformity of luminous brightness.
  • an embodiment of the present disclosure further provides a display panel including the above-mentioned display substrate provided by an embodiment of the present disclosure.
  • the display panel may be an organic electroluminescent display panel (OLED), a quantum dot light emitting display panel (QLED), or a micro light emitting diode display panel (Micro LED). Since the principle of solving the problem of the display panel is similar to the principle of solving the problem of the above-mentioned display substrate, the implementation of the display panel provided by the embodiment of the present disclosure may refer to the implementation of the above-mentioned display substrate provided by the embodiment of the present disclosure, and the repetition will not be repeated. Repeat.
  • OLED organic electroluminescent display panel
  • QLED quantum dot light emitting display panel
  • Micro LED micro light emitting diode display panel
  • an embodiment of the present disclosure also provides a display device, comprising: a light-taking module (such as a camera module), and the above-mentioned display panel; wherein, the light-taking module is arranged in a first display area of the display panel AA1.
  • a light-taking module such as a camera module
  • the display device can be: mobile phone, tablet computer, TV, monitor, notebook computer, digital photo frame, navigator, smart watch, fitness wristband, personal digital assistant, and any other product or component with display function.
  • Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be described in detail here, nor should it be regarded as a limitation of the present disclosure.
  • the implementation of the display device may refer to the above-mentioned embodiment of the display panel, and the repetition will not be repeated.

Abstract

显示基板、显示面板及显示装置，包括在第一显示区（AA1）的多个第一发光器件（102）、在第二显示区（AA2）的多个第二发光器件（103）、多个第一像素驱动电路（104）和多个第二像素驱动电路（105）；各第一像素驱动电路（104）与各第一发光器件（102）对应相连，各第二像素驱动电路（105）与各第二发光器件（103）对应相连；多个像素驱动电路（D）中的至少一个具有驱动晶体管（Td）；与驱动晶体管（Td）的栅极相连的栅极连接电极（106或N1）；多条走线（107），至少部分走线（107）中的每一条分别自至少一个第一像素驱动电路（104）跨越至少一个栅极连接电极（106或N1）与至少一个第一发光器件（102）电连接；包含多个隔离部（1081）的屏蔽层（108），每个隔离部（1081）在衬底基板（101）上的正投影与至少一个栅极连接电极（106或N1）的正投影至少部分交叠。

Description

显示基板、显示面板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板、显示面板及显示装置。
背景技术
随着智能手机的高速发展，不仅要求手机的外形美观，还需兼顾给手机使用者带来更出色的视觉体验。各大厂商开始在智能手机上提高屏占比，使得全面屏成为智能手机的一个新竞争点。随着全面屏的发展，在性能和功能上的提升需求也与日俱增，屏下摄像头在不影响高屏占比的前提下，在一定程度上可以带来视觉和使用体验上的冲击感。
发明内容
一方面，本公开实施例提供了一种显示基板，包括：
衬底基板，所述衬底基板的显示区域包括：第一显示区和第二显示区，其中，所述第一显示区的透光率大于所述第二显示区的透光率；
多个发光器件，在所述衬底基板上呈阵列排布；所述多个发光器件包括：位于所述第一显示区的多个第一发光器件，以及位于所述第二显示区的多个第二发光器件；
多个像素驱动电路，位于所述衬底基板与所述多个发光器件所在层之间；所述多个像素驱动电路包括：多个第一像素驱动电路和多个第二像素驱动电路；其中，所述多个第一像素驱动电路与所述多个第一发光器件对应电连接，所述多个第二像素驱动电路与所述多个第二发光器件相互至少部分交叠并对应电连接；所述多个像素驱动电路中的至少一个具有驱动晶体管；
栅极连接电极，连接所述驱动晶体管的栅极；
多条走线，位于所述多个像素驱动电路所在层与所述多个发光器件所在 层之间；至少部分所述走线中的每一条分别自至少一个所述第一像素驱动电路跨越至少一个所述栅极连接电极与至少一个所述第一发光器件电连接；
屏蔽层，包括多个隔离部，至少一个所述隔离部在所述衬底基板上的正投影与至少一个所述栅极连接电极在所述衬底基板上的正投影至少部分交叠。
可选地，在本公开实施例提供的上述显示基板中，所述屏蔽层位于所述至少部分所述走线所在层与所述栅极连接电极所在层之间。
可选地，在本公开实施例提供的上述显示基板中，各所述栅极连接电极在第一方向上排列并在第二方向上延伸，各所述隔离部在所述第一方向上排列并在所述第二方向上延伸。
可选地，在本公开实施例提供的上述显示基板中，所述屏蔽层还包括多个连接部，每一个所述连接部连接所述第一方向上的两个所述隔离部。
可选地，在本公开实施例提供的上述显示基板中，在所述第二方向上，所述隔离部的宽度大于所述连接部的宽度。
可选地，在本公开实施例提供的上述显示基板中，所述屏蔽层位于所述源漏金属层与所述多条走线所在层之间，且所述屏蔽层还包括与所述多个连接部及所述多个隔离部相互独立的多个导电部；其中，每个所述导电部连接一条所述走线、及一个所述第一像素驱动电路。
可选地，在本公开实施例提供的上述显示基板中，所述屏蔽层与所述至少部分所述走线之外的其余所述走线同层设置，且所述屏蔽层还包括与所述多个连接部及所述多个隔离部相互独立的多个导电部，其中，每个所述导电部连接所述至少部分所述走线中的一条、及一个所述第一像素驱动电路。
可选地，在本公开实施例提供的上述显示基板中，所述隔离部浮空设置或加载直流信号。
可选地，在本公开实施例提供的上述显示基板中，还包括：位于所述源漏金属层且与所述栅极连接电极相邻设置的电源信号线，所述电源信号线在靠近所述栅极连接电极的一侧具有内凹结构；
所述隔离部与所述电源信号线上加载信号相同，所述隔离部在所述衬底 基板上的正投影覆盖所述内凹结构的正投影并与所述电源信号线的正投影部分交叠。
可选地，在本公开实施例提供的上述显示基板中，还包括：位于所述源漏金属层且与所述栅极连接电极相邻设置的电源信号线，所述电源信号线在靠近所述栅极连接电极的一侧具有内凹结构；
所述隔离部在所述衬底基板上的正投影与所述内凹结构的正投影相互交叠且与所述电源信号线的正投影互不交叠。
可选地，在本公开实施例提供的上述显示基板中，所述多个第一发光器件在所述第一显示区的密度小于所述多个第二发光器件在所述第二显示区的密度；
所述多个像素驱动电路位于所述第二显示区，各所述第一像素驱动电路位于各所述第二像素驱动电路的间隙处。
可选地，在本公开实施例提供的上述显示基板中，所述多个第一发光器件在所述第一显示区的密度等于所述多个第二发光器件在所述第二显示区的密度；
所述多个第一像素电路位于临近所述第一显示区的边框区域，所述多个第二像素驱动电路位于所述第二显示区。
可选地，在本公开实施例提供的上述显示基板中，所述第一显示区被配置为安装取光模组。
可选地，在本公开实施例提供的上述显示基板中，所述多条走线的材料为透明导电材料。
可选地，在本公开实施例提供的上述显示基板中，所述像素驱动电路还包括阈值补偿晶体管，所述栅极连接电极还与阈值补偿晶体管的漏极电连接。
另一方面，本公开实施例提供了一种显示面板，包括上述显示基板。
另一方面，本公开实施例提供了一种显示装置，包括：取光模组，以及上述显示面板；其中，所述取光模组被设置在所述显示面板的第一显示区。
附图说明
图1为本公开实施例提供的显示装置的一种结构示意图；
图2为图1中a区域的放大结构示意图；
图3为相关技术中亮度不均的原理图；
图4为图3中一个像素驱动电路的实际排布图；
图5为本公开实施例提供的显示基板的一种结构示意图；
图6为本公开实施例提供的显示基板的又一种结构示意图；
图7为沿图5中I-II线、沿图6中III—IV线的一种剖面结构示意图；
图8为沿图5中I-II线、沿图6中III—IV线的又一种剖面结构示意图；
图9为本公开实施例提供的显示装置的又一种结构示意图；
图10为图9中b区域的放大结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“内”、“外”、“上”、“下”等仅用于表 示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
如图1和图2所示，具有屏下摄像头结构的一种显示装置包括：第一显示区AA1和第二显示区AA2，摄像头可以设置在第一显示区AA1的位置处。具体地，第二显示区AA2中设有多个像素P和多个像素驱动电路D，其中，每一个像素P包括一个发光器件EL及对应的像素驱动电路D；而在第二显示区AA2内单独设置的像素驱动电路D用来控制第一显示区AA1的发光器件EL发光。具体地，第一显示区AA1的一个发光器件EL通过一条走线L与第二显示区AA2内的一个像素驱动电路D电连接。
一般地，像素驱动电路D中均具有驱动晶体管Td，在走线L跨越驱动晶体管Td的栅极时，会影响驱动晶体管Td的栅极电压，从而导致该像素驱动电路D电连接的发光器件EL的亮度发生改变。在此以像素驱动电路D为图3和图4所示7T1C的结构为例进行详细说明。在图3和图4所示7T1C结构的像素驱动电路D中，T1至T6、及Td代表不同的晶体管，Cst代表存储电容，N1至N8代表不同节点，D1至D4代表不同的转接部。具体的，图3和图4所示7T1C结构的像素驱动电路D驱动发光器件EL的发光过程可分为以下三个阶段：第一阶段，在复位信号端Re1的控制下，第一晶体管T1开启，使得第一初始化信号端Vin1对驱动晶体管Td的栅极(即N1节点)进行复位，其余晶体管处于截止状态。第二阶段，在扫描信号端Gn的控制下第二晶体管T2和第三晶体管T3开启，数据信号端Dm的信号经第三晶体管T3写入N2节点，并通过第二晶体管T2实现对驱动晶体管Td的阈值补偿；另外，在第二复位信号端Re2的控制下，第六晶体管T6开启，使得第二初始化信号端Vin2对发光器件EL的阳极(即N4节点)进行复位，其余晶体管处于截止状态。第三阶段，在发光控制信号端EM的控制下，第四晶体管T4和第五晶体管T5开启，此时由于存储电容Cst的存在，驱动晶体管Td在该阶段也处于开启状态，从而为发光器件EL提供驱动电流。然而，在走线L跨越单独设置的像素驱动电路D或像素P所含像素驱动电路D中驱动晶体管Td的栅极(即 N1节点)时，该走线L与N1节点之间会形成一个较大的电容C_L_N1，在发光控制信号端EM的信号打开后N1节点的电压发生跳变，并且因走线L与多个像素驱动电路D所含N1节点的电容并不完全相同，故造成亮度不均。
针对相关技术中存在的上述技术问题，本公开实施例提供了一种显示基板，如图1、图2、图5至图8所示，包括：
衬底基板101，该衬底基板101的显示区域AA包括：第一显示区AA1和第二显示区AA2，其中，第一显示区AA1的透光率大于第二显示区AA2的透光率；
多个发光器件EL，在衬底基板101上呈阵列排布；多个发光器件EL包括：位于第一显示区AA1的多个第一发光器件102，以及位于第二显示区AA2的多个第二发光器件103；
多个像素驱动电路D，位于衬底基板101与多个发光器件EL所在层之间；多个像素驱动电路D包括：多个第一像素驱动电路104和多个第二像素驱动电路105；其中，多个第一像素驱动电路104与多个第一发光器件102对应电连接，多个第二像素驱动电路105与多个第二发光器件103相互至少部分交叠并对应电连接；多个像素驱动电路D中的至少一个具有驱动晶体管Td；
栅极连接电极106(即N1节点)，连接所述驱动晶体管的栅极；
多条走线107，位于多个像素驱动电路D所在层与多个发光器件EL所在层之间；至少部分走线107中的每一条分别自至少一个第一像素驱动电路104跨越至少一个栅极连接电极106与至少一个第一发光器件102电连接；
屏蔽层108，包括多个隔离部1081，至少一个隔离部1081在衬底基板101上的正投影与至少一个栅极连接电极106(即N1节点)在衬底基板101上的正投影至少部分交叠。
在本公开实施例提供的上述显示基板中，在至少部分走线107跨越至少一个栅极连接电极106(即N1节点)时，隔离部1081可以有效屏蔽走线107上的信号对驱动晶体管Td所含栅极连接电极106上电压的干扰，使得该栅极连接电极106(即N1节点)所在像素驱动电路D提供的驱动电流不会发生跳 变，从而提高了发光亮度的均一性。
需要说明的是，在本公开中第一显示区AA1的形状可以为图1所示的正方形，也可以为圆形等其他形状，具体可根据实际需要进行设计，在此不做限定。第二显示区AA2可以环绕第一显示区AA1的周边，也可以如图1所示包围部分第一显示区AA1，具体为包围第一显示区AA1的左侧、下侧和右侧，而第一显示区AA1的上侧边界与第二显示区AA2的上侧边界重合。
可选地，在本公开实施例提供的上述显示基板中，如图7和图8所示，为了实现较好的屏蔽效果，包含多个隔离部1081的屏蔽层108可以位于上述至少部分走线107所在层与栅极连接电极106所在层之间。
可选地，在本公开实施例提供的上述显示基板中，如图5和图6所示，各栅极连接电极106(即N1节点)可以在第一方向X上排列并在第二方向Y上延伸，相应地，各隔离部1081也在第一方向X上排列并在第二方向Y上延伸，以更好地屏蔽走线107上的信号对栅极连接电极106(即N1节点)的干扰。
可选地，在本公开实施例提供的上述显示基板中，为了实现屏蔽部1081的屏蔽作用，屏蔽层108的材料可以为本身具有屏蔽属性的铜、钼、铝等金属材料或氧化铟锡等透明导电材料。并且，在具体实施时，可将隔离部1081浮空设置(即不加载信号)或加载直流信号。可选地，直流信号可以为高电平(VDD)信号、低电平(VSS)信号、初始化(Vin)信号等。
可选地，在本公开实施例提供的上述显示基板中，如图5所示，屏蔽层108还可以包括多个连接部1082，每一个连接部1082连接第一方向X上的两个隔离部1081。通过连接部1082可以将同一行隔离部1081连接成一体结构，从而便于向各隔离部1081加载直流信号。当然，也可以为每个隔离部1081分别单独布线，以对应加载直流信号，在此不做限定。
可选地，在本公开实施例提供的上述显示基板中，由于连接部1082可能与其他导电膜层之间相互交叠产生寄生电容，因此，为了尽可能减小寄生电容，如图5所示，在第二方向Y上，连接部1082的宽度可以小于隔离部1081 的宽度。
在本公开中多条走线107可以同层设置，也可以异层设置。并且如图2所示，由于沿行方向延伸的每一走线107在列方向上具有一定的宽度，而像素在列方向上的尺寸也是一定的，因此第一显示区AA1内每行像素的数量受到了限制；然而在多条走线107异层设置时，则可以在列方向上一定尺寸范围内提供更多的走线107，以驱动更多的第一发光器件102，进而满足第一显示区AA1与第二显示区AA2具有相同分辨率，由此可提高整体显示效果。
具体地，在本公开实施例提供的上述显示基板中，在多条走线107同层设置时，如图7所示，屏蔽层108可以位于源漏金属层与多条走线107所在层之间，且屏蔽层108还可以包括与多个连接部1082及多个隔离部1081相互独立的多个导电部1083；其中，每个导电部1083连接一条走线107、及一个第一像素驱动电路104(具体为第一像素驱动电路104的N4节点)，且走线107延伸至与第一显示区AA的第一发光器件102电连接。
在多条走线107异层设置时，如图8所示，屏蔽层108可以与至少部分走线107(即跨越栅极连接电极106的走线107)之外的其余走线107(即未跨越栅极连接电极106的走线107)同层设置，且屏蔽层108还可以包括与多个连接部1082及多个隔离部1081相互独立的多个导电部1083，其中，每个导电部1083连接至少部分走线107中的一条、及一个第一像素驱动电路(具体为第一像素驱动电路104的N4节点)，且走线107延伸至与第一显示区AA的第一发光器件102电连接。
可选地，在本公开实施例提供的上述显示基板中，如图6所示，还可以包括：位于源漏金属层与栅极连接电极106相邻设置的电源信号线109，该电源信号线109在靠近栅极连接电极106的一侧具有内凹结构H；
隔离部108与电源信号线109上加载相同的信号(例如VDD信号)，此时隔离部108在衬底基板101上的正投影可以覆盖内凹结构H的正投影并与电源信号线109的正投影部分交叠。在此情况下，电源信号线109上的内凹结构H主要用于避让栅极连接电极106(即N1节点)，避免了电源信号线109 与栅极连接电极106(即N1节点)上信号之间相互干扰。
可选地，在本公开实施例提供的上述显示基板中，如图5所示，还可以包括：位于源漏金属层与栅极连接电极106相邻设置的电源信号线109，该电源信号线109在靠近栅极连接电极106的一侧具有内凹结构H；隔离部108在衬底基板101上的正投影与内凹结构H的正投影相互交叠且与电源信号线109的正投影互不交叠。通过在电源信号线109上设置避让隔离部108的内凹结构H，避免了电源信号线109、与栅极连接电极106(即N1节点)的信号分别与隔离部108的信号之间相互干扰。
需要说明的是，在本公开中源漏金属层具体可以指驱动晶体管的源极和漏极所在的金属层。在一些实施例中，栅极连接电极106可以位于源漏金属层。
可选地，在本公开实施例提供的上述显示基板中，如图2所示，多个第一发光器件102在第一显示区AA1的密度可以小于多个第二发光器件103在第二显示区AA2的密度；相应地，与多个第一发光器件102对应电连接的多个第一像素驱动电路104、及与多个第二发光器件103对应电连接的多个第二像素驱动电路105均位于第二显示区AA2，各第一像素驱动电路104具体位于各第二像素驱动电路105的间隙处。或者，如图9和图10所示，多个第一发光器件102在第一显示区AA1的密度还可以等于多个第二发光器件103在第二显示区AA2的密度；相应地，与多个第一发光器件102对应电连接的多个第一像素驱动电路104位于临近第一显示区AA1的边框区域BB，与多个第二发光器件103对应电连接的多个第二像素驱动电路105位于第二显示区AA2。或者，在一些实施例中，第一显示区AA1的中间区域可以为摄像头所在区域，且在中间区域仅设置第一有发光器件EL，第一显示区AA1的边缘区域可以设置第一像素驱动电路104、第二像素驱动电路105、及与第二像素驱动电路105至少部分交叠的第二发光器件103；第二显示区AA2为正常显示区域，设置有第二像素驱动电路105、及与第二像素驱动电路105至少部分交叠的第二发光器件103；并且，第二发光器件103在第一显示区AA1的边 缘区域的密度，大于第一发光器件102在第一显示区AA1的中间区域的密度，且小于第二发光器件103在第二显示区AA2的密度。
另外，在本公开实施例提供的上述显示基板中，如图5至图8所示，还可以包括：位于源漏金属层的数据线110、位于多条走线107之上的多个阳极111、位于源漏金属层与屏蔽层108之间的第一绝缘层112、位于屏蔽层108与至少部分走线107所在层之间的第二绝缘层113、位于至少部分走线107所在层与多个阳极111所在层之间的平坦层114、以及限定多个阳极111位置的像素界定层115。对于其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
可选地，在本公开实施例提供的上述显示基板中，第一显示区AA1被配置为安装取光模组，例如摄像头模组、光学指纹识别模组、环境光传感器等。
可选地，在本公开实施例提供的上述显示基板中，多条走线107的材料可以为透明导电材料，以提高第一显示区AA1的透光率。
可选地，在本公开实施例提供的上述显示基板中，像素驱动电路D还包括阈值补偿晶体管，栅极连接电极106还可以与阈值补偿晶体管的漏极电连接。通过设置栅极连接电极10连接驱动晶体管的栅极和阈值补偿晶体管的漏极，可以使得阈值补偿晶体管对驱动晶体管的阈值进行补偿，从而有效避免了不同像素驱动电路D所含驱动晶体管的阈值不同导致的驱动电流不同，进而保证了发光亮度的均一性。
另一方面，本公开实施例还提供了一种显示面板，包括本公开实施例提供的上述显示基板。
可选地，该显示面板可以为有机电致发光显示面板(OLED)、量子点发光显示面板(QLED)、或微发光二极管显示面板(Micro LED)。由于该显示面板解决问题的原理与上述显示基板解决问题的原理相似，因此，本公开实施例提供的该显示面板的实施可以参见本公开实施例提供的上述显示基板的实施，重复之处不再赘述。
另一方面，本公开实施例还提供了一种显示装置，包括：取光模组(例 如摄像头模组)，以及上述显示面板；其中，取光模组被设置在显示面板的第一显示区AA1。
该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、智能手表、健身腕带、个人数字助理等任何具有显示功能的产品或部件。对于显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。另外，由于该显示装置解决问题的原理与上述显示面板解决问题的原理相似，因此，该显示装置的实施可以参见上述显示面板的实施例，重复之处不再赘述。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (17)

  1. 一种显示基板，其中，包括：
    衬底基板，所述衬底基板的显示区域包括：第一显示区和第二显示区，其中，所述第一显示区的透光率大于所述第二显示区的透光率；
    多个发光器件，在所述衬底基板上呈阵列排布；所述多个发光器件包括：位于所述第一显示区的多个第一发光器件，以及位于所述第二显示区的多个第二发光器件；
    多个像素驱动电路，位于所述衬底基板与所述多个发光器件所在层之间；所述多个像素驱动电路包括：多个第一像素驱动电路和多个第二像素驱动电路；其中，所述多个第一像素驱动电路与所述多个第一发光器件对应电连接，所述多个第二像素驱动电路与所述多个第二发光器件相互至少部分交叠并对应电连接；所述多个像素驱动电路中的至少一个具有驱动晶体管；
    栅极连接电极，连接所述驱动晶体管的栅极；
    多条走线，位于所述多个像素驱动电路所在层与所述多个发光器件所在层之间；至少部分所述走线中的每一条分别自至少一个所述第一像素驱动电路跨越至少一个所述栅极连接电极与至少一个所述第一发光器件电连接；
    屏蔽层，包括多个隔离部，至少一个所述隔离部在所述衬底基板上的正投影与至少一个所述栅极连接电极在所述衬底基板的正投影至少部分交叠。
  2. 如权利要求1所述的显示基板，其中，所述屏蔽层位于所述至少部分所述走线所在层与所述栅极连接电极所在层之间。
  3. 如权利要求1所述的显示基板，其中，各所述栅极连接电极在第一方向上排列并在第二方向上延伸，各所述隔离部在所述第一方向上排列并在所述第二方向上延伸。
  4. 如权利要求3所述的显示基板，其中，所述屏蔽层还包括多个连接部，每一个所述连接部连接所述第一方向上的两个所述隔离部。
  5. 如权利要求4所述的显示基板，其中，在所述第二方向上，所述隔离 部的宽度大于所述连接部的宽度。
  6. 如权利要求5所述的显示基板，其中，所述屏蔽层位于所述源漏金属层与所述多条走线所在层之间，且所述屏蔽层还包括与所述多个连接部及所述多个隔离部相互独立的多个导电部；其中，每个所述导电部连接一条所述走线、及一个所述第一像素驱动电路。
  7. 如权利要求5所述的显示基板，其中，所述屏蔽层与所述至少部分所述走线之外的其余所述走线同层设置，且所述屏蔽层还包括与所述多个连接部及所述多个隔离部相互独立的多个导电部，其中，每个所述导电部连接所述至少部分所述走线中的一条、及一个所述第一像素驱动电路。
  8. 如权利要求1所述的显示基板，其中，所述隔离部浮空设置或加载直流信号。
  9. 如权利要求1-3任一项所述的显示基板，其中，还包括：位于所述源漏金属层且与所述栅极连接电极相邻设置的电源信号线，所述电源信号线在靠近所述栅极连接电极的一侧具有内凹结构；
    所述隔离部与所述电源信号线上加载信号相同，所述隔离部在所述衬底基板上的正投影覆盖所述内凹结构的正投影并与所述电源信号线的正投影部分交叠。
  10. 如权利要求4-8任一项所述的显示基板，其中，还包括：位于所述源漏金属层且与所述栅极连接电极相邻设置的电源信号线，所述电源信号线在靠近所述栅极连接电极的一侧具有内凹结构；
    所述隔离部在所述衬底基板上的正投影与所述内凹结构的正投影相互交叠且与所述电源信号线的正投影互不交叠。
  11. 如权利要求1-10任一项所述的显示基板，其中，所述多个第一发光器件在所述第一显示区的密度小于所述多个第二发光器件在所述第二显示区的密度；
    所述多个像素驱动电路位于所述第二显示区，各所述第一像素驱动电路位于各所述第二像素驱动电路的间隙处。
  12. 如权利要求1-10任一项所述的显示基板，其中，所述多个第一发光器件在所述第一显示区的密度等于所述多个第二发光器件在所述第二显示区的密度；
    所述多个第一像素电路位于临近所述第一显示区的边框区域，所述多个第二像素驱动电路位于所述第二显示区。
  13. 如权利要求1-12任一项所述的显示基板，其中，所述第一显示区被配置为安装取光模组。
  14. 如权利要求1-13任一项所述的显示基板，其中，所述多条走线的材料为透明导电材料。
  15. 如权利要求1-14任一项所述的显示基板，其中，所述像素驱动电路还包括阈值补偿晶体管，所述栅极连接电极还与阈值补偿晶体管的漏极电连接。
  16. 一种显示面板，其中，包括如权利要求1-15任一项所述的显示基板。
  17. 一种显示装置，其中，包括：取光模组，以及如权利要求16所述的显示面板；其中，所述取光模组被设置在所述显示面板的第一显示区。
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CN111326560A (zh) * 2020-01-23 2020-06-23 京东方科技集团股份有限公司 显示基板和显示装置
CN111668278A (zh) * 2020-06-29 2020-09-15 武汉天马微电子有限公司 一种显示面板及显示装置

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