WO2022086540A1 - Ensemble de circuits logique - Google Patents

Ensemble de circuits logique Download PDF

Info

Publication number
WO2022086540A1
WO2022086540A1 PCT/US2020/056857 US2020056857W WO2022086540A1 WO 2022086540 A1 WO2022086540 A1 WO 2022086540A1 US 2020056857 W US2020056857 W US 2020056857W WO 2022086540 A1 WO2022086540 A1 WO 2022086540A1
Authority
WO
WIPO (PCT)
Prior art keywords
image transfer
circuit
print
logic circuit
image
Prior art date
Application number
PCT/US2020/056857
Other languages
English (en)
Inventor
Boon Bing NG
John Rossi
James Michael GARDNER
Scott A. Linn
Michael W. Cumbie
Original Assignee
Hewlett-Packard Development Company, L.P.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett-Packard Development Company, L.P. filed Critical Hewlett-Packard Development Company, L.P.
Priority to PCT/US2020/056857 priority Critical patent/WO2022086540A1/fr
Publication of WO2022086540A1 publication Critical patent/WO2022086540A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/015—Ink jet characterised by the jet generation process
    • B41J2/04—Ink jet characterised by the jet generation process generating single droplets or particles on demand
    • B41J2/045—Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
    • B41J2/04501—Control methods or devices therefor, e.g. driver circuits, control circuits
    • B41J2/04541—Specific driving circuit
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/015—Ink jet characterised by the jet generation process
    • B41J2/04—Ink jet characterised by the jet generation process generating single droplets or particles on demand
    • B41J2/045—Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
    • B41J2/04501—Control methods or devices therefor, e.g. driver circuits, control circuits
    • B41J2/0458—Control methods or devices therefor, e.g. driver circuits, control circuits controlling heads based on heating elements forming bubbles
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/015—Ink jet characterised by the jet generation process
    • B41J2/04—Ink jet characterised by the jet generation process generating single droplets or particles on demand
    • B41J2/045—Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
    • B41J2/04501—Control methods or devices therefor, e.g. driver circuits, control circuits
    • B41J2/04581—Control methods or devices therefor, e.g. driver circuits, control circuits controlling heads based on piezoelectric elements
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/17—Ink jet characterised by ink handling
    • B41J2/175—Ink supply systems ; Circuit parts therefor
    • B41J2/17503—Ink cartridges
    • B41J2/17543—Cartridge presence detection or type identification
    • B41J2/17546—Cartridge presence detection or type identification electronically

Definitions

  • FIG. 1 is a diagram of an example of an image transfer component
  • FIG. 2 is a diagram representing another example of an image transfer component
  • FIG. 3 is a diagram of an example of an image transfer system
  • FIG. 4 is a diagram of another example of an image transfer system.
  • Fig. 5 is a diagram of another example of an image transfer component.
  • 2D and 3D image transfer components may be associated with logic circuitry that receive image transfer instructions from host-side logic circuitry of the print apparatus in which they are installed.
  • Inter-integrated Circuit (l 2 C, or I2C, which notation is adopted herein) protocol allows at least one ‘master’ integrated circuit (IC) to communicate with at least one ‘slave’ IC, for example via a bus.
  • I2C, and other communications protocols communicate data according to a clock frequency. For example, a voltage signal may be generated, where the value of the voltage is associated with data. For example, a voltage value above x volts may indicate a logic “1” whereas a voltage value below x volts may indicate a logic “0”, where x is a predetermined numerical value.
  • a voltage value above x volts may indicate a logic “1”
  • a voltage value below x volts may indicate a logic “0”, where x is a predetermined numerical value.
  • Host or master logic circuitry within a print apparatus may receive information from logic circuitry associated with a replaceable print apparatus component via a communications interface, and/or may send commands to the replaceable print apparatus component logic circuitry, which may comprise commands to write data to a memory associated therewith, or to read data therefrom.
  • Certain example print material containers have slave logic that utilize I2C communications, although in other examples, other forms of digital or analogue communications could also be used.
  • a master IC may generally be provided as part of the print apparatus (which may be referred to as the ‘host’) and a replaceable print apparatus component may comprise a counterpart ‘slave’ IC.
  • the slave IC(s) may comprise a processor to perform data operations before responding to requests from logic circuitry of the print system.
  • slave ICs are sometimes referred to as logic circuits.
  • Certain example slave ICs or logic circuits may function as secure microcontrollers.
  • print apparatus components which may include replaceable print apparatus components such as image transfer circuits.
  • Image transfer circuits may include printheads or toner transfer components such as electrophotographic developer rollers or photosensitive drums and/or toner reservoirs provided with logic.
  • Certain print apparatus components may include a reservoir holding print agent or print material.
  • print material includes any 2D or 3D print agent.
  • the print material encompasses different example print materials including ink, toner particles, liquid toner, three-dimensional printing agents (including stimulators and inhibitors), three- dimensional printing build material, three-dimensional print powder.
  • the disclosed principles and features in this disclosure could apply to other high precision integrated circuitry components including MEMS devices, lab-on-chips, digital titration dispensers, fluid propelling and/or diagnostic components for diagnostic, laboratory, forensic and/or medical applications, which components are provided with a relatively high precision capability and a logic communication circuit similar to certain image transfer components, sometimes involving the handling or sensing of materials or fluids at micro-, nano- or pico-sized volumes, resolutions, weights, etc. (e.g., micrometers, microliters, micrograms, nanometers, nanoliters, nanograms, picometers, picoliters, picograms, etc.).
  • Some of these other high precision components may have similar aspects as printhead dies.
  • the illustrated image transfer components may involve components for other types of high precision handling or sensing, not necessarily image transfer.
  • Certain components of this disclosure may provide for authentication functions to the above high precision replaceable components, for example, to raise the technical barrier to produce the components that are compatible with original equipment manufacturer host apparatuses. Certain features described in this disclosure may provide for certain authentication functions without adding too much latency to the inherent capabilities of the components, such as image transfer, fluid propelling, diagnostics, etc. Certain features of this disclosure may add functionality and/or security to replaceable components while only increasing the current consumption of the system (i.e., assembly of host and replaceable component) to an acceptable level or not at all. In some examples where additional secure logic is added to the image transfer circuitry this is done without adding too many unique interface connection points, internal wires, ortraces to the package. The integration of different circuitry types may be achieved while controlling costs and failure points. In certain examples, system monitoring (e.g., checking for ink shorts) and/or overall reliability may be increased.
  • Fig. 1 discloses an example of an imaging transfer component 1.
  • the component 1 may be adapted for replacement with respect to a host print apparatus.
  • the component is a replaceable printhead cartridge and the host print apparatus is a printer adapted to receive one or more of these cartridges.
  • the image transfer component 1 may be adapted to be replaced with respect to the host print apparatus in its entirety.
  • the component 1 may be a printhead assembly or toner image transfer device.
  • 1 could involve other components replaceable with respect to a host device, such as, for example, lab-on-chips, micro-electromechanical systems, biofluidics, digital titration dispensers, fluid propelling and/or diagnostic components for diagnostic, laboratory, forensic and/or medical applications.
  • a host device such as, for example, lab-on-chips, micro-electromechanical systems, biofluidics, digital titration dispensers, fluid propelling and/or diagnostic components for diagnostic, laboratory, forensic and/or medical applications.
  • the imaging transfer component 1 comprises a communications interface 3 to communicate with a host print apparatus, or, more specifically, with a logic circuit of the host print apparatus.
  • the interface 3 may be provided with a plurality of interface contacts.
  • the communication interface 3 may be adapted to communicate with a host controller of the host print apparatus via mating compatible interface contacts of the host print apparatus.
  • the interface contacts of the component 1 are to communicate the image transfer component 1 with the host logic circuit and may be referred to as interfaces or contacts.
  • the logic circuit of the host print apparatus comprises hardware and firmware including a logic controller with CPU and/or a secure microcontroller. Separate host logical hardware components may communicate through a single interface contact array that is provided on the same surface.
  • the image transfer component 1 comprises high precision logic, in this example an image transfer circuit 5 adapted to transfer an image to print media based on print instructions received over the interface 3 from the host print apparatus.
  • the print instructions may comprise print image data on the basis of which the image transfer circuit 5 can transfer a pattern, in accordance with a source digital image, onto or at least towards media.
  • the image transfer circuit 5 may include a printhead or toner transfer drum or the like, provided with circuitry for transferring patterns towards media.
  • Printhead may print directly onto media while certain toner image transfer components may use intermediate transfer rollers or the like so that the image may be directly or indirectly transferred to the media.
  • Typical print media includes paper but could also refer to additive manufacturing build powder or other 2D or 3D print media.
  • image transfer circuitry 5 instead of image transfer circuitry 5 other high precision circuitry types with similar features could be used such as lab-on-chips, MEMS, biofluidics, digital titration dispensing dies, fluid propelling dies and/or diagnostic circuits for diagnostic, laboratory, forensic and/or medical applications.
  • image transfer circuits 5 For the sake of explaining the illustration of Fig. 1 , reference will be made to image transfer circuits 5 but the skilled person will understand that other yet similar circuitry types may be applied, that may be similarly provided with integrated circuitry to handle or sense fluids or other materials at high precision.
  • the image transfer component 1 of Fig. 1 may further include second logic, in this example a logic circuit 7.
  • the logic circuit 7 may comprises a CPU 17 and memory 19.
  • the logic circuit 7 is, or functions as, a secure microcontroller, for example to exchange authenticated communications with a host print apparatus and/or a distant secure network server.
  • the component 1 may include different integrated circuitries with respective first and second logic, each on a different substrate and/or in different packaging.
  • the logic circuit may be provided in an integrated circuitry packaging and the image transfer circuit 5 may be provided in a printhead die packaging, whereby both may be housed in or on the component 1 .
  • the logic circuit 7 may be configured to cryptographically authenticate communications.
  • the logic circuit 7 and image transfer circuit 5 may be provided in distinct integrated circuitry packages, having distinct substrates and/or distinct substrates and/or thin film layers.
  • the logic circuit 7 and image transfer circuit 5 could be a secure chip and a thin film MEMS, respectively.
  • the separate logic circuit 7 and image transfer 5 packages could be embedded in, or commonly supported by, a base structure 11 and/or housing component 9.
  • the housing component 9 may comprise a reservoir with imaging material inside, such as ink or toner or 3D print agent/inhibitor.
  • a single base structure may be used for supporting both the image transfer circuit 5 and logic circuit 7.
  • the single base structure may comprise molded packaging material and may at least partially embed the logic circuit 7 and the image transfer circuit 5.
  • the logic circuit 7 is not qualifiable as a secure microcontroller.
  • the logic circuit 7 and image transfer circuit 5 could be integrated into a single larger integrated circuitry package, for example supported by a common substrate and/or using common thin film layers.
  • Fig. 2 illustrates another example of an imaging transfer component 1 .
  • the logic circuit 7 is configured to, in response to at least one enable instruction 15 from the host apparatus, over the interface 3, generate a device signal 21 to enable at least one function of the image transfer circuit 5.
  • the function may include image transfer, the image transfer circuit 5 to transfer the image only after being enabled by the device signal 21.
  • the enable instruction 15 may be sent by the host apparatus through the interface 3.
  • the image transfer component 1 may include a device signal line 13 between the logic circuit 7 and the image transfer circuit 5, as illustrated in Fig. 1 .
  • the device signal line 13 may be connected to a second interface contact of the logic circuit 7, separate from the communications interface 3 that is to communicate with a host logic circuit.
  • the device signal 21 may be a digital or analog signal sent over the device signal line 13, such as a data signal.
  • the logic circuit 7 may be configured to enable printing by the image transfer circuit 5 in a securely authenticated manner over the device signal line 13. In other examples, the logic circuit 7 may be configured to enable other handling or sensing functions by other high precision circuits in the securely authenticated manner over the device signal line.
  • the first device signal provides for a one-time reset signal, whereby the image transfer circuit 5 is configured to be reset based on the device signal. After such device signal the image transfer circuit 5 may be enabled.
  • the logic circuit 7 may maintain an active device signal for a controlled time period, based on the enable instruction, during which time period the image transfer circuit 5 is enabled to print.
  • control logic 29 may be configured to enable the image transfer circuit 5 in response to the active device signal 21.
  • the image transfer circuit 5 may only be enabled to print once securely enabled by the device signal of logic circuit 7.
  • the common interface 3 is connected, and configured to transmit instructions, to both the logic circuit 7 and the image transfer circuit 5.
  • the enable instruction 15 to the logic circuit 7 may be of a first protocol compliant with the logic circuit 7.
  • Print instructions 23 between the host print apparatus and the image transfer circuit 5 may be of a different protocol, not compliant with the first protocol.
  • the first protocol may be an industry standard digital communications protocol, for example a serial data communications protocol such as an I2C protocol as addressed earlier.
  • the print instructions 23 may be of a custom data protocol for image transfer, for example developed by an original equipment manufacturer for image transfer products also developed by that original equipment manufacturer.
  • the enable instructions and print instructions complying to the different protocols may be sent, at least partly, over a single common data contact.
  • the first protocol and the custom image transfer protocol may use different clock frequencies, whereby the different clock signals/frequencies are transmitted over a single common clock contact for both the image transfer circuit and logic circuit.
  • Package and manufacturing costs may be controlled on either host and/or component side by sharing contacts. Also, additional security may be obtained by sharing common data and/or clock contacts.
  • non-printing components such as diagnostics or other MEMS-type devices may be similarly enabled by the logic circuit 7 to execute their non-image transfer or sense function, and similarly, different protocols may be used over a common interface. In a similar way additional security and/or relative cost benefits may be obtained for those other devices.
  • a secure logic circuit 7 stores at least one base key 25 in a memory 19.
  • the portion of the memory 19 that stores the base key 25 is adapted to be difficult to access by external devices.
  • the memory 19 stores multiple base keys 25.
  • the base key 25 may be associated with at least one corresponding host-side base key.
  • the host-side base key may be associated with multiple base keys 25 of multiple image transfer components, such as multiple compatible cartridges of holding different color print materials.
  • the logic circuit 7 may be configured to generate a different session key for each of a plurality of communication sessions with the host print apparatus, each session key based on the at least one base key 25.
  • the logic circuit 7 may be configured to cryptographically authenticate each enable instruction 15 using the thus calculated session key.
  • the host print apparatus and logic circuit 7 may be configured to transmit session key identifiers to facilitate the opposite side to generate the session key based on its respective base key for each communication exchange.
  • the logic circuit 7 may be configured to generate a message authentication code to match a message authentication code of the enable instruction, for said authentication, using the session key.
  • a secure cryptographic authentication system including both a host and replaceable component is, amongst others, described in US patent No. US9619663B2, hereby incorporated by reference.
  • the memory 19 may store secure authentication instructions 27 to, when executed by the CPU 17, generate said session keys, session key identifiers and/or message authentication codes.
  • Other example logic circuits may use other secure authentication processes and algorithms to establish secure authentication, for example using a different type of cryptography and/or passwords.
  • the device signal 21 includes one or more discrete signals to lock and/or unlock the image transfer circuit 5 for image transfer.
  • the logic circuit 7 is configured to send or activate the device signal 21 in response to the enable instructions 15.
  • the image transfer circuit 5 may comprise control logic 29 configured to enable the image transfer circuit 5 based on a single, discrete, analog or digital signal over the device signal line 13, after which the image transfer circuit 5 is unlocked to transfer an image based on print instructions 23 transmitted by the host print apparatus.
  • a discrete device signal may also be used to lock the image transfer circuit 5.
  • the device signal 21 is a continuous signal to enable the image transfer circuit 5 for image transfer, whereby image transfer is only possible while the device signal 21 is active.
  • the device signal 21 may be represented by a continuous data stream, or by a certain high or low voltage state over the device signal line 13, or another predetermined measurable state of the line 13.
  • the logic circuit 7 may be configured to output a reset signal, followed by a continuous device signal. In this disclosure, such reset signal from the logic circuit 7 is also considered as a device signal 21.
  • a continuous device signal 21 may disable an image transfer function of the image transfer circuit 5 while such device signal is active, whereby the image transfer may be enabled once the signal stops.
  • the image transfer circuit 5 may comprise control logic 29 configured to enable certain functions of the image transfer circuit 5, such as image transfer.
  • the control logic 29 may be configured to enable image transfer while a device signal 21 is active, during which the image transfer circuit 5 may be unlocked to transfer the image, based on print instructions 23 transmitted by the print apparatus.
  • the control logic 29 may be configured to lock, disable, or at least not enable image transfer in the image transfer circuit 5, for example while the device signal 21 is not present.
  • the logic circuit 7 may be configured to drive the device signal for a given time duration, or for a selected one of multiple time durations.
  • the enable instruction or a separate command may include a time parameter that determines the time duration, and/or, a memory 19 of the logic circuit 7 may store one or more time parameters for determining the duration.
  • the continuous device signal 21 may expire at the end of the duration.
  • the image transfer circuit is configured to print after a single, e.g., discrete, enabling device signal 21 , after which it remains enabled for at least an entire print job.
  • the logic circuit 7 is configured to require a power cycle before reenabling the image transfer circuit 5, which in one example may be initiated by the host print apparatus.
  • the control logic 29 may be configured to control communications between the host logic circuit and the logic circuit 7, as indicated by arrow 45.
  • the control logic 29 may be configured to set a data line that communicates over the interface 3 with the logic circuit 7 to a high or low logical voltage state whereby communications may be transmitted to/from the logic circuit 7 in the high state and communications may be inhibited in the low state.
  • the data line, controllable by the control logic 29, may then be “safely” used to communicate with the image transfer circuit 5.
  • the control logic 29 may control a state of the data interface line or component-side pad, to control whether communications are transmitted to the logic circuit 7 or the image transfer circuit 5 without conflict or overlap between both.
  • control logic 29 may be configured to enable or disable communications to/from the logic circuit 7, only the control function/control logic 29 in the image transfer circuit 5 is enabled by the logic circuit 5 through the device signal 21 .
  • control logic 129 of the image transfer circuit 105 may be configured to enable the image transfer circuit 105 for image transfer based on (i) the device signal A_NRESET from the logic circuit 107 and (ii) a second signal NRESET from the host print apparatus over the interface 103.
  • the latter signal NRESET may be transmitted directly by a host print apparatus logic circuit 131 without interference from the logic circuit 107.
  • the device signal A_NRESET may be generated by the logic circuit 107 on the device line 113 in response to an enable instruction from the host print apparatus logic circuit 131 , as previously explained.
  • the device line 113 connects to a GPIO contact of the logic circuit 107 and a data contact of the image transfer circuit 105.
  • the GPIO contact of the logic circuit 107 may not be a part of the interface 103 to the host logic circuit 113, or at least the logic circuit 107 is not configured to communicate with the host logic circuit 113 overthe GPIO pad.
  • the GPIO pad is provided outside of the interface contact array configured to contact the host logic circuit, on a different surface or plane.
  • the image transfer circuit 105 comprises control logic 129 to enable image transfer while both the device signal A_NRESET and second signal NRESET are present.
  • the device signal A_NRESET and second signal NRESET are continuous whereby communications to and/or image transfer by the image transfer circuit 105 are enabled while both are active.
  • the device signal A_NRESET and second signal NRESET need not be continuous whereby image transfer can be enabled once both have been active, e.g., concurrently.
  • the control logic 129 may comprise an AND gate 135 for enabling the image transfer circuit 105 only when both said signals A_NRESET and NRESET are, or have been, active.
  • the control logic 129 may generate its own output enable signal over an output line or routing 133 to enable certain functions, such as communications over the interface 103 and/or image transfer, in the image transfer circuit 105 or the logic circuit 107.
  • the control logic 129 can be provided on the image transfer circuit die and/or can connect to a reset pad on the image transfer circuit die.
  • the output 133 of the control logic 129 may drive or activate digital blocks in the image transfer circuit 105. It is noted that for certain use cases the control logic includes an AND-gate 135 while in other embodiments different or more complex logic may be included.
  • Some of the mentioned discrete and continuous device signals may be static device signals.
  • the logic circuit 107 may be configured to generate the static device signal.
  • the static signal may be a reset signal, for example a discrete or continuous reset signal.
  • the static signal may be a power signal, for example a continuous power signal or a discrete power on signal.
  • the static signals are analog signals. These static signals may enable the image transfer circuit 105.
  • the logic circuit 7, 107 may be configured to generate dynamic device signals, for example (an) image transfer setting(s) or print image data.
  • the image transfer circuit 5, 105 may be configured to print patterns based on the print image data, for example, to eject fluid through printhead die actuators/nozzles based on input print image data.
  • the image transfer circuit 5, 105 comprises a printhead die and the print instructions are to address actuators in the printhead die to eject liquid from the associated nozzles.
  • the print instructions may be directly based on digital source image data of a print job.
  • the image transfer circuit 5, 105 may be configured to be “set” by the image transfer setting signals so that different colors, shades or patterns are printed based on the same input print image data, yet corresponding to different image transfer settings.
  • the image transfer settings comprise a printhead nozzle actuator address order
  • the image transfer circuit includes a printhead circuit including actuator and nozzle arrays to eject imaging liquid onto media applying said printhead nozzle actuator address order to the print instructions.
  • these actuators may comprise heater resistors and/or piezo-actuated devices.
  • certain registers on a printhead die or toner transfer component circuitry may be set by the image transfer settings.
  • the dynamic device signals may be digital data signals, or at least represent digital data.
  • the logic circuit 7, 107 is configured to receive the enable instructions 15 comprising first image transfer circuit settings and/or print image data and convert the received first image transfer settings and/or print image data to second image transfer settings and/or second print image data, respectively, in accordance with a custom protocol of the image transfer circuit 5, 105.
  • the image transfer circuit 5, 105 is configured to transfer the image based on the second image transfer settings and/or print image data, respectively.
  • the image transfer component is configured to always print based on the second print image data generated by the logic circuit 107.
  • the image transfer component is configured to print based on first and/or second print data as generated by either the host print apparatus logic circuit 131 or the logic circuit 107, respectively.
  • the communication interface 103 comprises at least one of a data interface 115, 123 and clock interface 137.
  • the logic circuit 107 is configured to process communications based on a first clock frequency over the clock interface 137
  • the image transfer circuit 105 is configured to transfer the image to print media based on a second clock frequency, different than the first clock frequency, via the same clock interface 137.
  • the image transfer component 101 may include a first clock interface routing 137A connected to the common clock interface 137 and the logic circuit 107.
  • the image transfer component 101 may include a second clock interface routing 137B connected to the common clock interface 137 and the image transfer circuit 105.
  • the first clock frequency is an I2C clock frequency.
  • the second clock frequency may be higher than the first clock frequency, for example to facilitate an appropriate image transfer speed.
  • the data interface 115, 123 and/or clock interface 137 may be configured to communicate with the image transfer circuit 105 using a different protocol than I2C and/or a different clock frequency than the I2C clock frequency, respectively.
  • the same common I2C data and clock interface 115, 123, 137 are to communicate print data to the image transfer circuit 105 using an OEM customized data protocol and clock frequency.
  • the communications interface 103 comprises further interface contacts to directly communicate the image transfer circuit 105 with the host apparatus logic circuit 131 , without interference of the logic circuit 107, including at least one of a fire pulse contact FIRE to provide power pulses for nozzle actuators to eject ink (e.g. resistor heat pulses), a second supply voltage contact V5P5 to provide voltage to a voltage supply rail that drives the printhead circuitry, a reset contact NRESET to reset the printhead die and/or provide an enable signal, a sense signal contact SENSE connected to sense circuitry and/or to internal memory cells of the die for reading and/or writing, and a mode contact MODE.
  • the contact may directly route to internal circuitry of the printhead die.
  • the image transfer component 101 may comprise a memory separate from the logic circuit 107 and a corresponding memory contact, for example such memory can be provided in the printhead die.
  • the sense contact SENSE may have a memory reading or writing function.
  • the interface 103 may include further data or other contacts that directly connect the printhead die with the host logic circuit 131 without interference of the logic circuit 107.
  • the communication interface 103 comprises a first voltage supply contact V3P3 for the voltage supply rail of the logic circuit 107.
  • the logic circuit 107 is configured to process and transmit data at a first voltage.
  • the first voltage may be approximately 3V and/or I2C compliant.
  • the communication interface 103 may comprise a second voltage supply contact V5P5 for the image transfer circuit 105.
  • the image transfer circuit 105 is configured to transfer images at a second voltage.
  • the second voltage for the image transfer circuit 105 may be higher than the first voltage for the logic circuit 107.
  • the interface 103 comprises a separate activation signal input FIRE for the image transfer circuit 105, the image transfer circuit 105 configured to operate at an activation signal voltage that is higher than the second voltage.
  • the image transfer circuit may be a printhead or MEMS device.
  • the printhead or MEMS device may be driven by said second voltage while the fluid actuators may be driven by the fire pulses FIRE.
  • a fluidic die of the printhead or MEMS may comprise of CMOS circuitry adapted to be driven by said second supply voltage.
  • the activation signals or pulses may activate other image transfer type such as certain toner image transfer components.
  • Fig. 4 illustrates another example of a diagram of an image transfer component 201 or MEMS type component.
  • the interface 231 includes a clock interface contact CLK, a data interface contact DATA and an enable or reset interface contact NRESET for enabling an image transfer circuit 205.
  • the logic circuit 207 may be configured to receive the enable instructions 215 over the data contact DATA.
  • the enable instructions may comprise first image transfer circuit settings and/or print image data/instructions.
  • the logic circuit 207 may be configured to convert the received first image transfer settings and/or print image data to second image transfer settings and/or second print image data, respectively, in accordance with a custom protocol of the image transfer circuit 205, over the second data line S_DATA.
  • the image transfer circuit 205 may be configured to transfer the image based on the second image transfer settings and/or print image data, respectively, as generated by, and received from, the logic circuit 207.
  • the logic circuit 207 may be configured to generate a custom clock frequency and may include a second clock interface S_CLK to the image transfer circuit 205, for the image transfer circuit 205 to process the second print image data and/or second image transfer settings based on the second clock frequency.
  • control logic 329 may be configured to, at least one of, prevent interference between said communications and instructions, and, enable communication transmission to and from the logic circuit 307 and image transfer circuit 305 at separate times. In certain examples this may inhibit conflicts between the different circuits 305, 307 that operate using different communication protocols.
  • the logic circuit 307 may be configured to transmit communications once data communications are enabled, or not disabled, by the control logic 329, and not transmit communications if these communications are not enabled, or disabled, respectively, by the control logic 329.
  • enabling may mean the same as not disabling and not enabling may mean the same as disabling.
  • control logic 329 may be configured to disable a pull up device 341 for a data line to inhibit communications between the host and the logic circuit 307, for example when the device line 113 is not driven high by the logic circuit 307.
  • control logic 329 may include interference control logic 345 and a pull device 339.
  • the interference control logic 345 may be configured to control the pull device 339 that controls the voltage state over a data pad 315.
  • the data pad 315 can be part of the image transfer circuit 305 and connected to the logic circuit 307 and the common data interface 115, 123 (Fig. 3), as a type of intermediate data interface.
  • the control logic 329 can be part of the image transfer circuit 305 because of the design freedom of the image transfer circuit 305 as compared to a more rigid and/or costly secure logic circuit 307.
  • the control logic 329 may be configured to inhibit the logic circuit 307 to respond to communications of its data protocol when communications to the image transfer circuit 305 are enabled.
  • the control logic 329 may include interference control logic 345 configured to prevent interference of signals, data and/or voltages between the logic circuit 307 and image transfer circuit 305.
  • the interference control logic 345 can be configured to control a state of at least one of the common communication interfaces of the control logic 307 and image transfer circuit 305, for example a data interface 115, 123, 315, by controlling a pull device 339.
  • the interference logic 345 enables the pullup device 341 whereby the pulldown is, effectively, disabled. This enables communications with the logic circuit 307 through the interface 303.
  • the control logic 329 may disable the pull up device 341 , thereby restricting communications to/from the logic circuit 307 via the data pad 315.
  • the pull down device 343 is enabled to pull the voltage low, e.g., close to zero, just high enough to load 0s (i.e., logical zeros) as communications over the logic circuit’s data interface, which in this example effectively results in the logic circuit 307, by design, not responding to (e.g., ignoring) communications over the data interface.
  • the pull device 339 may control a logical voltage state of the data routing 115A to the logic circuit 107 that is connected to the data pad 315.
  • the control logic 329 is configured to pull the voltage of the data pad 315 to a logical default (e.g., high) state when communications are to be transmitted with respect to the logic circuit 307, and/or to another state (e.g. low) when communications are to be transmitted to the image transfer circuit 305.
  • control logic 329 includes a pull up device 341 to pull a voltage of the data pad 305 of the logic circuit 307 to a logical high state.
  • the control logic 329 may also contain a pull down device 343 if only to keep the voltage at a lower voltage just above zero.
  • the logic circuit 307 will not respond when the data pad 315 is not in the default voltage state, for example in a low state.
  • the control logic 329 may inhibit interference between the logic circuit 307 and image transfer circuit 305 through the pull device 339 and integrated data pad 315, as instructed through an internal (A_NRESET) or external (NRESET) interface line.
  • control logic 329 can be configured to pull the voltage of the data pad 315, and, e.g., the routing 115Ato the logic circuit 307, to a logical default/high state to enable communications between the logic circuit 307 and the host apparatus logic circuit 331 , and/or disable communications by disabling the pull device 339.
  • control logic 329 can be configured to, effectively, pull the data line of the logic circuit 307 to a logical low state to disable communications with the logic circuit 307, whereby the image transfer circuit 305 is free to transfer images based on print instructions.
  • the data pad 315 and/or pull device 339 can be provided in the image transfer circuit 305, for example a die of the image transfer circuit 305. In some examples this may result in a relatively reliable, functional, manufacturing efficient and/or cost-efficient integration of that control function.
  • the logic circuit 7, 107, 207, 307 is configured to enable the image transfer circuit 5, 105, 205, 305 and the image transfer circuit 5, 105, 205, 305 may include control logic 29, 129, 329 to be enabled by the logic circuit 7, 107, 207, 307.
  • the image transfer circuit 305 may be configured to disable or enable (communications to/from) the logic circuit 307.
  • the control logic 329 can be configured to disable data communications with the logic circuit 307 by controlling a pull device 339 to control the logical voltage state of the data pad 315.
  • the control logic 329 may be, at least partly, signaled by a separate NRESET line from the host logic circuit directly to control the communications.
  • the control logic 329 and/or interference logic 345 may inhibit communication conflicts between different circuits using different communication protocols, without compromising too much on secure authentication.
  • the control logic 329 may also control a data input buffer 347 to the image transfer circuit 305 (DATAJN).
  • the interference control logic 345 may be configured to control the state of the pull device 339 and the data input buffer 347, based on a signal from the host apparatus logic circuit and/or the logic circuit 307, for example, at least partly based on the enable signal NRESET from the host apparatus and/or the device signal A_NRESET from the logic circuit 307.
  • the interference control logic 339 may be connected to a supply voltage pad V5P5 of the host apparatus logic circuit 131 , as may be the pull device 339.
  • the pull device 339 is configured to set the voltage of the data pad 315 to a voltage that is lower than the data interface with the image transfer circuit 305.
  • the pull device 339 is configured to pull the voltage of the data pad to a default logical voltage state for I2C slave component circuitry, for example of approximately 3V.
  • the logical voltage state of the image transfer circuit 305 may be different, for example higher.
  • the image transfer circuit 305 include CMOS-processed circuitry designed to operate at approximately 6 volts.
  • the pullup device 341 may be constructed using an NMOS transistor or other transistor.
  • the transistors drain can be connected to the V5p5 supply rail, and the source can be connected to the data pad 315.
  • the NMOS transistor When enabled, e.g., with the Pullup NMOS gate voltage equal to V5p5, the NMOS transistor is capable of pulling the Data pad 315 up to V5p5 minus a reference voltage, which in one example process may be approximately 1.2V.
  • a reference voltage which in one example process may be approximately 1.2V.
  • interference control circuits or pull devices may be used, such as for example an active circuit with voltage feedback inside a printhead die, or, control logic external to both the logic circuit and image transfer circuit, or, the logic circuit and image transfer circuit may be designed to operate at the same logical voltage state.
  • the afore mentioned logic circuits and image transfer circuits may be described as first and second integrated circuits, respectively, whereby the image transfer circuit may be any MEMS type device and the image transfer component may be any high precision replaceable component for propelling or sensing materials.
  • the examples of this disclosure mostly address an image transfer component.
  • the image transfer circuit may be a MEMS type circuit or other high precision circuitry for laboratory or diagnostic equipment including home diagnostic tools, and/or for fluid measuring and/or propelling purposes.
  • Such other type of replaceable component may comprise a secure logic circuit that enables the MEMS or other type of circuitry for its high precision function.
  • image transfer component may be replaced by any replaceable component that includes high precision circuitry such as MEMS devices.
  • an image transfer component or other high precision circuitry (e.g., MEMS) component, comprising a communications interface to communicate with a host (print) apparatus, a high precision circuit/image transfer circuit, for example, adapted to transfer an image to print media, or practice other functions, based on (print) instructions received over the interface from the host (print) apparatus.
  • the component comprises a logic circuit comprising a CPU.
  • the logic circuit is configured to, in response to at least one enable instruction, generate a device signal to enable image transfer, or said other function, by the high precision-Zimage transfer circuit.
  • the high precision-Zimage transfer circuit to transfer the image, or practice its function, only after such image transfer or function is enabled by the device signal.
  • a replaceable integrated circuitry component comprising a communications interface to communicate with a host print apparatus, thin film MEMS device adapted to transfer and/or sense liquids based on instructions received over the interface from the host print apparatus, a logic circuit comprising a CPU, the logic circuit configured to, in response to at least one enable instruction, generate a device signal to enable at least one function in the thin film MEMS device, the MEMS device to operate only after the function is enabled by the device signal.
  • an image transfer component comprising a communications interface, the communications interface including a data interface to communicate with a host logic circuit.
  • the component comprises a logic circuit comprising a CPU, and an image transfer circuit adapted to transfer an image to print media, o high precision circuit (e.g., MEMS) adapted to transfer or sense a fluid, based on (print) instructions received via the same data interface.
  • the component may further comprise control logic to, at least one of, prevent interference between said communications and instructions, and, enable communications to the logic circuit and image transfer circuit, or high precision circuit, at separate times.
  • a replaceable integrated circuitry component to be replaced with respect to a host apparatus, comprising a common interface to transmit data communications with respect to a host device logic circuit, the common interface comprising at least a data interface, a first secure integrated circuitry package comprising first logic to communicate over the common interface using cryptographic authentication over an I2C protocol.
  • This logic may be the logic circuit of the different examples mentioned in this disclosure, which may be packaged using IC packaging.
  • the first logic is configured to set a state of a device signal line to second logic (the second logic may comprise any of the example high precision circuits like image transfer circuits and MEMs), the device signal line being apart from the interface, and a second integrated circuitry package including said second logic, the second integrated circuitry package configured to propel, transfer or sense material based on instructions received over said data interface, and the second logic comprising control logic to enable or disable communications to the first logic.
  • the first logic is configured to enable or disable communications to the second integrated circuitry package to propel, transfer or sense material.
  • the first logic is configured to enable the second logic upon which the control logic may enable or disable communications with the first logic.
  • the second logic comprises a data pad connected as intermediate data interface to the first logic, the control logic including a pull-up and/or pull-down device to set a logical state of the data pad.
  • the first logic is configured to, in response to instructions and/or signals sent over the common interface, enable the control logic to enable or disable communications by the first logic, and/or image transfer by the second integrated circuitry package.
  • the control logic is configured to enable or disable data communications between the first logic and the host device logic circuit.
  • the first logic is designed to operate at a lower voltage than the second logic and the control logic is configured to pull the logical voltage state to the first logic to, approximately, the lower voltage.
  • the second integrated circuitry comprises a MEMS with thin film channels and/or chambers having actuators to propel liquid through the thin film channels, and/or sensors to sense properties of the liquid in the channels and/or chambers, wherein the propel instructions are based on an actuator or sensor address order.
  • any of the aspects and examples of this disclosure may comprise any of the following example features, alone or in combination.
  • the enable instruction is of a first protocol and the print instructions are not compliant to that first protocol.
  • the first protocol is an industry standard communications protocol and the (print) instructions are based on a custom protocol.
  • the logic circuit is, or functions as, a secure microcontroller, the logic circuit storing at least one base key related to a host key of the host logic circuit.
  • the logic circuit stores at least one base key that is associated with at least one host-side key, and may be configured to generate a different session key for each of a plurality of communication sessions with the host print apparatus, based on the at least one base key, and cryptographically authenticate the enable instruction using the session key.
  • the logic circuit is configured to generate at least one of at least one discrete device signal to lock and/or unlock the image transfer circuit/ high precision circuit for image transfer, or the other function, and a continuous device signal to unlock the image transfer circuit/high precision circuit for image transfer, or other function, during the device signal, to disable image transfer, or the other function, once the continuous device signal stops being active.
  • the image transfer circuit/high precision circuit comprises control logic to enable the image transfer, or the other function, by the image transfer circuit, or high precision circuit, based on the device signal from the logic circuit and a second signal from the host (print) apparatus over the interface.
  • the control logic includes interference control logic to inhibit interference between communications over (i) the data interface and the logic circuit, and (ii) the data interface and the image transfer or other high precision circuit.
  • the interference control logic and/or the pull device is provided in a die or integrated circuitry packaging of the image transfer circuit or other high precision circuit.
  • the high precision/image transfer circuit includes a data pad to transmit data from the data interface to the logic circuit and control logic to control the logical state of the data pad to prevent interference of communications of different protocols.
  • control logic is provided in a die or integrated circuitry packaging of the image transfer or other high precision circuit.
  • a device signal line is provided from the logic circuit to the image transfer circuit, wherein the logic circuit is configured to enable image transfer by the image transfer circuit over the device signal line, or another function by another high precision circuit.
  • the logic circuit is configured to enable image transfer, or another function, and control logic of the image transfer or other high precision circuit, and the control logic is configured to control communications to/from the logic circuit.
  • any of the foregoing components may comprise a single molded packaging material at least partially embedding the logic circuit and the image transfer circuit, or other high precision circuit, and connect the logic circuit and image transfer circuit, or other high precision circuit, with a single communications interface to communicate with an external host logic circuit.
  • the device signal includes at least one of a reset signal, a serial data signal, a power on signal, image transfer settings, and print image data.
  • the communication interface comprises at least one of a data and clock interface configured to communicate as an I2C compatible interface with the logic circuit, and using a different protocol than I2C and/or a different clock frequency, respectively, communicate with the image transfer circuit or high precision circuit.
  • the data and clock interface are to communicate (print) data to the image transfer circuit, or high precision circuit, using the different clock frequency.
  • the communications interface comprises a clock interface; and the logic circuit is configured to process communications based on a first clock frequency over the clock interface, and the image transfer circuit, or other high precision circuit, is configured to transfer the image to print media, or drive an actuator and/or sense function, based on a second clock frequency, different than the first clock frequency, via the same clock interface.
  • the second clock frequency is higher than the first clock frequency.
  • the communications interface comprising further interface contacts to transmit print signals directly to the image transfer circuit, including at least one of a supply voltage contact, a fire pulse contact, a reset contact, a mode contact, a sense contact, and a separate memory.
  • the communications interface comprises a first voltage supply contact for the logic circuit, the logic circuit configured to process and transmit data at a first voltage, a second voltage supply contact for the image transfer circuit, or other high precision circuit, the image transfer/high precision circuit configured to process (print image) data at a second voltage higher than the first voltage.
  • the component further comprises a separate activation signal contact for the image transfer or other high precision circuit, the image transfer or other high precision circuit configured to operate at an activation signal voltage that is higher than the second voltage.
  • a printhead cartridge or printhead assembly is provided comprising a component of any previous aspect and/or example wherein the activation signal is a fire pulse.
  • the logic circuit is configured to receive the enable instructions comprising first image transfer circuit settings and/or print image data, and convert the received first image transfer settings and/or print image data to second image transfer settings and/or second print image data, respectively, specific to the image transfer circuit, and the image transfer circuit is configured to transfer the image based on the second image transfer settings and/or second print image data, respectively.
  • the image transfer settings comprise a printhead nozzle actuator address order
  • the image transfer circuit includes a printhead circuit configured to convert the print image data to nozzle actuator addresses for ejection of liquid out of the respective nozzles based on said printhead nozzle actuator address order.
  • the image transfer circuit comprises a printhead die and the print instructions comprise actuator addresses to eject liquid from the associated nozzles based on input image data over the data interface, a fire pulse contact, a supply voltage contact, and at least one of a reset contact, a sense signal contact and a mode contact, which contacts are to directly connect the printhead die with the host logic circuit without interference of the logic circuit.
  • the logic circuit is configured to maintain the device signal active for a duration determined by a time parameter stored on the logic circuit and/or included in an instruction.
  • the component can be of a cartridge type, and adapted to be connected, disconnected and replaced with respect to the host device.
  • a component of the previous aspect or examples comprises a reservoir with imaging material, and is adapted to be replaced with respect to a host print apparatus in its entirety, the communication interface adapted to communicate with a host controller of the host print apparatus via compatible interface contacts of the host print apparatus.
  • a printhead assembly, printhead cartridge, toner transfer drum, fuser assembly, and/or toner reservoir is provided that comprises the image transfer component of any one or combination of the previous aspects or examples.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Accessory Devices And Overall Control Thereof (AREA)

Abstract

Un composant d'ensemble de circuits comprend une interface de communication pour communiquer avec un appareil hôte. Le composant peut comprendre un dispositif conçu pour transférer et/ou détecter des liquides sur la base d'instructions reçues sur l'interface. Le composant peut également comprendre un circuit logique configuré pour, en réponse à au moins une instruction d'activation, générer un signal de dispositif pour activer au moins une fonction du dispositif.
PCT/US2020/056857 2020-10-22 2020-10-22 Ensemble de circuits logique WO2022086540A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/US2020/056857 WO2022086540A1 (fr) 2020-10-22 2020-10-22 Ensemble de circuits logique

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2020/056857 WO2022086540A1 (fr) 2020-10-22 2020-10-22 Ensemble de circuits logique

Publications (1)

Publication Number Publication Date
WO2022086540A1 true WO2022086540A1 (fr) 2022-04-28

Family

ID=73544265

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2020/056857 WO2022086540A1 (fr) 2020-10-22 2020-10-22 Ensemble de circuits logique

Country Status (1)

Country Link
WO (1) WO2022086540A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6712439B1 (en) * 2002-12-17 2004-03-30 Lexmark International, Inc. Integrated circuit and drive scheme for an inkjet printhead
US9619663B2 (en) 2008-05-29 2017-04-11 Hewlett-Packard Development Company, L.P. Authenticating a replaceable printer component
WO2020117193A1 (fr) * 2018-12-03 2020-06-11 Hewlett-Packard Development Company, L.P. Circuits logiques
WO2020162913A1 (fr) * 2019-02-06 2020-08-13 Hewlett-Packard Development Company, L.P. Matrice pour tête d'impression

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6712439B1 (en) * 2002-12-17 2004-03-30 Lexmark International, Inc. Integrated circuit and drive scheme for an inkjet printhead
US9619663B2 (en) 2008-05-29 2017-04-11 Hewlett-Packard Development Company, L.P. Authenticating a replaceable printer component
WO2020117193A1 (fr) * 2018-12-03 2020-06-11 Hewlett-Packard Development Company, L.P. Circuits logiques
WO2020162913A1 (fr) * 2019-02-06 2020-08-13 Hewlett-Packard Development Company, L.P. Matrice pour tête d'impression

Similar Documents

Publication Publication Date Title
CN101859235B (zh) 具有多个存储装置的系统以及用于该系统的数据传输方法
JP4123739B2 (ja) 印刷記録材容器の識別システムおよび識別方法
JP6840592B2 (ja) インクジェットヘッド制御装置及びインクジェットプリンタ
US20060077215A1 (en) Head substrate having data memory, printing head, printing apparatus and producing method therefor
EP3767480B1 (fr) Circuits logiques
TW200538294A (en) Element board for printhead, printhead and printhead control method
JP4923544B2 (ja) ヘッドユニット、印刷装置及び印刷方法
JP6851756B2 (ja) インクジェットプリンタ、及びインクジェットヘッド
JP4692655B2 (ja) 画像処理装置
WO2022086540A1 (fr) Ensemble de circuits logique
WO2022086539A1 (fr) Circuiterie logique
US8308253B2 (en) Ink jet image forming apparatus and method of controlling the same
JP2016087859A (ja) 液体吐出装置、ヘッドユニット、集積回路、及び、液体吐出装置の制御方法
US9607253B2 (en) Printing apparatus and print control method
US20120212780A1 (en) Printing apparatus and electronic device
JP2006159781A (ja) ヘッド基板、記録ヘッド、ヘッドカートリッジ、及びその記録ヘッド或いはヘッドカートリッジを用いた記録装置
JP2021181220A (ja) 印刷データを送信する方法および印刷装置
JP2011235528A (ja) 記録ヘッド及び記録装置
US8322809B2 (en) Recording head and recording apparatus using recording head
JP2021135452A (ja) 画像形成装置
US11392809B2 (en) Follower circuits for communication
JP5383441B2 (ja) 記録素子基板、記録素子基板を備えた記録ヘッド、記録装置
WO2022086538A1 (fr) Ensemble de circuits logique
EP3717252B1 (fr) Moniteur de réinitialisation
JP2017185722A (ja) インクジェットヘッド及びインクジェットプリンタ

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20811784

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20811784

Country of ref document: EP

Kind code of ref document: A1