WO2022083749A1 - 比较器和逐次逼近模数转换器 - Google Patents

比较器和逐次逼近模数转换器 Download PDF

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Publication number
WO2022083749A1
WO2022083749A1 PCT/CN2021/125778 CN2021125778W WO2022083749A1 WO 2022083749 A1 WO2022083749 A1 WO 2022083749A1 CN 2021125778 W CN2021125778 W CN 2021125778W WO 2022083749 A1 WO2022083749 A1 WO 2022083749A1
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terminal
input
coupled
stage circuit
output
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PCT/CN2021/125778
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English (en)
French (fr)
Inventor
李彬
朱昊
罗小牛
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晶晨半导体(上海)股份有限公司
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Publication of WO2022083749A1 publication Critical patent/WO2022083749A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods

Definitions

  • the invention relates to the field of circuits, in particular to a comparator and a successive approximation analog-to-digital converter.
  • An analog-to-digital converter is a device that converts continuous analog signal acquisition into discrete digital signals for digital analysis and processing.
  • the successive approximation analog-to-digital converter uses the binary search method to continuously generate new analog voltages through the internal integrated digital-to-analog converter (DAC) to approximate the original input analog signal, and convert the integrated digital-to-analog converter.
  • the digital input corresponding to the DAC (DAC) is used as the output of the ADC.
  • Noise shaping successive approximation analog-to-digital converters are one of successive approximation analog-to-digital converters, which combine oversampling and noise shaping with successive approximation analog-to-digital converters, while ensuring speed and power consumption requirements. , which can improve the accuracy of successive approximation analog-to-digital converters.
  • a four-input comparator is often used in noise-shaping successive approximation analog-to-digital converters.
  • the problem solved by the present invention is to provide a comparator and a successive approximation analog-to-digital converter to improve the performance of the comparator.
  • the present invention provides a comparator, the comparator has a sampling phase and a comparison phase, and the comparator includes:
  • an input stage circuit adapted to amplify the received first input signal and the second input signal respectively during the phase comparison, generate the corresponding first output signal and the second output signal, and transmit them to the isolation transmission circuit respectively;
  • the noise shaping input stage circuit is adapted to amplify the received third input signal and the fourth input signal respectively during the phase comparison, generate the corresponding third output signal and the fourth output signal and transmit them to the isolation transmission circuit;
  • the isolation transmission circuit is adapted to perform noise isolation on the received first output signal, the second output signal, the third output signal and the fourth output signal respectively during the phase comparison , generate a first noise isolation signal, a second noise isolation signal, a third noise isolation signal and a fourth noise isolation signal and input them to the latch stage circuit;
  • the latch stage circuit is adapted to receive a first superposition level signal of the first noise isolation signal and the third noise isolation signal and a second superposition level of the second noise isolation signal and the fourth noise isolation signal The signals are compared, and the corresponding comparison results are generated and output.
  • the input stage circuit includes a first input amplifying unit and a second input amplifying unit;
  • the first input amplifying unit adapted to amplify the first input signal to generate the first output signal
  • the second input amplifying unit is adapted to amplify the second input signal to generate the second output signal.
  • the first input amplifying unit includes a first PMOS transistor
  • the gate terminal of the first PMOS transistor is used to receive the first input signal
  • the source terminal of the first PMOS transistor is coupled to the power supply voltage
  • the drain terminal of the first PMOS transistor is used as the input stage circuit.
  • the first output terminal is or is coupled with the first output terminal of the input stage circuit.
  • the second input amplifying unit includes a second PMOS transistor
  • the gate terminal of the second PMOS transistor is used to receive the second input signal
  • the source terminal of the second PMOS transistor is coupled to the power supply voltage
  • the drain terminal of the second PMOS transistor serves as the input stage circuit The second output end of or is coupled with the second output end of the input stage circuit.
  • the input stage circuit further includes:
  • the first latch unit has a first latch node and a second latch node, and is adapted to latch the first output signal and the second output signal to the first latch node and the first latch node, respectively. Two latch nodes are input to the isolated transmission circuit.
  • the first latch unit includes a first NMOS transistor and a second NMOS transistor;
  • the gate terminal of the first NMOS transistor is coupled to the drain terminals of the two NMOS transistors, and serves as the second latch node or is coupled to the second latch node, and the source of the first NMOS transistor
  • the terminal and the source terminal of the second NMOS transistor are both coupled to the ground voltage, and the drain terminal of the first NMOS transistor is coupled to the gate terminal of the second NMOS transistor, and is used as the first latch node or with the The first latch node is coupled.
  • the input stage circuit further includes a first gain increasing unit and a second gain increasing unit;
  • the first gain increasing unit adapted to increase the output gain of the first input amplifying unit
  • the second gain increasing unit is adapted to increase the output gain of the second input amplifying unit.
  • the first gain increasing unit includes a third NMOS transistor
  • the gate terminal and the drain terminal of the third NMOS transistor are coupled to the output terminal of the first input amplifying unit, and the source terminal of the third NMOS transistor is coupled to the ground voltage.
  • the second gain improving unit includes a fourth NMOS transistor
  • the gate terminal and the drain terminal of the fourth NMOS transistor are coupled to the output terminal of the second input amplifying unit, and the source terminal of the fourth NMOS transistor is coupled to the ground voltage.
  • the noise shaping input stage circuit includes a first noise shaping amplifying unit and a second noise shaping amplifying unit;
  • the first noise shaping amplifying unit is adapted to amplify the received third input signal to generate the third output signal
  • the second noise shaping and amplifying unit is adapted to amplify the received fourth input signal to generate the fourth output signal.
  • the first noise shaping and amplifying unit includes a third PMOS transistor
  • the gate terminal of the third PMOS transistor is used to receive the third input signal
  • the source terminal of the third PMOS transistor is coupled to the power supply voltage
  • the drain terminal of the third PMOS transistor serves as the noise shaping amplifying unit
  • the first output terminal of the noise shaping and amplifying unit is coupled to the first output terminal.
  • the second noise shaping amplifying unit includes a fourth PMOS transistor
  • the gate terminal of the fourth PMOS transistor is used to receive the fourth input signal
  • the source terminal of the fourth PMOS transistor is coupled to the power supply voltage
  • the drain terminal of the fourth PMOS transistor serves as the noise shaping amplifying unit
  • the second output terminal of the noise shaping and amplifying unit is coupled to the second output terminal.
  • the noise shaping input stage circuit further includes:
  • the second latch unit has a third latch node and a fourth latch node, and is adapted to latch the third output signal and the fourth output signal to the third latch node and the fourth latch node, respectively.
  • Four latch nodes are respectively input to the isolated transmission circuit.
  • the second latch unit includes a fifth NMOS transistor and a sixth NMOS transistor;
  • the gate terminal of the fifth NMOS transistor is coupled to the drain terminal of the sixth NMOS transistor, and serves as the fourth latch node or is coupled to the fourth latch node.
  • the source terminal and the source terminal of the sixth NMOS transistor are both coupled to the ground voltage, and the drain terminal of the fifth NMOS transistor is coupled to the gate terminal of the sixth NMOS transistor, and is used as the third latch node or with The third latch node is coupled.
  • the noise shaping input stage further includes a third gain increasing unit and a fourth gain increasing unit;
  • the third gain increasing unit adapted to increase the output gain of the first noise shaping amplifying unit
  • the fourth gain increasing unit is adapted to increase the output gain of the second noise shaping and amplifying unit.
  • the third gain improving unit includes a seventh NMOS transistor
  • the gate terminal and the drain terminal of the seventh NMOS transistor are coupled to the output terminal of the first noise shaping amplifying unit, and the source terminal of the seventh NMOS transistor is coupled to the ground voltage.
  • the fourth gain increasing unit includes an eighth NMOS transistor
  • the gate terminal of the eighth NMOS transistor is coupled to the drain terminal and the output terminal of the second noise shaping amplifying unit, and the source terminal of the eighth NMOS transistor is coupled to the ground voltage.
  • the isolation transmission circuit includes a first capacitor, a second capacitor, a third capacitor and a fourth capacitor;
  • the first end of the first capacitor is coupled to the first output end of the input stage circuit, and the second end of the first capacitor is coupled to the first input end of the latch stage circuit;
  • the first end of the second capacitor is coupled to the second output end of the input stage circuit, and the second end of the second capacitor is coupled to the second input end of the latch stage circuit;
  • the first end of the third capacitor is coupled to the first output end of the noise shaping input stage circuit, and the second end of the third capacitor is coupled to the first input end of the latching stage circuit;
  • the first terminal of the fourth capacitor is coupled to the second output terminal of the noise shaping input stage circuit, and the second terminal of the fourth capacitor is coupled to the second input terminal of the latching stage circuit.
  • the latch stage circuit includes a switch unit, a first lock storage unit, a second lock storage unit and a third latch unit;
  • a switch unit adapted to be turned on when the comparison phase is performed
  • the first lock stores a large unit, and is adapted to amplify the first superimposed level signal of the first output signal and the third output signal when the switch unit is turned on;
  • the second lock stores a large unit, and is adapted to amplify the received second superimposed level signal of the second output signal and the fourth output signal when the switch unit is turned on;
  • the third latching unit is adapted to latch and compare the amplified first superimposed level signal and the amplified second superimposed level signal, and output a corresponding comparison result.
  • the switch unit includes a ninth NMOS transistor
  • the gate terminal of the ninth NMOS transistor is used to receive the first clock control signal, the source terminal of the ninth NMOS transistor is coupled to the ground voltage, and the drain terminal of the ninth NMOS transistor is respectively stored with the first lock
  • the large unit and the second lock storage large unit are coupled.
  • the first lock storage unit includes a tenth NMOS transistor
  • the gate terminal of the tenth NMOS transistor serves as the first input terminal of the latch stage circuit or is coupled to the first input terminal of the latch stage circuit, and the source terminal of the tenth NMOS transistor is connected to the switch unit coupling, the drain terminals of the ten NMOS transistors are coupled with the third latch unit.
  • the second lock storage unit includes an eleventh NMOS transistor
  • the gate terminal of the eleventh NMOS transistor is used as the second input terminal of the latch stage circuit or is coupled to the second input terminal of the latch stage circuit, and the source terminal of the eleventh NMOS transistor is connected to the second input terminal of the latch stage circuit.
  • the switch unit is coupled, and the drain terminals of the eleven NMOS transistors are coupled to the third latch unit.
  • the third latch unit includes a fifth PMOS transistor, a twelfth NMOS transistor, a sixth PMOS transistor, and a thirteenth NMOS transistor;
  • the gate terminal of the fifth PMOS transistor is coupled to the gate terminal of the twelfth NMOS transistor and is coupled to the drain terminal of the sixth PMOS transistor and the drain terminal of the thirteenth NMOS transistor, and serves as the comparison
  • the inverting output terminal of the comparator or the inverting output terminal of the comparator is coupled, the drain terminal of the fifth PMOS transistor is coupled to the drain terminal of the twelfth NMOS transistor and is connected to the gate of the sixth PMOS transistor
  • the terminal is coupled to the gate terminal of the thirteenth NMOS transistor, and is used as the non-inverting output terminal of the comparator or coupled to the non-inverting output terminal of the comparator.
  • the source terminal of the fifth PMOS transistor and The source terminal of the sixth PMOS transistor is coupled to the power supply voltage, the source terminal of the twelfth NMOS transistor is coupled to the first lock storage unit, and the source terminal of the thirteenth NMOS transistor is coupled to the The second lock stores the large unit coupling.
  • the comparator further includes at least one of the following:
  • a first bias circuit adapted to provide a bias current for the input stage circuit
  • the second bias circuit is adapted to provide bias current for the noise shaping input stage circuit.
  • the first bias circuit includes a seventh PMOS transistor
  • the gate terminal of the seventh PMOS transistor is coupled to the bias voltage, the source terminal of the seventh PMOS transistor is coupled to the power supply voltage, and the drain terminal of the seventh PMOS transistor is coupled to the input stage circuit.
  • the second bias circuit includes an eighth PMOS transistor
  • the gate terminal of the eighth PMOS transistor is coupled to the bias voltage, the source terminal of the eighth PMOS transistor is coupled to the power supply voltage, and the drain terminal of the eighth PMOS transistor is coupled to the noise shaping input stage circuit .
  • the comparator further includes at least one of the following:
  • a first output reset circuit adapted to reset the non-inverting output terminal of the comparator to a power supply voltage during the sampling phase
  • the first output reset circuit is adapted to reset the inverting output terminal of the comparator to the power supply voltage during the sampling phase.
  • the first output reset circuit includes a ninth PMOS transistor
  • the gate terminal of the ninth PMOS transistor is used for receiving the first clock control signal, the source terminal of the ninth PMOS transistor is coupled to the power supply voltage, and the drain terminal of the ninth PMOS transistor is in positive phase with the comparator.
  • the output terminal is coupled.
  • the second output reset circuit includes a tenth PMOS transistor
  • the gate terminal of the tenth PMOS transistor is used to receive the first clock control signal, the source terminal of the tenth PMOS transistor is coupled to the power supply voltage, and the drain terminal of the tenth PMOS transistor is connected to the comparator.
  • the inverting output is coupled.
  • the comparator also includes at least one of the following:
  • a first input reset circuit adapted to reset the first input end of the input stage circuit to a preset common mode voltage when the sampling phase is performed
  • a second input reset circuit adapted to reset the second input terminal of the input stage circuit to the common mode voltage during the sampling phase
  • a third input reset circuit adapted to reset the first input terminal of the noise shaping input stage circuit to the common mode voltage during the sampling phase
  • a fourth input reset circuit adapted to reset the second input terminal of the noise shaping input stage circuit to the common mode voltage during the sampling phase
  • a fifth input reset circuit adapted to reset the first input terminal of the latch stage circuit to the common mode voltage when the sampling phase is performed
  • the sixth input reset circuit is adapted to reset the second input terminal of the latch stage circuit to the common mode voltage during the sampling phase.
  • the first input reset circuit includes a first switch
  • the control terminal of the first switch is used to receive the second clock control signal, the first conduction terminal of the first switch is used to receive the common mode voltage, and the second conduction terminal of the first switch is connected to the The first input end of the input stage circuit is coupled.
  • the second input reset circuit includes a second switch
  • the control terminal of the second switch is used for receiving the second clock control signal
  • the first conduction terminal of the second switch is used for receiving the common mode voltage
  • the second conduction terminal of the second switch is used for receiving the common mode voltage. is coupled to the second input terminal of the input stage circuit.
  • the third input reset circuit includes a third switch
  • the control terminal of the third switch is used to receive the second clock control signal, the first conduction terminal of the third switch is used to receive the common mode voltage, and the second conduction terminal of the third switch is connected to the The first input terminal of the noise shaping input stage circuit is coupled.
  • the fourth input reset circuit includes a fourth switch
  • the control terminal of the fourth switch is used for receiving the second clock control signal
  • the first conduction terminal of the fourth switch is used for receiving the common mode voltage
  • the second conduction terminal of the fourth switch is used for receiving the common mode voltage. is coupled to the second input terminal of the noise shaping input stage circuit.
  • the fifth input reset circuit includes a fifth switch
  • the control terminal of the fifth switch is used to receive the second clock control signal, the first conduction terminal of the fifth switch is used to receive the common mode voltage, and the second conduction terminal of the fifth switch is connected to the The first input end of the latch stage circuit is coupled.
  • the sixth input reset circuit includes a sixth switch
  • the control terminal of the sixth switch is used to receive the second clock control signal, the first conduction terminal of the sixth switch is used to receive the common mode voltage, and the second conduction terminal of the sixth switch is coupled to the second input terminal of the latch stage circuit.
  • an embodiment of the present invention further provides an asynchronous successive approximation analog-to-digital converter, including the comparator described in any of the above.
  • FIG. 1 is a schematic structural diagram of a four-input comparator.
  • FIG. 2 is a schematic diagram of a frame structure of a comparator in an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of an input stage circuit in an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a noise shaping input stage circuit in an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of an isolated transmission circuit in an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a latch stage circuit in an embodiment of the present invention.
  • FIG. 7 is a schematic time sequence diagram of a related pulse signal of a comparator in an embodiment of the present invention.
  • a four-input comparator for a successive approximation analog-to-digital converter specifically includes a pre-amplification input stage circuit 11 , a noise shaping input stage circuit 12 and a latch stage circuit 13 .
  • the first input terminal and the second input terminal of the pre-amplification input stage circuit 11 are respectively used to receive the first input signal Inp and the second input signal Inn, and after amplification, the first output signal and the second output signal are generated and transmitted to the lock
  • the first input terminal and the second input terminal of the storage stage 13, and the first input terminal and the second input terminal of the noise shaping input stage 12 are respectively used for receiving the third input signal Inp-ns and the fourth input signal In-ns, through After amplification, the third output signal and the fourth output signal are generated and transmitted to the first input terminal and the second input terminal of the latch stage 13 .
  • the first output signal output from the first input terminal of the pre-amplification input stage circuit 11 and the third input signal output from the first input terminal of the noise shaping input stage 12 are superimposed as the first input signal xp, and the noise shaping input stage
  • the second output signal output from the first output terminal of 12 and the fourth input signal output from the second input terminal of the noise shaping input stage 12 are superimposed as the second input signal xn, and the latch stage circuit 13 receives the first input signal according to the The magnitude of the signal xp and the second input signal xn outputs a corresponding comparison result.
  • the output terminals of the input stage circuit 11 and the noise shaping input stage circuit 12 are shared, and there will be relatively large kickback noise, which seriously affects the performance of the four-input comparator.
  • the technical solutions in the embodiments of the present invention provide an isolation transmission circuit between the input stage circuit, the noise shaping input stage circuit and the latch stage circuit, so that the first output signal output by the input stage circuit and the The second output signal, the third output signal and the fourth output signal output by the noise shaping input stage circuit are respectively isolated from noise and then input to the latch stage circuit, so that the output terminals of the input stage circuit and the noise shaping input stage circuit are mutually Independent, it can avoid the kickback noise caused by the sharing of the output end of the input stage circuit and the noise shaping input stage circuit, so it can improve the performance of the four-input comparator.
  • FIG. 2 shows a schematic structural diagram of a comparator in an embodiment of the present invention.
  • a comparator in an embodiment of the present invention may include an input stage circuit 21 , a noise shaping input stage circuit 22 and a latch stage circuit 24 .
  • the comparator has a first pair of input terminals (not marked), a second pair of input terminals (not marked), a non-inverting output terminal (not marked) and an inverting output terminal (not marked); the first pair of input terminals It includes a first input end (not shown) and a second input end (not shown), and the second pair of input ends includes a third input end (not shown) and a fourth input end (not shown).
  • the input stage circuit 21 has a first input terminal and a second input terminal.
  • the first input terminal of the input stage circuit 21 serves as the first input terminal of the comparator or is coupled to the first input terminal of the comparator for receiving the first input signal Inp; the input stage circuit 21
  • the second input terminal of is used as the second input terminal of the comparator or coupled with the second input terminal of the comparator, and is used for receiving the second input signal Inn.
  • the input stage circuit 21 can respectively amplify the first input signal Inp received by the first input terminal and the second input signal Inn received by the second input terminal during the phase comparison to generate a corresponding first input signal.
  • An output signal Inp-out and a second output signal Inn-out are respectively transmitted to the isolation transmission circuit. in,
  • the input stage circuit 21 includes a first input amplifying unit (not shown) and a second input amplifying unit (not shown). in:
  • the first input amplifying unit has an input terminal and an output terminal.
  • the input end of the first input amplifying unit serves as the first input end of the input stage circuit 21 or is coupled to the first input end of the input stage circuit 21 for receiving the first input signal Inp;
  • the output end of the first input amplifying unit is used as the second output end of the input stage circuit 21 or coupled with the second output end of the input stage circuit 21 for outputting the first output signal Inp-out .
  • the first input amplifying unit may amplify the received first input signal Inp to generate the first output signal Inp-out.
  • the first input amplifying unit includes a first PMOS transistor PM1.
  • the gate terminal of the first PMOS transistor PM1 is used to receive the first input signal Inp
  • the source terminal of the first PMOS transistor PM1 is coupled to the power supply voltage avdd
  • the drain terminal of the first PMOS transistor PM1 serves as the The first output terminal of the input stage circuit 21 is or is coupled to the first output terminal of the input stage circuit 21 .
  • the second input amplifying unit has an input terminal and an output terminal.
  • the input terminal of the second input amplifying unit serves as the second input terminal of the input stage circuit 21 or is coupled to the second input terminal of the input stage circuit 21 for receiving the second input signal Inn;
  • the output terminal of the second input amplifying unit serves as the second output terminal of the input stage circuit 21 or is coupled to the second output terminal of the input stage circuit 21 for outputting the second output signal Inn-out.
  • the second input amplifying unit may amplify the received second input signal Inn to generate the two output signals Inn-out.
  • the second input amplifying unit includes a second PMOS transistor PM2.
  • the gate terminal of the second PMOS transistor PM2 is used to receive the second input signal Inp
  • the source terminal of the second PMOS transistor PM2 is coupled to the power supply voltage avdd
  • the drain terminal of the second PMOS transistor PM2 serves as the The second output terminal of the input stage circuit 21 is or is coupled to the second output terminal of the input stage circuit 21 .
  • the input stage circuit 21 further includes a first latch unit (not shown).
  • the first latch unit has a first latch node N1 and a second latch node N2.
  • the first latch unit can latch the first output signal Inp-out to the first latch node N1 and input it to the first input terminal of the isolation transmission circuit, and output the second output signal Inn. -out is latched to the second latch node N2 and input to the second input terminal of the isolated transmission circuit 23 .
  • the first latch unit includes a first NMOS transistor NM1 and a second NMOS transistor NM2.
  • the gate terminal of the first NMOS transistor NM1 is coupled to the drain terminals of the two NMOS transistors NM2, and serves as the second latch node N2 or is coupled to the second latch node N2, the The source terminal of the first NMOS transistor NM1 and the source terminal of the second NMOS transistor NM2 are both coupled to the ground voltage avss, the drain terminal of the first NMOS transistor NM1 is coupled to the gate terminal of the second NMOS transistor NM2, and As the first latch node N1 or coupled to the first latch node N1.
  • the input stage circuit 21 further includes a first gain increasing unit (not shown) and a second gain increasing unit (not shown). in:
  • the first gain increasing unit can increase the output gain of the first input amplifying unit.
  • the first gain increasing unit includes a third NMOS transistor NM3.
  • the gate terminal and the drain terminal of the third NMOS transistor NM3 are coupled to the output terminal of the first input amplifying unit, and the source terminal of the third NMOS transistor NM3 is coupled to the ground voltage avss.
  • the second gain increasing unit may increase the output gain of the second input amplifying unit.
  • the second gain increasing unit includes a fourth NMOS transistor NM4.
  • the gate terminal and the drain terminal of the fourth NMOS transistor NM4 are coupled to the output terminal of the second input amplifying unit, and the source terminal of the fourth NMOS transistor NM4 is coupled to the ground voltage avss.
  • the noise shaping input stage circuit 22 has a first input terminal and a second input terminal, a first output terminal and a second output terminal.
  • the first input terminal of the noise shaping input stage circuit 22 is used as the third input terminal of the comparator or is coupled to the third input terminal of the comparator for receiving the third input signal Inp ⁇ ns;
  • the second input terminal of the noise shaping input stage circuit 22 is used as the fourth input terminal of the comparator or is coupled to the fourth input terminal of the comparator for receiving the fourth input signal Inn- ns.
  • the noise-shaping input stage circuit 22 may, when the comparator is in the comparison phase, compare the third input signal Inp-ns received by the first input terminal and the fourth input signal Inp-ns received by the second input terminal. ns are respectively amplified to generate corresponding third output signals Inp-ns-out and fourth output signals Inn-ns-out.
  • the noise shaping input stage circuit 22 includes a first noise shaping amplifying unit (not shown) and a second noise shaping amplifying unit (not shown). in:
  • the first noise shaping amplifying unit has an input terminal and an output terminal.
  • the input terminal of the first noise shaping amplifying unit serves as the first input terminal of the noise shaping input stage circuit 22 or is coupled to the first input terminal of the noise shaping input stage circuit 22 for receiving a third input signal Inp-ns.
  • the first noise shaping amplifying unit may amplify the received third input signal Inp-ns to generate the third output signal Inp-ns-out.
  • the first noise shaping and amplifying unit includes a third PMOS transistor PM3.
  • the gate terminal of the third PMOS transistor PM3 is used to receive the third input signal Inp-ns, the source terminal of the third PMOS transistor PM3 is coupled to the power supply voltage avdd, and the The drain terminal serves as the first output terminal of the noise shaping input stage circuit 22 or is coupled to the first output terminal of the noise shaping input stage circuit 22 .
  • the second noise shaping amplifying unit has an input terminal and an output terminal. Wherein, the input terminal of the second noise shaping amplifying unit is used as the second input terminal of the noise shaping input stage circuit 22 or is coupled with the second input terminal of the noise shaping input stage circuit 22 for receiving the fourth input terminal. Input signal Inn-ns.
  • the first noise shaping and amplifying unit may amplify the received fourth input signal Inn-ns to generate the fourth output signal Inn-ns-out.
  • the second noise shaping and amplifying unit includes a fourth PMOS transistor PM4.
  • the gate terminal of the fourth PMOS transistor PM4 is coupled to the fourth input signal Inn-ns
  • the source terminal of the fourth PMOS transistor PM4 is coupled to the power supply voltage avdd
  • the fourth PMOS transistor PM4 The drain terminal serves as the second output terminal of the noise shaping input stage circuit 22 or is coupled to the second output terminal of the noise shaping input stage circuit 22 .
  • the noise shaping input stage circuit 22 may further include a second latch unit (not shown).
  • the second latch unit has a third latch node N3 and a fourth latch node N4.
  • the second latch unit can latch the third output signal Inp-ns-out to the third latch node N3 and input it to the third input terminal of the isolation transmission circuit, and output the fourth output signal.
  • the signal Inn-ns-out is latched to the fourth latch node N4 and input to the fourth input terminal of the isolated transmission circuit.
  • the second latch unit includes a fifth NMOS transistor NM5 and a sixth NMOS transistor NM6.
  • the gate terminal of the fifth NMOS transistor NM5 is coupled to the drain terminal of the sixth NMOS transistor NM6, and serves as the fourth latch node N4 or is coupled to the fourth latch node N4, so
  • the source terminal of the fifth NMOS transistor NM5 and the source terminal of the sixth NMOS transistor NM6 are both coupled to the ground voltage avss
  • the drain terminal of the fifth NMOS transistor NM5 is coupled to the gate terminal of the sixth NMOS transistor NM6, And as the third latch node N3 or coupled to the third latch node N3.
  • the noise shaping input stage 22 further includes a third gain increasing unit (not shown) and a fourth gain increasing unit (not shown).
  • the third gain increasing unit can increase the output gain of the first noise shaping and amplifying unit.
  • the third gain increasing unit includes a seventh NMOS transistor NM7.
  • the gate terminal and the drain terminal of the seventh NMOS transistor NM7 are coupled to the output terminal of the first noise shaping and amplifying unit, and the source terminal of the seventh NMOS transistor NM7 is coupled to the ground voltage avss.
  • the fourth gain increasing unit can increase the output gain of the second noise shaping amplifying unit.
  • the fourth gain increasing unit includes an eighth NMOS transistor NM8.
  • the gate terminal of the eighth NMOS transistor NM8 is coupled to the drain terminal and the output terminal of the second noise shaping amplifying unit, and the source terminal of the eighth NMOS transistor NM8 is coupled to the ground voltage avss.
  • the isolated transmission circuit 23 has a first input end, a second input end, a third input end and a fourth input end, and has a first output end, a second output end, a third input end Three output terminals and a fourth output terminal.
  • the first input terminal of the isolated transmission circuit 23 is coupled to the first output terminal of the input stage circuit 21
  • the second input terminal of the isolated transmission circuit 23 is coupled to the second output terminal of the input stage circuit 21
  • the The third input terminal of the isolation transmission circuit 23 is coupled to the first output terminal of the noise shaping input stage circuit 21
  • the fourth input terminal of the isolation transmission circuit 23 is coupled to the second output terminal of the noise shaping input stage circuit 21 . terminal coupling.
  • the isolated transmission circuit 23 may, when the comparator is in the comparison phase, perform the first output signal Inp-out received by the first input end, the second output signal In-out received by the second input end,
  • the third output signal Inp-ns-out received by the third input terminal and the fourth output signal Inn-ns-out received by the fourth input terminal are noise isolated respectively to generate a first noise isolation signal and a second noise isolation signal , a third noise isolation signal and a fourth noise isolation signal, and input to the latch stage circuit.
  • the isolated transmission circuit 23 includes a first capacitor C1, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4.
  • the first end of the first capacitor C1 is coupled to the first output end of the input stage circuit, and the second end of the first capacitor C1 is coupled to the first input end (N5) of the latch stage circuit node) is coupled;
  • the first end of the second capacitor C2 is coupled to the second output end of the input stage circuit, and the second end of the second capacitor C2 is coupled to the second input of the latch stage circuit
  • the terminal (N6 node) is coupled;
  • the first terminal of the third capacitor C3 is coupled to the first output terminal of the noise shaping input stage circuit, and the second terminal of the third capacitor C3 is coupled to the latch stage
  • the first input end of the circuit is coupled;
  • the first end of the fourth capacitor C4 is coupled to the second output end of the noise shaping input stage circuit, and the second end of the fourth capacitor C4 is connected to the latch The second input terminal of the stage circuit is coupled.
  • the latch stage circuit 24 has a first input terminal and a second input terminal, a non-inverting output terminal and an inverting output terminal.
  • the first input terminal of the latch stage circuit 24 is respectively coupled to the first output terminal and the third output terminal of the isolation transmission circuit
  • the second input terminal of the latch stage circuit 24 is respectively coupled to the The second output terminal and the fourth output terminal of the isolated transmission circuit are coupled.
  • the latch stage circuit 24 can receive and compare the first superimposed level signal of the first noise isolation signal and the third noise isolation signal and the second superimposed level signal of the second noise isolation signal and the fourth noise isolation signal. , generate the corresponding comparison result and output it through its non-inverting output terminal and inverting output terminal respectively.
  • the latch stage circuit 24 includes a switch unit (not shown), a first lock storage unit (not shown), a second lock storage unit (not shown), and a third latch unit (not shown). not marked). in:
  • the switch unit has a control terminal, a first conduction terminal and a second conduction terminal.
  • the control terminal of the switch unit is used to receive the first clock control signal clk1, and the first conduction terminal of the switch unit is connected to the first lock storage unit and the second lock storage unit respectively. coupled, the second conducting terminal of the switch unit is coupled to the ground voltage avss.
  • the switching unit may be turned on when the comparator is in a comparison phase.
  • the switch unit includes a ninth NMOS transistor NM9.
  • the gate terminal of the ninth NMOS transistor NM9 serves as the control terminal of the switch unit or is coupled to the control terminal of the switch unit, and is used to receive the first clock control signal clk1;
  • the ninth NMOS transistor NM9 The source terminal of the switch unit is used as the first conduction terminal of the switch unit or is coupled to the first conduction terminal of the switch unit, and is coupled to the ground voltage avss; the drain terminal of the ninth NMOS transistor NM9 is used as the
  • the second conducting end of the switch unit is either coupled to the second conducting end of the switch unit, and is respectively coupled to the first lock storage unit and the second lock storage unit.
  • the first lock storage unit has a control end, a first conducting end and a second conducting end.
  • the control terminal of the first lock storage large unit is used as the first input terminal of the latch stage circuit 24 or is coupled with the first input terminal of the latch stage circuit 24, and the first lock storage large cell
  • the first conduction terminal is coupled to the third latch unit, and the second conduction terminal of the first latch storage unit is coupled to the switch unit.
  • the first lock storage unit can amplify the received first superimposed level signal of the first noise isolation signal and the third noise isolation signal when the switch unit is turned on.
  • the first lock storage unit includes a tenth NMOS transistor NM10.
  • the gate terminal of the tenth NMOS transistor NM10 is used as the first input terminal of the latch stage circuit 24 or is coupled to the first input terminal of the latch stage circuit 24, and the source of the tenth NMOS transistor NM10 The terminal is coupled to the switch unit, and the drain terminal of the ten NMOS transistors NM10 is coupled to the third latch unit.
  • the second lock storage unit has a control end, a first conducting end and a second conducting end.
  • the control terminal of the second lock storage large unit is used as the second input terminal of the latch stage circuit 24 or is coupled with the second input terminal of the latch stage circuit 24, and the second lock storage large cell first
  • the conduction terminal is coupled to the third latch unit, and the second conduction terminal of the second latch storage unit is coupled to the switch unit.
  • the second lock storage unit can amplify the received second superimposed level signal of the second noise isolation signal and the fourth noise isolation signal when the switch unit is turned on.
  • the second lock storage unit includes an eleventh NMOS transistor NM11.
  • the gate terminal of the eleventh NMOS transistor NM11 serves as the second input terminal of the latch stage circuit 24 or is coupled to the second input terminal of the latch stage circuit 24, and the eleven NMOS transistor NM11
  • the source terminal of the NMOS transistor is coupled to the switch unit, and the drain terminal of the eleven NMOS transistors NM11 is coupled to the third latch unit.
  • the third latch unit has a first input terminal, a second input terminal, a first output terminal and a second output terminal. Wherein, the first input end of the third latch unit is coupled to the first lock storage unit, the second input end of the third latch unit is coupled to the second lock storage unit, The first output terminal of the third latch unit is used as the non-inverting output terminal of the comparator or is coupled to the non-inverting output terminal of the comparator, and the second output terminal of the third latch unit is used as the non-inverting output terminal of the comparator.
  • the inverting output terminal of the comparator is or is coupled to the inverting output terminal of the comparator.
  • the third latch unit can latch and compare the amplified first superimposed level signal and the amplified second superimposed level signal, and output the corresponding comparison result and pass the first output terminal and the first output terminal respectively. Two output terminals output.
  • the third latch unit includes a fifth PMOS transistor PM5, a twelfth NMOS transistor NM12, a sixth PMOS transistor PM6, and a thirteenth NMOS transistor NM13.
  • the gate terminal of the fifth PMOS transistor PM5 is coupled to the gate terminal of the twelfth NMOS transistor NM12 and is coupled to the drain terminal of the sixth PMOS transistor PM6 and the drain terminal of the thirteenth NMOS transistor NM13 , and as the inverting output terminal of the comparator or coupled to the inverting output terminal of the comparator, the drain terminal of the fifth PMOS transistor PM5 is coupled to the drain terminal of the twelfth NMOS transistor NM12 and is coupled with the gate terminal of the sixth PMOS transistor PM6 and the gate terminal of the thirteenth NMOS transistor NM13, and is used as the non-inverting output terminal of the comparator or coupled with the non-inverting output terminal of the comparator,
  • the comparator further includes a first bias circuit 25 .
  • the first bias circuit 25 has a control terminal, a first conduction terminal and a second conduction terminal.
  • the control terminal of the first bias circuit 25 is used to receive a preset bias voltage vbias, the first conduction terminal of the first bias circuit is coupled to the power supply voltage avdd, and the first bias circuit
  • the second conducting end of the circuit is coupled to the input stage circuit 21 .
  • the first bias circuit 25 can provide bias current for the input stage circuit 21 .
  • the first bias circuit 25 includes a seventh PMOS transistor PM7.
  • the gate terminal of the seventh PMOS transistor PM7 serves as the control terminal of the first bias circuit 25 or is coupled to the control terminal of the first bias circuit 25, and is used to receive the bias voltage vbias ;
  • the source end of the seventh PMOS transistor PM7 is used as the first conducting end of the first bias circuit 25 or is coupled with the first conducting end of the first bias circuit 25, and is connected to the power supply voltage avdd coupling; the drain terminal of the seventh PMOS transistor PM7 is coupled to the input stage circuit 21 .
  • the comparator further includes a second bias circuit 26 .
  • the second bias circuit 26 has a control terminal, a first conducting terminal and a second conducting terminal.
  • the control terminal of the second bias circuit 26 is used for receiving the bias voltage Vbias
  • the first conducting terminal of the second bias circuit 26 is coupled to the power supply voltage avdd
  • the second bias circuit 26 The second conduction terminal of is coupled to the noise shaping input stage circuit 22 .
  • the second bias circuit 26 may provide bias current for the noise shaping input stage circuit 22 .
  • the second bias circuit 26 includes an eighth PMOS transistor PM8.
  • the gate terminal of the eighth PMOS transistor PM8 is coupled to the bias voltage vbias
  • the source terminal of the eighth PMOS transistor PM8 is coupled to the power supply voltage avdd
  • the drain terminal of the eighth PMOS transistor PM8 is coupled to the power supply voltage avdd.
  • the noise shaping input stage circuit 23 is coupled.
  • the comparator further includes a first output reset circuit 27 .
  • the first output reset circuit 27 has a control terminal, a first conducting terminal and a second conducting terminal.
  • the control terminal of the first output reset circuit 27 is used to receive the first clock control signal clk1, the first conduction terminal of the first output reset circuit 27 is coupled to the power supply voltage avdd, and the The second conducting terminal of the first output reset circuit 27 is coupled to the non-inverting output terminal of the comparator.
  • the first output reset circuit 27 can reset the non-inverting output terminal of the comparator to the power supply voltage avdd during the sampling phase.
  • the first output reset circuit 27 includes a ninth PMOS transistor PM9.
  • the gate terminal of the ninth PMOS transistor PM9 is used to receive the first clock control signal clk1, the source terminal of the ninth PMOS transistor PM9 is coupled to the power supply voltage avdd, and the drain of the ninth PMOS transistor PM9 The terminal is coupled to the non-inverting output terminal of the comparator.
  • the comparator further includes a second output reset circuit 28 .
  • the second output reset circuit 28 has a control terminal, a first conducting terminal and a second conducting terminal. Wherein, the control terminal of the second output reset circuit 28 is used to receive the first clock control signal clk1, the first conduction terminal of the second output reset circuit 28 is coupled to the power supply voltage avdd, the The second conducting terminal of the second output reset circuit 28 is coupled to the inverting output terminal of the comparator. The second output reset circuit 28 can reset the inverting output terminal of the comparator to the power supply voltage avdd during the sampling phase.
  • the second output reset circuit 28 includes a tenth PMOS transistor PM10.
  • the gate terminal of the tenth PMOS transistor PM10 is used to receive the first clock control signal clk1, the source terminal of the tenth PMOS transistor PM10 is coupled to the power supply voltage avdd, and the drain of the tenth PMOS transistor PM10 The terminal is coupled to the inverting output terminal of the comparator.
  • the comparator further includes a first input stage reset circuit 29 and a second input stage reset circuit 30 . in:
  • the first input stage reset circuit 29 has a control terminal, a first conducting terminal and a second conducting terminal. Wherein, the control terminal of the first input stage reset circuit 29 is used for receiving the preset second clock control signal clk2, and the first conduction terminal of the first input stage reset circuit 29 is used for receiving the common mode voltage vcm, The second conduction terminal of the first input stage reset circuit 29 is coupled to the first input terminal of the input stage circuit. The first input stage reset circuit 29 may reset the first input terminal of the input stage circuit to the common mode voltage vcm during the sampling phase.
  • the first input stage reset circuit 29 includes a first switch S1.
  • the control terminal of the first switch S1 is used to receive the second clock control signal clk2, the first conduction terminal of the first switch S1 is used to receive the common mode voltage vcm, and the The second conducting terminal is coupled to the first input terminal of the input stage circuit 21 .
  • the second input stage reset circuit 30 has a control terminal, a first conducting terminal and a second conducting terminal.
  • the control terminal of the second input stage reset circuit 30 is used to receive the second clock control signal clk2, and the first conduction terminal of the second input stage reset circuit 30 is used to receive the common mode voltage vcm, so
  • the second conduction terminal of the second input stage reset circuit 30 is coupled to the second input terminal of the input stage circuit 21 .
  • the second input stage reset circuit 30 can reset the second input terminal of the input stage circuit 21 to the common mode voltage vcm during the sampling phase.
  • the second input stage reset circuit 30 includes a second switch S2.
  • the control terminal of the second switch S2 is used for receiving the second clock control signal clk2, the first conducting terminal of the second switch S2 is used for receiving the common mode voltage vcm, and the The second conduction terminal is coupled to the second input terminal of the input stage circuit 21 .
  • the comparator further includes a first noise shaping input stage reset circuit 31 and a second noise shaping input stage reset circuit 32 . in:
  • the first noise shaping input stage reset circuit 31 has a control terminal, a first conducting terminal and a second conducting terminal.
  • the control terminal of the first noise shaping input stage reset circuit 31 is used to receive the second clock control signal clk2, and the first conduction terminal of the first noise shaping input stage reset circuit 31 is used to receive the second clock control signal clk2.
  • the second conducting terminal of the first noise shaping input stage reset circuit 31 is coupled to the first input terminal of the noise shaping input stage circuit 22 .
  • the first noise shaping input stage reset circuit 31 may reset the first input terminal of the noise shaping input stage circuit 22 to the common mode voltage vcm during the sampling phase.
  • the first noise shaping input stage reset circuit 31 includes a third switch S3.
  • the control terminal of the third switch S3 is used to receive the second clock control signal clk2
  • the first conduction terminal of the third switch S3 is used to receive the common mode voltage vcm
  • the The second conducting terminal is coupled to the first input terminal of the noise shaping input stage circuit 22 .
  • the second noise shaping input stage reset circuit 32 has a control terminal, a first conducting terminal and a second conducting terminal.
  • the control terminal of the second noise shaping input stage reset circuit 32 is used for receiving the second clock control signal clk2, and the first conducting terminal of the second noise shaping input stage reset circuit 32 is used for receiving the The common mode voltage vcm, the second conduction terminal of the second noise shaping input stage reset circuit 32 is coupled to the second input terminal of the noise shaping input stage circuit 22 .
  • the second noise shaping input stage reset circuit 32 may reset the second input terminal of the noise shaping input stage circuit 22 to the common mode voltage vcm during the sampling phase.
  • the second noise shaping input stage reset circuit 32 includes a fourth switch S4.
  • the control terminal of the fourth switch S4 is used to receive the second clock control signal clk2
  • the first conduction terminal of the fourth switch S4 is used to receive the common mode voltage vcm
  • the The second conducting terminal is coupled to the first input terminal of the noise shaping input stage circuit.
  • the comparator further includes a first latch-level reset circuit 33 and a second latch-level reset circuit 34 . in:
  • the first latch stage reset circuit 33 has a control terminal, a first conducting terminal and a second conducting terminal. Wherein, the control terminal of the first latch stage reset circuit 33 is used for receiving the second clock control signal clk2, and the first conduction terminal of the first latch stage reset circuit 33 is used for receiving the common mode voltage vcm, the second conduction terminal of the first latch stage reset circuit 33 is coupled to the first input terminal of the latch stage circuit 24 .
  • the first latch stage reset circuit 33 can reset the first input terminal of the latch stage circuit 24 to the common mode voltage vcm during the sampling phase.
  • the first latch stage reset circuit 33 includes a fifth switch S5.
  • the control terminal of the fifth switch S5 is used for receiving the second clock control signal clk2, the first conducting terminal of the fifth switch S5 is used for receiving the common mode voltage vcm, and the The second conducting terminal is coupled to the first input terminal of the noise shaping input stage circuit 22 .
  • the second latch stage reset circuit 34 has a control terminal, a first conducting terminal and a second conducting terminal. Wherein, the control terminal of the second latch stage reset circuit 34 is used to receive the second clock control signal clk2, and the first conduction terminal of the second latch stage reset circuit 34 is used to receive the common mode voltage vcm, the second conduction terminal of the second latch stage reset circuit 34 is coupled to the second input terminal of the latch stage circuit 24 .
  • the second latch stage reset circuit 34 can reset the second input terminal of the latch stage circuit 24 to the common mode voltage vcm during the sampling phase.
  • the second latch stage reset circuit 34 includes a sixth switch S6.
  • the control terminal of the sixth switch S6 is used for receiving the second clock control signal clk2
  • the first conducting terminal of the sixth switch S6 is used for receiving the common mode voltage vcm
  • the The second conduction terminal is coupled to the first input terminal of the latch stage circuit 24 .
  • the first output reset circuit 27 and the second output reset circuit 28 respectively reset the non-inverting output terminal and the inverting output terminal of the comparator to the power supply voltage avdd under the control of the first clock control signal clk1 .
  • the first clock control signal clk1 is at a logic low level
  • the ninth PMOS transistor PM9 and the tenth PMOS transistor PM10 are both turned on
  • the power supply voltage avdd is respectively transmitted to the comparator through the ninth PMOS transistor PM9 and the tenth PMOS transistor PM10
  • the non-inverting output terminal and the inverting output terminal of the comparator are pulled up to the power supply voltage avdd.
  • the two latching stage reset circuits 34 respectively connect the first input terminal and the second input terminal of the input stage circuit 21 to the first input terminal and the second input terminal of the noise shaping input stage circuit 22 and the first input terminal and the second input terminal of the latching stage circuit 24 respectively.
  • An input terminal and a second input terminal are respectively reset to the common mode voltage vcm.
  • the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5 and the sixth switch S6 are all turned on, and the common mode voltage vcm is transmitted to the first and second input terminals of the input stage circuit 21 , the first and second input terminals of the noise shaping input stage circuit 22 and the first and second input terminals of the latch stage circuit 24 terminal, thereby connecting the first and second input terminals of the input stage circuit 21, the first and second input terminals of the noise shaping input stage circuit 22, and the first and second input terminals of the latch stage circuit 24 The terminals are respectively reset to the common mode voltage vcm.
  • the first switch S1 , the second switch S2 , the third switch S3 , the fourth switch S4 , the fifth switch S5 and the sixth switch S6 are all turned off, and the common mode voltage vcm is connected to the first input terminal of the input stage circuit 21 . It is disconnected from the second input, the first and second inputs of the noise shaping input stage 22 and the first and second inputs of the latch stage 24 .
  • the first input signal Inp and the second input signal Inn are respectively input to the comparator through the first input terminal and the second input terminal of the input stage circuit 21, and the third input signal Inp-ns and the fourth input signal Inn-ns are respectively The first input terminal and the second input terminal of the noise shaping input stage circuit 22 are input to the comparator.
  • the first input signal Inp, the second input signal Inn, the third input signal Inp-ns, and the fourth input signal Inn-ns undergo a logic low for half a cycle in the sampling phase level time to reach steady state.
  • the input stage circuit 21 amplifies the first input signal Inp and the second input signal Inn, respectively, to generate the first output signal Inp-out and the second output signal Inn-out.
  • the voltage difference between the gate terminal and the source terminal of the first PMOS transistor PM1 in the first input amplifying unit will be smaller than that of the second PMOS transistor PM2 in the second input amplifying unit Therefore, the on-current of the first PMOS transistor PM1 is smaller than the on-current of the second PMOS transistor PM2, so that the charging speed of the drain terminal of the first PMOS transistor PM1 will be slower than that of the first PMOS transistor PM1.
  • the charging speed of the drain terminal of the tube PM2 makes the voltage of the drain terminal of the first PMOS transistor PM1 smaller than that of the second PMOS transistor PM2, that is, the voltage of the first latch node N1 will be lower than that of the second latch node N2.
  • the existence of the first NMOS transistor NM1 and the second NMOS transistor NM2 in the first latch unit will keep the voltage of the first latch node N1 lower than the voltage of the second latch node N2. Conversely, when the first input signal Inp is smaller than the second input signal Inn, the voltage of the first latch node N1 will be greater than the voltage of the second latch node N2.
  • the noise shaping input stage circuit 22 amplifies the third input signal Inp-ns and the fourth input signal Inn-ns, respectively, to generate the corresponding third output signal Inp-ns-out and the fourth output signal Inn-ns- out.
  • the voltage difference between the gate terminal and the source terminal of the third PMOS transistor PM3 in the first noise shaping amplifying unit will be smaller than the second noise shaping
  • the voltage difference between the gate terminal and the source terminal of the fourth PMOS transistor PM4 in the amplifying unit so the on-current of the third PMOS transistor PM3 is smaller than the on-current of the fourth PMOS transistor PM4, so that the upper part of the drain terminal of the third PMOS transistor PM3
  • the pull-up speed will be slower than the pull-up speed of the fourth PMOS transistor PM4, so that the drain voltage of the third PMOS transistor PM3 is smaller than the drain voltage of the fourth PMOS transistor PM4, that is, the voltage of the third latch node N3 will be less than The voltage of the fourth latch node N4.
  • the existence of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 in the second latch unit will keep the voltage of the third latch node N3 lower than the voltage of the fourth latch node N4. Conversely, when the third input signal Inp-ns is smaller than the fourth input signal Inn-ns, the voltage of the third latch node N3 is greater than the voltage of the fourth latch node N4.
  • the relationship between the voltages input to the first input terminal and the second input terminal of the latch stage circuit 24 can be It is equivalent to the relationship between the sum of the first differential input voltage Inp and the third differential input voltage Inp-ns and the sum of the second differential input voltage Inn and the fourth differential input voltage Inn_ns, that is, the voltage of the node N5 is smaller than that of the node N6.
  • the latch stage circuit 24 compares the voltages received by the first input terminal and the second input terminal thereof, that is, compares the voltages of the node N5 and the node N6.
  • the ninth NMOS transistor NM9 in the switch unit of the latch stage circuit 24 is turned on.
  • the source terminal of the ninth NMOS transistor NM9 has a ground voltage avss
  • the gate terminal voltages of the tenth NMOS transistor NM10 and the eleventh NMOS transistor NM11 are both Supply voltage avdd.
  • the drain terminal of the tenth NMOS transistor NM10 is earlier than the voltage received by the second input terminal.
  • the drain terminal of the eleventh NMOS transistor NM11 is pulled down to the ground voltage avss by the ninth NMOS transistor NM9, so that the voltage difference between the gate terminal and the source terminal of the twelfth NMOS transistor NM12 is greater than that of the gate terminal of the thirteenth NMOS transistor NM13
  • the voltage difference with the source terminal makes the gate terminal of the twelfth NMOS transistor NM12 larger than the gate terminal of the thirteenth NMOS transistor NM13, that is, the voltage outp of the non-inverting output terminal of the comparator is larger than the voltage outn of the inverting output terminal.
  • the cross-coupling positive feedback structure formed by the fifth PMOS transistor PM5, the twelfth NMOS transistor NM12, the sixth PMOS transistor PM6, and the thirteenth NMOS transistor NM13 in the third latch unit makes the positive-phase output of the comparator
  • the voltage outp is maintained in a state greater or less than the voltage outn of the inverting output terminal of the comparator.
  • the first output signal Inp-out and the second output signal Inn-out output by the first output terminal and the second output terminal of the input stage circuit 21 pass through the first capacitor C1 and the second output signal, respectively.
  • the capacitor C2 is coupled to the first input terminal and the second input terminal of the latch stage circuit 24, and the third output signals Inp-ns-out and the second output terminal of the noise shaping input stage circuit 22 output
  • the fourth output signal Inn-ns-out is coupled to the first input terminal and the second input terminal of the latch stage circuit 24 through the third capacitor C3 and the fourth capacitor C4, respectively, so that the input stage circuit 21 and the noise shaping input stage circuit 22 The outputs are independent of each other.
  • the first output terminal and the second output terminal of the input stage circuit 21 and the first output terminal and the second output terminal of the noise shaping input stage circuit 22 are directly connected to the first input terminal and the second output terminal of the latch stage circuit 24.
  • the second input terminal when the second input terminal is used, when the output voltage of the non-inverting output terminal and the non-inverting output terminal of the latch stage changes from the power supply voltage avdd in the sampling phase to outp and outn in the comparison phase, the input stage circuit 21 and the noise shaping input stage are changed.
  • the circuit 22 produces a coupling effect, so it can isolate and reduce kickback noise.
  • the input offset voltage of the comparator is amplified by the input stage circuit 21 and the noise shaping input stage circuit and stored in the first capacitor C1, the second capacitor C2, the first capacitor C2, the on the third capacitor C3 and the fourth capacitor C4.
  • the storage voltage on the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 is equivalent to the output offset voltage of the comparator, which is denoted as (Av*Voffset), where Av represents the input stage circuit or the gain of the noise-shaping input stage circuit, Voffset represents the input offset voltage.
  • the comparator when the comparator is in the comparison phase, that is, when the second clock control signal clk2 is at a low level, the first input signal Inp, the second input signal Inn, the third input signal Inp-ns, and the fourth output signal Inn-ns are connected to It is input into the input stage circuit 21 and the noise shaping input stage circuit 22, amplified by the input stage circuit 21 and the noise shaping input stage circuit 22, the output voltage is recorded as (Av*(VIn+Voffset)), and then transmitted to the latch stage circuit 24 Before, the output voltage is recorded as the input offset voltage (Av*Voffset) in (Av*(VIn+Voffset)) and the first capacitor C1, the first capacitor C2, the first capacitor C3 and the fourth capacitor C2 in the isolation transmission circuit 23, respectively.
  • the output offset voltages (Av*Voffset) stored respectively on the capacitor C4 are canceled, and the output value becomes (Av*VIn), so the offset voltage can be eliminated, thereby improving the accuracy of the comparator in the
  • the seventh PMOS transistor PM7 in the first bias circuit and the eighth PMOS transistor PM8 in the second bias circuit provide bias currents to the input stage circuit 21 and the noise shaping input stage circuit 22 respectively, which can avoid the transient noise generated during access, so the performance of the comparator in the embodiment of the present invention can be improved.
  • an embodiment of the present invention also provides a successive approximation analog-to-digital converter, including the comparator.
  • the comparator please refer to the detailed introduction in the foregoing part, and details are not repeated here.
  • embodiments of the present invention are combinations of elements and features of the present invention.
  • the elements or features may be considered selective unless otherwise mentioned.
  • Each element or feature can be practiced without being combined with other elements or features.
  • embodiments of the present invention may be constructed by combining some of the elements and/or features.
  • the order of operations described in the embodiments of the present invention may be rearranged. Some constructions of any one embodiment may be included in another embodiment and may be replaced with corresponding constructions of another embodiment. It will be apparent to those skilled in the art that claims in the appended claims that have no express reference relationship to each other may be combined into embodiments of the present invention, or may be included as new claims in amendments after filing this application.
  • Embodiments of the present invention may be implemented by various means such as hardware, firmware, software, or a combination thereof.
  • the method according to the exemplary embodiment of the present invention may be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices ( PLD), field programmable gate array (FPGA), processors, controllers, microcontrollers, microprocessors, etc.
  • ASICs application specific integrated circuits
  • DSPs digital signal processors
  • DSPDs digital signal processing devices
  • PLD programmable logic devices
  • FPGA field programmable gate array
  • processors controllers, microcontrollers, microprocessors, etc.
  • the embodiments of the present invention may be implemented in the form of modules, procedures, functions, and the like.
  • Software codes may be stored in a memory unit and executed by a processor.
  • the memory unit is located inside or outside the processor and can transmit and receive data to and from the processor via various known means.

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Abstract

一种比较器和逐次逼近模数转换器，所述比较器通过在输入级电路和噪声整形输入级电路之间设置隔离传输电路，可以将所述输入级电路输出的第一输出信号和第二输出信号，以及噪声整形输入级电路输出的第三输出信号和第四输出信号分别进行噪声隔离后输入至锁存级电路，使得输入级电路和噪声整形输入级电路的输出端之间相互独立，可以避免因输入级电路和噪声整形输入级电路的输出端共用所产生的回踢噪声，故可以提高四输入比较器的性能。

Description

比较器和逐次逼近模数转换器 技术领域
本发明涉及电路领域，尤其涉及一种比较器和逐次逼近模数转换器。
背景技术
模数转换器(ADC)是将连续性的模拟信号采集转换为离散性的数字信号以用于数字分析和处理的装置。逐次逼近型模数转换器(SAR ADC)是利用二分法查找方式，通过内部集成的数模转换器(DAC)不断产生新的模拟电压量去逼近原先输入模拟信号，并将集成的数模转换器(DAC)对应的数码输入作为ADC的输出。
噪声整形逐次逼近式模数转换器是逐次逼近型模数转换器中的一种，其将过采样和噪声整形与逐次逼近型模数转换器结合起来，在保证速度和功耗需求的条件下，可以提高逐次逼近型模数转换器的精度。为了实现这种功能，噪声整形逐次逼近式模数转换器中经常会用到四输入比较器。
但是，现有的四输入比较器中存在着较大的噪声，影响了比较器的工作性能。
技术问题
本发明解决的问题是提供一种比较器和逐次逼近模数转换器，以提升比较器的性能。
技术解决方案
为解决上述问题，本发明提供了一种比较器，所述比较器具有采样相和比较相，所述比较器包括：
输入级电路，适于在所述比较相时，对接收到的第一输入信号和第二输入信号分别进行放大，生成对应的第一输出信号和第二输出信号并分别传输至隔离传输电路；
噪声整形输入级电路，适于在所述比较相时，对接收到的第三输入信号和第四输入信号分别进行放大，生成对应的第三输出信号和第四输出信号并传输至所述隔离传输电路；
所述隔离传输电路，适于在所述比较相时，对所接收的所述第一输出信号、所述第二输出信号、所述第三输出信号和所述第四输出信号分别进行噪声隔离，生成第一噪声隔离信号、第二噪声隔离信号、第三噪声隔离信号和第四噪声隔离信号并输入至锁存级电路；
所述锁存级电路，适于接收到的第一噪声隔离信号和第三噪声隔离信号的第一叠加电平信号与所述第二噪声隔离信号和第四噪声隔离信号的第二叠加电平信号进行比较，生成对应的比较结果并输出。
可选地，所述输入级电路包括第一输入放大单元和第二输入放大单元；
所述第一输入放大单元，适于对所述第一输入信号进行放大，生成所述第一输出信号；
所述第二输入放大单元，适于对所述第二输入信号进行放大，生成所述第二输出信号。
可选地，所述第一输入放大单元包括第一PMOS管；
所述第一PMOS管的栅端用于接收所述第一输入信号，所述第一PMOS管的源端与电源电压耦接，所述第一PMOS管的漏端作为所述输入级电路的第一输出端或与所述输入级电路的第一输出端耦接。
可选地，所述第二输入放大单元包括第二PMOS管；
所述第二PMOS管的栅端用于接收所述第二输入信号，所述第二PMOS管的源端与电源电压耦接，所述第二PMOS管的漏端作为为所述输入级电路的第二输出端或与所述输入级电路的第二输出端耦接。
可选地，所述输入级电路还包括：
第一锁存单元，具有第一锁存节点和第二锁存节点，适于对所述第一输出信号和所述第二输出信号分别锁存至所述第一锁存节点和所述第二锁存节点并输入至所述隔离传输电路。
可选地，所述第一锁存单元包括第一NMOS管和第二NMOS管；
所述第一NMOS管的栅端与所述二NMOS管的漏端耦接，且作为所述第二锁存节点或与所述第二锁存节点耦接，所述第一NMOS管的源端与所述第二NMOS管的源端均与地电压耦接，所述第一NMOS管的漏端与第二NMOS管的栅端耦接，且作为所述第一锁存节点或与所述第一锁存节点耦接。
可选地，所述输入级电路还包括第一增益提高单元和第二增益提高单元；
所述第一增益提高单元，适于提高所述第一输入放大单元的输出增益；
所述第二增益提高单元，适于提高所述第二输入放大单元的输出增益。
可选地，所述第一增益提高单元包括第三NMOS管；
所述第三NMOS管的栅端和漏端耦接并与所述第一输入放大单元的输出端耦接，所述第三NMOS管的源端与地电压耦接。
可选地，所述第二增益提高单元包括第四NMOS管；
所述第四NMOS管的栅端与漏端耦接并与所述第二输入放大单元的输出端耦接，所述第四NMOS管的源端与地电压耦接。
可选地，所述噪声整形输入级电路包括第一噪声整形放大单元和第二噪声整形放大单元；
所述第一噪声整形放大单元，适于对所接收的第三输入信号进行放大，生成所述第三输出信号；
所述第二噪声整形放大单元，适于将所接收所述第四输入信号进行放大，生成所述第四输出信号。
可选地，所述第一噪声整形放大单元包括第三PMOS管；
所述第三PMOS管的栅端用于接收所述第三输入信号，所述第三PMOS管的源端与电源电压耦接，所述第三PMOS管的漏端作为所述噪声整形放大单元的第一输出端或与所述噪声整形放大单元的第一输出端耦接。
可选地，所述第二噪声整形放大单元包括第四PMOS管；
所述第四PMOS管的栅端用于接收所述第四输入信号，所述第四PMOS管的源端与电源电压耦接，所述第四PMOS管的漏端作为所述噪声整形放大单元的第二输出端或与所述噪声整形放大单元的第二输出端耦接。
可选地，所述噪声整形输入级电路还包括：
第二锁存单元，具有第三锁存节点和第四锁存节点，适于将所述第三输出信号和所述第四输出信号分别锁存至所述第三锁存节点和所述第四锁存节点并分别输入至所述隔离传输电路。
可选地，所述第二锁存单元包括第五NMOS管和第六NMOS管；
所述第五NMOS管的栅端与所述第六NMOS管的漏端耦接，且作为所述第四锁存节点或与所述第四锁存节点耦接，所述第五NMOS管的源端与所述第六NMOS管的源端均与地电压耦接，所述第五NMOS管的漏端与第六NMOS管的栅端耦接，且作为所述第三锁存节点或与所述第三锁存节点耦接。
可选地，所述噪声整形输入级还包括第三增益提高单元和第四增益提高单元；
所述第三增益提高单元，适于提高所述第一噪声整形放大单元的输出增益；
所述第四增益提高单元，适于提高所述第二噪声整形放大单元的输出增益。
可选地，所述第三增益提高单元包括第七NMOS管；
所述第七NMOS管的栅端与漏端耦接并与所述第一噪声整形放大单元的输出端耦接， 所述第七NMOS管的源端与地电压耦接。
可选地，所述第四增益提高单元包括第八NMOS管；
所述第八NMOS管的栅端与漏端及所述第二噪声整形放大单元的输出端耦接，所述第八NMOS管的源端与地电压耦接。
可选地，所述隔离传输电路包括第一电容、第二电容、第三电容和第四电容；
所述第一电容的第一端与所述输入级电路的第一输出端耦接，所述第一电容的第二端与所述锁存级电路的第一输入端耦接；
所述第二电容的第一端与所述输入级电路的第二输出端耦接，所述第二电容的第二端与所述锁存级电路的第二输入端耦接；
所述第三电容的第一端与所述噪声整形输入级电路的第一输出端耦接，所述第三电容的第二端与所述锁存级电路的第一输入端耦接；
所述第四电容的第一端与所述噪声整形输入级电路的第二输出端耦接，所述第四电容的第二端与所述锁存级电路的第二输入端耦接。
可选地，所述锁存级电路包括开关单元、第一锁存放大单元、第二锁存放大单元和第三锁存单元；
开关单元，适于在所述比较相时导通；
第一锁存放大单元，适于当所述开关单元导通时，对所述第一输出信号和第三输出信号的第一叠加电平信号进行放大；
第二锁存放大单元，适于当所述开关单元导通时，对所接收的第二输出信号和第四输出信号的第二叠加电平信号进行放大；
第三锁存单元，适于对所述放大后的第一叠加电平信号和放大后的第二叠加电平信号进行锁存并比较，输出对应的比较结果。
可选地，所述开关单元包括第九NMOS管；
所述第九NMOS管的栅端用于接收第一时钟控制信号，所述第九NMOS管的源端与地电压耦接，所述第九NMOS管的漏端分别与所述第一锁存放大单元和第二锁存放大单元耦接。
可选地，所述第一锁存放大单元包括第十NMOS管；
所述第十NMOS管的栅端作为所述锁存级电路的第一输入端或与所述锁存级电路的第一输入端耦接，所述十NMOS管的源端与所述开关单元耦接，所述十NMOS管的漏端与所述第三锁存单元耦接。
可选地，所述第二锁存放大单元包括第十一NMOS管；
所述第十一NMOS管的栅端作为所述锁存级电路的第二输入端或与所述锁存级电路的第二输入端耦接，所述十一NMOS管的源端与所述开关单元耦接，所述十一NMOS管的漏端与所述第三锁存单元耦接。
可选地，所述第三锁存单元包括第五PMOS管、第十二NMOS管、第六PMOS管和第十三NMOS管；
所述第五PMOS管的栅端与所述第十二NMOS管的栅端耦接并与第六PMOS管的漏端和所述第十三NMOS管的漏端耦接，且作为所述比较器的反相输出端或与所述比较器的反相输出端耦接，所述第五PMOS管的漏端与所述第十二NMOS管的漏端耦接并与第六PMOS管的栅端和所述第十三NMOS管的栅端耦接，且作为所述比较器的正相输出端或与所述比较器的正相输出端耦接，所述第五PMOS管的源端和所述第六PMOS管的源端与电源电压耦接，所述第十二NMOS管的源端与所述第一锁存放大单元耦接，所述第十三NMOS管的源端与所述第二锁存放大单元耦接。
可选地，所述比较器还包括以下至少一项：
第一偏置电路，适于为所述输入级电路提供偏置电流；
第二偏置电路，适于为所述噪声整形输入级电路提供偏置电流。
可选地，所述第一偏置电路包括第七PMOS管；
所述第七PMOS管的栅端与偏置电压耦接，所述第七PMOS管的源端与电源电压耦接，所述第七PMOS管的漏端与所述输入级电路耦接。
可选地，所述第二偏置电路包括第八PMOS管；
所述第八PMOS管的栅端与偏置电压耦接，所述第八PMOS管的源端与电源电压耦接，所述第八PMOS管的漏端与所述噪声整形输入级电路耦接。
可选地，所述比较器还包括以下至少一项：
第一输出复位电路，适于在所述采样相时，将所述比较器的正相输出端复位至电源电压；
第一输出复位电路，适于在所述采样相时，将所述比较器的反相输出端复位至电源电压。
可选地，所述第一输出复位电路包括第九PMOS管；
所述第九PMOS管的栅端用于接收第一时钟控制信号，所述第九PMOS管的源端与电源电压耦接，所述第九PMOS管的漏端与所述比较器的正相输出端耦接。
可选地，所述第二输出复位电路包括第十PMOS管；
所述第十PMOS管的栅端用于接收所述第一时钟控制信号，所述第十PMOS管的源端与电源电压耦接，所述第十PMOS管的漏端与所述比较器的反相输出端耦接。
可选地，所述比较器还包括以下至少一种：
第一输入复位电路，适于在所述采样相时，将所述输入级电路的第一输入端复位至预设的共模电压；
第二输入复位电路，适于在所述采样相时，将所述输入级电路的第二输入端复位至所述共模电压；
第三输入复位电路，适于在所述采样相时，将所述噪声整形输入级电路的第一输入端复位至所述共模电压；
第四输入复位电路，适于在所述采样相时，将所述噪声整形输入级电路的第二输入端复位至所述共模电压；
第五输入复位电路，适于在所述采样相时，将所述锁存级电路的第一输入端复位至所述共模电压；
第六输入复位电路，适于在所述采样相时，将所述锁存级电路的第二输入端复位至所述共模电压。
可选地，所述第一输入复位电路包括第一开关；
所述第一开关的控制端用于接收第二时钟控制信号，所述第一开关的第一导通端用于接收所述共模电压，所述第一开关的第二导通端与所述输入级电路的第一输入端耦接。
可选地，所述第二输入复位电路包括第二开关；
所述第二开关的控制端用于接收所述第二时钟控制信号，所述第二开关的第一导通端用于接收所述共模电压，所述第二开关的第二导通端与所述输入级电路的第二输入端耦接。
可选地，所述第三输入复位电路包括第三开关；
所述第三开关的控制端用于接收第二时钟控制信号，所述第三开关的第一导通端用于接收所述共模电压，所述第三开关的第二导通端与所述噪声整形输入级电路的第一输入端耦接。
可选地，所述第四输入复位电路包括第四开关；
所述第四开关的控制端用于接收所述第二时钟控制信号，所述第四开关的第一导通端用于接收所述共模电压，所述第四开关的第二导通端与所述噪声整形输入级电路的第二输入端耦接。
可选地，所述第五输入复位电路包括第五开关；
所述第五开关的控制端用于接收第二时钟控制信号，所述第五开关的第一导通端用于接收所述共模电压，所述第五开关的第二导通端与所述锁存级电路的第一输入端耦接。
可选地，所述第六输入复位电路包括第六开关；
所述第六开关的控制端用于接收所述第二时钟控制信号，所述第六开关的第一导通端用于接收所述共模电压，所述第六开关的第二导通端与所述锁存级电路的第二输入端耦接。
相应地，本发明实施例还提供了一种异步逐次逼近模数转换器，包括上述任一项所述比较器。
有益效果
与现有技术相比，本发明的技术方案具有以下优点：
上述的方案，通过在输入级电路、噪声整形输入级电路与锁存级电路之间设置隔离传输电路，可以将所述输入级电路输出的第一输出信号和第二输出信号，以及噪声整形输入级电路输出的第三输出信号和第四输出信号分别进行噪声隔离后输入至锁存级电路，使得输入级电路和噪声整形输入级电路的输出端之间相互独立，可以避免因输入级电路和噪声整形输入级电路的输出端共用所产生的回踢噪声，故可以提高四输入比较器的性能。
附图说明
图1为一种四输入比较器的结构示意图。
图2是本发明实施例中的一种比较器的框架结构示意图。
图3是本发明实施例中的一种输入级电路的结构示意图。
图4是本发明实施例中的一种噪声整形输入级电路的结构示意图。
图5是本发明实施例中的一种隔离传输电路的结构示意图。
图6是本发明实施例中的一种锁存级电路的结构示意图。
图7是本发明实施例中的一种比较器的相关脉冲信号的时序示意图。
本发明的实施方式
由背景技术可知，用于逐次逼近模数转换器的四输入比较器存在着性能差的问题。
参见图1，一种用于逐次逼近模数转换器的四输入比较器，具体包括预放大输入级电路11、噪声整形输入级电路12和锁存级电路13。
其中，预放大输入级电路11的第一输入端和第二输入端分别用于接收第一输入信号Inp和第二输入信号Inn，经放大后生成第一输出信号和第二输出信号传输至锁存级13的第一输入端和第二输入端，噪声整形输入级12的第一输入端和第二输入端分别用于接收第三输入信号Inp-ns和第四输入信号Inn-ns，经放大后生成第三输出信号和第四输出信号，且传输至锁存级13的第一输入端和第二输入端。
将预放大输入级电路11的第一输入端输出的第一输出信号与噪声整形输入级12的第一输入端输出的第三输入信号叠加后作为第一输入信号xp，并将噪声整形输入级12的第一输出端输出的第二输出信号与噪声整形输入级12的第二输入端输出的第四输入信号叠加后作为第二输入信号xn，锁存级电路13根据接收到的第一输入信号xp和第二输入信号xn的大小输出对应的比较结果。
上述的四输入比较器中，输入级电路11和噪声整形输入级电路12的输出端共用，将会存在较大的回踢噪声，严重影响了四输入比较器的性能。
为解决上述问题，本发明实施例中的技术方案通过在输入级电路、噪声整形输入级电路与锁存级电路之间设置隔离传输电路，可以将所述输入级电路输出的第一输出信号和第二输出信号，以及噪声整形输入级电路输出的第三输出信号和第四输出信号分别进行噪声隔离后 输入至锁存级电路，使得输入级电路和噪声整形输入级电路的输出端之间相互独立，可以避免因输入级电路和噪声整形输入级电路的输出端共用所产生的回踢噪声，故可以提高四输入比较器的性能。
为使本发明实施例的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图2示出了本发明实施例中的一种比较器的结构示意图。参见图2，本发明实施例中的一种比较器可以包括输入级电路21、噪声整形输入级电路22和锁存级电路24。
所述比较器具有第一对输入端(未标示)、第二对输入端(未标示)、正相输出端(未标示)和反相输出端(未标示)；所述第一对输入端包括第一输入端(未标示)和第二输入端(未标示)，所述第二对输入端包括第三输入端(未标示)和第四输入端(未标示)。
参见图3，所述输入级电路21具有第一输入端和第二输入端。所述输入级电路21的第一输入端作为所述比较器的第一输入端或与所述比较器的第一输入端耦接，用于接收第一输入信号Inp；所述输入级电路21的第二输入端作为所述比较器的第二输入端或与所述比较器的第二输入端耦接，用于接收第二输入信号Inn。所述输入级电路21可以在所述比较相时，对第一输入端接收到的第一输入信号Inp和所述第二输入端接收到的第二输入信号Inn分别进行放大，生成对应的第一输出信号Inp-out和第二输出信号Inn-out并分别传输至所述隔离传输电路。其中，
请参见图3，本发明一实施例中，所述输入级电路21包括第一输入放大单元(未标示)和第二输入放大单元(未标示)。其中：
所述第一输入放大单元具有输入端和输出端。所述第一输入放大单元的输入端作为所述输入级电路21的第一输入端或与所述输入级电路21的第一输入端耦接，用于接收所述第一输入信号Inp；所述第一输入放大单元的输出端作为所述输入级电路21的第二输出端或或与所述输入级电路21的第二输出端耦接，用于输出所述第一输出信号Inp-out。所述第一输入放大单元可以对所接收的所述第一输入信号Inp进行放大，生成所述第一输出信号Inp-out。
具体地，所述第一输入放大单元包括第一PMOS管PM1。其中，所述第一PMOS管PM1的栅端用于接收第一输入信号Inp，所述第一PMOS管PM1的源端与电源电压avdd耦接，所述第一PMOS管PM1的漏端作为所述输入级电路21的第一输出端或与所述输入级电路21的第一输出端耦接。
所述第二输入放大单元具有输入端和输出端。所述第二输入放大单元的输入端作为所述输入级电路21的第二输入端或与所述输入级电路21的第二输入端耦接，用于接收所述第二输入信号Inn；所述第二输入放大单元的输出端作为所述输入级电路21的第二输出端或与所述输入级电路21的第二输出端耦接，用于输出所述第二输出信号Inn-out。所述第二输入放大单元可以对所接收的所述第二输入信号Inn进行放大，生成所述二输出信号Inn-out。
具体地，所述第二输入放大单元包括第二PMOS管PM2。其中，所述第二PMOS管PM2的栅端用于接收第二输入信号Inp，所述第二PMOS管PM2的源端与电源电压avdd耦接，所述第二PMOS管PM2的漏端作为所述输入级电路21的第二输出端或与所述输入级电路21的第二输出端耦接。
本发明另一实施例中，所述输入级电路21还包括第一锁存单元(未标示)。
第一锁存单元具有第一锁存节点N1和第二锁存节点N2。所述第一锁存单元可以将所述第一输出信号Inp-out锁存至第一锁存节点N1且输入至所述隔离传输电路的第一输入端，并将所述第二输出信号Inn-out锁存至第二锁存节点N2且输入至所述隔离传输电路23的第二输入端。
具体地，所述第一锁存单元包括第一NMOS管NM1和第二NMOS管NM2。其中，所述第一NMOS管NM1的栅端与所述二NMOS管NM2的漏端耦接，且作为所述第二锁存节点 N2或与所述第二锁存节点N2耦接，所述第一NMOS管NM1的源端与所述第二NMOS管NM2的源端均与地电压avss耦接，所述第一NMOS管NM1的漏端与第二NMOS管NM2的栅端耦接，且作为所述第一锁存节点N1或与所述第一锁存节点N1耦接。
本发明又一实施例中，所述输入级电路21还包括第一增益提高单元(未标示)和第二增益提高单元(未标示)。其中：
所述第一增益提高单元可以提高所述第一输入放大单元的输出增益。具体地，所述第一增益提高单元包括第三NMOS管NM3。其中，所述第三NMOS管NM3的栅端和漏端耦接并与所述第一输入放大单元的输出端耦接，所述第三NMOS管NM3的源端与地电压avss耦接。
所述第二增益提高单元可以提高所述第二输入放大单元的输出增益。具体地，所述第二增益提高单元包括第四NMOS管NM4。其中，所述第四NMOS管NM4的栅端与漏端耦接并与所述第二输入放大单元的输出端耦接，所述第四NMOS管NM4的源端与地电压avss耦接。
请参见图4，所述噪声整形输入级电路22具有第一输入端和第二输入端、第一输出端和第二输出端。其中，所述噪声整形输入级电路22的第一输入端作为所述比较器的第三输入端或与所述比较器的第三输入端耦接，用于接收所述第三输入信号Inp-ns；所述噪声整形输入级电路22的第二输入端作为所述比较器的第四输入端或与所述比较器的第四输入端耦接，用于接收所述第四输入信号Inn-ns。所述噪声整形输入级电路22可以在所述比较器处于比较相时，对第一输入端接收到的第三输入信号Inp-ns和所述第二输入端接收到的第四输入信号Inn-ns分别进行放大，生成对应的第三输出信号Inp-ns-out和第四输出信号Inn-ns-out。
本发明一实施例中，所述噪声整形输入级电路22包括第一噪声整形放大单元(未标示)和第二噪声整形放大单元(未标示)。其中：
所述第一噪声整形放大单元具有输入端和输出端。所述第一噪声整形放大单元的输入端作为所述噪声整形输入级电路22的第一输入端或与所述噪声整形输入级电路22的第一输入端耦接，用于接收第三输入信号Inp-ns。所述第一噪声整形放大单元可以对所接收的第三输入信号Inp-ns进行放大，生成所述第三输出信号Inp-ns-out。
具体地，所述第一噪声整形放大单元包括第三PMOS管PM3。其中，所述第三PMOS管PM3的栅端用于接收所述第三输入信号Inp-ns，所述第三PMOS管PM3的源端与电源电压avdd耦接，所述第三PMOS管PM3的漏端作为所述噪声整形输入级电路22的第一输出端或与所述噪声整形输入级电路22的第一输出端耦接。
所述第二噪声整形放大单元具有输入端和输出端。其中，所述第二噪声整形放大单元的输入端作为所述噪声整形输入级电路22的第二输入端或与所述噪声整形输入级电路22的第二输入端耦接，用于接收第四输入信号Inn-ns。所述第一噪声整形放大单元可以对所接收的第四输入信号Inn-ns进行放大，生成所述第四输出信号Inn-ns-out。
具体地，所述第二噪声整形放大单元包括第四PMOS管PM4。其中，所述第四PMOS管PM4的栅端与所述第四输入信号Inn-ns耦接，所述第四PMOS管PM4的源端与电源电压avdd耦接，所述第四PMOS管PM4的漏端作为所述噪声整形输入级电路22的第二输出端或与所述噪声整形输入级电路22的第二输出端耦接。
在本发明一实施例中，所述噪声整形输入级电路22还可以包括第二锁存单元(未标示)。
第二锁存单元具有第三锁存节点N3和第四锁存节点N4。所述第二锁存单元可以将所述第三输出信号Inp-ns-out锁存至第三锁存节点N3且输入至所述隔离传输电路的第三输入端，并将所述第四输出信号Inn-ns-out锁存至第四锁存节点N4且输入至所述隔离传输电路的第四输入端。
具体地，所述第二锁存单元包括第五NMOS管NM5和第六NMOS管NM6。其中，所述第五NMOS管NM5的栅端与所述第六NMOS管NM6的漏端耦接，且作为所述第四锁存节点N4或与所述第四锁存节点N4耦接，所述第五NMOS管NM5的源端与所述第六NMOS 管NM6的源端均与地电压avss耦接，所述第五NMOS管NM5的漏端与第六NMOS管NM6的栅端耦接，且作为所述第三锁存节点N3或与所述第三锁存节点N3耦接。
在本发明另一实施例中，所述噪声整形输入级22还包括第三增益提高单元(未标示)和第四增益提高单元(未标示)。
所述第三增益提高单元可以提高所述第一噪声整形放大单元的输出增益。具体地，所述第三增益提高单元包括第七NMOS管NM7。其中，所述第七NMOS管NM7的栅端与漏端耦接并与所述第一噪声整形放大单元的输出端耦接，所述第七NMOS管NM7的源端与地电压avss耦接。
所述第四增益提高单元可以提高所述第二噪声整形放大单元的输出增益。具体地，所述第四增益提高单元包括第八NMOS管NM8。其中，所述第八NMOS管NM8的栅端与漏端及所述第二噪声整形放大单元的输出端耦接，所述第八NMOS管NM8的源端与地电压avss耦接。
请参见图5，在具体实施中，所述隔离传输电路23具有第一输入端、第二输入端、第三输入端和第四输入端，且具有第一输出端、第二输出端、第三输出端和第四输出端。所述隔离传输电路23的第一输入端与输入级电路21的第一输出端耦接，所述隔离传输电路23的第二输入端与输入级电路21的第二输出端耦接，所述隔离传输电路23的第三输入端与所述噪声整形输入级电路21的第一输出端耦接，所述隔离传输电路23的第四输入端与所述噪声整形输入级电路21的第二输出端耦接。所述隔离传输电路23可以在所述比较器处于比较相时，对所述第一输入端所接收的第一输出信号Inp-out、第二输入端所接收的第二输出信号Inn-out、第三输入端所接收的第三输出信号Inp-ns-out和第四输入端所接收的第四输出信号Inn-ns-out分别进行噪声隔离，生成第一噪声隔离信号、第二噪声隔离信号、第三噪声隔离信号和第四噪声隔离信号，并输入至所述锁存级电路。
具体地，所述隔离传输电路23包括第一电容C1、第二电容C2、第三电容C3和第四电容C4。其中，所述第一电容C1的第一端与所述输入级电路的第一输出端耦接，所述第一电容C1的第二端与所述锁存级电路的第一输入端(N5节点)耦接；所述第二电容C2的第一端与所述输入级电路的第二输出端耦接，所述第二电容C2的第二端与所述锁存级电路的第二输入端(N6节点)耦接；所述第三电容C3的第一端与所述噪声整形输入级电路的第一输出端耦接，所述第三电容C3的第二端与所述锁存级电路的第一输入端耦接；所述第四电容C4的第一端与所述噪声整形输入级电路的第二输出端耦接，所述第四电容C4的第二端与所述锁存级电路的第二输入端耦接。
请参见图6，在具体实施中，所述锁存级电路24具有第一输入端和第二输入端、正相输出端和反相输出端。其中，所述锁存级电路24的第一输入端分别与所述隔离传输电路的第一输出端和第三输出端耦接，所述锁存级电路24的第二输入端分别与所述隔离传输电路的第二输出端和第四输出端耦接。所述锁存级电路24可以接收第一噪声隔离信号与第三噪声隔离信号的第一叠加电平信号及所述第二噪声隔离信号、第四噪声隔离信号的第二叠加电平信号进行比较，生成对应的比较结果并分别通过其正相输出端和反相输出端输出。
本发明一实施例中，所述锁存级电路24包括开关单元(未标示)、第一锁存放大单元(未标示)、第二锁存放大单元(未标示)和第三锁存单元(未标示)。其中：
所述开关单元具有控制端、第一导通端和第二导通端。其中，所述开关单元的控制端用于接收所述第一时钟控制信号clk1，所述开关单元的第一导通端分别与所述第一锁存放大单元和所述第二锁存放大单元耦接，所述开关单元的第二导通端与地电压avss耦接。所述开关单元可以在所述比较器处于比较相时导通。
具体地，所述开关单元包括第九NMOS管NM9。其中，所述第九NMOS管NM9的栅端作为所述开关单元的控制端或者与所述开关单元的控制端耦接，且用于接收第一时钟控制信 号clk1；所述第九NMOS管NM9的源端作为所述开关单元的第一导通端或与所述开关单元的第一导通端耦接，且与地电压avss耦接；所述第九NMOS管NM9的漏端作为所述开关单元的第二导通端或者与所述开关单元的第二导通端耦接，且分别与所述第一锁存放大单元和第二锁存放大单元耦接。
第一锁存放大单元具有控制端、第一导通端和第二导通端。其中，所述第一锁存放大单元的控制端作为所述锁存级电路24的第一输入端或与所述锁存级电路24的第一输入端耦接，第一锁存放大单元的第一导通端与所述第三锁存单元耦接，所述第一锁存放大单元的第二导通端与所述开关单元耦接。所述第一锁存放大单元可以在所述开关单元导通时，对所接收的第一噪声隔离信号和第三噪声隔离信号的第一叠加电平信号进行放大。
具体地，所述第一锁存放大单元包括第十NMOS管NM10。其中，所述第十NMOS管NM10的栅端作为所述锁存级电路24的第一输入端或与所述锁存级电路24的第一输入端耦接，所述十NMOS管NM10的源端与所述开关单元耦接，所述十NMOS管NM10的漏端与所述第三锁存单元耦接。
所述第二锁存放大单元具有控制端、第一导通端和第二导通端。所述第二锁存放大单元的控制端作为所述锁存级电路24的第二输入端或与所述锁存级电路24的第二输入端耦接，第二锁存放大单元的第一导通端与所述第三锁存单元耦接，所述第二锁存放大单元的第二导通端与所述开关单元耦接。所述第二锁存放大单元可以在所述开关单元导通时，对所接收的所接收的第二噪声隔离信号和第四噪声隔离信号的第二叠加电平信号进行放大。
具体地，所述第二锁存放大单元包括第十一NMOS管NM11。其中，所述第十一NMOS管NM11的栅端作为所述锁存级电路24的第二输入端或与所述锁存级电路24的第二输入端耦接，所述十一NMOS管NM11的源端与所述开关单元耦接，所述十一NMOS管NM11的漏端与所述第三锁存单元耦接。
所述第三锁存单元具有第一输入端、第二输入端、第一输出端和第二输出端。其中，所述第三锁存单元的第一输入端与所述第一锁存放大单元耦接，所述第三锁存单元的第二输入端与所述第二锁存放大单元耦接，所述第三锁存单元的第一输出端作为所述比较器的正相输出端或与所述比较器的正相输出端耦接，所述第三锁存单元的第二输出端作为所述比较器的反相输出端或与所述比较器的反相输出端耦接。所述第三锁存单元可以对所述放大后的第一叠加电平信号和放大后的第二叠加电平信号进行锁存并比较，输出对应的比较结果并分别通过第一输出端和第二输出端输出。
具体地，所述第三锁存单元包括第五PMOS管PM5、第十二NMOS管NM12、第六PMOS管PM6和第十三NMOS管NM13。其中，所述第五PMOS管PM5的栅端与所述第十二NMOS管NM12的栅端耦接并与第六PMOS管PM6的漏端和所述第十三NMOS管NM13的漏端耦接，且作为所述比较器的反相输出端或与所述比较器的反相输出端耦接，所述第五PMOS管PM5的漏端与所述第十二NMOS管NM12的漏端耦接并与第六PMOS管PM6的栅端和所述第十三NMOS管NM13的栅端耦接，且作为所述比较器的正相输出端或与所述比较器的正相输出端耦接，所述第五PMOS管PM5的源端和所述第六PMOS管PM6的源端与电源电压avdd耦接，所述第十二NMOS管NM12的源端与所述第一锁存放大单元耦接，所述第十三NMOS管NM13的源端与所述第二锁存放大单元耦接。
请继续参见图3，本发明一实施例中，所述比较器还包括第一偏置电路25。
所述第一偏置电路25具有控制端、第一导通端和第二导通端。其中，所述第一偏置电路25的控制端用于接收预设的偏置电压vbias，所述第一偏置电路的第一导通端与电源电压avdd耦接，所述第一偏置电路的第二导通端与所述输入级电路21耦接。所述第一偏置电路25可以为所述输入级电路21提供偏置电流。
具体地，所述第一偏置电路25包括第七PMOS管PM7。其中，所述第七PMOS管PM7 的栅端作为所述第一偏置电路25的控制端或与所述第一偏置电路25的控制端耦接，且用于接收所述偏置电压vbias；所述第七PMOS管PM7的源端作为所述第一偏置电路25的第一导通端或与所述第一偏置电路25的第一导通端耦接，且与电源电压avdd耦接；所述第七PMOS管PM7的漏端与所述输入级电路21耦接。
请继续参见图4，本发明一实施例中，所述比较器还包括第二偏置电路26。
所述第二偏置电路26具有控制端、第一导通端和第二导通端。其中，所述第二偏置电路26的控制端用于接收偏置电压Vbias，所述第二偏置电路26的第一导通端与电源电压avdd耦接，所述第二偏置电路26的第二导通端与所述噪声整形输入级电路22耦接。所述第二偏置电路26可以为所述噪声整形输入级电路22提供偏置电流。
具体地，所述第二偏置电路26包括第八PMOS管PM8。其中，所述第八PMOS管PM8的栅端与偏置电压vbias耦接，所述第八PMOS管PM8的源端与电源电压avdd耦接，所述第八PMOS管PM8的漏端与所述噪声整形输入级电路23耦接。
请继续参见图6，在本发明另一实施例中，所述比较器还包括第一输出复位电路27。
所述第一输出复位电路27具有控制端、第一导通端和第二导通端。其中，所述第一输出复位电路27的控制端用于接收所述第一时钟控制信号clk1，所述第一输出复位电路27的第一导通端与所述电源电压avdd耦接，所述第一输出复位电路27的第二导通端与所述比较器的正相输出端耦接。所述第一输出复位电路27可以在所述采样相时，将所述比较器的正相输出端复位至电源电压avdd。
具体地，所述第一输出复位电路27包括第九PMOS管PM9。其中，所述第九PMOS管PM9的栅端用于接收所述第一时钟控制信号clk1，所述第九PMOS管PM9的源端与电源电压avdd耦接，所述第九PMOS管PM9的漏端与所述比较器的正相输出端耦接。
请继续参见图6，在本发明另一实施例中，所述比较器还包括第二输出复位电路28。
所述第二输出复位电路28具有控制端、第一导通端和第二导通端。其中，所述第二输出复位电路28的控制端用于接收所述第一时钟控制信号clk1，所述第二输出复位电路28的第一导通端与所述电源电压avdd耦接，所述第二输出复位电路28的第二导通端与所述比较器的反相输出端耦接。所述第二输出复位电路28可以在所述采样相时，将所述比较器的反相输出端复位至电源电压avdd。
具体地，所述第二输出复位电路28包括第十PMOS管PM10。其中，所述第十PMOS管PM10的栅端用于接收所述第一时钟控制信号clk1，所述第十PMOS管PM10的源端与电源电压avdd耦接，所述第十PMOS管PM10的漏端与所述比较器的反相输出端耦接。
请继续参见图3，在本发明又一实施例中，所述比较器还包括第一输入级复位电路29和第二输入级复位电路30。其中：
所述第一输入级复位电路29具有控制端、第一导通端和第二导通端。其中，所述第一输入级复位电路29的控制端用于接收预设的第二时钟控制信号clk2，所述第一输入级复位电路29的第一导通端用于接收共模电压vcm，所述第一输入级复位电路29的第二导通端与所述输入级电路的第一输入端耦接。所述第一输入级复位电路29可以在所述采样相时，将所述输入级电路的第一输入端复位至所述共模电压vcm。
具体地，所述第一输入级复位电路29包括第一开关S1。其中，所述第一开关S1的控制端用于接收第二时钟控制信号clk2，所述第一开关S1的第一导通端用于接收所述共模电压vcm，所述第一开关S1的第二导通端与所述输入级电路21的第一输入端耦接。
所述第二输入级复位电路30具有控制端、第一导通端和第二导通端。其中，所述第二输入级复位电路30的控制端用于接收第二时钟控制信号clk2，所述第二输入级复位电路30的第一导通端用于接收所述共模电压vcm，所述第二输入级复位电路30的第二导通端与所述输入级电路21的第二输入端耦接。所述第二输入级复位电路30可以在所述采样相时，将 所述输入级电路21的第二输入端复位至所述共模电压vcm。
具体地，所述第二输入级复位电路30包括第二开关S2。其中，所述第二开关S2的控制端用于接收第二时钟控制信号clk2，所述第二开关S2的第一导通端用于接收所述共模电压vcm，所述第二开关S2的第二导通端与所述输入级电路21的第二输入端耦接。
请继续参见图4，在本发明又一实施例中，所述比较器还包括第一噪声整形输入级复位电路31和第二噪声整形输入级复位电路32。其中：
所述第一噪声整形输入级复位电路31具有控制端、第一导通端和第二导通端。其中，所述第一噪声整形输入级复位电路31的控制端用于接收所述第二时钟控制信号clk2，所述第一噪声整形输入级复位电路31的第一导通端用于接收所述共模电压vcm，所述第一噪声整形输入级复位电路31的第二导通端与所述噪声整形输入级电路22的第一输入端耦接。所述第一噪声整形输入级复位电路31可以在所述采样相时，将所述噪声整形输入级电路22的第一输入端复位至所述共模电压vcm。
具体地，所述第一噪声整形输入级复位电路31包括第三开关S3。其中，所述第三开关S3的控制端用于接收第二时钟控制信号clk2，所述第三开关S3的第一导通端用于接收所述共模电压vcm，所述第三开关S3的第二导通端与所述噪声整形输入级电路22的第一输入端耦接。
所述第二噪声整形输入级复位电路32具有控制端、第一导通端和第二导通端。其中，所述第二噪声整形输入级复位电路32的控制端用于接收所述第二时钟控制信号clk2，所述第二噪声整形输入级复位电路32的第一导通端用于接收所述共模电压vcm，所述第二噪声整形输入级复位电路32的第二导通端与所述噪声整形输入级电路22的第二输入端耦接。所述第二噪声整形输入级复位电路32可以在所述采样相时，将所述噪声整形输入级电路22的第二输入端复位至所述共模电压vcm。
具体地，所述第二噪声整形输入级复位电路32包括第四开关S4。其中，所述第四开关S4的控制端用于接收第二时钟控制信号clk2，所述第四开关S4的第一导通端用于接收所述共模电压vcm，所述第四开关S4的第二导通端与所述噪声整形输入级电路的第一输入端耦接。
请继续参见图6，在本发明又一实施例中，所述比较器还包括第一锁存级复位电路33和第二锁存级复位电路34。其中：
所述第一锁存级复位电路33具有控制端、第一导通端和第二导通端。其中，所述第一锁存级复位电路33的控制端用于接收所述第二时钟控制信号clk2，所述第一锁存级复位电路33的第一导通端用于接收所述共模电压vcm，所述第一锁存级复位电路33的第二导通端与所述锁存级电路24的第一输入端耦接。所述第一锁存级复位电路33可以在所述采样相时，将所述锁存级电24路的第一输入端复位至所述共模电压vcm。
具体地，所述第一锁存级复位电路33包括第五开关S5。其中，所述第五开关S5的控制端用于接收第二时钟控制信号clk2，所述第五开关S5的第一导通端用于接收所述共模电压vcm，所述第五开关S5的第二导通端与所述噪声整形输入级电路22的第一输入端耦接。
所述第二锁存级复位电路34具有控制端、第一导通端和第二导通端。其中，所述第二锁存级复位电路34的控制端用于接收所述第二时钟控制信号clk2，所述第二锁存级复位电路34的第一导通端用于接收所述共模电压vcm，所述第二锁存级复位电路34的第二导通端与所述锁存级电路24的第二输入端耦接。所述第二锁存级复位电路34可以在所述采样相时，将所述锁存级电路24的第二输入端复位至所述共模电压vcm。
具体地，所述第二锁存级复位电路34包括第六开关S6。其中，所述第六开关S6的控制端用于接收第二时钟控制信号clk2，所述第六开关S6的第一导通端用于接收所述共模电压vcm，所述第六开关S6的第二导通端与所述锁存级电路24的第一输入端耦接。
上述对本发明实施例中的比较器的结构进行了描述，下面将对本发明实施例中的比较器的工作方法进行介绍。
请参见图7，并结合图2至图6，当第二时钟控制信号clk2为高电平时，所述比较器处于采样相。
此时，所述第一输出复位电路27、第二输出复位电路28在第一时钟控制信号clk1的控制下，分别将所述比较器的正相输出端和反相输出端复位至电源电压avdd。
具体地，第一时钟控制信号clk1为逻辑低电平，第九PMOS管PM9和第十PMOS管PM10均导通，电源电压avdd分别通过第九PMOS管PM9和第十PMOS管PM10传输至比较器的正相输出端和反相输出端，从而将所述比较器的正相输出端和反相输出端上拉至电源电压avdd。
与此同时，第一输入级复位电路29、第二输入级复位电路30、第三噪声整形输入级复位电路31、第二噪声整形输入级复位电路32、第一锁存级复位电路33和第二锁存级级复位电路34，分别将输入级电路21的第一输入端和第二输入端和噪声整形输入级电路22的第一输入端和第二输入端及锁存级电路24的第一输入端和第二输入端分别复位至共模电压vcm。
具体地，第二时钟控制信号clk2为高电平时，第一开关S1、第二开关S2、第三开关S3、第四开关S4、第五开关S5和第六开关S6均导通，共模电压vcm被传输至输入级电路21的第一输入端和第二输入端、噪声整形输入级电路22的第一输入端和第二输入端及锁存级电路24的第一输入端和第二输入端，从而将输入级电路21的第一输入端和第二输入端、噪声整形输入级电路22的第一输入端和第二输入端及锁存级电路24的第一输入端和第二输入端分别复位至共模电压vcm。
之后，当第二时钟控制信号CLK2低电平时，所述比较器处于比较相。
此时，第一开关S1、第二开关S2、第三开关S3、第四开关S4、第五开关S5和第六开关S6均断开，共模电压vcm与输入级电路21的第一输入端和第二输入端、噪声整形输入级电路22的第一输入端和第二输入端及锁存级电路24的第一输入端和第二输入端断开连接。
同时，第一输入信号Inp和第二输入信号Inn分别通过输入级电路21的第一输入端和第二输入端输入至比较器，第三输入信号Inp-ns和第四输入信号Inn-ns分别通过噪声整形输入级电路22的第一输入端和第二输入端输入至比较器。
当第一时钟控制信号clk1的下降沿到来时，第一输入信号Inp、第二输入信号Inn及第三输入信号Inp-ns、第四输入信号Inn-ns经过采样相中半个周期的逻辑低电平时间达到稳定状态。
在此过程中，输入级电路21分别对第一输入信号Inp、第二输入信号Inn进行放大，生成第一输出信号Inp-out和第二输出信号Inn-out。
当第一输入信号Inp大于第二输入信号Inn时，所述第一输入放大单元中的第一PMOS管PM1的栅端和源端的电压差将小于第二输入放大单元中的第二PMOS管PM2的栅端和源端的电压差，故而第一PMOS管PM1的导通电流小于第二PMOS管PM2的导通电流，从而使得第一PMOS管PM1的漏端的充电速度将慢于所述第一PMOS管PM2漏端的充电速度，进而使得第一PMOS管PM1漏端电压小于第二PMOS管PM2的漏端电压，也即第一锁存节点N1的电压将小于第二锁存节点N2的电压。同时，第一锁存单元中第一NMOS管NM1和第二NMOS管NM2的存在，将使得即第一锁存节点N1的电压维持在小于第二锁存节点N2的电压的状态。反之，当第一输入信号Inp小于第二输入信号Inn时，第一锁存节点N1的电压将大于第二锁存节点N2的电压。
类似地，噪声整形输入级电路22分别对第三输入信号Inp-ns、第四输入信号Inn-ns进行放大，分别生成对应第三输出信号Inp-ns-out和第四输出信号Inn-ns-out。
具体地，当第三输入信号Inp-ns大于第四输入信号Inn-ns时，所述第一噪声整形放大单元中的第三PMOS管PM3的栅端和源端的压差将小于第二噪声整形放大单元中的第四PMOS管PM4的栅端和源端的压差，故而第三PMOS管PM3的导通电流小于第四PMOS管PM4的导通电流，从而使得第三PMOS管PM3的漏端的上拉速度将慢于所述第四PMOS管PM4的上拉速度，进而使得第三PMOS管PM3漏端电压小于第四PMOS管PM4的漏端电压，也即第三锁存节点N3的电压将小于第四锁存节点N4的电压。同时，第二锁存单元中第三NMOS管NM3和第四NMOS管NM4的存在，将使得即第三锁存节点N3的电压维持在小于第四锁存节点N4的电压的状态。反之，当第三输入信号Inp-ns小于第四输入信号Inn-ns时，则第三锁存节点N3的电压大于第四锁存节点N4的电压。
输入级电路21输出的第一输出信号Inp-out和第二输出信号Inn-out，以及噪声整形输入级电路23输出的第三输出信号Inp-ns-out和第四输出信号Inn-ns-out，分别经所述隔离传输电路23中的第一电容C1、第二电容C2、第三电容C3和第四电容C4进行噪声隔离后传输至锁存级电路24的第一输入端和第二输入端。
具体而言，当第一差分输入电压Inp大于第二差分输入电压Inn，且第三差分输入电压Inp-ns大于第四差分输入电压Inn-ns时，则第一锁存节点N1的电压小于第二锁存节点N2的电压，且第三锁存节点N3的电压小于第四锁存节点N4的电压，输入至锁存级电路24的第一输入端与第二输入端的电压之间的关系可以等效为第一差分输入电压Inp与第三差分输入电压Inp-ns之和与第二差分输入电压Inn与第四差分输入电压Inn_ns之和之间的关系，即节点N5的电压小于节点N6的电压。反之，当第一差分输入电压Inp小于第二差分输入电压Inn，且第三差分输入电压Inp-ns小于第四差分输入电压Inn-ns时，则节点N5的电压将大于节点N6的电压。
随后，当第一时钟控制信号clk1的上升沿到来时，锁存级电路24将其第一输入端和第二输入端接收到的电压进行比较，也即将节点N5与节点N6的电压进行比较。
具体地，当第一时钟控制信号clk1为高电平时，锁存级电路24的开关单元中的第九NMOS管NM9导通。在第九NMOS管NM9导通时，第九NMOS管NM9的源端接地电压avss，且之前在比较器处于采样相时，第十NMOS管NM10和第十一NMOS管NM11的栅端电压均为电源电压avdd。因此，当节点N5的电压小于节点N6的电压，即所述锁存级电路24的第一输入端接收的电压小于第二输入端接收到的电压时，第十NMOS管NM10的漏端先于第十一NMOS管NM11的漏端被第九NMOS管NM9下拉至地电压avss，从而使得第十二NMOS管NM12的栅端与源端之间的电压差大于第十三NMOS管NM13的栅端与源端之间的电压差，进而使得第十二NMOS管NM12的栅端大于第十三NMOS管NM13的栅端，即比较器的正相输出端的电压outp大于反相输出端的电压outn。反之，当所述锁存级电路24的第一输入端接收的电压大于第二输入端接收到的电压，也即节点N5的电压大于节点N6的电压时，比较器的正相输出端的电压outp小于反相输出端的电压outn。
同时，第三锁存单元中的第五PMOS管PM5、第十二NMOS管NM12、第六PMOS管PM6和第十三NMOS管NM13构成的交叉耦合正反馈结构，使得比较器的正相输出端的电压outp维持在大于或小于比较器的反相输出端的电压outn的状态。
一方面，隔离传输电路23的存在，输入级电路21的第一输出端和第二输出端输出的第一输出信号Inp-out和第二输出信号Inn-out分别通过第一电容C1和第二电容C2耦合至锁存级电路24的第一输入端和第二输入端，所述噪声整形输入级电路22的第一输出端和第二输出端输出的第三输出信号Inp-ns-out和第四输出信号Inn-ns-out分别通过第三电容C3和第四电容C4耦合至锁存级电路24的第一输入端和第二输入端，使得输入级电路21和噪声整形输入级电路22的输出端之间相互独立。因此，可以避免因输入级电路21的第一输出端和第二输出端及噪声整形输入级电路22的第一输出端和第二输出端直接接入锁存级电路24 的第一输入端和第二输入端时，锁存级的正相输出端和反相输出端的输出电压从采样相时的电源电压avdd变化为比较相时的outp和outn时，对输入级电路21和噪声整形输入级电路22产生耦合作用，故而可以起到隔离和减少回踢噪声的作用。
另一方面，当比较器处于采样相时，比较器的输入失调电压被输入级电路21和噪声整形输入级电路放大后的存储至隔离传输电路23的第一电容C1、第二电容C2、第三电容C3和第四电容C4上。此时，第一电容C1、第二电容C2、第三电容C3和第四电容C4上的存储电压相当于比较器的输出失调电压，记为(Av*Voffset)，其中，Av表示输入级电路或噪声整形输入级电路的增益，Voffset表示所述输入失调电压。之后，当比较器处于比较相，即第二时钟控制信号clk2为低电平时，第一输入信号Inp和第二输入信号Inn及第三输入信号Inp-ns和第四输出信号Inn-ns分别接入到输入级电路21和噪声整形输入级电路22，经过输入级电路21和噪声整形输入级电路22放大，输出电压记为(Av*(VIn+Voffset))，在传输至锁存级电路24之前，输出电压记为(Av*(VIn+Voffset))中的输入失调电压(Av*Voffset)分别与隔离传输电路23中的第一电容C1、第一电容C2、第一电容C3和第四电容C4上分别存储的输出失调电压(Av*Voffset)进行抵消，输出值变为(Av*VIn)，故可以消除失调电压，进而可以提高本发明实施例中的比较器的精度。
此外，第一偏置电路中的第七PMOS管PM7和第二偏置电路中第八PMOS管PM8给输入级电路21和噪声整形输入级电路22分别提供偏置电流，可以避免因输入信号瞬间接入时所产生的噪声，故可以提高本发明实施例中的比较器的性能。
相应地，本发明实施例还提供了一种逐次逼近模数转换器，包括所述比较器。其中，所述比较器请参见前述部分的详细介绍，不再赘述。
上述本发明的实施方式是本发明的元件和特征的组合。除非另外提及，否则所述元件或特征可被视为选择性的。各个元件或特征可在不与其它元件或特征组合的情况下实践。另外，本发明的实施方式可通过组合部分元件和/或特征来构造。本发明的实施方式中所描述的操作顺序可重新排列。任一实施方式的一些构造可被包括在另一实施方式中，并且可用另一实施方式的对应构造代替。对于本领域技术人员而言明显的是，所附权利要求中彼此没有明确引用关系的权利要求可组合成本发明的实施方式，或者可在提交本申请之后的修改中作为新的权利要求包括。
本发明的实施方式可通过例如硬件、固件、软件或其组合的各种手段来实现。在硬件配置方式中，根据本发明示例性实施方式的方法可通过一个或更多个专用集成电路(ASIC)、数字信号处理器(DSP)、数字信号处理器件(DSPD)、可编程逻辑器件(PLD)、现场可编程门阵列(FPGA)、处理器、控制器、微控制器、微处理器等来实现。
在固件或软件配置方式中，本发明的实施方式可以模块、过程、功能等形式实现。软件代码可存储在存储器单元中并由处理器执行。存储器单元位于处理器的内部或外部，并可经由各种己知手段向处理器发送数据以及从处理器接收数据。
对所公开的实施例的上述说明，使本领域技术人员能够实现或使用本发明。对这些实施例的多种修改对本领域技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下，在其他实施例中实现。因此，本发明将不会被限制于本文所示的这些实施例，而是符合与本文所公开的原理和新颖特点相一致的最宽的范围。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (37)

  1. 一种比较器，所述比较器具有采样相和比较相，其特征在于，包括：
    输入级电路，适于在所述比较相时，对接收到的第一输入信号和第二输入信号分别进行放大，生成对应的第一输出信号和第二输出信号并分别传输至隔离传输电路；
    噪声整形输入级电路，适于在所述比较相时，对接收到的第三输入信号和第四输入信号分别进行放大，生成对应的第三输出信号和第四输出信号并传输至所述隔离传输电路；
    所述隔离传输电路，适于在所述比较相时，对所接收的所述第一输出信号、所述第二输出信号、所述第三输出信号和所述第四输出信号分别进行噪声隔离，生成第一噪声隔离信号、第二噪声隔离信号、第三噪声隔离信号和第四噪声隔离信号并输入至锁存级电路；
    所述锁存级电路，适于接收到的第一噪声隔离信号和第三噪声隔离信号的第一叠加电平信号与所述第二噪声隔离信号和第四噪声隔离信号的第二叠加电平信号进行比较，生成对应的比较结果并输出。
  2. 根据权利要求1所述的比较器，其特征在于，所述输入级电路包括第一输入放大单元和第二输入放大单元；
    所述第一输入放大单元，适于对所述第一输入信号进行放大，生成所述第一输出信号；
    所述第二输入放大单元，适于对所述第二输入信号进行放大，生成所述第二输出信号。
  3. 根据权利要求2所述的比较器，其特征在于，所述第一输入放大单元包括第一PMOS管；
    所述第一PMOS管的栅端用于接收所述第一输入信号，所述第一PMOS管的源端与电源电压耦接，所述第一PMOS管的漏端作为所述输入级电路的第一输出端或与所述输入级电路的第一输出端耦接。
  4. 根据权利要求2所述的比较器，其特征在于，所述第二输入放大单元包括第二PMOS管；
    所述第二PMOS管的栅端用于接收所述第二输入信号，所述第二PMOS管的源端与电源电压耦接，所述第二PMOS管的漏端作为为所述输入级电路的第二输出端或与所述输入级电路的第二输出端耦接。
  5. 根据权利要求2至4任一项所述的比较器，其特征在于，所述输入级电路还包括：
    第一锁存单元，具有第一锁存节点和第二锁存节点，适于对所述第一输出信号和所述第二输出信号分别锁存至所述第一锁存节点和所述第二锁存节点并输入至所述隔离传输电路。
  6. 根据权利要求5所述的比较器，其特征在于，所述第一锁存单元包括第一NMOS管和第二NMOS管；
    所述第一NMOS管的栅端与所述二NMOS管的漏端耦接，且作为所述第二锁存节点或与所述第二锁存节点耦接，所述第一NMOS管的源端与所述第二NMOS管的源端均与地电压耦接，所述第一NMOS管的漏端与第二NMOS管的栅端耦接，且作为所述第一锁存节点或与所述第一锁存节点耦接。
  7. 根据权利要求2所述比较器，其特征在于，所述输入级电路还包括第一增益提高单元和第二增益提高单元；
    所述第一增益提高单元，适于提高所述第一输入放大单元的输出增益；
    所述第二增益提高单元，适于提高所述第二输入放大单元的输出增益。
  8. 根据权利要求7所述比较器，其特征在于，所述第一增益提高单元包括第三NMOS管；
    所述第三NMOS管的栅端和漏端耦接并与所述第一输入放大单元的输出端耦接，所述第三NMOS管的源端与地电压耦接。
  9. 根据权利要求7所述比较器，其特征在于，所述第二增益提高单元包括第四NMOS管；
    所述第四NMOS管的栅端与漏端耦接并与所述第二输入放大单元的输出端耦接，所述第四NMOS管的源端与地电压耦接。
  10. 根据权利要求1所述的比较器，其特征在于，所述噪声整形输入级电路包括第一噪声整形放大单元和第二噪声整形放大单元；
    所述第一噪声整形放大单元，适于对所接收的第三输入信号进行放大，生成所述第三输出信号；
    所述第二噪声整形放大单元，适于将所接收所述第四输入信号进行放大，生成所述第四输出信号。
  11. 根据权利要求10所述的比较器，其特征在于，所述第一噪声整形放大单元包括第三PMOS管；
    所述第三PMOS管的栅端用于接收所述第三输入信号，所述第三PMOS管的源端与电源电压耦接，所述第三PMOS管的漏端作为所述噪声整形放大单元的第一输出端或与所述噪声整形放大单元的第一输出端耦接。
  12. 根据权利要求10所述的比较器，其特征在于，所述第二噪声整形放大单元包括第四PMOS管；
    所述第四PMOS管的栅端用于接收所述第四输入信号，所述第四PMOS管的源端与电源电压耦接，所述第四PMOS管的漏端作为所述噪声整形放大单元的第二输出端或与所述噪声整形放大单元的第二输出端耦接。
  13. 根据权利要求10至12任一项所述的比较器，其特征在于，所述噪声整形输入级电路还包括：
    第二锁存单元，具有第三锁存节点和第四锁存节点，适于将所述第三输出信号和所述第四输出信号分别锁存至所述第三锁存节点和所述第四锁存节点并分别输入至所述隔离传输电路。
  14. 根据权利要求13所述的比较器，其特征在于，所述第二锁存单元包括第五NMOS管和第六NMOS管；
    所述第五NMOS管的栅端与所述第六NMOS管的漏端耦接，且作为所述第四锁存节点或与所述第四锁存节点耦接，所述第五NMOS管的源端与所述第六NMOS管的源端均与地电压耦接，所述第五NMOS管的漏端与第六NMOS管的栅端耦接，且作为所述第三锁存节点或与所述第三锁存节点耦接。
  15. 根据权利要求13所述比较器，其特征在于，所述噪声整形输入级还包括第三增益提高单元和第四增益提高单元；
    所述第三增益提高单元，适于提高所述第一噪声整形放大单元的输出增益；
    所述第四增益提高单元，适于提高所述第二噪声整形放大单元的输出增益。
  16. 根据权利要求15所述比较器，其特征在于，所述第三增益提高单元包括第七NMOS管；
    所述第七NMOS管的栅端与漏端耦接并与所述第一噪声整形放大单元的输出端耦接，所述第七NMOS管的源端与地电压耦接。
  17. 根据权利要求15所述比较器，其特征在于，所述第四增益提高单元包括第八NMOS管；
    所述第八NMOS管的栅端与漏端及所述第二噪声整形放大单元的输出端耦接，所述第八NMOS管的源端与地电压耦接。
  18. 根据权利要求1所述的比较器，其特征在于，所述隔离传输电路包括第一电容、第二电容、第三电容和第四电容；
    所述第一电容的第一端与所述输入级电路的第一输出端耦接，所述第一电容的第二端与所述锁存级电路的第一输入端耦接；
    所述第二电容的第一端与所述输入级电路的第二输出端耦接，所述第二电容的第二端与所述锁存级电路的第二输入端耦接；
    所述第三电容的第一端与所述噪声整形输入级电路的第一输出端耦接，所述第三电容的第二端与所述锁存级电路的第一输入端耦接；
    所述第四电容的第一端与所述噪声整形输入级电路的第二输出端耦接，所述第四电容的第二端与所述锁存级电路的第二输入端耦接。
  19. 根据权利要求18所述的比较器，其特征在于，所述锁存级电路包括开关单元、第一锁存放大单元、第二锁存放大单元和第三锁存单元；
    开关单元，适于在所述比较相时导通；
    第一锁存放大单元，适于当所述开关单元导通时，对所述第一输出信号和第三输出信号的第一叠加电平信号进行放大；
    第二锁存放大单元，适于当所述开关单元导通时，对所接收的第二输出信号和第四输出信号的第二叠加电平信号进行放大；
    第三锁存单元，适于对所述放大后的第一叠加电平信号和放大后的第二叠加电平信号进行锁存并比较，输出对应的比较结果。
  20. 根据权利要求19所述的比较器，其特征在于，所述开关单元包括第九NMOS管；
    所述第九NMOS管的栅端用于接收第一时钟控制信号，所述第九NMOS管的源端与地电压耦接，所述第九NMOS管的漏端分别与所述第一锁存放大单元和第二锁存放大单元耦接。
  21. 根据权利要求19所述的比较器，其特征在于，所述第一锁存放大单元包括第十NMOS管；
    所述第十NMOS管的栅端作为所述锁存级电路的第一输入端或与所述锁存级电路的第一输入端耦接，所述十NMOS管的源端与所述开关单元耦接，所述十NMOS管的漏端与所述第三锁存单元耦接。
  22. 根据权利要求19所述的比较器，其特征在于，所述第二锁存放大单元包括第十一NMOS管；
    所述第十一NMOS管的栅端作为所述锁存级电路的第二输入端或与所述锁存级电路的第二输入端耦接，所述十一NMOS管的源端与所述开关单元耦接，所述十一NMOS管的漏端与所述第三锁存单元耦接。
  23. 根据权利要求19所述的比较器，其特征在于，所述第三锁存单元包括第五PMOS管、第十二NMOS管、第六PMOS管和第十三NMOS管；
    所述第五PMOS管的栅端与所述第十二NMOS管的栅端耦接并与第六PMOS管的漏端和所述第十三NMOS管的漏端耦接，且作为所述比较器的反相输出端或与所述比较器的反相输出端耦接，所述第五PMOS管的漏端与所述第十二NMOS管的漏端耦接并与第六PMOS管的栅端和所述第十三NMOS管的栅端耦接，且作为所述比较器的正相输出端或与所述比较器的正相输出端耦接，所述第五PMOS管的源端和所述第六PMOS管的源端与电源电压耦接，所述第十二NMOS管的源端与所述第一锁存放大单元耦接，所述第十三NMOS管的源端与所述第二锁存放大单元耦接。
  24. 根据权利要求1所述的比较器，其特征在于，还包括以下至少一项：
    第一偏置电路，适于为所述输入级电路提供偏置电流；
    第二偏置电路，适于为所述噪声整形输入级电路提供偏置电流。
  25. 根据权利要求24所述的比较器，其特征在于，所述第一偏置电路包括第七PMOS管；
    所述第七PMOS管的栅端与偏置电压耦接，所述第七PMOS管的源端与电源电压耦接，所述第七PMOS管的漏端与所述输入级电路耦接。
  26. 根据权利要求24所述的比较器，其特征在于，所述第二偏置电路包括第八PMOS管；
    所述第八PMOS管的栅端与偏置电压耦接，所述第八PMOS管的源端与电源电压耦接，所述第八PMOS管的漏端与所述噪声整形输入级电路耦接。
  27. 根据权利要求1所述的比较器，其特征在于，还包括以下至少一项：
    第一输出复位电路，适于在所述采样相时，将所述比较器的正相输出端复位至电源电压；
    第一输出复位电路，适于在所述采样相时，将所述比较器的反相输出端复位至电源电压。
  28. 根据权利要求27所述的比较器，其特征在于，所述第一输出复位电路包括第九PMOS管；
    所述第九PMOS管的栅端用于接收第一时钟控制信号，所述第九PMOS管的源端与电源电压耦接，所述第九PMOS管的漏端与所述比较器的正相输出端耦接。
  29. 根据权利要求27所述的比较器，其特征在于，所述第二输出复位电路包括第十PMOS管；
    所述第十PMOS管的栅端用于接收第一时钟控制信号，所述第十PMOS管的源端与电源电压耦接，所述第十PMOS管的漏端与所述比较器的反相输出端耦接。
  30. 根据权利要求1所述的比较器，其特征在于，还包括以下至少一种：
    第一输入复位电路，适于在所述采样相时，将所述输入级电路的第一输入端复位至预设的共模电压；
    第二输入复位电路，适于在所述采样相时，将所述输入级电路的第二输入端复位至所述共模电压；
    第三输入复位电路，适于在所述采样相时，将所述噪声整形输入级电路的第一输入端复位至所述共模电压；
    第四输入复位电路，适于在所述采样相时，将所述噪声整形输入级电路的第二输入端复位至所述共模电压；
    第五输入复位电路，适于在所述采样相时，将所述锁存级电路的第一输入端复位至所述共模电压；
    第六输入复位电路，适于在所述采样相时，将所述锁存级电路的第二输入端复位至所述共模电压。
  31. 根据权利要求30所述的比较器，其特征在于，所述第一输入复位电路包括第一开关；
    所述第一开关的控制端用于接收第二时钟控制信号，所述第一开关的第一导通端用于接收所述共模电压，所述第一开关的第二导通端与所述输入级电路的第一输入端耦接。
  32. 根据权利要求30所述的比较器，其特征在于，所述第二输入复位电路包括第二开关；
    所述第二开关的控制端用于接收第二时钟控制信号，所述第二开关的第一导通端用于接收所述共模电压，所述第二开关的第二导通端与所述输入级电路的第二输入端耦接。
  33. 根据权利要求30所述的比较器，其特征在于，所述第三输入复位电路包括第三开关；
    所述第三开关的控制端用于接收第二时钟控制信号，所述第三开关的第一导通端用于接收所述共模电压，所述第三开关的第二导通端与所述噪声整形输入级电路的第一输入端耦接。
  34. 根据权利要求30所述的比较器，其特征在于，所述第四输入复位电路包括第四开关；
    所述第四开关的控制端用于接收第二时钟控制信号，所述第四开关的第一导通端用于接收所述共模电压，所述第四开关的第二导通端与所述噪声整形输入级电路的第二输入端耦接。
  35. 根据权利要求30所述的比较器，其特征在于，所述第五输入复位电路包括第五开关；
    所述第五开关的控制端用于接收第二时钟控制信号，所述第五开关的第一导通端用于接收所述共模电压，所述第五开关的第二导通端与所述锁存级电路的第一输入端耦接。
  36. 根据权利要求30所述的比较器，其特征在于，所述第六输入复位电路包括第六开关；
    所述第六开关的控制端用于接收第二时钟控制信号，所述第六开关的第一导通端用于接收所述共模电压，所述第六开关的第二导通端与所述锁存级电路的第二输入端耦接。
  37. 一种逐次逼近模数转换器，其特征在于，包括权利要求1-36任一项所述比较器。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116865729A (zh) * 2023-09-04 2023-10-10 成都市九天睿芯科技有限公司 比较器、模数转换器及电子设备

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102571093A (zh) * 2010-12-23 2012-07-11 无锡华润上华半导体有限公司 比较器及a/d转换器
US8692582B1 (en) * 2012-01-06 2014-04-08 Altera Corporation Latched comparator circuitry
CN111628776A (zh) * 2020-06-22 2020-09-04 湖南国科微电子股份有限公司 一种高速sar adc电路及集成芯片
CN111682878A (zh) * 2020-06-11 2020-09-18 西安电子科技大学 一种零极点优化的无源噪声整形逐次逼近模数转换器

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102571093A (zh) * 2010-12-23 2012-07-11 无锡华润上华半导体有限公司 比较器及a/d转换器
US8692582B1 (en) * 2012-01-06 2014-04-08 Altera Corporation Latched comparator circuitry
CN111682878A (zh) * 2020-06-11 2020-09-18 西安电子科技大学 一种零极点优化的无源噪声整形逐次逼近模数转换器
CN111628776A (zh) * 2020-06-22 2020-09-04 湖南国科微电子股份有限公司 一种高速sar adc电路及集成芯片

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116865729A (zh) * 2023-09-04 2023-10-10 成都市九天睿芯科技有限公司 比较器、模数转换器及电子设备
CN116865729B (zh) * 2023-09-04 2023-11-24 成都市九天睿芯科技有限公司 比较器、模数转换器及电子设备

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