WO2022082656A1 - 低压差线性稳压器和供电电路 - Google Patents

低压差线性稳压器和供电电路 Download PDF

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Publication number
WO2022082656A1
WO2022082656A1 PCT/CN2020/122980 CN2020122980W WO2022082656A1 WO 2022082656 A1 WO2022082656 A1 WO 2022082656A1 CN 2020122980 W CN2020122980 W CN 2020122980W WO 2022082656 A1 WO2022082656 A1 WO 2022082656A1
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Prior art keywords
output
node
stage circuit
field effect
effect transistor
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PCT/CN2020/122980
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English (en)
French (fr)
Inventor
薛建锋
吴与伦
杨江
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深圳市汇顶科技股份有限公司
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Priority to PCT/CN2020/122980 priority Critical patent/WO2022082656A1/zh
Publication of WO2022082656A1 publication Critical patent/WO2022082656A1/zh

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices

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  • the embodiments of the present application relate to the field of electronic technologies, and in particular, to a low-dropout linear voltage regulator and a power supply circuit.
  • the preferred way of power management is to use multiple local voltage regulators to supply power to the sub-modules of the system.
  • the use of independent power supply voltages for different modules can reduce the problem of power supply crosstalk.
  • Low-dropout linear regulator Low-drop regulator, LDO
  • LDOs with external off-chip capacitors require additional chip pins and capacitors to provide better transient response.
  • one of the technical problems solved by the embodiments of the present invention is to provide a low-dropout linear voltage regulator and a power supply circuit, which improves the voltage regulation performance.
  • a low dropout linear regulator comprising: an output stage circuit including an output node, a feedback node and a sampling node corresponding to the output node, wherein the output node is used to provide the low dropout The output voltage of a linear regulator; an error amplifier including a first-stage circuit and a second-stage circuit connected to each other.
  • the first-stage circuit is connected to the sampling node, and is used for receiving the sampling signal of the sampling node, and feeding back and amplifying the sampling signal of the sampling node, and inputting the sampling signal to the second-stage circuit to form the The first negative feedback of the output voltage.
  • the second stage circuit is connected to the feedback node for outputting the first negative feedback of the output voltage to the feedback node.
  • the second stage circuit is also connected to the output node for receiving a signal of the output voltage to form a second negative feedback of the output voltage, and through the connection to the feedback node, converts the output voltage to a second negative feedback.
  • a second negative feedback is output to the feedback node.
  • the output stage circuit includes an output power transistor, wherein a drain and a gate of the output power transistor are connected to the output node and the feedback node, respectively, and the second The stage circuit and the output power tube form a push-pull fast response path to form the second negative feedback.
  • the push-pull fast response path includes forming a first path and a second path
  • the second stage circuit includes a first field effect transistor
  • the first field effect transistor has a The source is connected to the drain of the output power transistor
  • the drain of the first field effect transistor is connected to the gate of the output power transistor.
  • a positive correlation variation of the input voltage of the gate of the output power transistor with respect to the output voltage is formed by the first field effect transistor
  • the output voltage is formed by the output power transistor Negatively correlated variation on the input voltage.
  • the positive correlation variation of the input voltage to the output voltage is formed through the connection node between the first-stage circuit and the second-stage circuit, and is formed through the output power tube A negatively correlated variation of the output voltage with respect to the input voltage.
  • the drain of the output power transistor is connected to the source of the first field effect transistor through a first capacitor, and the drain of the output power transistor is connected through a second capacitor to the connection node.
  • the second-stage circuit further includes a second field effect transistor and a first current mirror, which are connected to the gate of the second field effect transistor through the connection node, wherein the The drain of the second field effect transistor generates the input current of the first current mirror, and the output current of the first current mirror flows into the gate of the output power transistor and the drain of the first field effect transistor respectively .
  • the first stage circuit outputs the first negative feedback to the feedback node via the connection node.
  • the second-stage circuit further includes a third field effect transistor, and the drain electrode of the third field effect transistor is connected to the source electrode of the first field effect transistor, wherein the The first stage circuit further includes a fourth field effect transistor, the first stage circuit is connected to the sampling node through the gate of the fourth field effect transistor, and the drain of the fourth field effect transistor is connected to the The gate of the third FET is connected.
  • the first-stage circuit further includes a fifth field effect transistor that forms a common-source differential pair with the fourth field effect transistor, and the connection node is connected to the fifth field effect transistor. Drain connection of the tube.
  • the first stage circuit further includes a second current mirror, the drain of the fourth field effect transistor generates an input current of the second current mirror, and the second current mirror The output current passes through the drain of the fifth field effect transistor, wherein the fourth field effect transistor is connected to the third field effect transistor via the common gate of the second current mirror.
  • a power supply circuit comprising: the low dropout linear regulator according to the first aspect and a DC power supply, where the DC power supply supplies power to an input node of the output stage circuit.
  • the first-stage circuit feeds back and amplifies the sampling signal of the sampling node corresponding to the output node, and inputs it to the second-stage circuit, and the second-stage circuit outputs the first negative feedback of the output voltage to all the
  • the feedback node effectively realizes the low dropout voltage regulation of the output voltage through the first negative feedback formed by feedback amplification.
  • the second stage circuit in the error amplifier receives the signal of the output node to form a second negative feedback, and outputs the second negative feedback to the feedback node, and further realizes the regulation of the output voltage through the second negative feedback.
  • FIG. 1 is a schematic diagram of a low dropout linear voltage regulator of the related art
  • FIG. 2 is a schematic diagram of a low dropout linear voltage regulator according to a first embodiment of the present application
  • FIG. 3 is a schematic diagram of a low dropout linear voltage regulator according to a second embodiment of the present application.
  • FIG. 4 is a schematic illustration diagram of the feedback principle of the second negative feedback in the low dropout linear regulator according to the second embodiment of the present application;
  • FIG. 5 is a schematic diagram of the working principle of the low dropout linear regulator according to the second embodiment of the application when the output voltage drops instantaneously;
  • FIG. 6 is a schematic diagram of the working principle of the low-dropout linear regulator of the second embodiment of the application when the output voltage rises instantaneously;
  • FIG. 7 is a schematic diagram of a power supply circuit according to a third embodiment of the present application.
  • FIG. 1 is a schematic diagram of a low dropout linear regulator of the related art.
  • the LDO of Figure 1 includes an error amplifier and an output stage circuit.
  • the output stage circuit is composed of power tube, feedback network and load (CL and RL).
  • the feedback network includes a resistor Rf1 and a resistor Rf2 in series. Among them, one end of the feedback network is grounded, and the other end is connected to the output end (also called an output node) of the power tube of the output stage circuit, and the output end of the power tube also serves as the output end of the output stage circuit.
  • the feedback terminal of the error amplifier is connected between the resistor Rf1 and the resistor Rf2.
  • the output of the error amplifier is connected to the input (gate) of the power transistor.
  • FIG. 2 is a schematic diagram of a low dropout linear regulator according to a first embodiment of the present application.
  • the low dropout linear regulator of FIG. 2 includes an output stage circuit 210 and an error amplifier 220 .
  • the output stage circuit 210 includes an output node 211 and a feedback node 212 and a sampling node 213 corresponding to the output node 211 .
  • the output node 211 is used to provide the output voltage of the low dropout linear regulator.
  • the error amplifier 220 includes a first-stage circuit 221 and a second-stage circuit 222 connected to each other.
  • the first stage circuit 221 is connected to the sampling node 213 for receiving the sampling signal of the sampling node 213, and feedback and amplify the sampling signal of the sampling node 213, and input it to the second stage circuit 222 to form the first negative feedback of the output voltage .
  • the second stage circuit 222 is connected to the feedback node for outputting the first negative feedback of the output voltage to the feedback node.
  • the second stage circuit 222 is also connected to the output node 211 for receiving a signal of the output voltage to form a second negative feedback of the output voltage, and through the connection to the feedback node 212, outputs the second negative feedback of the output voltage to the feedback node 212.
  • the first-stage circuit feeds back and amplifies the sampling signal of the sampling node corresponding to the output node, and inputs it to the second-stage circuit, and the second-stage circuit outputs the output
  • the first negative feedback of the voltage is output to the feedback node, and the first negative feedback formed by feedback amplification effectively realizes the low-dropout voltage regulation of the output voltage.
  • the second stage circuit in the error amplifier receives the signal of the output node to form a second negative feedback, and outputs the second negative feedback to the feedback node, and further realizes the regulation of the output voltage through the second negative feedback.
  • the negative feedback in the embodiment of the present invention means that the signal is processed, and the negative feedback is performed by outputting to the negative feedback node.
  • the first negative feedback and the second negative feedback are used to realize the negative feedback, which can be realized as a positive correlation change of the voltage signal in the negative feedback path, and can also be realized as a positive correlation change of the voltage signal.
  • the above-mentioned negative feedback appears as a negative correlation variation, thereby forming a negative feedback path.
  • the path from the feedback node to the output node forms a negative correlation variation of the voltage signal
  • the above-mentioned negative feedback appears as a positive correlation variation, thereby forming a negative feedback path.
  • the output node can effectively indicate the output voltage change of the output stage load
  • the negative feedback to the output stage circuit formed by the error amplifier and the output node improves the speed of transient response, thus realizing regulation without off-chip capacitors. Effect.
  • the first-stage circuit of the error amplifier is connected with the second-stage circuit, and the second-stage circuit is connected with the third-stage circuit (output stage circuit), so a large static gain and loop gain are realized, thereby improving the DC accuracy .
  • “connected” described herein may be “coupled” under certain possible circumstances.
  • the error amplifier in the LDO circuit of FIG. 3 includes a first-stage circuit and a second-stage circuit connected to each other, and is connected to the third stage for output, that is, the third stage
  • the stage circuit acts as the output stage circuit of the LDO circuit.
  • the output end of the first-stage circuit is connected to the input end of the second-stage circuit, the input end of the first-stage circuit is connected to the sampling node, and the output end of the second-stage circuit is connected to the feedback node.
  • the output stage circuit also includes an input node for obtaining the input voltage of the low dropout linear regulator.
  • the third-stage circuit may include an output power transistor M3, equivalent loads CL, RL, and a feedback network composed of Rf1 and Rf2.
  • the sampling node of the feedback network is located at the junction of the two series resistors Rf1 and Rf2.
  • the source of the output power transistor M3 can be used for the input voltage of the DC power supply.
  • the drain of the output power transistor M3 can be used as an output node.
  • the gate of the output power tube M3 can be used as the input of the third-stage circuit to be connected to the output of the second-stage circuit.
  • the output voltage Vout of the output node of the third-stage circuit can be used as the output of the LDO to provide a stable local power supply voltage to, for example, an SoC module.
  • the SOC module may be powered via the LDO, such as from a battery or via a transformed DC power source.
  • the input voltage of the source of the output power transistor M3, which is an input node can provide a bias voltage for the first-stage circuit and the second-stage circuit.
  • the first stage circuit can be implemented as a differential amplifier circuit, and receives the reference voltage VREF and the first sampling node voltage VFB from the sampling node of the output stage circuit as two input signals of the first stage, according to the reference voltage VREF and the first sampling node
  • the voltage VFB outputs the differentially amplified signal to the second stage circuit.
  • the first stage circuit receives the first sampling node voltage VFB at the input end, and outputs the differentially amplified signal at the output end, so as to form a positive correlation change to the first sampling node voltage VFB.
  • the first-stage circuit outputs a differential amplified signal at point N1, and N1 can be used as a connection node between the output end of the first-stage circuit and the input end of the second-stage circuit.
  • the output of the second stage circuit is connected to the feedback node of the output stage circuit, eg by connecting via point N2. It should be understood that the output signal at the output terminal of the second stage circuit exhibits a positive correlation change with the differentially amplified signal received by the second stage circuit at the input terminal. There is a negative correlation between the input signal of the feedback node of the output stage circuit and the output signal of the output node.
  • the differential amplification signal of the positive correlation fluctuation of the first sampling node voltage VFB is formed through the first stage circuit as the differential amplifying circuit, and then the differential amplification signal is formed through the second sampling node voltage VFB.
  • the first negative feedback from the sampling node to the output node is formed.
  • the output stage circuit includes an output power tube.
  • the drain and gate of the output power tube are respectively connected to the output node and the feedback node, and the second-stage circuit and the output power tube form a push-pull fast response path to form a second negative feedback.
  • the circuit transient response is enhanced due to the push-pull fast response path.
  • the push-pull fast response path in this example can be used as an embedded path to enhance the performance of the fast response.
  • the push-pull fast response path can be implemented by sampling one path, or more than two paths can be used. to fulfill.
  • the circuit of the fast response path is also a part of the error amplifier (main circuit).
  • this example can simplify the circuit structure.
  • this example maintains the stability of circuit performance due to the simple and unique structure and avoids the deterioration of circuit performance.
  • the push-pull fast response path may include forming a first path and a second path, the second stage circuit includes a first field effect transistor, the source of the first field effect transistor is connected to the drain of the output power transistor, The drain of the first field effect transistor is connected to the gate of the output power transistor.
  • the first path the positive correlation variation of the input voltage of the gate of the output power tube with respect to the output voltage is formed by the first field effect transistor, and the negative correlation variation of the output voltage against the input voltage is formed by the output power tube.
  • the positive correlation variation of the input voltage to the output voltage is formed through the connection node between the first stage circuit and the second stage circuit, and the negative correlation variation of the output voltage to the input voltage is formed by the output power tube.
  • the first stage circuit may output the first negative feedback to the feedback node via the connection node.
  • This example uses the first path and the second path of the above simple circuit to achieve the push-pull effect.
  • both the first channel and the second channel are fed back through the output end of the second-stage circuit, which facilitates functional coupling and separation of the circuits.
  • any coupling manner such as direct coupling, capacitive coupling, etc. can be adopted.
  • the second-stage circuit may further include a first capacitor Cc and a second capacitor Cm, which may also be referred to herein as feedback capacitor Cm and feedback capacitor Cc, or compensation capacitor Cm and compensation capacitor Cc.
  • Two ends of the second capacitor Cm are respectively connected to the first stage output and the third stage output (output node).
  • Two ends of the first capacitor Cc are respectively connected to the source of the first field effect transistor Mt and the output of the third stage. Since the second capacitor and the first capacitor are beneficial to ensure the static operating point of the circuits at all levels, they are beneficial to ensure the stability of the LDO. In other words, the compensation capacitors Cm and Cc on the fast response path can optimize the stability of the loop.
  • the second-stage circuit may further include a second field effect transistor and a first current mirror, which are connected to the gate of the second field effect transistor through a connection node.
  • the drain of the second field effect transistor generates the input current of the first current mirror, and the output current of the first current mirror flows into the gate of the output power transistor and the drain of the first field effect transistor respectively.
  • the first path may be composed of a first capacitor Cc, a first field effect transistor Mt and an output power transistor M3.
  • the second path may be composed of a second capacitor Cm, a second field effect transistor M2, field effect transistors M8 and M9 serving as a first current mirror, and an output power transistor M3.
  • the drain of the output power transistor M3 is connected to the source of the first field effect transistor Mt through the first capacitor Cc, and the drain of the output power transistor M3 is connected to the connection node (point N1) through the second capacitor Cm.
  • the gate of the second field effect transistor M2 can be used as an input end of the second stage circuit to be connected to the output end (N1 point) of the first stage circuit.
  • a positive correlation variation of the voltage of the input end of the second-stage circuit is formed, and the field effect transistors M8 and M9 as the first current mirror and the The structure formed by the second field effect transistor M2.
  • the increase in the gate voltage of the second field effect transistor M2 will cause the voltage of the common gate of the field effect transistors M8 and M9 as the first current mirror to become smaller, thereby causing the field effect transistors M8 and M9 as the first current mirror.
  • the voltage on the controlled output current side of M9 becomes larger, thereby achieving a positively correlated change, and vice versa.
  • the first field effect transistor Mt may be an N-type MOS transistor.
  • the second field effect transistor M2 may be an N-type MOS transistor. Any one of the field effect transistors M8 and M9 serving as the first current mirror may be a P-type MOS transistor.
  • the field effect transistors M5 and M6 may both be N-type MOS transistors.
  • the field effect transistor in the text can be a junction field effect transistor, a depletion type field effect transistor, an enhancement type field effect transistor, or other field effect transistors.
  • the field effect transistor in the text can be either an N-type field effect transistor or a P-type field effect transistor.
  • MOS transistors metal oxide semiconductor field effect transistors
  • N-type MOS transistors or P-type MOS transistors The structure and function of the circuit are described; however, other field effect transistors or other elements may also be used in the embodiments of the present invention to implement the functions of various circuits.
  • FIG. 4 is a schematic illustration diagram of the feedback principle of the second negative feedback in the low dropout linear regulator according to the second embodiment of the present application.
  • Vout to the source of the first field effect transistor Mt there is a positive correlation to the change of the output voltage.
  • the voltage of the source of the first field effect transistor Mt increases.
  • the voltage of the output terminal of the second stage circuit (for example, the voltage of the N2 point) becomes larger, and vice versa.
  • a positive correlation to the output voltage change is formed, and from the input of the second-stage circuit to the output of the second-stage circuit, the input to the second-stage circuit is formed.
  • the positive correlation change of the voltage at the terminal As the output voltage increases, the gate of the second FET M2 (eg, the voltage of N1 ) becomes greater, and the voltage of the output terminal of the second-stage circuit (eg, the voltage of the point N2 ) becomes greater, and vice versa.
  • the gate of the second FET M2 eg, the voltage of N1
  • the voltage of the output terminal of the second-stage circuit eg, the voltage of the point N2
  • any element and circuit configuration can be used. In one example, this can be achieved via one or more positive correlation changes, e.g., with two positive correlation changes. In another example, an even number of negative correlation changes or any number of positive correlation changes can also be used to achieve, for example, it can be achieved through two negative correlation changes in succession.
  • the second stage circuit may further include a third field effect transistor, and the drain electrode of the third field effect transistor is connected to the source electrode of the first field effect transistor, wherein the first stage circuit further includes a fourth field effect transistor, The first stage circuit is connected to the sampling node through the gate of the fourth field effect transistor, and the drain of the fourth field effect transistor is connected to the gate of the third field effect transistor.
  • the first-stage circuit may further include a fifth field effect transistor that forms a common source differential pair with the fourth field effect transistor, and the connection node is connected to the drain of the fifth field effect transistor. Specifically, as shown in FIG.
  • the first-stage circuit may include a fourth field effect transistor M1A, a fifth field effect transistor M1B, and field effect transistors M5 and M6 as second current mirrors.
  • the fourth field effect transistor M1A and the fifth field effect transistor M1B constitute a differential pair of the differential amplifier circuit
  • VREF may be a reference voltage of the input LDO
  • VB1 may be a bias voltage of the input LDO.
  • the output points of the first stage can be N1 and N1A.
  • the first stage circuit may further include a sixth field effect transistor M4, the drain electrode of the sixth field effect transistor M4 may be connected with the respective source electrodes of the differential pair, and the source electrode of the sixth field effect transistor M4 may be connected with the bias voltage source .
  • the first sampling node voltage VFB may be connected to the gate of the fourth field effect transistor M1A as the input of the first stage circuit.
  • the gate of the third field effect transistor M7 can be used as another input terminal of the second-stage circuit to be connected to the output terminal (point N1A) of the first-stage circuit.
  • VB2 is another bias voltage input to the LDO, and is connected to the gate terminal of the first field effect transistor Mt.
  • the second stage output node is N2. It should be understood that the elements and their connection relationships in the above examples are only exemplary, and in other examples, the second-stage circuit may have other structures and connection relationships.
  • the first stage circuit may further include a second current mirror, the drain of the fourth field effect transistor generates an input current of the second current mirror, and the output current of the second current mirror passes through the drain of the fifth field effect transistor.
  • the fourth field effect transistor is connected to the third field effect transistor via the common gate of the second current mirror.
  • the FETs M5 and M6 as the second current mirror and the third FET M7 can generate a feedforward path, and the feedforward path introduces the zero point of the left half-plane, thereby optimizing the phase margin for improved stability.
  • the feedforward path can realize the rapid response of the second-level circuit to the first-level circuit, and improve the start-up of the LDO speed.
  • the gate voltage of the third field effect transistor M7 will be quickly established, the third field effect transistor M7 will generate current, and the voltage at the point N2 will be pulled down, thereby causing the output power transistor M3 to generate current to establish the output voltage Vout.
  • FIG. 5 is a schematic diagram of the working principle of the low dropout linear regulator according to the second embodiment of the application when the output voltage drops instantaneously.
  • the output node forms a positive correlation change to the input voltage of the feedback node through the source stage of the first FET, and then completes the negative change to the output voltage of the output node through the output power transistor. related changes.
  • the output node forms a positive correlation change to the source voltage of the first field effect transistor through the first capacitor.
  • the source of the first field effect transistor Mt drops instantaneously due to the coupling effect of the feedback capacitor Cc.
  • the source voltage has a positive correlation with the drain voltage, which increases the current drawn from the N2 point and causes the N2 point voltage to drop.
  • the output node forms a positive correlation change to the input voltage of the feedback node through the input terminal of the second stage circuit, and then completes the negative correlation change to the output voltage of the output node through the output power tube.
  • the output node forms a positive correlation change to the input terminal voltage of the second stage circuit through the second capacitor.
  • the gate voltage of the second field effect transistor M2 drops instantaneously due to the coupling effect of the feedback capacitor Cm, which increases the field of the first current mirror.
  • the gate voltage and the drain voltage have a negatively correlated variation relationship, thereby reducing the current input to the N2 point, so that the N2 point voltage drops.
  • the voltage input from M9 decreases, and the current drawn by the first field effect transistor Mt increases, showing the push-pull effect described in the text.
  • the voltage of the N2 point drops, and the voltage of the N2 point drops accordingly, which increases the current of the output power tube M3, thereby slowing the undershoot of Vout. Therefore, the push-pull fast response path of the LDO can reduce the undershoot caused by the change of the LDO output load.
  • FIG. 6 is a schematic diagram of the working principle of the low dropout linear regulator according to the second embodiment of the application when the output voltage rises instantaneously.
  • the push-pull action of the two fast response paths can reduce the overshoot caused by the LDO output load change.
  • FIG. 7 is a schematic diagram of a power supply circuit according to a third embodiment of the present application.
  • the power supply circuit of FIG. 7 includes: a low dropout linear regulator 710 and a DC power supply 720 , and the DC power supply 720 supplies power to the input end of the output stage circuit 712 .
  • the output stage circuit 712 may be connected or coupled to the error amplifier 711 .
  • Low dropout linear regulator 710 includes an output stage circuit 712 and an error amplifier.
  • the output stage circuit 712 includes an output node and a feedback node and a sampling node corresponding to the output node.
  • the error amplifier includes a first-stage circuit and a second-stage circuit connected to each other. The error amplifier amplifies the first negative feedback of the output voltage of the output node.
  • the first stage circuit is connected to the sampling node and receives the input of the first negative feedback from the sampling node.
  • the second stage circuit is connected to the feedback node and outputs the first negative feedback to the feedback node.
  • the second stage circuit is connected to the output node and receives an input of a second negative feedback of the output voltage of the output node.
  • the second stage circuit also outputs the second negative feedback to the feedback node through the connection with the feedback node.
  • the output stage circuit may include an output power tube, wherein the output node and the feedback node are configured in the output power tube, and the input end of the output stage circuit may be configured with the output power tube.
  • the output node may be the drain of the output power tube
  • the input terminal of the output stage circuit may be the source of the output power tube
  • the feedback node may be the gate of the output power tube.
  • the bias voltage of the error amplifier is sourced to the input voltage including the input of the output stage circuit.
  • the second-stage circuit and the output power tube can form a push-pull fast response path, and the push-pull fast response path forms a second negative feedback.
  • the input voltage of the source of the output power tube as the input node can provide the bias voltage for the first-stage circuit and the second-stage circuit.
  • the first-stage circuit feeds back and amplifies the sampling signal of the sampling node corresponding to the output node, and inputs it to the second-stage circuit, and the second-stage circuit outputs the output
  • the first negative feedback of the voltage is output to the feedback node, and the first negative feedback formed by feedback amplification effectively realizes the low-dropout voltage regulation of the output voltage.
  • the second stage circuit in the error amplifier receives the signal of the output node to form a second negative feedback, and outputs the second negative feedback to the feedback node, and further realizes the voltage regulation of the output voltage through the second negative feedback, thereby realizing the power supply. Current regulated voltage output.
  • the low dropout linear regulator and the power supply circuit of the embodiments of the present application can be applied to various devices, including but not limited to:
  • Mobile communication equipment This type of equipment is characterized by having mobile communication functions, and its main goal is to provide voice and data communication.
  • Such terminals include: smart phones (eg iPhone), multimedia phones, functional phones, and low-end phones.
  • Ultra-mobile personal computer equipment This type of equipment belongs to the category of personal computers, has computing and processing functions, and generally has the characteristics of mobile Internet access.
  • Such terminals include: PDAs, MIDs, and UMPC devices, such as iPads.
  • Portable entertainment equipment This type of equipment can display and play multimedia content.
  • Such devices include: audio and video players (eg iPod), handheld game consoles, e-books, as well as smart toys and portable car navigation devices.
  • a Programmable Logic Device (such as a Field Programmable Gate Array (FPGA)) is an integrated circuit whose logic function is determined by user programming of the device.
  • HDL Hardware Description Language
  • ABEL Advanced Boolean Expression Language
  • AHDL Altera Hardware Description Language
  • HDCal JHDL
  • Lava Lava
  • Lola MyHDL
  • PALASM RHDL
  • VHDL Very-High-Speed Integrated Circuit Hardware Description Language
  • Verilog Verilog
  • the controller may be implemented in any suitable manner, for example, the controller may take the form of eg a microprocessor or processor and a computer readable medium storing computer readable program code (eg software or firmware) executable by the (micro)processor , logic gates, switches, application specific integrated circuits (ASICs), programmable logic controllers and embedded microcontrollers, examples of controllers include but are not limited to the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20 and Silicon Labs C8051F320, the memory controller can also be implemented as part of the control logic of the memory.
  • the controller may take the form of eg a microprocessor or processor and a computer readable medium storing computer readable program code (eg software or firmware) executable by the (micro)processor , logic gates, switches, application specific integrated circuits (ASICs), programmable logic controllers and embedded microcontrollers
  • ASICs application specific integrated circuits
  • controllers include but are not limited to
  • the controller in addition to implementing the controller in the form of pure computer-readable program code, the controller can be implemented as logic gates, switches, application-specific integrated circuits, programmable logic controllers and embedded devices by logically programming the method steps.
  • the same function can be realized in the form of a microcontroller, etc. Therefore, such a controller can be regarded as a hardware component, and the devices included therein for realizing various functions can also be regarded as a structure within the hardware component. Or even, the means for implementing various functions can be regarded as both a software module implementing a method and a structure within a hardware component.
  • a typical implementation device is a computer.
  • the computer can be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or A combination of any of these devices.
  • the embodiments of the present application may be provided as a method, a system, or a computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
  • computer-usable storage media including, but not limited to, disk storage, CD-ROM, optical storage, etc.
  • These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory result in an article of manufacture comprising instruction means, the instructions
  • the apparatus implements the functions specified in the flow or flow of the flowcharts and/or the block or blocks of the block diagrams.
  • a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
  • processors CPUs
  • input/output interfaces network interfaces
  • memory volatile and non-volatile memory
  • Memory may include forms of non-persistent memory, random access memory (RAM) and/or non-volatile memory in computer readable media, such as read only memory (ROM) or flash memory (flash RAM). Memory is an example of a computer-readable medium.
  • RAM random access memory
  • ROM read only memory
  • flash RAM flash memory
  • Computer-readable media includes both persistent and non-permanent, removable and non-removable media, and storage of information may be implemented by any method or technology.
  • Information may be computer readable instructions, data structures, modules of programs, or other data.
  • Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read only memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), Flash Memory or other memory technology, Compact Disc Read Only Memory (CD-ROM), Digital Versatile Disc (DVD) or other optical storage, Magnetic tape cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission medium that can be used to store information that can be accessed by a computing device.
  • computer-readable media does not include transitory computer-readable media, such as modulated data signals and carrier waves.
  • the embodiments of the present application may be provided as a method, a system or a computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
  • computer-usable storage media including, but not limited to, disk storage, CD-ROM, optical storage, etc.
  • the application may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer.
  • program modules include routines, programs, objects, components, data structures, etc. that perform particular transactions or implement particular abstract data types.
  • the application may also be practiced in distributed computing environments where transactions are performed by remote processing devices that are linked through a communications network.
  • program modules may be located in both local and remote computer storage media including storage devices.

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Abstract

提供一种低压差线性稳压器和供电电路，低压差线性稳压器包括输出级电路（210）和误差放大器（220）；输出级电路（210）包括输出节点（211）以及与输出节点（211）对应的反馈节点（212）和采样节点（213），其中输出节点（211）用于提供低压差线性稳压器的输出电压；误差放大器（220）包括彼此连接的第一级电路（221）和第二级电路（222），其中第一级电路（221）与采样节点（213）连接，用于接收采样节点（213）的采样信号，并且对采样节点（213）的采样信号进行反馈放大，输入到第二级电路（222），以形成输出电压的第一负反馈，第二级电路（222）与反馈节点（212）连接，用于将输出电压的第一负反馈输出到反馈节点（212）；其中第二级电路（222）还与输出节点（211）连接，用于接收输出电压的信号，以形成输出电压的第二负反馈，并且通过与反馈节点（212）的连接，将输出电压的第二负反馈输出到反馈节点（212）。该低压差线性稳压器具有更高的稳压性能。

Description

低压差线性稳压器和供电电路 技术领域
本申请实施例涉及电子技术领域，尤其涉及一种低压差线性稳压器和供电电路。
背景技术
通常，在片上系统(System on Chip,SoC)中，电源管理的优选方式是利用多个本地的稳压器来为系统的子模块进行供电。不同模块使用独立的电源电压，可以减少电源串扰的问题。低压差线性稳压器(Low-drop regulator,LDO)具有噪声低、快速瞬态响应和高电源抑制比的优点，被认为是一种优选的SoC稳压器。外接片外电容的LDO需要额外的芯片引脚和电容器件，可以提供更好的瞬态响应。
但是，对于片上系统而言，需要的外接片外电容的电容值较大,使得相应的面积开销也比较大，因此，需要提供一种更高稳压性能的无外接片外电容的低压差线性稳压器。
发明内容
有鉴于此，本发明实施例所解决的技术问题之一在于提供一种低压差线性稳压器和供电电路，提高了稳压性能。
第一方面，提供了一种低压差线性稳压器，包括：输出级电路，包括输出节点以及与所述输出节点对应的反馈节点和采样节点，其中所述输出节点用于提供所述低压差线性稳压器的输出电压；误差放大器，包括彼此连接的第一级电路和第二级电路。所述第一级电路与所述采样节点连接，用于接收所述采样节点的采样信号，并且对所述采样节点的采样信号进行反馈放大，输入到所述第二级电路，以形成所述输出电压的第一负反馈。所述第二级电路与所述反馈节点连接，用于将所述输出电压的第一负反馈输出到所述反馈节点。所述第 二级电路还与所述输出节点连接，用于接收所述输出电压的信号，以形成输出电压的第二负反馈，并且通过与所述反馈节点的连接，将所述输出电压的第二负反馈输出到所述反馈节点。
在本发明的另一实现方式中，所述输出级电路包括输出功率管，其中，所述输出功率管的漏极和栅极分别连接到所述输出节点和所述反馈节点，所述第二级电路与所述输出功率管组成推挽式快速响应通路，形成所述第二负反馈。
在本发明的另一实现方式中，所述推挽式快速响应通路包括形成第一通路以及第二通路，所述第二级电路中包括第一场效应管，所述第一场效应管的源极与所述输出功率管的漏极连接，所述第一场效应管的漏极与所述输出功率管的栅极连接。在所述第一通路中，通过所述第一场效应管形成所述输出功率管的栅极的输入电压关于所述输出电压的正相关变动，并且通过所述输出功率管形成所述输出电压对所述输入电压的负相关变动。在所述第二通路中,通过所述第一级电路与所述第二级电路之间的连接节点形成所述输入电压对所述输出电压的正相关变动，并且通过所述输出功率管形成所述输出电压对所述输入电压的负相关变动。
在本发明的另一实现方式中，所述输出功率管的漏极通过第一电容连接到所述第一场效应管的源极，并且所述输出功率管的漏极通过第二电容形成连接到所述连接节点。
在本发明的另一实现方式中，所述第二级电路还包括第二场效应管和第一电流镜，通过所述连接节点连接到所述第二场效应管的栅极，其中，所述第二场效应管的漏极产生所述第一电流镜的输入电流，所述第一电流镜的输出电流分别流入所述输出功率管的栅极和所述第一场效应管的漏极。
在本发明的另一实现方式中，所述第一级电路经由所述连接节点将所述第一负反馈输出到所述反馈节点。
在本发明的另一实现方式中，所述第二级电路还包括第三场效应管，所述第三场效应管的漏极与所述第一场效应管的源极连接，其中，所述第一级电路还包括第四场效应管，所述第一级电路通过所述第四场效应管的栅极连接到所述采样节点，所述第四场效应管的漏极与所述第三场效应管的栅极连接。
在本发明的另一实现方式中，所述第一级电路还包括与所述第四场效应管形成共源极差分对的第五场效应管，所述连接节点与所述第五场效应管的漏极连接。
在本发明的另一实现方式中，所述第一级电路还包括第二电流镜，所述第四场效应管的漏极产生所述第二电流镜的输入电流，所述第二电流镜的输出电流经过所述第五场效应管的漏极，其中，所述第四场效应管经由所述第二电流镜的共用栅极与所述第三场效应管连接。
第二方面，提供了一种供电电路，包括：如第一方面所述的低压差线性稳压器以及直流电源，所述直流电源向所述输出级电路的输入节点供电。
在本发明实施例的方案中，第一级电路对输出节点对应的采样节点的采样信号进行反馈放大，输入到第二级电路，并且第二级电路将输出电压的第一负反馈输出到所述反馈节点，有效地通过反馈放大形成的第一负反馈实现了输出电压的低压差稳压。此外，误差放大器中的第二级电路接收输出节点的信号形成第二负反馈，并且将第二负反馈输出到反馈节点，进一步通过第二负反馈实现了输出电压的稳压。
附图说明
后文将参照附图以示例性而非限制性的方式详细描述本申请实施例的一些具体实施例。附图中相同的附图标记标示了相同或类似的部件或部分。本领域技术人员应该理解，这些附图未必是按比值绘制的。附图中：
图1为相关技术的低压差线性稳压器的示意图；
图2为本申请的第一实施例的低压差线性稳压器的示意图；
图3为本申请的第二实施例的低压差线性稳压器的示意图；
图4为本申请的第二实施例的低压差线性稳压器中第二负反馈的反馈原理的示意性说明图；
图5为本申请的第二实施例的低压差线性稳压器在输出电压的瞬间下降的情况下的工作原理的示意图；
图6为本申请的第二实施例的低压差线性稳压器在输出电压的瞬间上升 的情况下的工作原理的示意图；
图7为本申请的第三实施例的供电电路的示意图。
具体实施方式
下面结合本发明实施例附图进一步说明本发明实施例具体实现。图1为相关技术的低压差线性稳压器的示意图。图1的LDO包括误差放大器和输出级电路。输出级电路由功率管、反馈网络和负载(CL和RL)组成。反馈网络中包括串联的电阻Rf1和电阻Rf2。其中，反馈网络的一端接地，另一端与输出级电路的功率管的输出端(也可以称为输出节点)连接，功率管的输出端同时也作为输出级电路的输出端。误差放大器的反馈端连接在电阻Rf1和电阻Rf2之间。误差放大器的输出端连接到功率管的输入端(栅极)。当输出级负载变化令其产生的输出电压变化时，反馈端的电压相应地变化，从而经由误差放大器引起功率管的输出端的变化，即，当输出级负载变化会产生输出电压Vout的(瞬间上升)上冲与(瞬间下降)下冲时，通过基于误差放大器的反馈回路进行稳压，使得输出电压Vout稳定。
图2为本申请的第一实施例的低压差线性稳压器的示意图。图2的低压差线性稳压器包括输出级电路210和误差放大器220。
输出级电路210包括输出节点211以及与输出节点211对应的反馈节点212和采样节点213。输出节点211用于提供低压差线性稳压器的输出电压。误差放大器220包括彼此连接的第一级电路221和第二级电路222。
第一级电路221与采样节点213连接，用于接收采样节点213的采样信号，并且对采样节点213的采样信号进行反馈放大，输入到第二级电路222，以形成输出电压的第一负反馈。第二级电路222与反馈节点连接，用于将输出电压的第一负反馈输出到反馈节点。第二级电路222还与输出节点211连接，用于接收输出电压的信号，以形成输出电压的第二负反馈，并且通过与反馈节点212的连接，将输出电压的第二负反馈输出到反馈节点212。
在本发明实施例的方案中，在本发明实施例的方案中，第一级电路对输出节点对应的采样节点的采样信号进行反馈放大，输入到第二级电路，并且第 二级电路将输出电压的第一负反馈输出到所述反馈节点，有效地通过反馈放大形成的第一负反馈实现了输出电压的低压差稳压。此外，误差放大器中的第二级电路接收输出节点的信号形成第二负反馈，并且将第二负反馈输出到反馈节点，进一步通过第二负反馈实现了输出电压的稳压。
应理解，在本发明实施例中，一方面，对于输出电压的第一负反馈而言，间接地通过输出节点的采样节点的采样信号对输出节点的输出电压进行负反馈。对于输出电压的第二负反馈而言，直接地对输出节点的输出电压进行负反馈。换言之，本发明实施例的负反馈表示对信号进行处理过程，并且通过输出到负反馈节点进行负反馈。另一方面，第一负反馈和第二负反馈是指用于实现负反馈，其可以为实现负反馈通路中电压信号的正相关变动，也可以实现为电压信号的正相关变动。例如，如果从反馈节点到输出节点的通路形成电压信号的正相关变动时，则上述的负反馈表现为负相关变动，以此形成负反馈通路。又例如，如果从反馈节点到输出节点的通路形成电压信号的负相关变动时，则上述的负反馈表现为正相关变动，以此形成负反馈通路。
此外，由于输出节点能够有效地指示输出级负载的输出电压变化，因此误差放大器与输出节点形成的对输出级电路的负反馈提高了瞬态响应的速度，从而无需片外电容即实现了稳压效果。
此外，误差放大器的第一级电路与第二级电路连接，第二级电路与第三级电路(输出级电路)连接，因此实现了较大的静态增益以及环路增益，进而提高了直流精度。应理解，本文中所述的“连接”，在某些可能的情况下可以是“耦接”。
以下结合图3说明一下本发明的一个具体实施例，其中图3的LDO电路中误差放大器包括彼此连接的第一级电路和第二级电路，并连接到第三级进行输出，也就是第三级电路作为LDO电路的输出级电路。其中，第一级电路的输出端与第二级电路的输入端连接，第一级电路的输入端与采样节点连接，第二级电路的输出端与反馈节点连接。输出级电路的还包括输入节点，用于获取低压差线性稳压器的输入电压。
第三级电路可以包括输出功率管M3、等效负载CL、RL，以及Rf1与Rf2 组成的反馈网络。反馈网络的采样节点位于两个串联电阻Rf1与Rf2的连接点。输出功率管M3的源极可以用于直流电源的输入电压。输出功率管M3的漏极可以作为输出节点。输出功率管M3的栅极可以作为第三级电路的输入接第二级电路的输出。第三级电路的输出节点的输出电压Vout可以作为LDO的输出，用于向诸如SoC模块提供稳定的本地电源电压。换言之，诸如电池或经由变换后的直流电源可以经由LDO向SOC模块供电。
此外，作为输入节点的输出功率管M3的源极的输入电压可以为第一级电路和第二级电路提供偏置电压。
第一级电路可以实现为差分放大电路，并接收参考电压VREF和来自输出级电路的采样节点的第一采样节点电压VFB作为第一级的两个输入信号，根据参考电压VREF和第一采样节点电压VFB输出差分放大信号到第二级电路。第一级电路在输入端接收第一采样节点电压VFB，并且在输出端输出上述差分放大信号，形成对第一采样节点电压VFB的正相关变动。
如图3所示，第一级电路在N1点输出差分放大信号，N1可以作为第一级电路的输出端与第二级电路的输入端的连接节点。第二级电路的输出端与输出级电路的反馈节点连接，例如，通过经由N2点连接。应理解，第二级电路的输出端的输出信号与第二级电路在输入端接收的差分放大信号之间呈现正相关变动。输出级电路的反馈节点的输入信号与输出节点的输出信号之间呈现负相关变动。因此，在输出级电路的输出节点的输出电压瞬间下降或瞬间上升时，经由作为差分放大电路的第一级电路，形成第一采样节点电压VFB的正相关变动的差分放大信号，然后经由第二级电路的正相关变动的作用，输入到反馈节点，到达输出节点。从而形成了从采样节点到输出节点的第一负反馈。
作为一个示例，输出级电路包括输出功率管。输出功率管的漏极和栅极分别连接到输出节点和反馈节点，第二级电路与输出功率管组成推挽式快速响应通路，形成第二负反馈。由于采用了推挽式快速响应通路，因此能够增强电路瞬态响应。应理解，本示例中的推挽式快速响应通路可以作为一种内嵌的通路以增强快速响应的性能，另外，推挽式快速响应通路可以采样一个通路实现，也可以采用两个以上的通路来实现。在本示例中，作为快速响应通路的电路， 也是误差放大器(主体电路)的一部分，相比于在实现LDO功能的主体电路之外还包括其他快速响应通路的方案，本示例能够简化电路结构。此外，相比于诸如加入电路元件作为快速响应通路等其他增大快速响应的方案，本示例由于简单独特的结构，保持了电路性能的稳定，避免了电路性能的恶化。
作为一个示例，推挽式快速响应通路可以包括形成第一通路以及第二通路，第二级电路中包括第一场效应管，第一场效应管的源极与输出功率管的漏极连接，第一场效应管的漏极与输出功率管的栅极连接。在第一通路中，通过第一场效应管形成输出功率管的栅极的输入电压关于输出电压的正相关变动，并且通过输出功率管形成输出电压对输入电压的负相关变动。在第二通路中,通过第一级电路与第二级电路之间的连接节点形成输入电压对输出电压的正相关变动，并且通过输出功率管形成输出电压对输入电压的负相关变动。此外，第一级电路可以经由连接节点将第一负反馈输出到反馈节点。本示例采用了上述的简单电路的第一通路和第二通路，实现了推挽效果。此外，第一通路与第二通路都是经由第二级电路的输出端进行反馈，便于电路的功能耦合与分拆等。应连接，在上述的第一通路和/或第二通路中，可以采用诸如直接耦合、电容耦合等任意耦合方式。具体而言，如图3所示，第二级电路还可以包括第一电容Cc和第二电容Cm，本文中也可以被称为反馈电容Cm和反馈电容Cc，或者，补偿电容Cm和补偿电容Cc。第二电容Cm的两端分别接第一级输出与第三级输出(输出节点)。第一电容Cc的两端分别接第一场效应管Mt的源极和第三级输出。由于第二电容和第一电容有利于保证各级电路的静态工作点，因此有利于保证LDO的稳定性，换言之，快速响应通路上的补偿电容Cm和Cc能够优化环路的稳定性。
作为一个示例，第二级电路还可以包括第二场效应管和第一电流镜，通过连接节点连接到第二场效应管的栅极。第二场效应管的漏极产生第一电流镜的输入电流，第一电流镜的输出电流分别流入输出功率管的栅极和第一场效应管的漏极。具体而言，如图3所示，第一通路可以由第一电容Cc、第一场效应管Mt和输出功率管M3组成。第二通路可以由第二电容Cm、第二场效应管M2、作为第一电流镜的场效应管M8和M9、以及输出功率管M3组成。输出功 率管M3的漏极通过第一电容Cc连接到第一场效应管Mt的源极，并且输出功率管M3的漏极通过第二电容Cm形成连接到连接节点(N1点)。第二场效应管M2的栅极可以作为第二级电路的一个输入端连接第一级电路的输出端(N1点)。此外，从第二级电路的输入端到第二级电路的输出端，形成了对第二级电路的输入端的电压的正相关变动，可以采用作为第一电流镜的场效应管M8和M9以及第二场效应管M2构成的结构。具体地，第二场效应管M2的栅极电压变大会引起作为第一电流镜的场效应管M8和M9的共用栅极的电压变小，从而引起作为第一电流镜的场效应管M8和M9的受控输出电流侧的电压变大，从而实现了正相关变化，反之亦然。
应理解，第一场效应管Mt可以为N型MOS管。第二场效应管M2可以为N型MOS管。作为第一电流镜的场效应管M8和M9中的任一场效应管可以为P型MOS管。场效应管M5和M6可以均为N型MOS管。还应理解，文中的场效应管可以为结型场效应管、耗尽型场效应管、增强型场效应管等场效应管。文中的场效应管既可以为N型场效应管，也可以为P型场效应管。应理解，本申请的说明书多处以MOS管(金属氧化物半导体场效应管)为例，对电路的结构及其功能进行了说明，例如，以N型MOS管或P型MOS管为例，对电路的结构及其功能进行了说明；但是本发明实施例还可以采用其他的场效应管或其他元件来实现各种电路的功能。
图4为本申请的第二实施例的低压差线性稳压器中第二负反馈的反馈原理的示意性说明图。如图4所示，从Vout到第一场效应管Mt的源极，形成了对输出电压变化的正相关变动，例如，输出电压变大，第一场效应管Mt的源极的电压变大，第二级电路的输出端的电压(例如，N2点的电压)变大，反之亦然。此外，从Vout到第二级电路的输入端，形成了对输出电压变化的正相关变动，从第二级电路的输入端到第二级电路的输出端，形成了对第二级电路的输入端的电压的正相关变动。输出电压变大，第二场效应管M2的栅极(例如，N1的电压)变大，第二级电路的输出端的电压(例如，N2点的电压)变大，反之亦然。此外，从第二级电路的输入端到第二级电路的输出端，形成了对第二级电路的输入端的电压的正相关变动，可以采用任意的元件与电路结构。在 一个示例中，可以经由一次或多次正相关变动实现，例如，采用两次正相关变动实现。在另一示例中，也可以采用偶数次的负相关变动或任意次数的正相关变动实现，例如，可以相继经由两次负相关变动实现。
作为一个示例，第二级电路还可以包括第三场效应管，第三场效应管的漏极与第一场效应管的源极连接，其中，第一级电路还包括第四场效应管，第一级电路通过第四场效应管的栅极连接到采样节点，第四场效应管的漏极与第三场效应管的栅极连接。此外，第一级电路还可以包括与第四场效应管形成共源极差分对的第五场效应管，连接节点与第五场效应管的漏极连接。具体而言，如图3所示，第一级电路可以包括第四场效应管M1A、第五场效应管M1B以及作为第二电流镜的场效应管M5和M6。其中，第四场效应管M1A和第五场效应管M1B构成了差分放大电路的差分对，VREF可以为输入LDO的参考电压，VB1可以为输入LDO的一个偏置电压。第一级的输出点可以为N1和N1A。第一级电路还可以包括第六场效应管M4，第六场效应管M4的漏极可以与差分对的各自的源极连接，第六场效应管M4的源极可以与偏置电压源连接。第一采样节点电压VFB可以作为第一级电路的输入连接到第四场效应管M1A的栅极。此外，第三场效应管M7的栅极可以作为第二级电路的另一输入端连接第一级电路的输出端(N1A点)。VB2为输入LDO的另一个偏置电压，接第一场效应管Mt的栅端。第二级输出节点为N2。应理解，上述示例的元件及其连接关系仅仅为示例性的，在其他示例中，第二级电路可以具有其他的结构和连接关系。
具体而言，第一级电路还可以包括第二电流镜，第四场效应管的漏极产生第二电流镜的输入电流，第二电流镜的输出电流经过第五场效应管的漏极。第四场效应管经由第二电流镜的共用栅极与第三场效应管连接。具体而言，如图3所示，作为第二电流镜的场效应管M5和M6、以及第三场效应管M7可以产生前馈通路，此前馈通路引入了左半平面的零点，进而优化了相位裕度，改善稳定性。由于第四场效应管的漏极与第三场效应管的栅极连接，形成了前馈通路，因此还可以通过该前馈通路向第三场效应管进行反馈，从而提高了电路的稳定性。此外，由于第四场效应管位于第一级电路，第三场效应管位于第二 级电路，因此该前馈通路能够实现第二级电路对第一级电路的快速响应，提高了LDO的启动速度。例如，在上电过程，第三场效应管M7的栅极电压会快速建立，第三场效应管M7会产生电流，下拉N2点电压，进而使输出功率管M3产生电流，建立输出电压Vout。
图5为本申请的第二实施例的低压差线性稳压器在输出电压的瞬间下降的情况下的工作原理的示意图。如图5所示，在第一通路中，输出节点，经由第一场效应管的源级形成对反馈节点的输入电压的正相关变动，再经由输出功率管完成对输出节点的输出电压的负相关变动。例如，输出节点通过第一电容形成对第一场效应管的源极电压的正相关变动。例如，当Vout电压由于负载变化出现瞬间下降时，在第一通路上，第一场效应管Mt的源极由于反馈电容Cc耦合作用，瞬间电压下降，应理解，针对同一场效应管而言，源极电压与漏极电压具有正相关的变动关系，从而能增大了从N2点抽取的电流，使得N2点电压下降。
此外，在第二通路中,输出节点,经由第二级电路的输入端形成对反馈节点的输入电压的正相关变动，再经由输出功率管完成对输出节点的输出电压的负相关变动。例如，输出节点通过第二电容形成对第二级电路的输入端电压的正相关变动。例如，当Vout电压由于负载变化出现瞬间下降时，在第二通路上，第二场效应管M2的栅极电压由于反馈电容Cm耦合作用，电压瞬间下降，增大了作为第一电流镜的场效应管M8和M9的栅极电压。应理解，针对同一场效应管而言，栅极电压与漏极电压具有负相关的变动关系，从而减小了输入N2点的电流，使得N2点电压下降。从M9输入的电压减小，被第一场效应管Mt抽取的电流增大，呈现文中所述的推挽效果。基于上述技术手段，使得N2点电压下降，相应地N2点电压下降，增大了输出功率管M3电流，从而减缓了Vout的下冲。因此，LDO具备的推挽式快速响应通路，可以减小由LDO输出负载变化引起的下冲。
图6为本申请的第二实施例的低压差线性稳压器在输出电压的瞬间上升的情况下的工作原理的示意图。同理，如图6所示，当Vout电压由于负载变化出现瞬间上升，两条快速响应通路的推挽作用，可以减小LDO输出负载变化 引起的上冲。
图7为本申请的第三实施例的供电电路的示意图。图7的供电电路包括：低压差线性稳压器710以及直流电源720，直流电源720向输出级电路712的输入端供电。例如，输出级电路712可以与误差放大器711连接或耦接。
低压差线性稳压器710包括输出级电路712和误差放大器。输出级电路712包括输出节点以及与输出节点对应的反馈节点和采样节点。误差放大器包括彼此连接的第一级电路和第二级电路。误差放大器对输出节点的输出电压的第一负反馈进行放大。
第一级电路与采样节点连接，从采样节点接收第一负反馈的输入。第二级电路与反馈节点连接，将第一负反馈输出到反馈节点。第二级电路与输出节点连接，接收输出节点的输出电压的第二负反馈的输入。第二级电路还通过与反馈节点的连接，将第二负反馈输出到反馈节点。
例如，输出级电路可以包括输出功率管，其中，输出节点和反馈节点配置于输出功率管，输出级电路的输入端可以配置与输出功率管。在一个示例中，输出节点可以为输出功率管的漏极，输出级电路的输入端可以为输出功率管的源极，反馈节点可以为输出功率管的栅极。误差放大器的偏置电压源至包括输出级电路的输入端的输入电压。此外，第二级电路与输出功率管可以组成推挽式快速响应通路，推挽式快速响应通路形成第二负反馈。作为输入节点的输出功率管的源极的输入电压可以为第一级电路和第二级电路提供偏置电压。
在本发明实施例的方案中，在本发明实施例的方案中，第一级电路对输出节点对应的采样节点的采样信号进行反馈放大，输入到第二级电路，并且第二级电路将输出电压的第一负反馈输出到所述反馈节点，有效地通过反馈放大形成的第一负反馈实现了输出电压的低压差稳压。此外，误差放大器中的第二级电路接收输出节点的信号形成第二负反馈，并且将第二负反馈输出到反馈节点，进一步通过第二负反馈实现了输出电压的稳压，从而实现了供电电流的稳定的电压输出。
本申请实施例的低压差线性稳压器和供电电路可以应用于以多种设备，包括但不限于：
(1)移动通信设备：这类设备的特点是具备移动通信功能，并且以提供话音、数据通信为主要目标。这类终端包括：智能手机(例如iPhone)、多媒体手机、功能性手机，以及低端手机等。
(2)超移动个人计算机设备：这类设备属于个人计算机的范畴，有计算和处理功能，一般也具备移动上网特性。这类终端包括：PDA、MID和UMPC设备等，例如iPad。
(3)便携式娱乐设备：这类设备可以显示和播放多媒体内容。该类设备包括：音频、视频播放器(例如iPod)，掌上游戏机，电子书，以及智能玩具和便携式车载导航设备。
(4)其他电子设备。
至此，已经对本主题的特定实施例进行了描述。其它实施例在所附权利要求书的范围内。在一些情况下，在权利要求书中记载的动作可以按照不同的顺序来执行并且仍然可以实现期望的结果。另外，在附图中描绘的过程不一定要求示出的特定顺序或者连续顺序，以实现期望的结果。在某些实施方式中，多任务处理和并行处理可以是有利的。
在20世纪90年代，对于一个技术的改进可以很明显地区分是硬件上的改进(例如，对二极管、晶体管、开关等电路结构的改进)还是软件上的改进(对于方法流程的改进)。然而，随着技术的发展，当今的很多方法流程的改进已经可以视为硬件电路结构的直接改进。设计人员几乎都通过将改进的方法流程编程到硬件电路中来得到相应的硬件电路结构。因此，不能说一个方法流程的改进就不能用硬件实体模块来实现。例如，可编程逻辑器件(Programmable Logic Device,PLD)(例如现场可编程门阵列(Field Programmable Gate Array，FPGA))就是这样一种集成电路，其逻辑功能由用户对器件编程来确定。由设计人员自行编程来把一个数字系统“集成”在一片PLD上，而不需要请芯片制造厂商来设计和制作专用的集成电路芯片。而且，如今，取代手工地制作集成电路芯片，这种编程也多半改用“逻辑编译器(logic compiler)”软件来实现，它与程序开发撰写时所用的软件编译器相类似，而要编译之前的原始代码也得用特定的编程语言来撰写，此称之为硬件描述语言(Hardware Description  Language，HDL)，而HDL也并非仅有一种，而是有许多种，如ABEL(Advanced Boolean Expression Language)、AHDL(Altera Hardware Description Language)、Confluence、CUPL(Cornell University Programming Language)、HDCal、JHDL(Java Hardware Description Language)、Lava、Lola、MyHDL、PALASM、RHDL(Ruby Hardware Description Language)等，目前最普遍使用的是VHDL(Very-High-Speed Integrated Circuit Hardware Description Language)与Verilog。本领域技术人员也应该清楚，只需要将方法流程用上述几种硬件描述语言稍作逻辑编程并编程到集成电路中，就可以很容易得到实现该逻辑方法流程的硬件电路。
控制器可以按任何适当的方式实现，例如，控制器可以采取例如微处理器或处理器以及存储可由该(微)处理器执行的计算机可读程序代码(例如软件或固件)的计算机可读介质、逻辑门、开关、专用集成电路(Application Specific Integrated Circuit，ASIC)、可编程逻辑控制器和嵌入微控制器的形式，控制器的例子包括但不限于以下微控制器：ARC 625D、Atmel AT91SAM、Microchip PIC18F26K20以及Silicone Labs C8051F320，存储器控制器还可以被实现为存储器的控制逻辑的一部分。本领域技术人员也知道，除了以纯计算机可读程序代码方式实现控制器以外，完全可以通过将方法步骤进行逻辑编程来使得控制器以逻辑门、开关、专用集成电路、可编程逻辑控制器和嵌入微控制器等的形式来实现相同功能。因此这种控制器可以被认为是一种硬件部件，而对其内包括的用于实现各种功能的装置也可以视为硬件部件内的结构。或者甚至，可以将用于实现各种功能的装置视为既可以是实现方法的软件模块又可以是硬件部件内的结构。
上述实施例阐明的系统、装置、模块或单元，具体可以由计算机芯片或实体实现，或者由具有某种功能的产品来实现。一种典型的实现设备为计算机。具体的，计算机例如可以为个人计算机、膝上型计算机、蜂窝电话、相机电话、智能电话、个人数字助理、媒体播放器、导航设备、电子邮件设备、游戏控制台、平板计算机、可穿戴设备或者这些设备中的任何设备的组合。
为了描述的方便，描述以上装置时以功能分为各种单元分别描述。当然， 在实施本申请时可以把各单元的功能在同一个或多个软件和/或硬件中实现。
本领域内的技术人员应明白，本申请的实施例可提供为方法、系统、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
在一个典型的配置中，计算设备包括一个或多个处理器(CPU)、输入/输出接口、网络接口和内存。
内存可能包括计算机可读介质中的非永久性存储器，随机存取存储器(RAM)和/或非易失性内存等形式，如只读存储器(ROM)或闪存(flash RAM)。内存是计算机可读介质的示例。
计算机可读介质包括永久性和非永久性、可移动和非可移动媒体可以由任何方法或技术来实现信息存储。信息可以是计算机可读指令、数据结构、程 序的模块或其他数据。计算机的存储介质的例子包括，但不限于相变内存(PRAM)、静态随机存取存储器(SRAM)、动态随机存取存储器(DRAM)、其他类型的随机存取存储器(RAM)、只读存储器(ROM)、电可擦除可编程只读存储器(EEPROM)、快闪记忆体或其他内存技术、只读光盘只读存储器(CD-ROM)、数字多功能光盘(DVD)或其他光学存储、磁盒式磁带，磁带磁磁盘存储或其他磁性存储设备或任何其他非传输介质，可用于存储可以被计算设备访问的信息。按照本文中的界定，计算机可读介质不包括暂存电脑可读媒体(transitory media)，如调制的数据信号和载波。
还需要说明的是，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、商品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、商品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、商品或者设备中还存在另外的相同要素。
本领域技术人员应明白，本申请的实施例可提供为方法、系统或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请可以在由计算机执行的计算机可执行指令的一般上下文中描述，例如程序模块。一般地，程序模块包括执行特定事务或实现特定抽象数据类型的例程、程序、对象、组件、数据结构等等。也可以在分布式计算环境中实践本申请，在这些分布式计算环境中，由通过通信网络而被连接的远程处理设备来执行事务。在分布式计算环境中，程序模块可以位于包括存储设备在内的本地和远程计算机存储介质中。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于系统实施例而言，由于其基本相似于方法实施例，所以描述的 比较简单，相关之处参见方法实施例的部分说明即可。
以上所述仅为本申请的实施例而已，并不用于限制本申请。对于本领域技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原理之内所作的任何修改、等同替换、改进等，均应包含在本申请的权利要求范围之内。

Claims (10)

  1. 一种低压差线性稳压器，其特征在于，包括：
    输出级电路，包括输出节点以及与所述输出节点对应的反馈节点和采样节点，其中所述输出节点用于提供所述低压差线性稳压器的输出电压；
    误差放大器，包括彼此连接的第一级电路和第二级电路，其中，所述第一级电路与所述采样节点连接，用于接收所述采样节点的采样信号，并且对所述采样节点的采样信号进行反馈放大，输入到所述第二级电路，以形成所述输出电压的第一负反馈，
    其中，所述第二级电路与所述反馈节点连接，用于将所述输出电压的第一负反馈输出到所述反馈节点，
    其中，所述第二级电路还与所述输出节点连接，用于接收所述输出电压的信号，以形成所述输出电压的第二负反馈，并且通过与所述反馈节点的连接，将所述输出电压的第二负反馈输出到所述反馈节点。
  2. 根据权利要求1所述的低压差线性稳压器，其特征在于，所述输出级电路包括输出功率管，其中，所述输出功率管的漏极和栅极分别连接到所述输出节点和所述反馈节点，所述第二级电路与所述输出功率管组成推挽式快速响应通路，形成所述第二负反馈。
  3. 根据权利要求2所述的低压差线性稳压器，其特征在于，所述推挽式快速响应通路包括第一通路以及第二通路，所述第二级电路中包括第一场效应管，所述第一场效应管的源极与所述输出功率管的漏极连接，所述第一场效应管的漏极与所述输出功率管的栅极连接，
    其中，在所述第一通路中，通过所述第一场效应管形成所述输出功率管的栅极的输入电压关于所述输出电压的正相关变动，并且通过所述输出功率管形成所述输出电压对所述输入电压的负相关变动，
    其中，在所述第二通路中,通过所述第一级电路与所述第二级电路之间的连接节点形成所述输入电压对所述输出电压的正相关变动，并且通过所述输出功率管形成所述输出电压对所述输入电压的负相关变动。
  4. 根据权利要求3所述的低压差线性稳压器，其特征在于，所述输出功率 管的漏极通过第一电容连接到所述第一场效应管的源极，并且所述输出功率管的漏极通过第二电容连接到所述连接节点。
  5. 根据权利要求3所述的低压差线性稳压器，其特征在于，所述第二级电路还包括第二场效应管和第一电流镜，通过所述连接节点连接到所述第二场效应管的栅极，其中，所述第二场效应管的漏极产生所述第一电流镜的输入电流，所述第一电流镜的输出电流分别流入所述输出功率管的栅极和所述第一场效应管的漏极。
  6. 根据权利要求3所述的低压差线性稳压器，其特征在于，所述第一级电路经由所述连接节点将所述第一负反馈输出到所述反馈节点。
  7. 根据权利要求6所述的低压差线性稳压器，其特征在于，所述第二级电路还包括第三场效应管，所述第三场效应管的漏极与所述第一场效应管的源极连接，其中，所述第一级电路还包括第四场效应管，所述第一级电路通过所述第四场效应管的栅极连接到所述采样节点，所述第四场效应管的漏极与所述第三场效应管的栅极连接。
  8. 根据权利要求7所述的低压差线性稳压器，其特征在于，所述第一级电路还包括与所述第四场效应管形成共源极差分对的第五场效应管，所述连接节点与所述第五场效应管的漏极连接。
  9. 根据权利要求8所述的低压差线性稳压器，其特征在于，所述第一级电路还包括第二电流镜，所述第四场效应管的漏极产生所述第二电流镜的输入电流，所述第二电流镜的输出电流经过所述第五场效应管的漏极，其中，所述第四场效应管经由所述第二电流镜的共用栅极与所述第三场效应管连接。
  10. 一种供电电路，其特征在于，包括：如权利要求1-9中的任一项所述的低压差线性稳压器以及直流电源，所述直流电源向所述输出级电路的输入节点供电。
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CN117539318A (zh) * 2024-01-09 2024-02-09 龙骧鑫睿(厦门)科技有限公司 一种高电源抑制比的无片外电容ldo电路
CN117539318B (zh) * 2024-01-09 2024-03-26 龙骧鑫睿(厦门)科技有限公司 一种高电源抑制比的无片外电容ldo电路

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