WO2022074858A1 - Dispositif de commande de mémoire et procédé de commande - Google Patents

Dispositif de commande de mémoire et procédé de commande Download PDF

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Publication number
WO2022074858A1
WO2022074858A1 PCT/JP2021/008885 JP2021008885W WO2022074858A1 WO 2022074858 A1 WO2022074858 A1 WO 2022074858A1 JP 2021008885 W JP2021008885 W JP 2021008885W WO 2022074858 A1 WO2022074858 A1 WO 2022074858A1
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WO
WIPO (PCT)
Prior art keywords
memory
receiving
transmission
descriptor
data
Prior art date
Application number
PCT/JP2021/008885
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English (en)
Japanese (ja)
Inventor
好博 中谷
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オムロン株式会社
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Filing date
Publication date
Application filed by オムロン株式会社 filed Critical オムロン株式会社
Publication of WO2022074858A1 publication Critical patent/WO2022074858A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus

Definitions

  • the control unit of the transmitting unit first sorts the data A to E in the order in which they are desired to be tags. For example, as shown in FIG. 6, the control unit copies the data A to E to any area in the memory so that the data A to E are stored at consecutive addresses (STEP: 1). .. Next, the CPU generates the tag X from the sorted and stored data A to E, and copies the tag X to any area in the memory (STEP: 2). For example, if there is another tag Y to be packetized together, the tag X is copied to an address contiguous with the tag Y. Finally, the tags stored in the consecutive addresses (tag X and tag Y in the example of FIG. 6) are put together to generate a packet (STEP: 3).
  • the memory control device can read out the transfer target data separately even when a plurality of transfer target data are stored at non-consecutive addresses in the transmitting side memory, for example. Therefore, the transmitting side control unit does not need to combine a plurality of transfer target data into one packet or the like in advance. That is, the transmitting side control unit does not need to access the transmitting side memory and copy data or the like in order to generate packets and / or tags. Therefore, according to the above configuration, it is possible to reduce the frequency with which the transmitting side control unit accesses the transmitting side memory, as compared with the case where a plurality of transfer target data are collectively transferred as a packet and / or a tag or the like.
  • the control method of the memory control device accesses the transmission side memory and the reception side memory by the DMA (Direct Memory Access) method, and transfers a plurality of transfer target data. It is a control method of a memory control device that transfers data from the transmitting side memory to the receiving side memory, and the receiving side memory stores at least a receiving descriptor table including a plurality of receiving descriptors, and the transmitting side. From the identifier receiving step of receiving the identifier specifying the receiving descriptor table from the control unit and the receiving descriptor table corresponding to the identifier determined by the transmitting side control unit, the order specified by the receiving descriptor table is specified.
  • DMA Direct Memory Access
  • transferring data from the first processing device 110 to the second processing device 210 may be referred to as “downlink transfer”. Further, transferring data from the second processing device 210 to the first processing device 110 may be referred to as "uplink transfer”.
  • the first unit 100 includes a first processing device 110 and a first memory 120.
  • the first unit 100 may also include an input device, an output device, a non-volatile storage device such as a ROM (Read Only Memory), and the like.
  • the second PCIe interface 213 is an interface for the second processing device 210 to connect to the transfer device 230 via PCIe via PCIebus.
  • FIG. 5 is a block diagram showing an example of a main part configuration of the data transfer system 600 according to the present embodiment.
  • the third unit 300 according to the data transfer system 600 includes a first processing device (transmitter control unit) 110, a first memory 120, and a transfer device (memory control device) 330.
  • the memory control device writes a plurality of transfer target data separately. Therefore, for example, it is not necessary for the receiving side control unit to decompress a packet and / or a tag that summarizes a plurality of transfer target data and copy each transfer target data back to an appropriate area. Therefore, according to the above configuration, it is possible to reduce the frequency with which the receiving side control unit accesses the receiving side memory as compared with the case where a plurality of transfer target data are collectively transferred as a packet and / or a tag or the like.
  • the receiving side memory may store at least a receiving descriptor table including a plurality of receiving descriptors, and the identifier includes the transmitting descriptor table and the receiving descriptor table corresponding to the transmitting descriptor table. It may be a designated identifier.
  • the memory control device includes a receive descriptor reading unit that reads a plurality of receive descriptors included in the receive descriptor table in the order specified by the receive descriptor table from the receive descriptor table designated by the identifier.
  • a data writing unit for sequentially writing the plurality of transfer target data read from the transmitting side memory to the receiving side memory according to the description of the plurality of receiving descriptors sequentially read from the receiving side memory. May be good.
  • the memory control device reads a plurality of transfer target data separately from the transmission side memory and writes them separately. Therefore, the sender control unit does not need to access the sender memory for packet and / or tag generation, and the receiver control unit decompresses the packet and / or tag that summarizes a plurality of transfer target data. , It is not necessary to copy each transfer target data to an appropriate area again. Therefore, according to the above configuration, the frequency with which the transmitting side control unit accesses the transmitting side memory and the frequency with which the receiving side control unit accesses the storage side memory, as compared with the case where a plurality of transfer target data are collectively transferred to a packet and / or a tag or the like. Both the frequency of accessing the receiving memory can be reduced.
  • a RAM RandomAccessMemory
  • the program may be supplied to the computer via any transmission medium (communication network, broadcast wave, etc.) capable of transmitting the program. It should be noted that one aspect of the present invention can also be realized in the form of a data signal embedded in a carrier wave, in which the above program is embodied by electronic transmission.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)

Abstract

La présente invention réduit la lecture et l'écriture en mémoire par un procédé autre que DMA lors du transfert de données par DMA. Un dispositif de transfert (230) reçoit un numéro d'étiquette à partir d'un premier micrologiciel (112), lit, à partir d'une table de descripteur d'émission correspondant au numéro d'étiquette, une pluralité de descripteurs d'émission inclus dans la table de descripteur d'émission, les descripteurs d'émission étant lus dans un ordre désigné par la table de descripteurs d'émission, et transfère successivement une pluralité de données à transférer selon des descriptions dans la pluralité de descripteurs d'émission lus successivement.
PCT/JP2021/008885 2020-10-07 2021-03-08 Dispositif de commande de mémoire et procédé de commande WO2022074858A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2020169750A JP2022061674A (ja) 2020-10-07 2020-10-07 メモリ制御装置および制御方法
JP2020-169750 2020-10-07

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WO2022074858A1 true WO2022074858A1 (fr) 2022-04-14

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JP (1) JP2022061674A (fr)
WO (1) WO2022074858A1 (fr)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002140286A (ja) * 2000-10-31 2002-05-17 Ricoh Co Ltd 情報処理装置及びｄｍａ転送方法
JP2010157129A (ja) * 2008-12-27 2010-07-15 Toshiba Information Systems (Japan) Corp 半導体記憶装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002140286A (ja) * 2000-10-31 2002-05-17 Ricoh Co Ltd 情報処理装置及びｄｍａ転送方法
JP2010157129A (ja) * 2008-12-27 2010-07-15 Toshiba Information Systems (Japan) Corp 半導体記憶装置

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
"1. Overview of Ethernet Controller. Interface Special Issue: Introduction to SH-1 &SH-2 Microcomputers", CQ PUBLISHINGCO., LTD., 1 September 2004 (2004-09-01), pages 222 - 237 *
IWATA, TOSHIO ET AL.: "Linux I/O Minicomputer for Making FPGA PCs with ZYBO.", ZYBO, 1 June 2016 (2016-06-01), pages 110 - 112, ISBN: 978-4-7898-4809-1 *

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