WO2022068262A1 - 半导体制作工艺的检测方法 - Google Patents

半导体制作工艺的检测方法 Download PDF

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Publication number
WO2022068262A1
WO2022068262A1 PCT/CN2021/099757 CN2021099757W WO2022068262A1 WO 2022068262 A1 WO2022068262 A1 WO 2022068262A1 CN 2021099757 W CN2021099757 W CN 2021099757W WO 2022068262 A1 WO2022068262 A1 WO 2022068262A1
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Prior art keywords
detection method
pattern
wafer
process according
photomask
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PCT/CN2021/099757
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English (en)
French (fr)
Inventor
汪恒
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长鑫存储技术有限公司
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Priority to US17/647,659 priority Critical patent/US20220128909A1/en
Publication of WO2022068262A1 publication Critical patent/WO2022068262A1/zh

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/708—Construction of apparatus, e.g. environment aspects, hygiene aspects or materials
    • G03F7/7085—Detection arrangement, e.g. detectors of apparatus alignment possibly mounted on wafers, exposure dose, photo-cleaning flux, stray light, thermal load
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70058—Mask illumination systems
    • G03F7/70091—Illumination settings, i.e. intensity distribution in the pupil plane or angular distribution in the field plane; On-axis or off-axis settings, e.g. annular, dipole or quadrupole settings; Partial coherence control, i.e. sigma or numerical aperture [NA]
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70625—Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70641—Focus

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a method for detecting a semiconductor fabrication process.
  • An exposure system for lithography includes a lithography illuminator, a photomask, a projection objective, and a workpiece stage for loading wafers.
  • the photolithography illumination device projects the photomask pattern on the photomask onto the wafer through the projection objective lens to form the photolithography pattern.
  • the quality of the lithographic patterns formed on the wafer varies with different lighting conditions. In order to guarantee the quality of the lithographic pattern, it is necessary to detect changes in lighting conditions.
  • the technical problem to be solved by the present application is to provide a detection method for a semiconductor manufacturing process, which can simultaneously obtain detection results under different lighting conditions on the same wafer, shorten detection time, improve production efficiency, and save costs.
  • the present application provides a detection method for a semiconductor manufacturing process, which uses the same photomask to expose different regions of the same wafer under different lighting conditions to obtain multiple lithography patterns; Check the engraved pattern.
  • the illumination conditions include spot shape, numerical aperture (NA, Numerical Aperture) and coherence (Sigma).
  • the use of the same photomask to expose different regions of the same wafer under different lighting conditions to obtain multiple lithography patterns includes: performing exposure to the same region on the photomask under different lighting conditions. photomask pattern for exposure.
  • the use of the same photomask to expose different regions of the same wafer under different lighting conditions to obtain multiple lithography patterns includes: exposing the same photomask to the same photomask under different lighting conditions. The mask pattern is exposed.
  • the different illumination conditions are set such that the shapes of the light spots are the same, and at least one of the numerical aperture and the coherence degree is different.
  • the coherence degree includes an outer coherence degree and an inner coherence degree, and the difference between the outer coherence degree and/or the inner coherence degree under different lighting conditions ranges from 0 to 0.1.
  • the difference range of the numerical aperture of the different lighting conditions is 0-0.05.
  • the values of the internal coherence degrees of several of the lighting conditions are arithmetic progressions; the lighting conditions with the optimum process results are determined by detecting the lithography patterns; the optimum lighting conditions with the process results are used.
  • the lighting conditions expose subsequent wafers.
  • the detecting the lithography pattern includes: detecting the depth of focus and/or overlay accuracy of the lithography pattern.
  • the shape of the light spot includes any one of a dipole, a quadrupole, a ring or a circle.
  • the exposed areas are arranged adjacently or at intervals.
  • the wafer is a wafer with a preset pattern
  • different regions of the wafer include regions of the wafer with a preset pattern and/or regions without a preset pattern.
  • the advantages of the present application are that the detection results of different lighting conditions can be obtained on the same wafer at the same time, the detection time is shortened, the production efficiency is improved, and the cost is saved. At the same time, using the inspection results to further optimize the lighting conditions, and using the optimized lighting conditions to expose the subsequent wafers can increase the process window and improve the yield.
  • FIG. 1 is a schematic diagram of a pattern formed on a wafer using the method of the first embodiment of the present application
  • FIG. 2 is a schematic diagram of a pattern formed on a wafer using the method of the second embodiment of the present application;
  • FIG. 3 is a schematic diagram of a pattern formed on a wafer using the method of the third embodiment of the present application.
  • FIG. 4 is a schematic diagram of a pattern formed on a wafer using the method of the fourth embodiment of the present application.
  • FIG. 5 is a table corresponding to the exposed area and irradiation conditions in the fourth embodiment of the present application.
  • FIG. 6 is a schematic diagram of a pattern formed on a wafer using the method of the fifth embodiment of the present application.
  • the detection method of the semiconductor manufacturing process of the present application includes: using the same photomask to expose different regions of the same wafer under different lighting conditions to obtain a plurality of lithography patterns; and detecting the lithography patterns.
  • the photomask can be a detection photomask matching the exposure system, or a photomask set by the user according to their own needs, such as a test photomask or a photomask for mass production.
  • photomask patterns on the photomask there are photomask patterns on the photomask, and the photomask patterns are distributed on different areas of the photomask.
  • the shape of the photomask patterns can be various, for example, the photomask patterns include lines, round holes, broken lines, etc. etc., the photomask pattern may be a discrete single pattern, or may be a plurality of connected patterns.
  • Illumination conditions include spot shape, numerical aperture (NA, Numerical Aperture) and coherence (Sigma).
  • the spot shape includes any one of a dipole (Dipole), a quadrupole (Quadrupole), an annular (Annular) or a circular (Circular).
  • the spot shape may be a freeform shape, for example, for an ASML flexray illumination system, various shaped spots can be formed by adjusting the reflection angles of multiple micro-mirrors.
  • the same photomask is used to expose different areas of the same wafer under different illumination conditions to obtain multiple lithography patterns, including: exposing the photomask patterns of the same area on the photomask using different illumination conditions.
  • the photomask is divided into four quadrants with the center point of the photomask as the coordinate origin, and each quadrant corresponds to an area; in other embodiments, the areas can also be divided according to the needs of engineers, such as a certain type of light
  • the distribution area of the mask pattern specifically, the mark pattern area, the line array test pattern area, etc.
  • the same photomask is used to expose different regions of the same wafer under different lighting conditions to obtain multiple lithography patterns, including: exposing the same photomask pattern on the photomask with different lighting conditions.
  • the photomask pattern may be an overlay mark, a weak point pattern, or the like.
  • Different photomask patterns have different sensitivities to lighting conditions. If different photomask patterns are used for exposure detection, the detection results may not be comparable. Therefore, the use of the same photomask pattern can rule out this problem. interference, making the detection results more accurate.
  • the same photomask pattern can also eliminate the interference caused by the photomask manufacturing process, such as the surface roughness of the photomask version itself and the uniformity of the size of the photomask pattern on the photomask version.
  • Different lighting conditions may be set such that the shape of the light spot is the same and at least one of numerical aperture and coherence is different.
  • the degree of coherence includes the degree of external coherence ( ⁇ out) and the degree of internal coherence ( ⁇ in), and the difference between the degree of external coherence and/or the degree of internal coherence under different lighting conditions ranges from 0 to 0.1.
  • the difference in numerical aperture of different lighting conditions ranges from 0 to 0.05.
  • the difference range of the outer coherence degree and/or the inner coherence degree of different lighting conditions can be understood as the range of the maximum difference and the minimum difference of the outer coherence degree and/or the inner coherence degree of different lighting conditions, for example, different
  • the internal coherence degrees of the lighting conditions were 0.7, 0.72, 0.74, 0.76, 0.78, 0.8; the external coherence degrees of the different lighting conditions were 0.8, 0.82, 0.84, 0.86, 0.88, 0.9, respectively.
  • the difference range of the numerical aperture of different lighting conditions can be understood as the range of the maximum difference and the minimum difference of the numerical aperture of different lighting conditions, for example, the numerical apertures of different lighting conditions are 1.3, 1.31, 1.32, 1.33, 1.34, 1.35. This setting ensures that the interference of the lighting conditions to the OPC is minimal, and at the same time, the optimal lighting conditions can be selected according to the best process results.
  • the difference in lighting conditions also includes a difference in the shape of the light spot.
  • the photomask is irradiated with light spots of different shapes, and the photomask pattern on the photomask is projected to different areas on the wafer.
  • lithography patterns corresponding to different spot shapes can be obtained on the wafer. For example, using the same photomask to expose different areas on the same wafer with Dipole, Quadrupole, Annular, and Circular spots respectively, after development, the The lithography patterns corresponding to the four spot shapes are obtained.
  • the detection of the lithography pattern includes: detecting the depth of focus (DOF) and/or the overlay accuracy (OVL) of the lithography pattern.
  • the same photomask pattern can be used to perform focal length matrix (FM) exposure on the same wafer under different lighting conditions. Exposures with focal lengths (Focus) of 0, ⁇ 20nm, ⁇ 30nm, and ⁇ 40nm are carried out under one lighting condition, respectively, and the second lighting condition is used to perform exposures at different positions of the second region of the wafer (such as the right semicircle of the wafer) with the focal lengths of 0, ⁇ 20nm, ⁇ 30nm, ⁇ 40nm exposure.
  • FM focal length matrix
  • the DOF of the lithography pattern under different illumination conditions is determined by detecting the size and image of the lithography pattern obtained by exposure at different focal lengths under different illumination conditions.
  • the overlay mark lithography pattern can be obtained on the wafer, and the overlay mark lithography pattern under different lighting conditions can be obtained by measuring the overlay mark lithography pattern. engraving accuracy.
  • the detection method of the semiconductor manufacturing process of the present application further includes the following steps: presetting illumination parameters for forming illumination conditions, and automatically executing the exposure step according to the preset illumination parameters.
  • the illumination parameters can be preset in the exposure system to form multiple illumination conditions, then in the exposure step, the same photomask pattern is used as a mask, the preset illumination parameters are used, and different illumination conditions are used to align the crystals. Different areas of the circle are exposed to form multiple lithographic patterns.
  • the wafer is a bare wafer, that is, the wafer is a wafer without any pattern.
  • the wafer can also be a wafer with a preset pattern.
  • FIG. 1 is a schematic diagram of a lithography pattern formed on a wafer using the method of the first embodiment of the present application, wherein, in FIG. 1 , the shape of each lithography pattern is not specifically depicted, but only each The location of the lithographic pattern.
  • the same lithography mask pattern is used as a mask to form a plurality of lithography patterns in different regions of the wafer 10 , wherein the exposed region 11 (ie, the lithography pattern is formed) pattern area) adjacent to each other.
  • the exposed areas 11 are represented by hatching, and it can be seen from FIG. 1 that a plurality of exposed areas 11 are arranged adjacent to each other.
  • the number of exposed areas 11 is consistent with the number of lighting conditions, that is, there are as many exposed areas as there are lighting conditions, and only five exposed areas are schematically shown in FIG. 1 .
  • area 11, and in other embodiments of the present application, the number of exposed areas 11 may be other, which is not limited herein.
  • the exposed area 11 may be one or more exposure units corresponding to the exposure system.
  • the detection method of the semiconductor manufacturing process of the present application can simultaneously obtain detection results of different lighting conditions on the same wafer, shorten the detection time, improve the production efficiency, and save the cost.
  • a plurality of exposed areas are arranged adjacently, while in other embodiments of the present application, the exposed areas are arranged at intervals.
  • FIG. 2 is a schematic diagram of a lithography pattern formed on a wafer by the method of the second embodiment of the present application, wherein the shape of each lithography pattern is not specifically depicted in FIG. 2 . , but only the positions of each lithography pattern are shown.
  • the exposed areas 11 are arranged at intervals.
  • the exposed areas 11 are arranged at intervals, and an exposure unit is spaced between adjacent exposed areas 11 to avoid mutual interference between adjacent exposed areas 11 .
  • the exposed areas 11 are arranged at intervals, and multiple exposure units may be spaced between adjacent exposed areas 11 , which is not limited in this application.
  • the plurality of exposed regions are arranged adjacently, and in the second embodiment, the plurality of exposed regions are arranged at intervals. It can be seen that in the first embodiment and the second embodiment, the exposed areas are arranged in an orderly manner, and in other embodiments of the present application, the exposed areas can also be arranged in random order, that is, the exposed areas are arranged randomly.
  • FIG. 3 is a schematic diagram of a lithography pattern formed on a wafer by the method of the third embodiment of the present application, wherein the shape of each lithography pattern is not specifically depicted in FIG. 3 . , but only shows the positions of each lithography pattern.
  • the difference between the third embodiment and the first embodiment is that the exposed areas 11 are arranged in random order. Specifically, a plurality of exposed areas 11 are randomly arranged on the wafer. 10, instead of being set in an orderly manner according to a certain rule, the advantage is that the step of selecting the exposed area is omitted, the procedure is simplified, and the test time is further shortened.
  • the lighting parameters are changed, and then the lighting conditions are changed, so that the shapes of the light spots formed on the wafer are different.
  • the basic shape remains unchanged.
  • FIG. 4 is a schematic diagram of a pattern formed on a wafer by the method of the fourth embodiment of the present application, wherein the shape of each lithography pattern is not specifically depicted in FIG. 4 , but Only the positions of each lithography pattern are shown.
  • the difference between the fourth embodiment and the first embodiment is that the basic shapes of the plurality of light spots remain unchanged and are only fine-tuned.
  • the value of the external coherence ( ⁇ out) of several lighting conditions is an arithmetic sequence; the lighting conditions with the optimal process results are determined by detecting the lithography pattern; the subsequent wafers are exposed using the lighting conditions with the optimal process results .
  • the optimal process result refers to the optimal parameters that can characterize the quality of the lithography process, such as DOF, OVL, CDU, etc. Specifically, please refer to FIG. 4 and FIG.
  • the exposed area corresponding to the preset lighting condition DOE (20010-1) is A, and the lighting parameters of the preset lighting condition are fine-tuned to obtain multiple lighting conditions, for example, the lighting condition DOE (20010-1), DOE (20010-2), DOE (20010-3), DOE (20010-4), DOE (20010-5)... ⁇ out is 0.8, 0.81, 0.82, 0.83, 0.84... etc., respectively,
  • the corresponding exposed areas are A, B, C, D, E, etc. respectively.
  • the optimal lighting conditions can be screened out by fine-tuning the external coherence of the lighting conditions, thereby improving the overlay process window of the product. For example, as shown in FIG.
  • the lithography pattern of the exposed area is detected and it is found that the overlay process window of the lithography pattern of the exposed area R and the exposed area T is the best, then the exposure area R and the exposed area can be
  • the lighting condition corresponding to T is used as the lighting condition for the subsequent formation of the lithography pattern, thereby improving the process window of the product and increasing the product yield.
  • Photolithography is a common process often used in semiconductor manufacturing. With the development of semiconductor manufacturing technology and the development of integrated circuit design and manufacturing, lithography imaging technology has developed along with it, and the feature size of semiconductor devices has been continuously reduced.
  • interlayer alignment that is, overlay alignment
  • the overlay accuracy refers to the alignment accuracy (superposition accuracy) between the pattern existing on the surface of the silicon wafer and the pattern on the current reticle.
  • Overlay accuracy is one of the important performance indicators of modern high-precision step-and-scan projection lithography machines, and it is also an important part of the new lithography technology that needs to be considered. Registration accuracy will seriously affect product yield and performance. Improving the registration accuracy of the lithography machine is also the key to determining the minimum unit size.
  • the wafer is a bare wafer, and in this embodiment, the wafer is a wafer with a preset pattern, that is, a wafer used for measuring the overlay accuracy.
  • the wafer is a wafer with a predetermined pattern.
  • the exposure system monitors OVL wafers (HOLY wafers).
  • FIG. 6 is a schematic diagram of a pattern formed on a wafer by the method of the fifth embodiment of the present application, wherein the shape of each lithography pattern is not specifically depicted in FIG. 6 , but Only the positions of the lithography patterns are shown.
  • the difference between the fifth embodiment and the first embodiment is that the wafer 10 is a wafer with a preset pattern.
  • patterns can be formed in both regions of the wafer with the predetermined pattern and regions without the predetermined pattern.
  • the area marked by the exposed area A is the area with a preset pattern on the wafer, that is, the area used for monitoring overprinting (OVL), and the areas marked by the exposed areas B and C are Areas that do not have patterns.
  • the same photomask pattern can be used as a mask to expose different areas of the wafer (such as the exposed areas A, B, C) under different lighting conditions to obtain multiple lithography patterns to monitor the sleeves. The relationship between engraving accuracy and lighting conditions.

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Abstract

一种半导体制作工艺的检测方法，采用同一光掩模版在不同的照明条件下对同一晶圆（10）的不同区域进行曝光，获得多个光刻图案；对光刻图案进行检测。可以同时在同一晶圆（10）上获得不同照明条件的检测结果，缩短了检测时间，提高了生产效率，节约了成本。

Description

半导体制作工艺的检测方法
交叉引用
本申请基于申请号为202011047267.8、申请日为2020年09月29日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体制作工艺的检测方法。
背景技术
现如今随着半导体和集成电路制造行业的发展，光刻技术逐渐成为集成电路制造的关键之处。
用于光刻技术的曝光系统包括光刻照明装置、光掩模版、投影物镜以及用于装载晶圆(wafer)的工件台。光刻照明装置通过投影物镜将光掩模版上的光掩模图案投影到晶圆上形成光刻图案。不同的照明条件，在晶圆上形成的光刻图案的质量不同。为了保证光刻图案的质量，需要检测照明条件的变化。
发明内容
本申请所要解决的技术问题是，提供一种半导体制作工艺的检测方法，其能够同时在同一晶圆上获得不同照明条件的检测结果，缩短了检测时间，提高了生产效率，节约了成本。
为了解决上述问题，本申请提供了一种半导体制作工艺的检测方法，采用同一光掩模版在不同的照明条件下对同一晶圆的不同区域进 行曝光，获得多个光刻图案；对所述光刻图案进行检测。
进一步的，所述照明条件包括光斑形状，数值孔径(NA，Numerical Aperture)和相干度(Sigma)。
进一步的，所述采用同一光掩模版在不同的照明条件下对同一晶圆的不同区域进行曝光，获得多个光刻图案，包括：在不同的照明条件下对所述光掩模版上同一区域的光掩模图案进行曝光。
进一步的，所述采用同一光掩模版在不同的照明条件下对同一晶圆的不同区域进行曝光，获得多个光刻图案，包括：在不同的照明条件下对所述光掩模版上同一光掩模图案进行曝光。
进一步的，所述不同的所述照明条件设置为，所述光斑的形状相同，所述数值孔径和所述相干度中的至少一种不同。
进一步的，所述相干度包括外相干度和内相干度，不同的所述照明条件的所述外相干度和/或所述内相干度的差异范围为0～0.1。
进一步的，不同的所述照明条件的所述数值孔径的差异范围为0～0.05。
进一步的，若干个所述照明条件的内相干度的数值为等差数列；通过对所述光刻图案进行检测确定所述工艺结果最优的所述照明条件；利用所述工艺结果最优的所述照明条件对后续晶圆进行曝光。
进一步的，所述对所述光刻图案进行检测，包括：检测所述光刻图案的焦深和/或套刻精度。
进一步的，所述光斑形状包括偶极、四极、环形或圆形中的任一种。
进一步的，在所述晶圆上，被曝光的区域相邻设置或间隔设置。
进一步的，所述晶圆为具有预设图案的晶圆，所述晶圆的不同区域包括晶圆具有预设图案的区域和/或不具有预设图案的区域。
本申请的优点在于，能够同时在同一晶圆上获得不同照明条件的检测结果，缩短了检测时间，提高了生产效率，节约了成本。同时，利用检测的结果进一步优化照明条件，利用优化后的照明条件对后续晶圆晶圆进行曝光可以增大工艺窗口，提高良率。
附图说明
图1是采用本申请的第一实施例的方法在晶圆上形成的图案的示意图；
图2是采用本申请的第二实施例的方法在晶圆上形成的图案的示意图；
图3是采用本申请的第三实施例的方法在晶圆上形成的图案的示意图；
图4是采用本申请的第四实施例的方法在晶圆上形成的图案的示意图；
图5是采用本申请第四实施例中被曝光区域与照射条件的对应表格；
图6是采用本申请的第五实施例的方法在晶圆上形成的图案的示意图。
具体实施方式
下面结合附图对本申请提供的半导体制作工艺的检测方法的具体实施方式做详细说明。
第一实施例
本申请半导体制作工艺的检测方法包括：采用同一光掩模版在不同的照明条件下对同一晶圆的不同区域进行曝光，获得多个光刻图案；对光刻图案进行检测。
光掩模版可以为曝光系统配套的检测光掩模版，也可为使用者根据自身需求而另外设置的光掩模版，如测试光掩模版或量产产品的光掩模版。
光掩模版上具有光掩模图案，光掩模图案分布在光掩模版的不同区域上，光掩模图案的形状可以为多种多样的，例如光掩模图案包括线条，圆孔，折线等等，光掩模图案可以为分立的单个图案，也可以为相连的多个图案。
照明条件包括光斑形状，数值孔径(NA，Numerical Aperture)和相干度(Sigma)。具体的，光斑形状包括偶极(Dipole)、四极(Quadrupole)、环形(Annular)或圆形(Circular)中的任一种。在其他示例中，光斑形状可以是自由形态(freeform)形状，例如，对于ASML flexray照明系统，通过调节多个微镜(micro-mirror)的反射角度可以形成各种形状的光斑。
采用同一光掩模版在不同的照明条件下对同一晶圆的不同区域进行曝光，获得多个光刻图案，包括：利用不同的照明条件对光掩模版上同一区域的光掩模图案进行曝光。例如，以光掩模版的中心点为 坐标原点将光掩模版划分为四个象限，每个象限对应一个区域；在其他实施例中，区域也可以根据工程人员的需要划分，例如某一类型光掩模图案的分布区域，具体的，标记图形区域，线条阵列测试图形区域等。或者采用同一光掩模版在不同的照明条件下对同一晶圆的不同区域进行曝光，获得多个光刻图案，包括：用不同的照明条件对光掩模版上同一光掩模图案进行曝光。例如，光掩模图案可以为套刻标记，弱窗口图案(weak point)等。不同的光掩模图案对照明条件的敏感性是不一样的，如果采用不同的光掩模图案进行曝光检测，可能会导致检测的结果没有可比性，因此采用同一光掩模图案可以排除这种干扰，使得检测结果更加精确。同时，同一光掩模图案也能排除光掩模制作工艺带来的干扰，如光掩模版本身的表面粗超度以及光掩模版上光掩模图案的尺寸的均匀度。
不同的照明条件可以设置为，光斑的形状相同，数值孔径和相干度中的至少一种不同。相干度包括外相干度(σout)和内相干度(σin)，不同的照明条件的外相干度和/或内相干度的差异范围为0～0.1。不同的照明条件的数值孔径的差异范围为0～0.05。不同的照明条件的外相干度和/或内相干度的差异范围可以理解为不同的照明条件的外相干度和/或内相干度的差异最大值和差异最小值所处的范围，例如，不同的照明条件的内相干度分别0.7，0.72，0.74，0.76，0.78，0.8；不同的照明条件的外相干度分别0.8，0.82，0.84，0.86，0.88，0.9。不同的照明条件的数值孔径的差异范围可以理解为不同的照明条件的数值孔径的差异最大值和差异最小值所处的范围，例 如，不同的照明条件的数值孔径分别为1.3，1.31，1.32，1.33，1.34，1.35。如此设置，保证照明条件对OPC的干扰最小，同时，又可以根据最佳工艺结果选择最优的照明条件。
在其他实施例中，照明条件的不同还包括光斑形状的不同。例如，在同一光掩模版作为掩模的情况下，利用不同形状的光斑照射光掩模版，将光掩模版上的光掩模图案投影到晶圆上的不同区域，通过对晶圆上的光刻胶进行显影可以在晶圆上得到对应不同光斑形状的光刻图案。例如，利用同一光掩模版分别采用偶极(Dipole)、四极(Quadrupole)、环形(Annular)和圆形(Circular)光斑对同一晶圆上的不同区域进行曝光，经过显影可以在晶圆上得到分别对应四种光斑形状的光刻图案。
一些具体实施中，对光刻图案进行检测，包括：检测光刻图案的焦深(DOF)和/或套刻精度(OVL)。具体的，可以利用同一光掩模图案在不同的照明条件下对同一晶圆进行焦距矩阵(FM)的曝光，例如在晶圆的第一区域(如晶圆的左半圆)的不同位置利用第一照明条件分别进行焦距(Focus)为0，±20nm，±30nm，±40nm的曝光，利用第二照明条件在晶圆的第二区域(如晶圆的右半圆)的不同位置分别进行焦距为0，±20nm，±30nm，±40nm的曝光。通过检测不同照明条件在不同焦距下曝光得到的光刻图案的尺寸以及图像，确定不同照明条件下的光刻图案的DOF。当采用不同的照明条件对光掩模版上的套刻标记图案进行曝光时，可以在晶圆上得到套刻标记光刻图案，通过量测套刻标记光刻图案得到不同的照明条件下的套刻精度。
本申请半导体制作工艺的检测方法还包括如下步骤：预先设置形成照明条件的照明参数，在曝光步骤中自动按照预设的照明参数执行。具体地说，可在曝光系统中预先设置照明参数，形成多个照明条件，则在曝光的步骤中，以同一光掩模图案作为掩模，采用预设照明参数，利用不同的照明条件对晶圆的不同区域曝光形成多个光刻图案。
在本实施例中，晶圆为裸片晶圆，即晶圆为未设置有任何图案的晶圆，而在本申请其他实施例中，晶圆也可为预设有图案的晶圆。
图1是采用本申请的第一实施例的方法在晶圆上形成的光刻图案的示意图，其中，在图1中并未具体绘示各个光刻图案的形状，而是仅绘示了各个光刻图案的位置。请参阅图1，在第一实施例中，采用同一光刻掩模图案作为掩模，在晶圆10的不同区域，形成多个光刻图案，其中，被曝光区域11(即形成有光刻图案的区域)相邻设置。具体地说，在图1中，被曝光区域11采用阴影绘示，从图1可以看出，多个被曝光区域11相邻设置。其中，在本实施例中，被曝光区域11的数量与照明条件的数量一致，即有多少个照明条件，就有多少个被曝光区域，在图1中仅示意性地绘示五个被曝光区域11，而在本申请其他实施例中，被曝光区域11可为其他数量，本文对此不进行限定。其中，被曝光区域11可以为曝光系统对应的一个或多个曝光单元。
本申请的半导体制作工艺的检测方法能够同时在同一晶圆上获得不同照明条件的检测结果，缩短了检测时间，提高了生产效率，节 约了成本。
第二实施例
在第一实施例中，多个被曝光区域相邻设置，而在本申请其他实施例中，被曝光区域间隔设置。具体地说，请参阅图2，其为采用本申请的第二实施例的方法在晶圆上形成的光刻图案的示意图，其中，在图2中并未具体绘示各个光刻图案的形状，而是仅绘示了各个光刻图案的位置，第二实施例与第一实施例的区别在于，被曝光区域11间隔设置。具体地说，在第二实施例中，被曝光区域11间隔设置，且相邻的被曝光区域11之间间隔一个曝光单元，以避免相邻的被曝光区域11之间相互干扰。而在本申请其他实施例中，被曝光区域11间隔设置，且相邻的被曝光区域11之间可间隔多个曝光单元，本申请对此不进行限制。
第三实施例
在第一实施例中，多个被曝光区域相邻设置，在第二实施例中，多个被曝光区域间隔设置。可见，在第一实施例及第二实施例中，被曝光区域均是有序设置，而在本申请其他实施例中，被曝光区域也可无序设置，即被曝光区域随机设置。具体地说，请参阅图3，其为采用本申请的第三实施例的方法在晶圆上形成的光刻图案的示意图，其中，在图3中并未具体绘示各个光刻图案的形状，而是仅绘示了各个光刻图案的位置，第三实施例与第一实施例的区别在于，被曝光区域11无序设置，具体地说，多个被曝光区域11随机设置在晶圆10的 任意位置，而并非是按照一定规律有序设置，其优点在于，省略了被曝光区域选择的步骤，简化了程序，进一步缩短测试时间。
第四实施例
在第一实施例中，改变照明参数，进而改变照明条件，使得在晶圆上形成的光斑的形状不同，而在本申请其他实施例中，也可改变照明参数，仅微调照明条件，光斑的基本形状不变。具体地说，请参阅图4，其为采用本申请的第四实施例的方法在晶圆上形成的图案的示意图，其中，在图4中并未具体绘示各个光刻图案的形状，而是仅绘示了各个光刻图案的位置，第四实施例与第一实施例的区别在于，多个光斑的基本形状不变，仅是被微调。例如，若干个照明条件的外相干度(σout)的数值为等差数列；通过对光刻图案进行检测确定工艺结果最优的照明条件；利用工艺结果最优的照明条件对后续晶圆进行曝光。工艺结果最优指DOF，OVL，CDU等能够表征光刻工艺质量的参数最优。具体地说，请参阅图4及图5，预设照明条件DOE(20010-1)对应的被曝光区域为A，微调预设照明条件的照明参数，获得多个照明条件，例如，照明条件DOE(20010-1)、DOE(20010-2)、DOE(20010-3)、DOE(20010-4)、DOE(20010-5)…的σout分别为0.8、0.81、0.82、0.83、0.84…等，其分别对应的被曝光区域为A、B、C、D、E等。本实施例通过微调照明条件的外相干度可从中筛选出最优的照明条件，从而改善产品的套刻工艺窗口。例如，如图4所示，检测被曝光区域的光刻图案发现，被曝光区域R及被曝光区域T的光刻图案的套刻 工艺窗口为最佳，则可将曝光区域R及被曝光区域T对应的照明条件作为后续形成该光刻图案的照明条件，从而改善产品的工艺窗口，增加产品良率。
第五实施例
光刻工艺是半导体制造过程中经常采用到的一种常见工艺。随着半导体制造技术的发展以及集成电路设计及制造的发展，光刻成像技术随之发展，半导体器件的特征尺寸也不断的缩小。光刻时需要注意层间对准，即套刻对准，以保证当前图形与硅片上已经存在的图形之间的对准，因此，为了实现良好的产品性能以高产率，希望实现较高的套刻精度。其中，具体地说，套刻精度指的是硅片表面上存在的图案与当前掩模版上图案的对准精度(叠对精度)。套刻精度是现代高精度步进扫描投影光刻机的重要性能指标之一，也是新型光刻技术需要考虑的一个重要部分。套准精度将会严重影响产品的良率和性能。提高光刻机的套准精度，也是决定最小单元尺寸的关键。
在第一实施例中，晶圆为裸片晶圆，而在本实施例中，晶圆为具有预设图案的晶圆，即用于测量套刻精度的晶圆，例如，晶圆为使用曝光系统监测OVL的晶圆(HOLY晶圆)。具体地说，请参阅图6，其为采用本申请的第五实施例的方法在晶圆上形成的图案的示意图，其中，在图6中并未具体绘示各个光刻图案的形状，而是仅绘示了各个光刻图案的位置，第五实施例与第一实施例的区别在于，晶圆10为具有预设图案的晶圆。在进行曝光时，可在晶圆具有预设图案的区域 及不具有预设图案的区域均形成图案。具体地说，请参阅图6，被曝光区域A标示的区域为在晶圆上具有预设图案的区域，即用于监测套刻(OVL)的区域，被曝光区域B及C标示的区域为不具有图案的区域。则可采用同一光掩模图案作为掩模，在不同的照明条件下，对该晶圆的不同区域(例如被曝光区域A、B、C)进行曝光，获得多个光刻图案，以监测套刻精度与照明条件的关系。
以上仅是本申请的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (14)

  1. 一种半导体制作工艺的检测方法，其特征在于，包括：
    采用同一光掩模版在不同的照明条件下对同一晶圆的不同区域进行曝光，获得多个光刻图案；
    对所述光刻图案进行检测。
  2. 根据权利要求1所述的半导体制作工艺的检测方法，其特征在于，所述照明条件包括光斑形状，数值孔径和相干度。
  3. 根据权利要求2所述的半导体制作工艺的检测方法，其特征在于，所述采用同一光掩模版在不同的照明条件下对同一晶圆的不同区域进行曝光，获得多个光刻图案，包括：在不同的照明条件下对所述光掩模版上同一区域的光掩模图案进行曝光。
  4. 根据权利要求2所述的半导体制作工艺的检测方法，其特征在于，所述采用同一光掩模版在不同的照明条件下对同一晶圆的不同区域进行曝光，获得多个光刻图案，包括：在不同的照明条件下对所述光掩模版上同一光掩模图案进行曝光。
  5. 根据权利要求3或4所述的半导体制作工艺的检测方法，其特征在于，
    所述不同的所述照明条件设置为，所述光斑的形状相同，所述数值孔径和所述相干度中的至少一种不同。
  6. 根据权利要求5所述的半导体制作工艺的检测方法，其特征在于，所述相干度包括外相干度和内相干度，不同的所述照明条件的所述外相干度和/或所述内相干度的差异范围为0～0.1。
  7. 根据权利要求5所述的半导体制作工艺的检测方法，其特征在于，不同的所述照明条件的所述数值孔径的差异范围为0～0.05。
  8. 根据权利要求6所述的半导体制作工艺的检测方法，其特征在于，
    若干个所述照明条件的外相干度的数值为等差数列；
    通过对所述光刻图案进行检测确定所述工艺结果最优的所述照明条件；
    利用所述工艺结果最优的所述照明条件对后续晶圆进行曝光。
  9. 根据权利要求1所述的半导体制作工艺的检测方法，其特征在于，所述对所述光刻图案进行检测，包括：
    检测所述光刻图案的焦深和/或套刻精度。
  10. 根据权利要求1所述的半导体制作工艺的检测方法，其特征在于，
    所述照明条件的不同包括光斑形状的不同。
  11. 根据权利要求2所述的半导体制作工艺的检测方法，其特征在于，
    所述光斑形状包括偶极、四极、环形或圆形中的任一种。
  12. 根据权利要求2所述的半导体制作工艺的检测方法，其特征在于，
    所述光斑形状包括通过调节多个微镜的反射角度形成的光斑。
  13. 根据权利要求1所述的半导体制作工艺的检测方法，其特征在于，在所述晶圆上，被曝光的区域相邻设置或间隔设置。
  14. 根据权利要求1所述的半导体制作工艺的检测方法，所述晶圆为具有预设图案的晶圆，所述晶圆的不同区域包括具有预设图案的区域和/或不具有预设图案的区域。
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