WO2022068256A1 - 半导体器件的外延结构及其制备方法 - Google Patents

半导体器件的外延结构及其制备方法 Download PDF

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WO2022068256A1
WO2022068256A1 PCT/CN2021/099163 CN2021099163W WO2022068256A1 WO 2022068256 A1 WO2022068256 A1 WO 2022068256A1 CN 2021099163 W CN2021099163 W CN 2021099163W WO 2022068256 A1 WO2022068256 A1 WO 2022068256A1
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buffer layer
layer
doping concentration
thickness
substrate
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PCT/CN2021/099163
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English (en)
French (fr)
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张晖
李仕强
张乃千
裴轶
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苏州能讯高能半导体有限公司
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Priority claimed from CN202011065977.3A external-priority patent/CN114335159A/zh
Priority claimed from CN202022206942.9U external-priority patent/CN213212169U/zh
Application filed by 苏州能讯高能半导体有限公司 filed Critical 苏州能讯高能半导体有限公司
Priority to JP2023518044A priority Critical patent/JP2023542021A/ja
Priority to US17/921,869 priority patent/US20230170214A1/en
Publication of WO2022068256A1 publication Critical patent/WO2022068256A1/zh

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Definitions

  • Embodiments of the present disclosure relate to the technical field of semiconductors, and in particular, to an epitaxial structure of a semiconductor device, a method for fabricating the same, and a semiconductor device.
  • the semiconductor material gallium nitride has the characteristics of large band gap, high electron mobility, high breakdown field strength, good thermal conductivity, and strong spontaneous and piezoelectric polarization effects.
  • the first-generation semiconductor materials and the second-generation semiconductor materials are more suitable for the manufacture of high-frequency, high-voltage and high-temperature-resistant high-power electronic devices, especially in the fields of radio frequency and power supply.
  • GaN-based optoelectronic devices and power devices there are thermal mismatches and lattice mismatches between the GaN epitaxial layer and the substrate.
  • the thermal mismatch stress and lattice mismatch strain caused during the epitaxial growth process will cause the epitaxial wafer to deform.
  • the uniformity of the epitaxial layer decreases, the yield of epitaxial products decreases, and the cost increases.
  • a nucleation layer is introduced between the GaN epitaxial layer and the substrate.
  • the existence of the nucleation layer will increase the overall thermal resistance of the epitaxial layer. Therefore, in order to alleviate this problem, most of the industry uses a thin nucleation layer, but the thin nucleation layer has the problem of poor crystal quality, and poor crystal quality will It affects the crystal quality of the subsequently grown GaN, which in turn affects the reliability of the final device.
  • the thin nucleation layer has the problem of poor crystal quality, and poor crystal quality will It affects the crystal quality of the subsequently grown GaN, which in turn affects the reliability of the final device.
  • it is inseparable from the semiconductor epitaxial structure with good crystal quality, good uniformity and low industrial cost as the basis to match the performance of semiconductor devices.
  • the High Electron Mobility Transistor (HEMT) formed by the AlGaN/GaN heterojunction is usually a depletion-mode device.
  • a high-resistance GaN buffer layer must be obtained first.
  • embodiments of the present disclosure provide an epitaxial structure of a semiconductor device, a method for fabricating the same, and a semiconductor device, so as to provide an epitaxial structure with good thermal resistance and crystal quality of a nucleation layer, and further provide a buffer layer with high thermal resistance.
  • An epitaxial structure with good resistance characteristics and crystal quality are provided.
  • embodiments of the present disclosure provide an epitaxial structure of a semiconductor device, including:
  • the epitaxial layer on one side of the substrate, the epitaxial layer comprising a nucleation layer on one side of the substrate and a buffer layer on the side of the nucleation layer away from the substrate;
  • the thickness of the buffer layer is inversely proportional to the thickness of the nucleation layer.
  • the thickness of the nucleation layer is h1, and the thickness of the buffer layer is h2;
  • h1 0.17/h2.
  • the thickness of the nucleation layer is h1, and the thickness of the substrate is h3;
  • the thickness of the nucleation layer is h1, and the thickness of the epitaxial layer is h4;
  • the thickness of the nucleation layer is h1, wherein 100nm ⁇ h1 ⁇ 150nm.
  • the epitaxial layer further includes:
  • the buffer layer includes a first-type buffer layer and a second-type buffer layer arranged in layers, the first-type buffer layer is located on a side close to the substrate, and the first-type buffer layer is The doping concentration of is greater than the doping concentration of the second type buffer layer.
  • the first type buffer layer includes at least one first buffer layer
  • the second type buffer layer includes at least one second buffer layer
  • the doping concentration of the first buffer layer is greater than the doping concentration of the second buffer layer.
  • the first type of buffer layer includes a first A buffer layer and a first B buffer layer arranged in layers, and the first A buffer layer is located on a side close to the substrate; the first A buffer layer is The doping concentration of the buffer layer is greater than or equal to the doping concentration of the first B buffer layer;
  • the second type of buffer layer includes a second A buffer layer and a second B buffer layer arranged in layers, the second A buffer layer is located on the side close to the substrate; the second A buffer layer is doped with The impurity concentration is greater than that of the second B buffer layer.
  • the first A buffer layer, the first B buffer layer, the second A buffer layer and the second B buffer layer are all doped with carbon ions;
  • the doping concentration of carbon ions in the first A buffer layer is a first doping concentration C1
  • the doping concentration of carbon ions in the first B buffer layer is a second doping concentration C2
  • the second A buffer The doping concentration of carbon ions in the layer is the third doping concentration C3, and the doping concentration of carbon ions in the second B buffer layer is the fourth doping concentration C4, wherein C1>C2 ⁇ C3>C4.
  • the first A buffer layer and the first B buffer layer are further doped with iron ions, and the second A buffer layer and the second B buffer layer are not doped with iron ions;
  • the doping concentration of iron ions in the first A buffer layer is the fifth doping concentration
  • the doping concentration of iron ions in the first B buffer layer is the sixth doping concentration, wherein the fifth doping concentration is the same as the The sixth doping concentration is the same.
  • the thickness of the first buffer layer is greater than the thickness of the second buffer layer.
  • the first type of buffer layer includes a first A buffer layer and a first B buffer layer arranged in layers, and the first A buffer layer is located on a side close to the substrate; the first A buffer layer is The thickness of the buffer layer is greater than or equal to the thickness of the first B buffer layer;
  • the second type of buffer layer includes a second A buffer layer and a second B buffer layer arranged in layers, and the second A buffer layer is located on the side close to the substrate; the thickness of the second A buffer layer is greater than the thickness of the second B buffer layer.
  • the thickness of the first A buffer layer is h1
  • the thickness of the first B buffer layer is h2
  • the thickness of the second A buffer layer is h3
  • the thickness of the second B buffer layer is h4;
  • h2 h1, 2/10 ⁇ h3/h2 ⁇ 9/10, 4/10 ⁇ h4/h3 ⁇ 9/10.
  • embodiments of the present disclosure further provide a semiconductor device, including the epitaxial structure described in the first aspect, where the epitaxial structure includes a substrate and a nucleation layer, a buffer layer, a nucleation layer, a buffer layer, Spacer layer, barrier layer and cap layer;
  • the semiconductor device further includes:
  • a gate electrode located on a side of the cap layer away from the substrate, the gate electrode being located between the source electrode and the drain electrode.
  • an embodiment of the present disclosure also provides a method for fabricating an epitaxial structure of a semiconductor device, including:
  • a barrier layer is prepared on the side of the spacer layer away from the substrate, and the barrier layer and the buffer layer form a heterojunction structure;
  • a capping layer is prepared on the side of the barrier layer away from the substrate,
  • the thickness of the buffer layer is inversely proportional to the thickness of the nucleation layer.
  • the nucleation layer in the epitaxial structure of the semiconductor device and the semiconductor device provided by the embodiments of the present disclosure, by setting the thickness of the nucleation layer to be inversely proportional to the thickness of the buffer layer, the nucleation can be improved without increasing the thermal resistance of the nucleation layer in the epitaxial structure.
  • the crystal quality of the layer is improved, thereby improving the quality of the epitaxial structure and the reliability of the semiconductor device.
  • the epitaxial structure of the semiconductor device provided by the embodiments of the present disclosure, the preparation method thereof, and the semiconductor device, by providing the buffer layer include the first-type buffer layer and the second-type buffer layer arranged in a stack, and the first-type buffer layer is provided at the same time.
  • the doping concentration is higher than the doping concentration of the second type of buffer layer, which ensures the high resistance characteristic of the buffer layer in the epitaxial structure and the good crystal quality of the buffer layer, thereby improving the quality of the epitaxial structure and the semiconductor device.
  • FIG. 1 is a schematic structural diagram of an epitaxial structure of a semiconductor device provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic flowchart of a method for fabricating an epitaxial structure of a semiconductor device provided by an embodiment of the present disclosure
  • FIG. 4 is a schematic flowchart of a method for fabricating a semiconductor device provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of an epitaxial structure of a semiconductor device provided by an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic flowchart of a method for fabricating an epitaxial structure of a semiconductor device provided by an embodiment of the present disclosure
  • FIG. 8 is a schematic flowchart of a method for fabricating a semiconductor device provided by an embodiment of the present disclosure.
  • the epitaxial structure of a semiconductor device provided by an embodiment of the present disclosure includes a substrate 11 , and an epitaxial structure located on one side of the substrate 11 layer 12; the epitaxial layer 12 includes a nucleation layer 121 on the side of the substrate 11 and a buffer layer 122 on the side of the nucleation layer 12 away from the substrate 11; wherein the thickness of the buffer layer 122 is equal to the thickness of the nucleation layer 121. inverse proportional relationship.
  • the substrate 11 may be one or more of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, and silicon.
  • gallium nitride aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, and silicon.
  • a combination of species, or any other material capable of growing group III nitrides, the specific type of the substrate 11 is not limited in this embodiment of the present disclosure.
  • the epitaxial layer 12 is located on one side of the substrate 11 , and the epitaxial layer 12 may specifically include a semiconductor material based on group III-V compounds.
  • the epitaxial layer 12 includes a nucleation layer 121 on the side close to the substrate 11 and a buffer layer 122 on the side of the nucleation layer 121 away from the substrate 11 .
  • the nucleation layer 121 affects parameters such as crystal quality, surface morphology and electrical properties of other film layers above the nucleation layer 121 in the epitaxial layer 12 ; the nucleation layer 121 mainly serves to match the material of the substrate 11 and the epitaxial layer 12 The role of semiconductor material layers in medium heterojunction structures.
  • the buffer layer 122 serves to bond the layer of semiconductor material to be grown next.
  • the material of the nucleation layer 121 may be aluminum nitride, and the material of the buffer layer 122 may be gallium nitride.
  • the existence of the AlN nucleation layer will increase the overall thermal resistance of the epitaxial layer 12, in order to alleviate this problem, most of the industry uses thin AlN as the AlN nucleation layer, but the thin AlN nucleation layer needs to obtain good crystal quality. The difficulty is very high. Increasing the thickness of the AlN nucleation layer is one of the ways to improve the crystal quality, but simply increasing the thickness of the AlN will lead to an increase in thermal resistance and affect device performance.
  • the embodiments of the present disclosure creatively set the thickness of the nucleation layer 121 in the epitaxial layer 12 to be inversely proportional to the thickness of the buffer layer 122.
  • the thickness of the nucleation layer 121 when the thickness of the nucleation layer 121 is increased, the thickness of the buffer layer 122 needs to be reduced at the same time. After the thickness of the nucleation layer 121 is thinned, the thickness of the buffer layer 122 needs to be increased. After a lot of verification, when the thickness of the nucleation layer 121 in the epitaxial layer 12 is inversely proportional to the thickness of the buffer layer 122, the crystal quality of the nucleation layer 121 can be improved without increasing the thermal resistance, ensuring that the nucleation layer is located in the nucleation layer. The crystal quality, surface morphology and electrical properties of other epitaxial layers above 121 are good, which ensures that the epitaxial structure and the overall quality of the semiconductor device are good and have high reliability.
  • the nucleation layer in the epitaxial structure of the semiconductor device provided by the embodiments of the present disclosure, by setting the thickness of the nucleation layer to be inversely proportional to the thickness of the buffer layer, the nucleation can be improved without increasing the thermal resistance of the nucleation layer in the epitaxial structure.
  • the crystal quality of the layer is improved, thereby improving the quality of the epitaxial structure and the semiconductor device.
  • the thickness of the nucleation layer 121 is h1, and the thickness of the buffer layer 122 is h2;
  • the thickness of the nucleation layer 121 in the epitaxial layer 12 is inversely proportional to the thickness of the buffer layer 122, and the thickness h1 of the nucleation layer 121 and the thickness h2 of the buffer layer 122 can be set to satisfy 0.1/h2 ⁇ h1 ⁇ 0.25/h2,
  • the thickness h1 of the nucleation layer 121 and the thickness h2 of the buffer layer 122 satisfy the above proportional relationship, the crystal quality of the nucleation layer 121 can be improved without increasing the thermal resistance of the nucleation layer 121, and the epitaxial structure and the semiconductor device can be guaranteed. of high reliability.
  • the thickness h1 of the layer 121 and the thickness h2 of the buffer layer 122 are sufficient to satisfy 0.1/h2 ⁇ h1 ⁇ 0.25/h2, so as to ensure that the thermal resistance of the nucleation layer 121 is not increased to improve the crystal quality of the nucleation layer 121, ensuring that Epitaxial structures and semiconductor devices have high reliability.
  • the thickness of the nucleation layer 121 is h1, and the thickness of the substrate is h3; wherein, 2* 10-5 ⁇ h1 /h3 ⁇ 5* 10-4 .
  • the thermal resistance of the nucleation layer 121 and the crystallinity of the nucleation layer 121 are guaranteed. In the case of good quality, it is ensured that the nucleation layer 121 can fully match the substrate 11, thereby further improving the reliability of the epitaxial structure and the semiconductor device.
  • the specific proportional relationship between the thickness h1 of the nucleation layer 121 and the thickness h3 of the substrate 11 is not limited, it only needs to ensure that the thickness h1 of the nucleation layer 121 and the thickness h3 of the substrate 11 satisfy 2*10 ⁇ 5 ⁇ h1/h3 ⁇ 5 *10 -4 is sufficient.
  • the thickness of the nucleation layer 121 is h1
  • the thickness of the epitaxial layer 12 is h4; wherein, 0.05 ⁇ h1/h4 ⁇ 0.3.
  • the thickness h1 of the nucleation layer 121 and the thickness h4 of the epitaxial layer 12 are guaranteed to be good, to ensure that the thickness of the nucleation layer 121 can match the overall thickness of the epitaxial layer 12, to ensure that other films in the epitaxial layer 12 except the nucleation layer 121 have a suitable thickness range, to ensure that the overall quality of the epitaxial layer 12 is good, and the epitaxial structure and semiconductor Device reliability is high.
  • the thickness h4 may satisfy 0.05 ⁇ h1/h4 ⁇ 0.3.
  • the thickness h1 of the nucleation layer 121 and the thickness h4 of the epitaxial layer 12 satisfy 0.07 ⁇ h1/h4 ⁇ 0.1, so as to ensure that the thermal resistance and crystal quality of the nucleation layer 121 are relatively better
  • the overall quality of the layer 12 further improves the reliability of the epitaxial structure and the semiconductor device.
  • the thickness of the nucleation layer 121 is h1 , where 100 nm ⁇ h1 ⁇ 150 nm.
  • the thickness h1 of the nucleation layer 121 is reasonably set to satisfy 100nm ⁇ h1 ⁇ 150nm, so as to ensure that the nucleation layer 121 has lower thermal resistance and good crystal quality.
  • the specific thickness is not limited, it only needs to ensure that the thickness h1 of the nucleation layer 121 satisfies 100nm ⁇ h1 ⁇ 150nm.
  • the epitaxial layer 12 provided by the embodiment of the present disclosure may further include a spacer layer 123 located on the side of the buffer layer 122 away from the substrate 11 ; the spacer layer 123 located away from the substrate 11
  • the barrier layer 124 on the substrate side, the barrier layer 124 and the buffer layer 122 form a heterojunction structure; the cap layer 125 is located on the side of the barrier layer 124 away from the substrate 11 .
  • the spacer layer 123 can be an AlN spacer layer, and the spacer layer 123 can raise the potential barrier, increase the confinement of the two-dimensional electron gas, reduce alloy scattering, and improve the mobility.
  • the barrier layer 124 may be an AlGaN barrier layer, and the barrier layer 124 and the buffer layer 122 together form a heterojunction structure to form a movement channel of the two-dimensional electron gas.
  • the main function of the cap layer 125 is to reduce the surface state, reduce the surface leakage of the subsequent semiconductor device, and suppress the current collapse, thereby improving the performance and reliability of the epitaxial structure and the semiconductor device.
  • the material of the cap layer 125 is group III nitride, preferably P-type doped gallium nitride (P-GaN).
  • P-GaN P-type doped gallium nitride
  • the P-GaN structure can effectively reduce the barrier height of the AlGaN layer.
  • an embodiment of the present disclosure further provides a semiconductor device, and the semiconductor device provided by the embodiment of the present disclosure includes the epitaxial structure of the semiconductor device described in the foregoing embodiments.
  • FIG. 2 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present disclosure. As shown in FIG. 2 , the semiconductor device provided by an embodiment of the present disclosure includes:
  • the gate electrode 133 is located on the side of the cap layer 125 away from the substrate 11 , and the gate electrode 133 is located between the source electrode 131 and the drain electrode 132 .
  • the source electrode 131 and the drain electrode 132 are located on the side of the barrier layer 124 away from the substrate 11, and the source electrode 131 and the drain electrode 132 respectively form ohmic contact with the barrier layer 124; the gate electrode 133 is located at the source electrode 131 and the drain electrode 132. Between the electrodes 132 and at the side of the cap layer 125 away from the substrate 11 , the gate 133 forms a Schottky contact with the cap layer 125 .
  • FIG. 3 is a schematic flowchart of a method for fabricating an epitaxial structure of a semiconductor device provided by an embodiment of the present disclosure, as shown in FIG. 3 .
  • the preparation method of the epitaxial structure of the semiconductor device provided by the embodiment of the present disclosure may include:
  • the material of the substrate may be one or more of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, and silicon. combination of species, or any other material capable of growing Group III nitrides.
  • the preparation method of the substrate can be atmospheric pressure chemical vapor deposition method, sub-atmospheric pressure chemical vapor deposition method, metal organic compound vapor deposition method, low pressure chemical vapor deposition method, high density plasma chemical vapor deposition method, ultra-high vacuum chemical vapor deposition method Deposition, Plasma Enhanced Chemical Vapor Deposition, Catalyst Chemical Vapor Deposition, Hybrid Physical Chemical Vapor Deposition, Rapid Thermal Chemical Vapor Deposition, Vapor Epitaxy, Pulsed Laser Deposition, Atomic Layer Epitaxy, Molecular Beam Epitaxy, Sputtering injection or evaporation.
  • the epitaxial layer includes a nucleation layer on the side of the substrate and a buffer layer on the side of the nucleation layer away from the substrate; wherein, the The thickness of the buffer layer is inversely proportional to the thickness of the nucleation layer.
  • the embodiments of the present disclosure creatively set the thickness of the nucleation layer in the epitaxial layer to be inversely proportional to the thickness of the buffer layer, so as to improve the crystal quality of the nucleation layer without increasing the thermal resistance, and ensure that other components located above the nucleation layer are The crystal quality, surface morphology and electrical properties of the epitaxial layer are good, ensuring that the epitaxial structure and the overall quality and reliability of the semiconductor device are good.
  • the method for preparing the epitaxial structure of the semiconductor device provided by the embodiments of the present disclosure, by setting the thickness of the nucleation layer to be inversely proportional to the thickness of the buffer layer, it is ensured that the thermal resistance of the nucleation layer in the epitaxial structure does not increase. Improve the crystal quality of the nucleation layer, thereby improving the quality of epitaxial structures and semiconductor devices.
  • an epitaxial layer is prepared on one side of the substrate, which may include:
  • a barrier layer is prepared on the side of the spacer layer away from the substrate, and the barrier layer and the buffer layer form a heterojunction structure;
  • a capping layer is prepared on the side of the barrier layer away from the substrate.
  • the potential barrier is raised by the spacer layer, the confinement of the two-dimensional electron gas is increased, the scattering of the alloy is reduced, and the mobility is improved.
  • a heterojunction structure is formed by the barrier layer and the buffer layer together, and the movement channel of the two-dimensional electron gas is formed.
  • the surface state is reduced by the cap layer, the surface leakage of the subsequent semiconductor device is reduced, and the current collapse is suppressed, thereby improving the performance and reliability of the epitaxial structure and the semiconductor device.
  • FIG. 4 is a schematic flowchart of a method for fabricating a semiconductor device provided by an embodiment of the present disclosure. As shown in FIG. 4 , the present disclosure implements The manufacturing method of the semiconductor device provided by the example may include:
  • S220 Prepare an epitaxial layer on one side of the substrate, where the epitaxial layer includes a nucleation layer, a buffer layer, a spacer layer, a potential barrier layer and a cap layer that are sequentially located on one side of the substrate.
  • the source electrode and the drain electrode respectively form ohmic contact with the barrier layer, and the gate electrode and the cap layer form Schottky contact.
  • FIG. 5 is a schematic structural diagram of an epitaxial structure of a semiconductor device provided by an embodiment of the present disclosure. As shown in FIG.
  • the epitaxial structure provided by an embodiment of the present disclosure includes a substrate 11 , an epitaxial layer 12 located on one side of the substrate 11 ,
  • the epitaxial layer 12 includes a buffer layer 122, the buffer layer 122 includes a first-type buffer layer 1221 and a second-type buffer layer 1222 arranged in layers, the first-type buffer layer 1221 is located on the side close to the substrate 11, and the first-type buffer layer 1221
  • the doping concentration of the layer 1221 is greater than the doping concentration of the second type buffer layer 1222 .
  • the epitaxial layer 12 is located on one side of the substrate 11 , and the epitaxial layer 12 may specifically include a semiconductor material based on group III-V compounds.
  • the epitaxial layer 12 includes a buffer layer 122, and the buffer layer 122 plays a role of bonding the semiconductor material layer to be grown next.
  • the buffer layer 122 includes a first-type buffer layer 1221 and a second-type buffer layer 1222 arranged in layers.
  • the materials of the first type buffer layer 1221 and the second type buffer layer 1222 may be the same, and preferably may be gallium nitride. Further, the thickness and doping of the first type buffer layer 1221 and the second type buffer layer 1222 may be different.
  • the buffer layer 122 is creatively arranged to include multiple buffer layers, for example, a first-type buffer layer 1221 and a second-type buffer layer 1222 are arranged in a stack, and the first-type buffer layer 1221 is located on the side close to the substrate 11 .
  • the high resistance buffer is realized through the specific doping concentration relationship between the first type buffer layer 1221 and the second type buffer layer 1222
  • the buffer layer can be set to be lightly doped, so that the reliability of the epitaxial structure and the semiconductor device can be improved on the premise that the leakage and breakdown performance of the semiconductor device are not deteriorated.
  • the buffer layer includes a first-type buffer layer and a second-type buffer layer arranged in layers, and the doping concentration of the first-type buffer layer is set higher than that of the second-type buffer layer.
  • the doping concentration of the buffer layer in the epitaxial structure ensures the high resistance characteristics of the buffer layer and the good crystal quality of the buffer layer; at the same time, the high resistance buffer layer is realized through the specific doping concentration relationship between the first type buffer layer and the second type buffer layer.
  • the buffer layer can be set to be lightly doped, so that the reliability of the epitaxial structure and the semiconductor device can be improved on the premise that the leakage and breakdown performance of the semiconductor device are not deteriorated.
  • the first type buffer layer 1221 may include at least one first buffer layer
  • the second type buffer layer 1222 may include at least one second buffer layer; the doping concentration of the first buffer layer is greater than that of the first buffer layer. The doping concentration of the second buffer layer.
  • the first type buffer layer 1221 may include one or more first buffer layers
  • the second type buffer layer 1222 may include one or more second buffer layers
  • the doping concentration of each first buffer layer is Both are greater than the doping concentration of the second buffer layer, which ensures the high resistance characteristics of the buffer layer and the good crystal quality of the buffer layer; at the same time, the buffer layer can be lightly doped, which can ensure that the leakage and breakdown performance of the semiconductor device are not stable. Improve the reliability of epitaxial structures and semiconductor devices under the premise of deterioration.
  • the first type buffer layer 1221 may include two layers of first buffer layers
  • the second type buffer layer 1222 may include two layers of second buffer layers.
  • the first type buffer layer 1221 includes two layers of first buffer layers. layer
  • the second type buffer layer 1222 includes two second buffer layers as an example for description. 5
  • the first type buffer layer 1221 includes a first A buffer layer 1221a and a first B buffer layer 1221b arranged in a stack, and the first A buffer layer 1221a is located on the side close to the substrate 11.
  • the doping concentration of the first A buffer layer 1221a is greater than or equal to the doping concentration of the first B buffer layer 1221b;
  • the second A buffer layer 1222a is located on the side close to the substrate 11; the doping concentration of the second A buffer layer 1222a is greater than the doping concentration of the second B buffer layer 1222b.
  • the buffer layer 122 may sequentially include a first A buffer layer 1221a, a first B buffer layer 1221b, a second A buffer layer 1222a, and a second B buffer layer 1222b from bottom to top.
  • the doping concentration of any one of the buffer layer 1221a and the first B buffer layer 1221b is greater than the doping concentration of any one of the second A buffer layer 1222a and the second B buffer layer 1222b, and the doping concentration of the first A buffer layer 1221a
  • the impurity concentration is greater than or equal to the doping concentration of the first B buffer layer 1221b
  • the doping concentration of the second A buffer layer 1222a is greater than the doping concentration of the second B buffer layer 1222b, so that the doping concentration of the lower buffer layer in the buffer layer 122
  • the impurity concentration is not less than the doping concentration of the upper buffer layer.
  • the doping concentrations of the first A buffer layer 1221a, the first B buffer layer 1221b, the second A buffer layer 1222a and the second B buffer layer 1222b gradually decrease in the direction away from the substrate.
  • the high-resistance buffer layer is realized through the specific doping concentration relationship in the buffer layer, and the specific doping concentration of the buffer layer is not required, so as to ensure the improvement of the epitaxial structure on the premise that the leakage and breakdown performance of the semiconductor device does not deteriorate. and the reliability of semiconductor devices.
  • the first A buffer layer 1221a, the first B buffer layer 1221b, the second A buffer layer 1222a and the second B buffer layer 1222b may all be doped with carbon ions; the first A buffer layer 1221a
  • the doping concentration of C1 is C1
  • the doping concentration of the first B buffer layer 1221b is C2
  • the doping concentration of the second A buffer layer 1222a is C3
  • the doping concentration of the second B buffer layer 1222b is C4; wherein, C1> C2 ⁇ C3>C4.
  • the doping concentration C1 of the first A buffer layer 1221a the doping concentration C2 of the first B buffer layer 1221b, the doping concentration C3 of the second A buffer layer 1222a, and the doping concentration of the second B buffer layer 1222b
  • the impurity concentration C4 satisfies C1>C2 ⁇ C3>C4, and it is ensured that the doping concentration of the buffer layer located in the lower layer in the buffer layer 122 is not less than the doping concentration of the buffer layer located in the upper layer.
  • the corresponding doping concentration relationship of the first B buffer layer 1221b, the second A buffer layer 1222a and the second B buffer layer 1222b can achieve the same function of the traditional high-resistance GaN buffer layer while ensuring that the crystal quality does not deteriorate.
  • the first A buffer layer 1221a and the first B buffer layer 1221b are also doped with iron ions, and the second A buffer layer 1222a and the second B buffer layer 1222b are not doped with iron ions;
  • the doping concentration of iron ions in the first buffer layer 1221a is the fifth doping concentration
  • the doping concentration of iron ions in the first B buffer layer 1221b is the sixth doping concentration, wherein the fifth doping concentration and the sixth doping concentration the same concentration.
  • the first A buffer layer 1221a and the first B buffer layer 1221b may also be doped with iron ions of the same concentration, and the second A buffer layer 1222a and the second B buffer layer 1222b are not doped with iron ions.
  • the doping composition in each buffer layer is set to ensure that the same effect of the traditional high-resistance GaN buffer layer is achieved while the crystal quality is not deteriorated.
  • the epitaxial structure and the semiconductor device are of good quality and high reliability.
  • the doping concentration of carbon ions in the first B buffer layer 1221b, the second A buffer layer 1222a and the second B buffer layer 1222b is directly or spaced from the doping concentration of carbon ions in the first A buffer layer 1221a is related, and the doping concentration of carbon ions in the first formazan buffer layer 1221a is related to the doping concentration of iron ions in the first formazan buffer layer 1221a.
  • the doping concentration of iron ions in the first formazan buffer layer 1221a changes, the The doping concentration of carbon ions in the first A buffer layer 1221a should also be adjusted accordingly, and the doping concentration of carbon ions in the first B buffer layer 1221b, the second A buffer layer 1222a and the second B buffer layer 1222b should also be adjusted accordingly.
  • the doping concentration of iron ions in the first A buffer layer 1221a is increased to twice the doping concentration
  • the doping concentration of carbon ions in the first A buffer layer 1221a should also be adjusted accordingly, while the first B buffer layer 1221b,
  • the doping concentrations of carbon ions in the second A buffer layer 1222a and the second B buffer layer 1222b are also adjusted accordingly.
  • the doping concentration C2 of carbon ions and the doping concentration C6 of iron ions in the first B-doped layer 1221b are different.
  • the doping concentration C4 of carbon ions in the second B-doped layer 1222b is equal to
  • the doping concentration of iron ions in the first A buffer layer 1221a and the doping concentration of iron ions in the first B buffer layer 1221b are both lightly doped, The crystal quality of each buffer layer is not affected, and the performance of the epitaxial structure and the semiconductor device is guaranteed to be stable.
  • the doping concentration C1 of carbon ions in the first formazan buffer layer 1221a may be 2*10 17 /cm 3
  • the doping concentration C5 of iron ions in the first formazan buffer layer 1221a may be 2*10 18 /cm 3
  • the doping concentration C2 of carbon ions in the first B buffer layer 1221b may be 5*10 16 /cm 3
  • the doping concentration C6 of iron ions in the first B buffer layer 1221b may be 2*10 18 /cm 3.
  • the doping concentration C3 of carbon ions in the second A buffer layer 1222a may be 5*10 16 /cm 3 , the doping concentration of iron ions in the second A buffer layer 1222a is 0, and the carbon ions in the second B buffer layer 1222b
  • the doping concentration C4 may be 2.5*10 16 /cm 3 , and the doping concentration of iron ions in the second B buffer layer 1222b is 0.
  • the above embodiment describes the doping situation in each buffer layer.
  • the doping concentration in each buffer layer reasonably, the high resistance characteristic of the buffer layer in the epitaxial structure can be ensured, and the crystal quality of the buffer layer can be ensured to be good.
  • the reliability of the epitaxial structure and the semiconductor device can be improved on the premise that the leakage and breakdown performance of the semiconductor device are not deteriorated.
  • the thickness of the first type buffer layer 1221 and the second type buffer layer 1222 will be described.
  • the thickness of the first buffer layer is greater than the thickness of the second buffer layer.
  • the first type buffer layer 1221 may include one or more first buffer layers
  • the second type buffer layer 1222 may include one or more second buffer layers
  • the thickness of each first buffer layer is greater than
  • the thickness of the second buffer layer can ensure the high resistance characteristics of the buffer layer and the good crystal quality of the buffer layer; at the same time, the buffer layer can be lightly doped, so as to ensure that the performance of the semiconductor device such as leakage and breakdown does not deteriorate. Improve the reliability of epitaxial structures and semiconductor devices.
  • the first type buffer layer 1221 may include two layers of first buffer layers
  • the second type buffer layer 1222 may include two layers of second buffer layers.
  • the first type buffer layer 1221 includes two layers of first buffer layers. layer
  • the second type buffer layer 1222 includes two second buffer layers as an example for description. 5
  • the first type buffer layer 1221 includes a first A buffer layer 1221a and a first B buffer layer 1221b arranged in a stack, and the first A buffer layer 1221a is located on the side close to the substrate 11.
  • the thickness of the first first buffer layer 1221a is greater than or equal to the thickness of the first buffer layer 1221b;
  • the layer 1222a is located on the side close to the substrate 11; the thickness of the second buffer layer 1222a is greater than the thickness of the second buffer layer 1222b.
  • the buffer layer 122 may sequentially include a first A buffer layer 1221a, a first B buffer layer 1221b, a second A buffer layer 1222a, and a second B buffer layer 1222b from bottom to top.
  • the thickness of any one of the buffer layer 1221a and the first B buffer layer 1221b is greater than the thickness of any one of the second A buffer layer 1222a and the second B buffer layer 1222b, and the thickness of the first A buffer layer 1221a is greater than or equal to the thickness of the second A buffer layer 1222a and the second B buffer layer 1222b.
  • the thickness of the first B buffer layer 1221b, the thickness of the second A buffer layer 1222a is greater than the thickness of the second B buffer layer 1222b, so the thickness of the lower buffer layer in the buffer layer 122 is not less than the thickness of the upper buffer layer.
  • the thickness of each buffer layer gradually decreases in the direction away from the substrate. That is, the thickness h1 of the first type A buffer layer is a preset thickness, and the thickness h of the other buffer layers is determined according to the thickness relationship of h1, and h ⁇ h1.
  • a high-resistance buffer layer is realized through a specific thickness relationship in the buffer layer, and the doping concentration of the buffer layer is not required, so as to ensure that the epitaxial structure and semiconductor device are improved on the premise that the leakage and breakdown performance of the semiconductor device are not deteriorated. reliability.
  • the thickness of the first A buffer layer 1221a is h1
  • the thickness of the first B buffer layer 1221b is h2
  • the thickness of the second A buffer layer 1222a is h3
  • the corresponding thickness ratio between the layers 1222b can achieve the same function of the traditional high-resistance GaN buffer layer while ensuring that the crystal quality is not deteriorated.
  • the thickness h1 of the first A buffer layer 1221a may be 500 nm
  • the thickness h2 of the first B buffer layer 1221b may be 500 nm
  • the thickness h3 of the second A buffer layer 1222a may be 400 nm
  • the thickness h3 of the second B buffer layer 1222a may be 400 nm
  • the thickness h4 of the buffer layer 1222b may be 300 nm.
  • each buffer layer By reasonably setting the thickness of each buffer layer, the high resistance characteristic of the buffer layer in the epitaxial structure can be ensured while the crystal quality of the buffer layer is good, and the leakage and shock of the semiconductor device can be ensured. The reliability of the epitaxial structure and the semiconductor device is improved on the premise that the wear and other properties are not deteriorated.
  • the above embodiments have respectively described the specific arrangement of the epitaxial layer from the two aspects of the doping concentration and the thickness of the different buffer layers. It can be understood that in the actual epitaxial layer setting, the doping concentration and thickness of different buffer layers can be comprehensively considered.
  • the buffer layer can be set to have a smaller doping concentration.
  • the epitaxial layer 12 provided by the embodiments of the present disclosure may further include a nucleation layer 121 located on the side of the buffer layer 122 close to the substrate 11 ; the buffer layer 122 located away from the substrate
  • the spacer layer 123 on the side of 11; the barrier layer 124 on the side of the spacer layer 123 away from the substrate 11, the barrier layer 124 and the buffer layer 122 form a heterojunction structure; the barrier layer 124 on the side away from the substrate 11 the cover layer 125.
  • the nucleation layer 121 affects parameters such as crystal quality, surface morphology and electrical properties of other film layers located above the nucleation layer 121 in the epitaxial layer 12; The role of the layer of semiconductor material in the heterojunction structure in layer 12.
  • the spacer layer 123 can be an AlN spacer layer, and the spacer layer 123 can raise the potential barrier, increase the confinement of the two-dimensional electron gas, reduce alloy scattering, and improve the mobility.
  • the barrier layer 124 may be an AlGaN barrier layer, and the barrier layer 124 and the buffer layer 122 together form a heterojunction structure to form a movement channel of the two-dimensional electron gas.
  • the main function of the capping layer 125 is to reduce the surface state, reduce the surface leakage of the subsequent semiconductor device, and suppress the current collapse, thereby improving the performance and reliability of the epitaxial structure and the semiconductor device.
  • the material of the cap layer 125 is group III nitride, preferably P-type doped gallium nitride (P-GaN).
  • P-GaN P-type doped gallium nitride
  • an embodiment of the present disclosure further provides a semiconductor device, and the semiconductor device provided by the embodiment of the present disclosure includes the epitaxial structure of the semiconductor device described in the foregoing embodiments.
  • FIG. 6 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present disclosure. As shown in FIG. 6 , the semiconductor device provided by an embodiment of the present disclosure includes:
  • the gate electrode 133 is located on the side of the cap layer 125 away from the substrate 11 , and the gate electrode 133 is located between the source electrode 131 and the drain electrode 132 .
  • the source electrode 131 and the drain electrode 132 are located on the side of the barrier layer 124 away from the substrate 11, and the source electrode 131 and the drain electrode 132 respectively form ohmic contact with the barrier layer 124; the gate electrode 133 is located at the source electrode 131 and the drain electrode 132. Between the electrodes 132 and at the side of the cap layer 125 away from the substrate 11 , the gate 133 forms a Schottky contact with the cap layer 125 .
  • Semiconductor devices include but are not limited to: high-power gallium nitride high-electron mobility transistors (High Electron Mobility Transistor, HEMT for short) operating in a high-voltage and high-current environment, silicon-on-insulator (Silicon-On-Insulator, referred to as SOI) structure transistors, gallium arsenide (GaAs)-based transistors and metal oxide semiconductor field effect transistors (Metal-Oxide-Semiconductor Field-Effect Transistor, referred to as MOSFET), metal insulating layer semiconductor field effect transistors (Metal-Semiconductor Field-Effect Transistor (MISFET), Double Heterojunction Field-Effect Transistor (DHFET), Junction Field-Effect Transistor (
  • an embodiment of the present disclosure also provides a method for fabricating an epitaxial structure of a semiconductor device.
  • FIG. 7 is a schematic flowchart of a method for fabricating an epitaxial structure of a semiconductor device provided by an embodiment of the present disclosure, as shown in FIG. 7 .
  • the preparation method of the epitaxial structure of the semiconductor device provided by the embodiment of the present disclosure may include:
  • the epitaxial layer includes a buffer layer
  • the buffer layer includes a first-type buffer layer and a second-type buffer layer arranged in layers, and the first-type buffer layer is located at A side close to the substrate, and the doping concentration of the first type buffer layer is greater than the doping concentration of the second type buffer layer.
  • the buffer layer 122 is creatively arranged to include multiple buffer layers, for example, a first-type buffer layer 1221 and a second-type buffer layer 1222 are arranged in a stack, and the first-type buffer layer 1221 is located on the side close to the substrate 11 .
  • the high resistance buffer is realized through the specific doping concentration relationship between the first type buffer layer 1221 and the second type buffer layer 1222
  • the specific doping concentration of the buffer layer is not required.
  • the buffer layer can be set to be lightly doped, which can ensure that the reliability of the epitaxial structure and the semiconductor device can be improved on the premise that the leakage and breakdown performance of the semiconductor device are not deteriorated. sex.
  • the method for fabricating the epitaxial structure of the semiconductor device includes setting the buffer layer including the first type buffer layer and the second type buffer layer arranged in a stack, and simultaneously setting the doping concentration of the first type buffer layer.
  • the doping concentration is greater than that of the second type of buffer layer, which ensures the high resistance characteristics of the buffer layer in the semiconductor device and the good crystal quality of the buffer layer; at the same time, the specific doping concentration relationship between the first type of buffer layer and the second type of buffer layer is achieved
  • the specific doping concentration of the buffer layer is not required.
  • the buffer layer can be set to be lightly doped, so as to ensure that the performance of the semiconductor device such as leakage and breakdown does not deteriorate. Improve the epitaxial structure and the reliability of semiconductor devices.
  • an epitaxial layer is prepared on one side of the substrate, which may include:
  • a barrier layer is prepared on the side of the spacer layer away from the substrate, and the barrier layer and the buffer layer form a heterojunction structure;
  • a capping layer is prepared on the side of the barrier layer away from the substrate.
  • the heterojunction structure is formed by the barrier layer and the buffer layer together to form the movement channel of the two-dimensional electron gas; the surface state is reduced by the cap layer, the surface leakage of subsequent semiconductor devices is reduced, and current collapse is suppressed, thereby improving the epitaxial structure and performance and reliability of semiconductor devices.
  • FIG. 8 is a schematic flowchart of a method for fabricating a semiconductor device provided by an embodiment of the present disclosure. As shown in FIG. 8 , the present disclosure implements The manufacturing method of the semiconductor device provided by the example may include:
  • S220 Prepare an epitaxial layer on one side of the substrate, where the epitaxial layer includes a nucleation layer, a buffer layer, a spacer layer, a potential barrier layer and a cap layer that are sequentially located on one side of the substrate.
  • the source electrode and the drain electrode respectively form ohmic contact with the barrier layer, and the gate electrode and the cap layer form Schottky contact.

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Abstract

本公开的实施例提供了一种半导体器件的外延结构及其制备方法，所述外延结构包括衬底；位于所述衬底一侧的外延层，所述外延层包括位于所述衬底一侧的成核层以及位于所述成核层远离所述衬底一侧的缓冲层，其中，所述缓冲层的厚度与所述成核层的厚度成反比例关系。采用上述技术方案，通过设置成核层的厚度与缓冲层的厚度成反比例关系，保证外延结构中成核层的热阻不变高的情况下提升成核层的晶体质量，进而提升外延结构的质量以及半导体器件的质量。

Description

半导体器件的外延结构及其制备方法 技术领域
本公开实施例涉及半导体技术领域，尤其涉及一种半导体器件的外延结构、其制备方法及半导体器件。
背景技术
半导体材料氮化镓(GaN)由于具有禁带宽度大、电子迁移率高、击穿场强高、导热性能好等特点，且具有很强的自发和压电极化效应，相较于第一代半导体材料和第二代半导体材料更适合于制造高频、高压和耐高温的大功率电子器件，尤其是在射频和电源领域优势明显。
目前制造GaN基光电器件与功率器件，GaN外延层与基底存在热失配和晶格失配，在外延生长过程中引起的热失配应力以及晶格失配应变会使得外延片发生形变，从而使得外延层均匀性下降，外延产品良率下降，成本提高。为此，在GaN外延层与基底之间引入了成核层。
但是成核层的存在会使外延层总体热阻变高，因此为了缓解这个问题业内多数采用的是薄的成核层，但是薄成核层又存在晶体质量差的问题，而晶体质量差会影响后续生长的GaN的晶体质量，进而影响最终器件的可靠性。目前，要制造电学性能优越，可靠性稳定的第三代半导体器件，都离不开晶体质量好，均匀性好，工业成本低的半导体外延结构作为基础匹配半导体器件的性能。
因此如何在热阻不变高的情况下获得晶体质量好，成本低的外延结构成为了目前亟需解决的问题。
另外，由于AlGaN/GaN异质结构中存在较强的二维电子气，通常采用AlGaN/GaN异质结形成的高电子迁移率晶体管(High Electron Mobility Transistor；HEMT)为耗尽型器件，为了使该器件获得更大的击穿电压、更好的开关特性以及更可靠的性能，则必须先获得高阻的GaN缓冲层。
要获得高阻的GaN缓冲层方法有多种，常用的方法是进行C掺杂或者Fe掺杂。但是为了获得足够高阻的GaN缓冲层所需的C含量会导致晶体质量变差，进而影响最终器件的可靠性，并且C杂质形成的深能级陷阱容易使最终器件的输出功率等性能衰减；而为了获得足够高阻的GaN缓冲层所需的Fe含量则会引起外延层表面和晶体质量变差，同时也会影响最终器件的性能。因此如何在保证外延层晶体质量的同时又能保证最终器件的性能成为了目前亟需解决的问题。
发明内容
有鉴于此，本公开实施例提供一种半导体器件的外延结构、其制备方法及半导体器件，以提供一种成核层热阻情况以及晶体质量均良好的外延结构，进而提供一种缓冲层高阻特性以及晶体质量均良好的外延结构。
第一方面，本公开实施例提供了一种半导体器件的外延结构，包括：
衬底；
位于所述衬底一侧的外延层，所述外延层包括位于所述衬底一侧的成核层以及位于所述成核层远离所述衬底一侧的缓冲层；
其中，所述缓冲层的厚度与所述成核层的厚度成反比例关系。
可选的，所述成核层的厚度为h1，所述缓冲层的厚度为h2；
其中，0.1/h2≤h1≤0.25/h2。
可选的，h1＝0.17/h2。
可选的，所述成核层的厚度为h1，所述衬底的厚度为h3；
其中，2*10 -5≤h1/h3≤5*10 -4。
可选的，所述成核层的厚度为h1，所述外延层的厚度为h4；
其中，0.05≤h1/h4≤0.3。
可选的，0.07≤h1/h4≤0.1。
可选的，所述成核层的厚度为h1，其中，100nm≤h1≤150nm。
可选的，所述外延层还包括：
位于所述缓冲层远离所述衬底一侧的间隔层；
位于所述间隔层远离所述衬底基板一侧的势垒层，所述势垒层与所述缓冲层形成异质结结构；
位于所述势垒层远离所述衬底一侧的盖层。
可选的，所述缓冲层包括叠层设置的第一类缓冲层和第二类缓冲层，所述第一类缓冲层位于靠近所述衬底的一侧，且所述第一类缓冲层的掺杂浓度大于所述第二类缓冲层的掺杂浓度。
可选的，所述第一类缓冲层包括至少一层第一缓冲层，所述第二类缓冲层包括至少一层第二缓冲层；
所述第一缓冲层的掺杂浓度大于所述第二缓冲层的掺杂浓度。
可选的，所述第一类缓冲层包括叠层设置的第一甲缓冲层和第 一乙缓冲层，所述第一甲缓冲层位于靠近所述衬底的一侧；所述第一甲缓冲层的掺杂浓度大于或者等于所述第一乙缓冲层的掺杂浓度；
所述第二类缓冲层包括叠层设置的第二甲缓冲层和第二乙缓冲层，所述第二甲缓冲层位于靠近所述衬底的一侧；所述第二甲缓冲层的掺杂浓度大于所述第二乙缓冲层的掺杂浓度。
可选的，所述第一甲缓冲层、所述第一乙缓冲层、所述第二甲缓冲层和所述第二乙缓冲层中均掺杂有碳离子；
所述第一甲缓冲层中碳离子的掺杂浓度为第一掺杂浓度C1，所述第一乙缓冲层中碳离子的掺杂浓度为第二掺杂浓度C2，所述第二甲缓冲层中碳离子的掺杂浓度为第三掺杂浓度C3，所述第二乙缓冲层中碳离子的掺杂浓度为第四掺杂浓度C4，其中，C1＞C2≥C3＞C4。
可选的，所述第一甲缓冲层和所述第一乙缓冲层中还掺杂有铁离子，所述第二甲缓冲层和所述第二乙缓冲层中不掺杂铁离子；
所述第一甲缓冲层中铁离子的掺杂浓度为第五掺杂浓度，所述第一乙缓冲层中铁离子的掺杂浓度为第六掺杂浓度，其中，所述第五掺杂浓度与所述第六掺杂浓度相同。
可选的，所述第一甲缓冲层中碳离子的掺杂浓度为第一掺杂浓度C1，所述第五掺杂浓度C5，其中，C1/C5＝(0.5～1.2)/10；
所述第一乙缓冲层中碳离子的掺杂浓度为第二掺杂浓度C2，所述第六掺杂浓度C6，其中C2/C6＝(0.1～0.3)/10；
所述第二甲缓冲层中碳离子的掺杂浓度为第三掺杂浓度C3，其中，C3＝C2；
所述第二乙缓冲层中碳离子的掺杂浓度为第四掺杂浓度C4，其中，C4/C3＝(1～2)/10。
可选的，所述第一缓冲层的厚度大于所述第二缓冲层的厚度。
可选的，所述第一类缓冲层包括叠层设置的第一甲缓冲层和第一乙缓冲层，所述第一甲缓冲层位于靠近所述衬底的一侧；所述第一甲缓冲层的厚度大于或者等于所述第一乙缓冲层的厚度；
所述第二类缓冲层包括叠层设置的第二甲缓冲层和第二乙缓冲层，所述第二甲缓冲层位于靠近所述衬底的一侧；所述第二甲缓冲层的厚度大于所述第二乙缓冲层的厚度。
可选的，所述第一甲缓冲层的厚度为h1，所述第一乙缓冲层的厚度为h2，所述第二甲缓冲层的厚度为h3，所述第二乙缓冲层的厚度为h4；
其中，h2＝h1，2/10≤h3/h2≤9/10，4/10≤h4/h3≤9/10。
第二方面，本公开实施例还提供了一种半导体器件，包括第一方面所述的外延结构，所述外延结构包括衬底以及依次位于所述衬底一侧的成核层、缓冲层、间隔层、势垒层以及帽层；
所述半导体器件还包括：
位于所述势垒层远离所述衬底一侧的源极和漏极：
位于所述盖层远离所述衬底一侧的栅极，所述栅极位于所述源极和所述漏极之间。
第三方面，本公开实施例还提供了一种半导体器件的外延结构的制备方法，包括：
提供衬底；
在所述衬底一侧制备成核层；
在所述成核层远离所述衬底的一侧制备缓冲层；
在所述缓冲层远离所述衬底的一侧制备间隔层；
在所述间隔层远离所述衬底的一侧制备势垒层，所述势垒层与所述缓冲层形成异质结结构；
在所述势垒层远离所述衬底的一侧制备盖层，
其中，所述缓冲层的厚度与所述成核层的厚度成反比例关系。
本公开实施例提供的半导体器件的外延结构及半导体器件，通过设置成核层的厚度与缓冲层的厚度成反比例关系，保证外延结构中成核层的热阻不变高的情况下提升成核层的晶体质量，进而提升外延结构的质量以及半导体器件的可靠性。
另外，本公开实施例提供的半导体器件的外延结构及其制备方法、半导体器件，通过设置缓冲层包括叠层设置的第一类缓冲层和第二类缓冲层，同时设置第一类缓冲层的掺杂浓度大于第二类缓冲层的掺杂浓度，保证外延结构中缓冲层的高阻特性的同时保证缓冲层的晶体质量良好，进而提升外延结构以及半导体器件的质量。
附图说明
图1是本公开实施例提供的一种半导体器件的外延结构的结构示意图；
图2是本公开实施例提供的一种半导体器件的结构示意图；
图3是本公开实施例提供的一种半导体器件的外延结构的制备方法的流程示意图；
图4是本公开实施例提供的一种半导体器件的制备方法的流程示意图。
图5是本公开实施例提供的一种半导体器件的外延结构的结构示意图；
图6是本公开实施例提供的一种半导体器件的结构示意图；
图7是本公开实施例提供的一种半导体器件的外延结构的制备方法的流程示意图；
图8是本公开实施例提供的一种半导体器件的制备方法的流程示意图。
具体实施方式
下面结合附图和实施例对本公开作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释本公开，而非对本公开的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本公开相关的部分而非全部结构。
图1是本公开实施例提供的一种半导体器件的外延结构的结构示意图，如图1所示，本公开实施例提供的半导体器件的外延结构包括衬底11，位于衬底11一侧的外延层12；外延层12包括位于衬底11一侧的成核层121以及位于成核层12远离衬底11一侧的缓冲层122；其中，缓冲层122的厚度与成核层121的厚度成反比例关系。
示例性的，衬底11可以是氮化镓、铝镓氮、铟镓氮、铝铟镓氮、磷化铟、砷化镓、碳化硅、金刚石、蓝宝石、锗、硅中的一种或多种的组合，或任何其他能够生长III族氮化物的材料，本公开实施例对衬底11的具体类型不进行限定。
外延层12位于衬底11一侧，外延层12具体可以包括基于III- V族化合物的半导体材料。
具体的，外延层12包括靠近衬底11一侧的成核层121以及位于成核层121远离衬底11一侧的缓冲层122。其中，成核层121影响外延层12中位于成核层121上方的其他膜层的晶体质量、表面形貌以及电学性质等参数；成核层121主要起到匹配衬底11材料和外延层12中异质结结构中的半导体材料层的作用。缓冲层122起到粘合接下来需要生长的半导体材料层的作用。
进一步的，成核层121的材料可以为氮化铝，缓冲层122的材料可以为氮化镓。
由于AlN成核层的存在会使外延层12总体热阻变高，因此为了缓解这个问题业内多数采用的是薄的AlN作为AlN成核层，但薄的AlN成核层要获得好的晶体质量难度非常高。通过增加AlN成核层厚度则是实现晶体质量提升的方法之一，但如果只是单纯的增加AlN厚度会导致热阻升高，影响器件性能。本公开实施例创造性地设置外延层12中成核层121的厚度和缓冲层122的厚度成反比例关系，即当增加成核层121的厚度后，需要同时减薄缓冲层122的厚度，当减薄成核层121的厚度后，需要增加缓冲层122的厚度。经过大量验证，当外延层12中成核层121的厚度和缓冲层122的厚度成反比例关系时可以实现在热阻不变高的情况下提升成核层121的晶体质量，保证位于成核层121上方的其他外延层的晶体质量、表面形貌以及电学性质良好，保证外延结构以及半导体器件整体质量良好，可靠性高。
综上，本公开实施例提供的半导体器件的外延结构，通过设置成核层的厚度与缓冲层的厚度成反比例关系，保证外延结构中成核 层的热阻不变高的情况下提升成核层的晶体质量，进而提升外延结构以及半导体器件的质量。
在上述实施例的基础上，成核层121的厚度为h1，缓冲层122的厚度为h2；
其中，0.1/h2≤h1≤0.25/h2。
示例性的，外延层12中成核层121的厚度和缓冲层122的厚度成反比例关系可以设置成核层121的厚度h1和缓冲层122的厚度h2满足0.1/h2≤h1≤0.25/h2，当成核层121的厚度h1和缓冲层122的厚度h2满足上述比例关系时，能够保证成核层121的热阻不变高的情况下提升成核层121的晶体质量，保证外延结构以及半导体器件的可靠性高。
具体的，成核层121的厚度h1和缓冲层122的厚度h2满足0.1/h2≤h1≤0.25/h2，可以是h1＝0.1/h2、或者是h1＝0.15/h2、或者是h1＝0.17/h2、或者是h1＝0.2/h2、或者是h1＝0.25/h2，本公开实施例对成核层121的厚度h1和缓冲层122的厚度h2的具体比例关系不进行限定，只需保证成核层121的厚度h1和缓冲层122的厚度h2满足0.1/h2≤h1≤0.25/h2即可，如此保证成核层121的热阻不变高的情况下提升成核层121的晶体质量，保证外延结构以及半导体器件的可靠性高。
在上述实施例的基础上，优选的，成核层121的厚度h1和缓冲层122的厚度h2可以满足h1＝0.17/h2，如此保证成核层121的热阻情况以及晶体质量情况处于最佳平衡状态，保证实现在成核层121热阻不变高的情况下成核层121的晶体质量最佳，或者保证实现在成核层121晶体质量良好的情况下热阻最小，保证成核层121 的质量最佳，进而保证外延结构以及半导体器件的整体可靠性最佳。
可选的，成核层121的厚度为h1，衬底的厚度为h3；其中，2*10 -5≤h1/h3≤5*10 -4。
示例性的，通过合理设置成核层121的厚度h1与衬底11的厚度h3满足2*10 -5≤h1/h3≤5*10 -4，在保证成核层121的热阻情况以及晶体质量均较好的情况下，保证成核层121可以充分匹配衬底11，进一步提升外延结构以及半导体器件的可靠性。
具体的，成核层121的厚度h1与衬底11的厚度h3满足2*10 - 5≤h1/h3≤5*10 -4，可以是h1/h3＝2*10 -5、或者是h1/h3＝5*10 -5、或者是h1/h3＝1*10 -4、或者是h1/h3＝3*10 -4、或者是h1/h3＝5*10 - 4，本公开实施例对成核层121的厚度h1和衬底11的厚度h3的具体比例关系不进行限定，只需保证成核层121的厚度h1与衬底11的厚度h3满足2*10 -5≤h1/h3≤5*10 -4即可。
可选的，成核层121的厚度为h1，外延层12的厚度为h4；其中，0.05≤h1/h4≤0.3。
示例性的，通过合理设置成核层121的厚度h1与外延层12的厚度h4满足0.05≤h1/h4≤0.3，在保证成核层121的热阻情况以及晶体质量均较好的情况下，保证成核层121的厚度可以匹配外延层12的整体厚度，保证外延层12中除成核层121之外的其他膜层具备合适的厚度范围，保证外延层12整体质量良好，外延结构以及半导体器件可靠性高。
具体的，成核层121的厚度h1与外延层12的厚度h4满足0.05≤h1/h4≤0.3，可以是h1/h4＝0.05、或者是h1/h4＝0.1、或者是h1/h4＝0.2、或者是h1/h4＝0.3，本公开实施例对成核层121的厚 度h1和外延层12的厚度h4的具体比例关系不进行限定，只需保证成核层121的厚度h1与外延层12的厚度h4满足0.05≤h1/h4≤0.3即可。
在上述实施例的基础上，优选的，成核层121的厚度h1和外延层12的厚度h4满足0.07≤h1/h4≤0.1，如此保证成核层121的热阻情况以及晶体质量情况均较好的情况下，保证实现在成核层121的厚度可以完美匹配外延层12的整体厚度，进一步保证外延层12中除成核层121之外的其他膜层具备合适的厚度范围，进一步提升外延层12整体质量，进一步提升外延结构以及半导体器件可靠性。
可选的，当衬底的厚度h3在400μm至600μm之间时，成核层121的厚度为h1，其中，100nm≤h1≤150nm。
示例性的，合理设置成核层121的厚度h1满足100nm≤h1≤150nm，保证成核层121即具备较小的热阻，同时具备良好的晶体质量。
具体的，成核层121的厚度h1满足100nm≤h1≤150nm，可以是h1＝100nm、或者是h1＝110nm、或者是h1＝130nm、或者是h1＝150nm，本公开实施例对成核层121的具体厚度不进行限定，只需保证成核层121的厚度h1满足100nm≤h1≤150nm即可。
在上述实施例的基础上，继续参考图1所示，本公开实施例提供的外延层12还可以包括位于缓冲层122远离衬底11一侧的间隔层123；位于间隔层123远离衬底11基板一侧的势垒层124，势垒层124与缓冲层122形成异质结结构；位于势垒层124远离衬底11一侧的盖层125。
示例性的，间隔层123可以为AlN间隔层，间隔层123可以抬高势垒，增加二维电子气的限域性，同时减小合金散射，提升迁移率。
势垒层124可以为AlGaN势垒层，势垒层124与缓冲层122一起形成异质结结构，形成二维电子气的运动沟道。
盖层125的主要作用是减小表面态，减小后续半导体器件的表面漏电，抑制电流崩塌，从而提升外延结构以及半导体器件的性能和可靠性。可选的，盖层125的材料为III族氮化物，优选为P型掺杂氮化镓(P-GaN)，P-GaN结构能够有效降低AlGaN层的势垒高度。
基于同样的发明构思，本公开实施例还提供了一种半导体器件，本公开实施例提供的半导体器件包括上述实施例所述的半导体器件的外延结构。进一步的，图2是本公开实施例提供的一种半导体器件的结构示意图，如图2所示，本公开实施例提供的半导体器件包括：
衬底11；
位于衬底11一侧的外延层12，外延层12包括依次位于衬底11一侧的成核层121、缓冲层122、间隔层123、势垒层124以及帽层125；
位于势垒层124远离衬底11一侧的源极131和漏极132；
位于帽层125远离衬底11一侧的栅极133，栅极133位于源极131和漏极132之间。
示例性的，源极131和漏极132位于势垒层124远离衬底11的一侧，源极131和漏极132分别与势垒层124形成欧姆接触；栅极 133位于源极131和漏极132之间，同时位于盖层125远离衬底11的一侧，栅极133与盖层125形成肖特基接触。
基于同一发明构思，本公开实施例还提供了一种半导体器件的外延结构的制备方法，图3是本公开实施例提供的一种半导体器件的外延结构的制备方法的流程示意图，如图3所示，本公开实施例提供的半导体器件的外延结构的制备方法可以包括：
S110、提供衬底。
示例性的，衬底的材料可以氮化镓、铝镓氮、铟镓氮、铝铟镓氮、磷化铟、砷化镓、碳化硅、金刚石、蓝宝石、锗、硅中的一种或多种的组合，或任何其他能够生长III族氮化物的材料。衬底的制备方法可以是常压化学气相沉积法、亚常压化学气相沉积法、金属有机化合物气相沉淀法、低压力化学气相沉积法、高密度等离子体化学气相沉积法、超高真空化学气相沉积法、等离子体增强化学气相沉积法、触媒化学气相沉积法、混合物理化学气相沉积法、快速热化学气相沉积法、气相外延法、脉冲激光沉积法、原子层外延法、分子束外延法、溅射法或蒸发法。
S120、在所述衬底一侧制备外延层，所述外延层包括位于所述衬底一侧的成核层以及位于所述成核层远离所述衬底一侧的缓冲层；其中，所述缓冲层的厚度与所述成核层的厚度成反比例关系。
由于成核层的存在会使外延层总体热阻变高，但薄的AlN成核层要获得好的晶体质量难度非常高，而单纯的增加AlN厚度会导致热阻升高，影响器件性能。本公开实施例创造性的设置外延层中成核层的厚度和缓冲层的厚度成反比例关系，实现在热阻不变高的情况下提升成核层的晶体质量，保证位于成核层上方的其他外延层的 晶体质量、表面形貌以及电学性质良好，保证外延结构以及半导体器件整体质量良好，可靠性好。
综上，本公开实施例提供的半导体器件的外延结构的制备方法，通过设置成核层的厚度与缓冲层的厚度成反比例关系，保证外延结构中成核层的热阻不变高的情况下提升成核层的晶体质量，进而提升外延结构以及半导体器件的质量。
在上述实施的基础上，在衬底一侧制备外延层，可以包括：
在衬底一侧制备成核层；
在成核层远离衬底的一侧制备缓冲层；
在缓冲层远离衬底的一侧制备间隔层；
在间隔层远离衬底的一侧制备势垒层，述势垒层与缓冲层形成异质结结构；
在势垒层远离衬底的一侧制备盖层。
通过间隔层抬高势垒，增加二维电子气的限域性，同时减小合金散射，提升迁移率。通过势垒层与缓冲层一起形成异质结结构，形成二维电子气的运动沟道。通过盖层减小表面态，减小后续半导体器件的表面漏电，抑制电流崩塌，从而提升外延结构以及半导体器件的性能和可靠性。
基于同样的发明构思，本公开实施例还提供了一种半导体器件的制备方法，图4是本公开实施例提供的一种半导体器件的制备方法的流程示意图，如图4所示，本公开实施例提供的半导体器件的制备方法可以包括：
S210、提供衬底。
S220、在所述衬底一侧制备外延层，所述外延层包括依次位于 所述衬底一侧的成核层、缓冲层、间隔层、势垒层和帽层。
S230、在所述势垒层远离所述衬底的一侧制备源极和漏极；在所述帽层远离所述衬底的一侧制备栅极，所述栅极位于所述源极和所述漏极之间。
源极和漏极分别与势垒层形成欧姆接触，栅极与盖层形成肖特基接触。
为了进一步提高外延结构的质量，提高外延结构使用可靠性，对半导体外延结构进一步优化。图5是本公开实施例提供的一种半导体器件的外延结构的结构示意图，如图5所示，本公开实施例提供的外延结构包括衬底11，位于衬底11一侧的外延层12，外延层12包括缓冲层122，缓冲层122包括叠层设置的第一类缓冲层1221和第二类缓冲层1222，第一类缓冲层1221位于靠近衬底11的一侧，且第一类缓冲层1221的掺杂浓度大于第二类缓冲层1222的掺杂浓度。
外延层12位于衬底11一侧，外延层12具体可以包括基于III-V族化合物的半导体材料。
具体的，外延层12包括缓冲层122，缓冲层122起到粘合接下来需要生长的半导体材料层的作用。
缓冲层122包括叠层设置的第一类缓冲层1221和第二类缓冲层1222，第一类缓冲层1221位于靠近衬底11的一侧，第二类缓冲层1222位于远离衬底11的一侧，第一类缓冲层1221和第二类缓冲层1222的材料可以相同，优选可以为氮化镓。进一步的，第一类缓冲层1221和第二类缓冲层1222的厚度和掺杂可以不同。
首先对第一类缓冲层1221和第二类缓冲层1222的掺杂情况进 行说明。
由于获得高阻GaN缓冲层所需的C掺杂浓度需要满足>1*10 19/cm 3，如此会导致GaN缓冲层晶体质量变差；而获得高阻GaN缓冲层所需的Fe掺杂浓度需要满足>1*10 19/cm 3，如此会影响最终器件的性能。本公开实施例创造性地设置缓冲层122包括多层缓冲层，例如包括叠层设置的第一类缓冲层1221和第二类缓冲层1222，第一类缓冲层1221位于靠近衬底11的一侧，同时设置第一类缓冲层1221的掺杂浓度大于第二类缓冲层1222的掺杂浓度，通过第一类缓冲层1221和第二类缓冲层1222特定的掺杂浓度关系来实现高阻缓冲层，例如可以设置缓冲层为轻掺杂，如此可以保证在半导体器件漏电和击穿等性能不变差的前提下提升外延结构以及半导体器件的可靠性。
综上，本公开实施例提供的外延结构，通过设置缓冲层包括叠层设置的第一类缓冲层和第二类缓冲层，同时设置第一类缓冲层的掺杂浓度大于第二类缓冲层的掺杂浓度，保证外延结构中缓冲层的高阻特性的同时保证缓冲层的晶体质量良好；同时通过第一类缓冲层和第二类缓冲层特定的掺杂浓度关系来实现高阻缓冲层，例如可以设置缓冲层为轻掺杂，如此可以保证在半导体器件漏电和击穿等性能不变差的前提下提升外延结构以及半导体器件的可靠性。
在上述实施例的基础上，第一类缓冲层1221可以包括至少一层第一缓冲层，第二类缓冲层1222可以包括至少一层第二缓冲层；第一缓冲层的掺杂浓度大于第二缓冲层的掺杂浓度。
示例性的，第一类缓冲层1221可以包括一层或者多层第一缓冲层，第二类缓冲层1222可以包括一层或者多层第二缓冲层，每层 第一缓冲层的掺杂浓度均大于第二缓冲层的掺杂浓度，保证缓冲层的高阻特性的同时保证缓冲层的晶体质量良好；同时缓冲层可以为轻掺杂，如此可以保证在半导体器件漏电和击穿等性能不变差的前提下提升外延结构以及半导体器件的可靠性。
具体的，第一类缓冲层1221可以包括两层第一缓冲层，第二类缓冲层1222可以包括两层第二缓冲层，本公开实施例以第一类缓冲层1221包括两层第一缓冲层，第二类缓冲层1222包括两层第二缓冲层为例进行说明。示例性的，继续参考图5所示，第一类缓冲层1221包括叠层设置的第一甲缓冲层1221a和第一乙缓冲层1221b，第一甲缓冲层1221a位于靠近衬底11的一侧；第一甲缓冲层1221a的掺杂浓度大于或者等于第一乙缓冲层1221b的掺杂浓度；第二类缓冲层1222包括叠层设置的第二甲缓冲层1222a和第二乙缓冲层1222b，第二甲缓冲层1222a位于靠近衬底11的一侧；第二甲缓冲层1222a的掺杂浓度大于第二乙缓冲层1222b的掺杂浓度。
示例性的，如图5所示，缓冲层122从下至上可以依次包括第一甲缓冲层1221a、第一乙缓冲层1221b、第二甲缓冲层1222a和第二乙缓冲层1222b，第一甲缓冲层1221a和第一乙缓冲层1221b中任意一层的掺杂浓度大于第二甲缓冲层1222a和第二乙缓冲层1222b中任意一层的掺杂浓度，且第一甲缓冲层1221a的掺杂浓度大于或者等于第一乙缓冲层1221b的掺杂浓度，第二甲缓冲层1222a的掺杂浓度大于第二乙缓冲层1222b的掺杂浓度，如此缓冲层122中位于下层的缓冲层的掺杂浓度均不小于位于上层的缓冲层的掺杂浓度。进一步的，第一甲缓冲层1221a、第一乙缓冲层1221b、第二甲缓冲层1222a和第二乙缓冲层1222b在远离衬底的方向上四层 缓冲层的掺杂浓度逐渐减小。如此通过缓冲层中特定的掺杂浓度关系来实现高阻缓冲层，而对缓冲层的具体掺杂浓度不做要求，保证在半导体器件漏电和击穿等性能不变差的前提下提升外延结构以及半导体器件的可靠性。
在上述实施例的基础上，第一甲缓冲层1221a、第一乙缓冲层1221b、第二甲缓冲层1222a和第二乙缓冲层1222b中可以均掺杂有碳离子；第一甲缓冲层1221a的掺杂浓度为C1，第一乙缓冲层1221b的掺杂浓度为C2，第二甲缓冲层1222a的掺杂浓度为C3，第二乙缓冲层1222b的掺杂浓度为C4；其中，C1＞C2≥C3＞C4。
示例性的，通过设置第一甲缓冲层1221a的掺杂浓度C1、第一乙缓冲层1221b的掺杂浓度C2，第二甲缓冲层1222a的掺杂浓度C3以及第二乙缓冲层1222b的掺杂浓度C4满足C1＞C2≥C3＞C4，保证缓冲层122中位于下层的缓冲层的掺杂浓度均不小于位于上层的缓冲层的掺杂浓度，通过合理设置第一甲缓冲层1221a、第一乙缓冲层1221b、第二甲缓冲层1222a以及第二乙缓冲层1222b相应的掺杂浓度关系，可以在实现传统高阻GaN缓冲层相同作用的同时保证晶体质量不变差。
在上述实施例的基础上，第一甲缓冲层1221a和第一乙缓冲层1221b中还掺杂有铁离子，第二甲缓冲层1222a和第二乙缓冲层1222b中不掺杂铁离子；第一甲缓冲层中1221a铁离子的掺杂浓度为第五掺杂浓度，第一乙缓冲层1221b中铁离子的掺杂浓度为第六掺杂浓度，其中，第五掺杂浓度与第六掺杂浓度相同。
示例性的，第一甲缓冲层1221a和第一乙缓冲层1221b中还可以掺杂有相同浓度铁离子，第二甲缓冲层1222a和第二乙缓冲层 1222b中不掺杂铁离子，通过合理设置各个缓冲层中的掺杂成分，保证在实现传统高阻GaN缓冲层相同作用的同时保证晶体质量不变差。
进一步的，第一甲缓冲层1221a中碳离子的掺杂浓度为第一掺杂浓度C1，第五掺杂浓度C5，其中，C1/C5＝(0.5～1.2)/10；第一乙缓冲层1221b中碳离子的掺杂浓度为第二掺杂浓度C2，第六掺杂浓度C6，其中C2/C6＝(0.1～0.3)/10；第二甲缓冲层1222a中碳离子的掺杂浓度为第三掺杂浓度C3，其中，C3＝C2；第二乙缓冲层1222b中碳离子的掺杂浓度为第四掺杂浓度C4，其中，C4/C3＝(1～2)/10。通过合理设置同一缓冲层中碳离子和铁离子的掺杂比例，同时设置不同缓冲层中碳离子的掺杂比例，保证最终可以好的高阻的缓冲层，且缓冲层的晶体质量良好，保证外延结构以及半导体器件的质量良好，可靠性高。
进一步的，由于第一乙缓冲层1221b、第二甲缓冲层1222a以及第二乙缓冲层1222b中的碳离子的掺杂浓度均直接或者间距与第一甲缓冲层1221a中碳离子的掺杂浓度相关，且第一甲缓冲层1221a中碳离子的掺杂浓度与第一甲缓冲层1221a中铁离子的掺杂浓度相关，因此当第一甲缓冲层1221a中铁离子的掺杂浓度发生变化后，第一甲缓冲层1221a中碳离子的掺杂浓度也要相应调整，同时第一乙缓冲层1221b、第二甲缓冲层1222a以及第二乙缓冲层1222b中的碳离子的掺杂浓度也要相应调整。例如当第一甲缓冲层1221a中铁离子的掺杂浓度增大至两倍掺杂浓度时，第一甲缓冲层1221a中碳离子的掺杂浓度也要相应调整，同时第一乙缓冲层1221b、第二甲缓冲层1222a以及第二乙缓冲层1222b中的碳离子的掺杂浓度也 要相应调整。
具体的，第一甲掺杂层1221a中碳离子的掺杂浓度C1与铁离子的掺杂浓度C5满足C1/C5＝(0.5～1.2)/10，可以是C1/C5＝0.5/10，也可以是C1/C5＝0.8/10，也可以是C1/C5＝1.0/10，也可以是C1/C5＝1.2/10，本公开实施例对第一甲掺杂层1221a中碳离子的掺杂浓度C1与铁离子的掺杂浓度C5的具体掺杂比例不进行限定，只需满足C1/C5＝(0.5～1.2)/10即可。进一步的，第一乙掺杂层1221b中碳离子的掺杂浓度C2与铁离子的掺杂浓度C6满足C2/C6＝(0.1～0.3)/10，可以是C2/C6＝0.1/10，也可以是C2/C6＝0.2/10，也可以是C2/C6＝0.3/10，本公开实施例对第一乙掺杂层1221b中碳离子的掺杂浓度C2与铁离子的掺杂浓度C6的具体掺杂比例不进行限定，只需满足C2/C6＝(0.1～0.3)/10即可。进一步的，第二乙掺杂层1222b中碳离子的掺杂浓度C4与第二甲掺杂层1222a中碳离子的掺杂浓度C3满足C4/C3＝(1～2)/10，可以是C4/C3＝1/10，也可以是C4/C3＝1.5/10，也可以是C4/C3＝2/10，本公开实施例对第二乙掺杂层1222b中碳离子的掺杂浓度C4与第二甲掺杂层1222a中碳离子的掺杂浓度C3的具体掺杂比例不进行限定，只需满足C4/C3＝(1～2)/10即可。
进一步的，第一甲缓冲层1221a中铁离子的掺杂浓度C5可以满足C5＝1*10 18/cm 3～1*10 19/cm 3，第一乙缓冲层1221b中铁离子的掺杂浓度C6可以满足C6＝1*10 18/cm 3～1*10 19/cm 3，第一甲缓冲层1221a中铁离子的掺杂浓度和第一乙缓冲层1221b中铁离子的掺杂浓度均为轻掺杂，不会影响各个缓冲层的晶体质量，保证外延结构以及半导体器件性能稳定。作为一种可行的实施方式，第一甲缓冲层1221a 中碳离子的掺杂浓度C1可以为2*10 17/cm 3，第一甲缓冲层1221a中铁离子的掺杂浓度C5可以为2*10 18/cm 3，第一乙缓冲层1221b中碳离子的掺杂浓度C2可以为5*10 16/cm 3，第一乙缓冲层1221b中铁离子的掺杂浓度C6可以为2*10 18/cm 3，第二甲缓冲层1222a中碳离子的掺杂浓度C3可以为5*10 16/cm 3，第二甲缓冲层1222a中铁离子的掺杂浓度为0，第二乙缓冲层1222b中碳离子的掺杂浓度C4可以为2.5*10 16/cm 3，第二乙缓冲层1222b中铁离子的掺杂浓度为0。
上述实施例对各个缓冲层中的掺杂情况进行说明，通过合理设置各个缓冲层中的掺杂浓度，可以保证外延结构中缓冲层的高阻特性的同时保证缓冲层的晶体质量良好，保证在半导体器件漏电和击穿等性能不变差的前提下提升外延结构以及半导体器件的可靠性。
接下来对第一类缓冲层1221和第二类缓冲层1222的厚度情况进行说明。
可选的，第一缓冲层的厚度大于第二缓冲层的厚度。
示例性的，第一类缓冲层1221可以包括一层或者多层第一缓冲层，第二类缓冲层1222可以包括一层或者多层第二缓冲层，每层第一缓冲层的厚度均大于第二缓冲层的厚度，保证缓冲层的高阻特性的同时保证缓冲层的晶体质量良好；同时缓冲层可以为轻掺杂，如此可以保证在半导体器件漏电和击穿等性能不变差的前提下提升外延结构以及半导体器件的可靠性。
具体的，第一类缓冲层1221可以包括两层第一缓冲层，第二类缓冲层1222可以包括两层第二缓冲层，本公开实施例以第一类缓冲层1221包括两层第一缓冲层，第二类缓冲层1222包括两层第二缓冲层为例进行说明。示例性的，继续参考图5所示，第一类缓冲 层1221包括叠层设置的第一甲缓冲层1221a和第一乙缓冲层1221b，第一甲缓冲层1221a位于靠近衬底11的一侧；第一甲缓冲层1221a的厚度大于或者等于第一乙缓冲层1221b的厚度；第二类缓冲层1222包括叠层设置的第二甲缓冲层1222a和第二乙缓冲层1222b，第二甲缓冲层1222a位于靠近衬底11的一侧；第二甲缓冲层1222a的厚度大于第二乙缓冲层1222b的厚度。
示例性的，如图5所示，缓冲层122从下至上可以依次包括第一甲缓冲层1221a、第一乙缓冲层1221b、第二甲缓冲层1222a和第二乙缓冲层1222b，第一甲缓冲层1221a和第一乙缓冲层1221b中任意一层的厚度大于第二甲缓冲层1222a和第二乙缓冲层1222b中任意一层的厚度，且第一甲缓冲层1221a的厚度大于或者等于第一乙缓冲层1221b的厚度，第二甲缓冲层1222a的厚度大于第二乙缓冲层1222b的厚度，如此缓冲层122中位于下层的缓冲层的厚度均不小于位于上层的缓冲层的厚度。例如，以靠近衬底的第一类甲缓冲层厚度h1为基础，在远离衬底的方向上各缓冲层的厚度逐渐减小。即第一类甲缓冲层厚度h1为预设厚度，其他缓冲层厚度h根据h1的厚度关系确定，h≤h1。如此通过缓冲层中特定的厚度关系来实现高阻缓冲层，而对缓冲层的掺杂浓度不做要求，保证在半导体器件漏电和击穿等性能不变差的前提下提升外延结构以及半导体器件的可靠性。
在上述实施例的基础上，第一甲缓冲层1221a的厚度为h1，第一乙缓冲层1221b的厚度为h2，第二甲缓冲层1222a的厚度为h3，第二乙缓冲层1222b的厚度为h4；其中，h2＝h1，2/10≤h3/h2≤9/10，4/10≤h4/h3≤9/10。
示例性的，通过设置第一甲缓冲层1221a的厚度h1、第一乙缓冲层1221b的厚度h2，第二甲缓冲层1222a的厚度h3以及第二乙缓冲层1222b的厚度h4满足h2＝h1、2/10≤h3/h2≤9/10、410≤h4/h3≤9/10，通过合理设置第一甲缓冲层1221a、第一乙缓冲层1221b、第二甲缓冲层1222a以及第二乙缓冲层1222b之间相应的厚度比例，可以在实现传统高阻GaN缓冲层相同作用的同时保证晶体质量不变差。
具体的，第一乙缓冲层1221b的厚度h2和第二甲缓冲层1222a的厚度h3满足2/10≤h3/h2≤9/10，可以是h3/h2＝2/10、或者是h3/h2＝4/10、或者是h3/h2＝6/10、或者是h3/h2＝8/10、或者是h3/h2＝9/10，本公开实施例对第一乙缓冲层1221b的厚度h2和第二甲缓冲层1222a的厚度h3的具体比例关系不进行限定，只需满足2/10≤h3/h2≤9/10即可。进一步的，第二甲缓冲层1222a的厚度h3和第二乙缓冲层1222b的厚度h4满足4/10≤h4/h3≤9/10，可以是h4/h3＝4/10、或者是h4/h3＝6/10、或者是h4/h3＝8/10、或者是h4/h3＝9/10，本公开实施例对第二甲缓冲层1222a的厚度h3和第二乙缓冲层1222b的厚度h4的具体比例关系不进行限定，只需满足4/10≤h4/h3≤9/10即可。作为一种可行的实施方式，第一甲缓冲层1221a的厚度h1可以为500nm，第一乙缓冲层1221b的厚度h2可以为500nm，第二甲缓冲层1222a的厚度h3可以为400nm，第二乙缓冲层1222b的厚度h4可以为300nm。
上述实施例对各个缓冲层的厚度情况进行说明，通过合理设置各个缓冲层的厚度，可以保证外延结构中缓冲层的高阻特性的同时保证缓冲层的晶体质量良好，保证在半导体器件漏电和击穿等性能 不变差的前提下提升外延结构以及半导体器件的可靠性。
综上，上述实施例分别从不同缓冲层的掺杂浓度情况以及厚度情况两个方面对外延层的具体设置方式进行了说明。可以理解的是，在实际外延层设置中，可以综合考虑不同缓冲层的掺杂浓度情况以及厚度情况，例如对于厚度较厚的缓冲层，可以设置其掺杂浓度较大，对于厚度较小的缓冲层，可以设置其掺杂浓度较小。通过综合考虑不同缓冲层的掺杂浓度情况以及厚度情况，保证外延结构中缓冲层的高阻特性的同时保证缓冲层的晶体质量良好，保证在半导体器件漏电和击穿等性能不变差的前提下提升外延结构以及半导体器件的可靠性。
在上述实施例的基础上，继续参考图5所示，本公开实施例提供的外延层12还可以包括位于缓冲层122靠近衬底11一侧的成核层121；位于缓冲层122远离衬底11一侧的间隔层123；位于间隔层123远离衬底11基板一侧的势垒层124，势垒层124与缓冲层122形成异质结结构；位于势垒层124远离衬底11一侧的盖层125。
示例性的，成核层121影响外延层12中位于成核层121上方的其他膜层的晶体质量、表面形貌以及电学性质等参数；成核层121主要起到匹配衬底11材料和外延层12中异质结结构中的半导体材料层的作用。
间隔层123可以为AlN间隔层，间隔层123可以抬高势垒，增加二维电子气的限域性，同时减小合金散射，提升迁移率。
势垒层124可以为AlGaN势垒层，势垒层124与缓冲层122一起形成异质结结构，形成二维电子气的运动沟道。
盖层125的主要作用是减小表面态，减小后续半导体器件的表 面漏电，抑制电流崩塌，从而提升外延结构以及半导体器件的性能和可靠性。可选的，盖层125的材料为III族氮化物，优选为P型掺杂氮化镓(P-GaN)，P-GaN结构能够有效降低AlGaN层的势垒高度。
基于同样的发明构思，本公开实施例还提供了一种半导体器件，本公开实施例提供的半导体器件包括上述实施例所述的半导体器件的外延结构。进一步的，图6是本公开实施例提供的一种半导体器件的结构示意图，如图6所示，本公开实施例提供的半导体器件包括：
衬底11；
位于衬底11一侧的外延层12，外延层12包括依次位于衬底11一侧的成核层121、缓冲层122、间隔层123、势垒层124以及帽层125；
位于势垒层124远离衬底11一侧的源极131和漏极132；
位于帽层125远离衬底11一侧的栅极133，栅极133位于源极131和漏极132之间。
示例性的，源极131和漏极132位于势垒层124远离衬底11的一侧，源极131和漏极132分别与势垒层124形成欧姆接触；栅极133位于源极131和漏极132之间，同时位于盖层125远离衬底11的一侧，栅极133与盖层125形成肖特基接触。
应该理解，本公开实施例是从半导体器件结构设计的角度来保证半导体器件中成核层的热阻不变高的情况下提升成核层的晶体质量。半导体器件包括但不限制于：工作在高电压大电流环境下的大功率氮化镓高电子迁移率晶体管(High Electron Mobility  Transistor，简称HEMT)、绝缘衬底上的硅(Silicon-On-Insulator，简称SOI)结构的晶体管、砷化镓(GaAs)基的晶体管以及金属氧化层半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，简称MOSFET)、金属绝缘层半导体场效应晶体管(Metal-Semiconductor Field-Effect Transistor，简称MISFET)、双异质结场效应晶体管(Double Heterojunction Field-Effect Transistor，简称DHFET)、结型场效应晶体管(Junction Field-Effect Transistor，简称JFET)，金属半导体场效应晶体管(Metal-Semiconductor Field-Effect Transistor，简称MESFET)，金属绝缘层半导体异质结场效应晶体管(Metal-Semiconductor Heterojunction Field-Effect Transistor，简称MISHFET)或者其他场效应晶体管。
基于同一发明构思，本公开实施例还提供了一种半导体器件的外延结构制备方法，图7是本公开实施例提供的一种半导体器件的外延结构的制备方法的流程示意图，如图7所示，本公开实施例提供的半导体器件的外延结构的制备方法可以包括：
S110、提供衬底。
S120、在所述衬底一侧制备外延层，所述外延层包括缓冲层，所述缓冲层包括叠层设置的第一类缓冲层和第二类缓冲层，所述第一类缓冲层位于靠近所述衬底的一侧，且所述第一类缓冲层的掺杂浓度大于所述第二类缓冲层的掺杂浓度。
由于获得高阻GaN缓冲层所需的C掺杂浓度需要满足>1*10 19/cm 3，如此会导致GaN缓冲层晶体质量变差；而获得高阻GaN缓冲层所需的Fe掺杂浓度需要满足>1*10 19/cm 3，如此会影响最终器件的性能。本公开实施例创造性地设置缓冲层122包括多层 缓冲层，例如包括叠层设置的第一类缓冲层1221和第二类缓冲层1222，第一类缓冲层1221位于靠近衬底11的一侧，同时设置第一类缓冲层1221的掺杂浓度大于第二类缓冲层1222的掺杂浓度，通过第一类缓冲层1221和第二类缓冲层1222特定的掺杂浓度关系来实现高阻缓冲层，而对缓冲层的具体掺杂浓度不作要求，例如可以设置缓冲层为轻掺杂，如此可以保证在半导体器件漏电和击穿等性能不变差的前提下提升外延结构以及半导体器件的可靠性。
综上，本公开实施例提供的半导体器件的外延结构的制备方法，通过设置缓冲层包括叠层设置的第一类缓冲层和第二类缓冲层，同时设置第一类缓冲层的掺杂浓度大于第二类缓冲层的掺杂浓度，保证半导体器件中缓冲层的高阻特性的同时保证缓冲层的晶体质量良好；同时通过第一类缓冲层和第二类缓冲层特定的掺杂浓度关系来实现高阻缓冲层，而对缓冲层的具体掺杂浓度不作要求，例如可以设置缓冲层为轻掺杂，如此可以保证在半导体器件漏电和击穿等性能不变差的前提下提升外延结构以及半导体器件的可靠性。
在上述实施的基础上，在衬底一侧制备外延层，可以包括：
在衬底一侧制备成核层；
在成核层远离衬底的一侧制备缓冲层；
在缓冲层远离衬底的一侧制备间隔层；
在间隔层远离衬底的一侧制备势垒层，述势垒层与缓冲层形成异质结结构；
在势垒层远离衬底的一侧制备盖层。
通过成核层匹配衬底材料和外延层中异质结结构中的半导体材料层；通过间隔层抬高势垒，增加二维电子气的限域性，同时减 小合金散射，提升迁移率；通过势垒层与缓冲层一起形成异质结结构，形成二维电子气的运动沟道；通过盖层减小表面态，减小后续半导体器件的表面漏电，抑制电流崩塌，从而提升外延结构以及半导体器件的性能和可靠性。
基于同样的发明构思，本公开实施例还提供了一种半导体器件的制备方法，图8是本公开实施例提供的一种半导体器件的制备方法的流程示意图，如图8所示，本公开实施例提供的半导体器件的制备方法可以包括：
S210、提供衬底。
S220、在所述衬底一侧制备外延层，所述外延层包括依次位于所述衬底一侧的成核层、缓冲层、间隔层、势垒层和帽层。
S230、在所述势垒层远离所述衬底的一侧制备源极和漏极；在所述帽层远离所述衬底的一侧制备栅极，所述栅极位于所述源极和所述漏极之间。
源极和漏极分别与势垒层形成欧姆接触，栅极与盖层形成肖特基接触。
注意，上述仅为本公开的较佳实施例及所运用技术原理。本领域技术人员会理解，本公开不限于这里所述的特定实施例，对本领域技术人员来说能够进行各种明显的变化、重新调整、相互结合和替代而不会脱离本公开的保护范围。因此，虽然通过以上实施例对本公开进行了较为详细的说明，但是本公开不仅仅限于以上实施例，在不脱离本公开构思的情况下，还可以包括更多其他等效实施例，而本公开的范围由所附的权利要求范围决定。

Claims (16)

  1. 一种半导体器件的外延结构，其特征在于，包括：
    衬底；
    位于所述衬底一侧的外延层，所述外延层包括位于所述衬底一侧的成核层以及位于所述成核层远离所述衬底一侧的缓冲层；
    其中，所述缓冲层的厚度与所述成核层的厚度成反比例关系。
  2. 根据权利要求1所述的外延结构，其特征在于，所述成核层的厚度为h1，所述缓冲层的厚度为h2；
    其中，0.1/h2≤h1≤0.25/h2。
  3. 根据权利要求2所述的外延结构，其特征在于，h1＝0.17/h2。
  4. 根据权利要求1所述的外延结构，其特征在于，所述成核层的厚度为h1，所述衬底的厚度为h3；
    其中，2*10 -5≤h1/h3≤5*10 -4。
  5. 根据权利要求1所述的外延结构，其特征在于，所述成核层的厚度为h1，所述外延层的厚度为h4；
    其中，0.05≤h1/h4≤0.3。
  6. 根据权利要求5所述的外延结构，其特征在于，0.07≤h1/h4≤0.1。
  7. 根据权利要求1所述的外延结构，其特征在于，所述成核层的厚度为h1，其中，100nm≤h1≤150nm。
  8. 根据权利要求1-7任一项所述的外延结构，其特征在于，
    所述缓冲层包括叠层设置的第一类缓冲层和第二类缓冲层，所述第一类缓冲层位于靠近所述衬底的一侧，且所述第一类缓冲层的 掺杂浓度大于所述第二类缓冲层的掺杂浓度。
  9. 根据权利要求8所述的外延结构，其特征在于，所述第一类缓冲层包括至少一层第一缓冲层，所述第二类缓冲层包括至少一层第二缓冲层；
    所述第一缓冲层的掺杂浓度大于所述第二缓冲层的掺杂浓度。
  10. 根据权利要求9所述的外延结构，其特征在于，所述第一类缓冲层包括叠层设置的第一甲缓冲层和第一乙缓冲层，所述第一甲缓冲层位于靠近所述衬底的一侧；所述第一甲缓冲层的掺杂浓度大于或者等于所述第一乙缓冲层的掺杂浓度；
    所述第二类缓冲层包括叠层设置的第二甲缓冲层和第二乙缓冲层，所述第二甲缓冲层位于靠近所述衬底的一侧；所述第二甲缓冲层的掺杂浓度大于所述第二乙缓冲层的掺杂浓度。
  11. 根据权利要求10所述的外延结构，其特征在于，所述第一甲缓冲层、所述第一乙缓冲层、所述第二甲缓冲层和所述第二乙缓冲层中均掺杂有碳离子；
    所述第一甲缓冲层中碳离子的掺杂浓度为第一掺杂浓度C1，所述第一乙缓冲层中碳离子的掺杂浓度为第二掺杂浓度C2，所述第二甲缓冲层中碳离子的掺杂浓度为第三掺杂浓度C3，所述第二乙缓冲层中碳离子的掺杂浓度为第四掺杂浓度C4，其中，C1＞C2≥C3＞C4。
  12. 根据权利要求10所述的外延结构，其特征在于，所述第一甲缓冲层和所述第一乙缓冲层中还掺杂有铁离子，所述第二甲缓冲层和所述第二乙缓冲层中不掺杂铁离子；
    所述第一甲缓冲层中铁离子的掺杂浓度为第五掺杂浓度，所述 第一乙缓冲层中铁离子的掺杂浓度为第六掺杂浓度，其中，所述第五掺杂浓度与所述第六掺杂浓度相同。
  13. 根据权利要求12所述的外延结构，其特征在于，所述第一甲缓冲层中碳离子的掺杂浓度为第一掺杂浓度C1，所述第五掺杂浓度C5，其中，C1/C5＝(0.5～1.2)/10；
    所述第一乙缓冲层中碳离子的掺杂浓度为第二掺杂浓度C2，所述第六掺杂浓度C6，其中C2/C6＝(0.1～0.3)/10；
    所述第二甲缓冲层中碳离子的掺杂浓度为第三掺杂浓度C3，其中，C3＝C2；
    所述第二乙缓冲层中碳离子的掺杂浓度为第四掺杂浓度C4，其中，C4/C3＝(1～2)/10。
  14. 根据权利要求9所述的外延结构，其特征在于，所述第一缓冲层的厚度大于所述第二缓冲层的厚度。
  15. 根据权利要求14所述的外延结构，其特征在于，所述第一类缓冲层包括叠层设置的第一甲缓冲层和第一乙缓冲层，所述第一甲缓冲层位于靠近所述衬底的一侧；所述第一甲缓冲层的厚度大于或者等于所述第一乙缓冲层的厚度；
    所述第二类缓冲层包括叠层设置的第二甲缓冲层和第二乙缓冲层，所述第二甲缓冲层位于靠近所述衬底的一侧；所述第二甲缓冲层的厚度大于所述第二乙缓冲层的厚度。
  16. 一种半导体器件的外延结构的制备方法，用于制备权利要求1-15任一项所述的外延结构，其特征在于，包括：
    提供衬底；
    在所述衬底一侧制备成核层；
    在所述成核层远离所述衬底的一侧制备缓冲层；
    在所述缓冲层远离所述衬底的一侧制备间隔层；
    在所述间隔层远离所述衬底的一侧制备势垒层，所述势垒层与所述缓冲层形成异质结结构；
    在所述势垒层远离所述衬底的一侧制备盖层，
    其中，所述缓冲层的厚度与所述成核层的厚度成反比例关系。
PCT/CN2021/099163 2020-09-30 2021-06-09 半导体器件的外延结构及其制备方法 WO2022068256A1 (zh)

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