WO2022062535A1 - 半导体结构 - Google Patents

半导体结构 Download PDF

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Publication number
WO2022062535A1
WO2022062535A1 PCT/CN2021/103321 CN2021103321W WO2022062535A1 WO 2022062535 A1 WO2022062535 A1 WO 2022062535A1 CN 2021103321 W CN2021103321 W CN 2021103321W WO 2022062535 A1 WO2022062535 A1 WO 2022062535A1
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WO
WIPO (PCT)
Prior art keywords
capacitor array
conductive plug
capacitor
semiconductor structure
substrate
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PCT/CN2021/103321
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English (en)
French (fr)
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吴秉桓
刘杰
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长鑫存储技术有限公司
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Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP21870914.5A priority Critical patent/EP4195262A4/en
Priority to US17/448,892 priority patent/US12068239B2/en
Publication of WO2022062535A1 publication Critical patent/WO2022062535A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure

Definitions

  • the embodiments of the present application relate to the field of semiconductors, and in particular, to a semiconductor structure.
  • the interconnection between chips is often realized by through-silicon vias (TSV).
  • TSV through-silicon vias
  • the TSV technology is to form through holes connecting the upper and lower sides of the wafer, and fill the through holes with conductive materials to form an interconnection structure.
  • the conductive material includes different types of metal materials.
  • the arrangement of the interconnect structure will affect the components located on the surface of the silicon wafer and the components located in the dielectric layer on the silicon wafer.
  • the embodiment of the present application provides a semiconductor structure, which is beneficial to reduce the influence of the deformation stress generated by the conductive plug on the functional element.
  • An embodiment of the present application provides a semiconductor structure, including: a substrate and a dielectric layer on the substrate; a conductive plug, a first part of the conductive plug is located in the substrate, and a second part of the conductive plug is located in the substrate inside the dielectric layer; a capacitor array surrounding at least a second portion of the conductive plug.
  • the capacitor array can have more interfaces.
  • the interface includes the contact interface between the upper electrode and the lower electrode.
  • the deformation stress needs to continuously pass through the interface or bypass the interface. , thereby generating greater transmission attenuation, which is beneficial to ensure that the deformation stress has little influence on the functional elements located on the side of the capacitor array away from the conductive plug, thereby ensuring that the semiconductor structure has good performance.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor structure in the related art
  • FIG. 2 is a top view of the semiconductor structure shown in FIG. 1;
  • FIG. 3 is a schematic cross-sectional view of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 4 is a top view of the semiconductor structure shown in FIG. 3;
  • FIG. 5 is a schematic cross-sectional view of another semiconductor structure provided by an embodiment of the present application.
  • FIG. 6 is a top view of the semiconductor structure shown in FIG. 5;
  • FIG. 7 is a top view of another semiconductor structure provided by an embodiment of the present application.
  • FIG. 8 is a top view of still another semiconductor structure provided by an embodiment of the present application.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor structure in the related art
  • FIG. 2 is a top view of the semiconductor structure shown in FIG. 1
  • the semiconductor structure includes: a substrate 10 and a dielectric layer 11 on the substrate 10 ; a conductive plug 12 , and the conductive plug 12 is located in the substrate 10 and the dielectric layer 11 .
  • the conductive plug 12 usually contains a metal material, and the metal material tends to expand and contract when subjected to thermal stress.
  • the thermal expansion coefficient of the conductive plug 12 is different from the thermal expansion coefficient of the dielectric layer 11 and the substrate 10 , a stress concentration phenomenon will occur, thereby causing the substrate 10 and the dielectric layer 11 to deform.
  • the deformation of the substrate 10 and the dielectric layer 11 may affect the functional element properties of the functional area, and even cause structural damage to the semiconductor structure.
  • the functional area is the workable area of the functional element, including the surface of the substrate 10 and the interior of the dielectric layer 11 .
  • the functional elements on the surface of the substrate 10 are generally referred to as active regions.
  • the stress that causes the deformation of the substrate 10 and the dielectric layer 11 may come from the secondary stress generated by the deformation of other adjacent film layers in addition to the direct stress of the conductive plug 12 .
  • the compressive stress of the conductive plug 12 causes the substrate 10 to deform, and the deformed substrate 10 applies stress to the dielectric layer 11 due to the structural change, thereby causing the dielectric layer 11 to deform.
  • the functional elements are usually arranged outside the exclusion zone KOZ (Keep Out Zone), that is, the functional elements are kept away from the conductive plug 12 .
  • KOZ Keep Out Zone
  • the present application provides a semiconductor structure in which a capacitor array surrounding a conductive plug is arranged to reduce the magnitude of the deformation stress passing through the capacitor array, so as to ensure that the deformation stress has little influence on the functional area located on the side of the capacitor array away from the conductive plug, Thus, it is ensured that the functional elements of the functional area can work effectively and the semiconductor structure has good performance.
  • the semiconductor structure includes: a substrate 20 and a dielectric layer 21 on the substrate 20 ; a conductive plug 22 , the first part of which is located in the substrate 20 , and the conductive plug The second part of 22 is located in the dielectric layer 21 ; the capacitor array 24 surrounds at least the second part of the conductive plug 22 .
  • the capacitor array 24 is formed by arranging a plurality of capacitor units 24a. In the direction parallel to the surface of the substrate 20 and away from the conductive plug 22, the capacitor array 24 has a plurality of interfaces. The interface will hinder the transmission of deformation stress, that is, attenuation The deformation stress ensures that the deformation stress transmitted to the functional area 202 is small, and ensures that the functional elements of the functional area 202 have good performance.
  • the capacitor unit 24a includes double-sided capacitor units, and the capacitor array 24 is formed by continuously arranging the double-sided capacitor units 24a.
  • the interface in the capacitor array 24 mainly refers to the contact interface between the lower electrode 24b and the upper electrode 24c
  • the capacitor unit includes a single-sided capacitor unit, the capacitor array can be formed by spaced arrangement of the capacitor units, and the interface in the capacitor array also includes the sidewall surface of the capacitor unit.
  • the substrate 20 includes an exclusion area 201 and a functional area 202.
  • the functional area 202 is located on the side of the exclusion area 201 away from the conductive plug 22.
  • the exclusion area 201 and the functional area 202 have a capacitor array 24.
  • the exclusion area 201 The capacitor array 24 surrounds the second portion of the conductive plug 22 .
  • the capacitor array 24 is arranged in the functional area 202 as an example, in fact, any functional element can be arranged in the functional area 202; in addition, for the sake of simplicity, the area 201 will be excluded in the following.
  • the capacitor array 24 of the functional area 202 is referred to as the first capacitor array 241
  • the capacitor array 24 of the functional area 202 is referred to as the second capacitor array 242 .
  • the substrate 20 of the exclusion region 201 has an active region 203 , and the first capacitor array 241 is electrically connected to the active region 203 of the exclusion region 201 .
  • the first capacitor array 241 can be actuated through the active region 203, so that the first capacitor array 241 can be used as a backup capacitor and put into use during fuse repair.
  • the exclusion area 201 further includes a capacitor contact window 24d connecting the active area 203 and the first capacitor array 241, and necessary bit lines (not shown) and word lines (not shown), etc.
  • the structure, that is, the electrical structure of the exclusion area 201 may be exactly the same as that of the functional area 202, the difference between the two is only the location difference and the electrical structure of the exclusion area 201 is not put into practical use before repairing.
  • the substrate 20 of the exclusion region 201 further has an isolation structure 204 for isolating adjacent active regions 203.
  • the first capacitor array 241 is formed by arranging a plurality of capacitor units 24a, the first capacitor The array 241 corresponds to a plurality of active regions 203 and a plurality of isolation structures 204.
  • the existence of the plurality of isolation structures 204 can make the transmission of deformation stress in the substrate 20 attenuate greatly, thereby preventing the deformation stress from passing through the substrate 20 and affecting the dielectric layer 21.
  • the functional elements within it have a greater impact.
  • the arrangement of the first capacitor array 241 and the second capacitor array 242 is the same. In this way, the first capacitor array 241 and the second capacitor array 242 can be formed in the same fabrication process, which is beneficial to reduce the difficulty of fabrication of the semiconductor structure.
  • the capacitor array 24 at the edge of the structure under the same manufacturing process is selected as the capacitor array 24 surrounding the conductive plug 22, because the capacitor array at the edge of the structure is selected.
  • 24 is easily affected by the edge effect of the structure during the formation process. For example, among the multiple trenches formed by etching with the same mask, the opening of the top of the trench at the edge of the structure is smaller, so the data storage of the capacitor array 24 at the edge of the structure is small. Performance may be poor.
  • the data storage performance of the capacitor array 24 at the edge of the structure may be poor
  • using it as a transitional high density functional element located in the exclusion area 201 is beneficial to realize the value of the capacitor array 24 at the edge of the structure and avoid the edge of the structure.
  • the capacitor arrays 24 in the functional area 202 occupy the space of the functional area 202 , so that more capacitor arrays 24 with good performance are arranged in the functional area 202 to improve the performance of the semiconductor structure.
  • a reserved space area for the conductive plug may be embedded in the entire capacitor array area. In this case, a portion close to and surrounding the reserved space area The capacitor array in the area is more easily affected by the conductive plug, and the partial area can be defined as the exclusion area, and the capacitor array in the partial area can be defined as the backup capacitor.
  • first predetermined distance d1 between the first capacitor array 241 and the second capacitor array 242 .
  • the existence of the first preset distance d1 is beneficial to avoid the influence of the first capacitor array 241 affected by the conductive plug 22 on the second capacitor array 242, and to ensure that the second capacitor array 242 has better performance.
  • the effects of the first capacitor array 241 on the second capacitor array 242 include potential effects and structural effects.
  • the first capacitor array 241 is grounded itself, or the active area 203 and the capacitive contact window 24d are grounded. , word lines or bit lines are grounded to form electrostatic shielding; correspondingly, the grounded first capacitor array 241 is at a low potential, while at least part of the capacitor cells 24a of the second capacitor array 242 for data storage have stored charges, that is, at least Part of the capacitor unit 24a is at a high potential.
  • the first preset distance d1 is used for isolation, which can effectively block the transfer path of the charge, thereby ensuring accurate data storage in the second capacitor array 242. sex and effectiveness.
  • the grounded first capacitor array 242 can be disconnected from the ground wire when it is put into use subsequently, so as to perform data storage.
  • the deformation stress can be transmitted through the upper electrode 24c with less transmission attenuation.
  • arranging the first capacitor array 241 and the second capacitor array 242 consecutively may cause the second capacitor array 242 to be more easily affected by deformation stress, while the electrodes of the capacitor array 24 are usually of a high aspect ratio structure, which is relatively resistant to deformation stress. It is sensitive and prone to collapse when subjected to deformation stress. Therefore, setting the first preset distance d1 and splitting the upper electrodes 24c of different capacitor arrays 24 is beneficial to ensure that the second capacitor array 242 bears less deformation stress and ensures that The second capacitor array 242 has high structural stability.
  • the first preset distance d1 is 0.2 ⁇ m ⁇ 20 ⁇ m, for example, 1 ⁇ m, 5 ⁇ m or 10 ⁇ m. If the first preset spacing d1 is too small, the first capacitor array 241 will affect the data storage accuracy and structural stability of the second capacitor array 242; if the first preset spacing d1 is too large, the functional area 202 will be compressed. Reserved space.
  • the capacitor array 34 is a continuously formed whole, and the first capacitor array 341 and the second capacitor array 342 are arranged continuously. In this way, the first capacitor array 341 and the second capacitor array 342 can be continuously formed by using the same mask, which reduces the difficulty of manufacturing the semiconductor structure.
  • the second capacitor array 242 surrounds the second portion of the conductive plug 22 , and the surrounding shape of the first capacitor array 241 is different from the surrounding shape of the second capacitor array 242 .
  • both the first capacitor array 241 and the second capacitor array 242 completely surround the conductive plug 22, but the surrounding shapes are different. In this way, the distances between the first capacitor array 241 and the second capacitor array 242 in different directions away from the conductive plug 22 can be made different, and further, the part of the second capacitor array 242 that is more sensitive to deformation stress can be made It is located far away from the first capacitor array 241 , thereby ensuring that any part of the second capacitor array 242 has high structural stability.
  • the first capacitor array 241 may be circular, the second capacitor array 242 may be elliptical, and the part corresponding to the end point of the long axis of the ellipse is the part of the second capacitor array 242 that is sensitive to deformation stress
  • the first capacitor array 241 is a square, and the second capacitor array 242 is a circle; or, the first capacitor array 241 is a circle, and the second capacitor array 242 is a polygon such as a rhombus.
  • the first capacitor array 241 does not completely surround the conductive plug 22 , and the second capacitor array 242 completely surrounds the conductive plug 22 . In this way, by arranging the first capacitor array 241 in a partial area, the sensitive parts in the second capacitor array 242 can be protected, thereby ensuring that the second capacitor array 242 has high structural stability as a whole.
  • the first capacitor array 241 may be arc-shaped, the second capacitor array 242 may be circular; the first capacitor array 241 may be linear, the second capacitor array 242 may be square, etc. .
  • the semiconductor structure further includes: an isolation ring structure 23, the isolation ring structure 23 surrounds at least the second part of the conductive plug 22, and the isolation ring structure 23 is located between the conductive plug 22 and the first capacitor array 241, The arrangement density of the first capacitor array 241 is greater than that of the isolation ring structure 23 . In this way, functional elements with a relatively high density can be arranged in the functional area 202 .
  • the isolation ring structure 23 may be grounded, and the first capacitor array 241 may not be grounded.
  • the isolation ring structure 23 plays the role of electrostatic shielding, and the first capacitor array 241 plays the role of blocking deformation stress. In this way, when the first capacitor array 241 is put into use later, there is no need to disconnect the ground wire of the first capacitor array 241, which is beneficial to improve the practicability of the semiconductor structure.
  • the isolation ring structure 23 may include a contact portion extending in the same direction as the conductive plug 22, and a metal portion disposed on the top of the contact portion.
  • the capacitor array 44 is composed of a plurality of discontinuous capacitor sub-arrays, and the isolation ring structure 43 includes a plurality of discontinuous isolation sub-rings, and each isolation sub-ring is located in adjacent two Between the capacitor sub-arrays, the isolation ring structure 43 and the capacitor array 44 form a pattern surrounding the conductive plugs 42, and the pattern can be any shape such as a square, a circle, an ellipse or a polygon.
  • the isolation ring structure 43 is electrically isolated from the capacitor array 44, the isolation ring structure 43 is grounded, and plays the role of electrostatic shielding, and the capacitor array 44 is not grounded, which plays the role of blocking deformation stress.
  • a capacitor array 54 including a plurality of capacitor sub-arrays forms a first pattern surrounding the conductive plugs 52
  • an isolation ring structure 53 including a plurality of spacer sub-rings forms a surrounding conductive plug
  • the first pattern and the second pattern have the same shape but different positions.
  • the orthographic projection of the second pattern can be complementary to the first pattern, that is, a Complete closed pattern.
  • the shape of the first pattern and the shape of the second pattern may also be different, and the orthographic projection of the second pattern may also partially overlap with the first pattern or have a gap between the first pattern and the first pattern.
  • the second preset distance d2 in the direction in which the conductive plug 22 faces the first capacitor array 241 , there is a second preset distance d2 between the conductive plug 22 and the first capacitor array 241 , and the second preset distance d2 is 0.5 ⁇ m ⁇ 50 ⁇ m, such as 2 ⁇ m, 10 ⁇ m or 25 ⁇ m. If the second preset distance d2 is too small, the first capacitor array 241 is easily damaged by the deformation stress of the conductive plug 22 , which in turn causes the first capacitor array 241 to fail to perform the deformation isolation effect, and the first capacitor array 241 cannot It is used as a backup capacitor; if the second preset distance d2 is too large, the reserved space of the functional area 202 will be compressed.
  • the top surface of the second portion of the conductive plug 22 is lower than or flush with the top surface of the first capacitor array 241 .
  • the deformation stress applied to the dielectric layer 21 generated by the conductive plug 22 must pass through the interface in the first capacitor array 241 or bypass the first capacitor array 241 , and cannot directly affect the active surface of the substrate 20 .
  • the functional element in the region 203 or the dielectric layer 21 has an influence, that is, the deformation stress transmitted to the functional element or the active region 203 is reduced, and the functional element or the active region 203 is guaranteed to have good performance.
  • the capacitor array is used as the deformation isolation structure, and the capacitor array may have more interfaces, and the interface includes the contact interface between the upper electrode and the lower electrode.
  • the deformation stress needs to be continuously Passing through the interface or bypassing the interface results in greater transmission attenuation, which is beneficial to ensure that the deformation stress has little influence on the components located on the side of the capacitor array away from the conductive plug, thereby ensuring that the semiconductor structure has good performance.
  • An embodiment of the present application provides a semiconductor structure, which includes: a substrate and a dielectric layer on the substrate; a conductive plug, a first part of the conductive plug is located in the substrate, and a second part of the conductive plug is located in the substrate within the dielectric layer; a capacitor array surrounding at least a second portion of the conductive plug.
  • the embodiments of the present application are beneficial to reduce the influence of the deformation stress generated by the conductive plug on the functional element.

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Abstract

本申请实施例提供一种半导体结构，包括：基底和位于基底上的介质层；导电插塞，所述导电插塞的第一部分位于所述基底内，所述导电插塞的第二部分位于所述介质层内；电容阵列，所述电容阵列至少环绕所述导电插塞的第二部分。本申请实施例有利于减小导电插塞产生的形变应力对功能元件的影响。

Description

半导体结构
相关申请的交叉引用
本申请基于申请号为202011013111.8、申请日为2020年09月23日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请实施例涉及半导体领域，特别涉及一种半导体结构。
背景技术
为实现芯片在Z轴方向上的集成和组装，常通过硅穿孔技术(Through-Silicon Vias，TSV)实现芯片间的互连。具体来说，硅穿孔技术就是形成连通晶圆上下两侧的通孔，并在通孔内填充导电材料以形成互连结构。其中，导电材料包括不同类型的金属材料。
然而，在实际应用过程中，互连结构的设置会对位于硅晶圆表面的元件以及位于硅晶圆上的介质层内的元件造成影响。
发明内容
本申请实施例提供一种半导体结构，有利于减小导电插塞产生的形变应力对功能元件的影响。
本申请实施例提供一种半导体结构，包括：基底和位于基底上的介质层；导电插塞，所述导电插塞的第一部分位于所述基底内，所述导电插塞的第二部分位于所述介质层内；电容阵列，所述电容阵列至少环绕所述导电插塞的第二部分。
本申请实施例提供的技术方案具有以下优点：
采用电容阵列作为形变隔离结构，电容阵列内可具有更多的界面，界面包括上电极与下电极的接触界面，当形变应力在电容阵列内传递时，形变应力需要不断穿过界面或者绕开界面，进而产生较大的传递衰减，如此，有利于保证形变应力对位于电容阵列远离导电插塞的一侧的功能元件造成的影响较小，进而保证半导体结构具有良好性能。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1为相关技术中一种半导体结构的剖面示意图；
图2为图1所示半导体结构的俯视图；
图3为本申请实施例提供的一种半导体结构的剖面示意图；
图4为图3所示半导体结构的俯视图；
图5为本申请实施例提供的另一种半导体结构的剖面示意图；
图6为图5所示半导体结构的俯视图；
图7为本申请实施例提供的又一种半导体结构的俯视图；
图8为本申请实施例提供的再一种半导体结构的俯视图。
其中，10、20：基底；11、21：介质层；12、22、42、52：导电插塞；13、23、43、53：隔离环结构；201、KOZ：排除区；202：功能区；203：有源区；204：隔离结构；24、34、44、54：电容阵列；24a：电容单元；24b：下电极；24c：上电极；24d：电容接触窗；241、341：第一电容阵列；242、342：第二电容阵列。
具体实施方式
参考图1和图2，图1为相关技术中一种半导体结构的剖面示意图，图2为图1所示半导体结构的俯视图。半导体结构包括：基底10和位于基底10上的介质层11；导电插塞12，导电插塞12位于基底10和介质层11内。
导电插塞12通常包含有金属材料，而金属材料在受到热应力作用时容易发生膨胀和收缩现象。当导电插塞12的热膨胀系数与介质层11和基底10的热膨胀系数不同时，就会产生应力集中现象，进而导致基底10和介质层11发生形变。基底10和介质层11的形变可能对功能区的功能元件特性造成影响，甚至造成半导体结构的结构性破坏。
功能区为功能元件的可工作区域，包括基底10表面和介质层11内部。基底10表面的功能元件通常指的是有源区。
需要说明的是，促使基底10和介质层11发生形变的应力除了源于导电插塞12的直接应力以外，也可能来自于相邻其他膜层发生形变所产生的二次应力。举例来说，导电插塞12的压应力使得基底10发生形变，发生形变的基底10又因为结构发生变化而向介质层11施加应力，进而导致介质层11发生形变。
目前，仅通过设置接地的隔离环结构13以屏蔽导电插塞12的部分电场，降低导电插塞12的电场的影响，并没有解决或对抗基底10和介质层11形变的方法。为避免基底10和介质层11的形变对功能区的功能元件造成影响， 通常将功能元件设置在排除区KOZ(Keep Out Zone)之外，即使得功能元件远离导电插塞12。而这样的解决方式会使得功能元件的预留空间被大大压缩，不利于芯片或功能元件的集成。
本申请实施提供一种半导体结构，设置环绕导电插塞的电容阵列，以减弱穿过电容阵列的形变应力的大小，保证形变应力对位于电容阵列远离导电插塞一侧的功能区影响较小，进而保证功能区的功能元件能够有效工作，以及保证半导体结构具有良好性能。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
本申请的实施例中，参考图3和图4，半导体结构包括：基底20和位于基底20上的介质层21；导电插塞22，导电插塞22的第一部分位于基底20内，导电插塞22的第二部分位于介质层21内；电容阵列24，电容阵列24至少环绕导电插塞22的第二部分。
电容阵列24由多个电容单元24a排列而成，在平行于基底20表面且远离导电插塞22的方向上，电容阵列24内具有多个界面，界面会对形变应力的传递造成阻碍，即衰减形变应力，保证传递至功能区202的形变应力较小，保证功能区202的功能元件具有良好性能。
本申请的实施例中，电容单元24a包括双面电容单元，电容阵列24由双面电容单元24a连续排列而成，电容阵列24中的界面主要指的是下电极24b和上电极24c的接触界面；在本申请的一些实施例中，电容单元包括单面电容单元，电容阵列可由电容单元间隔排列而成，电容阵列中的界面还包括电容单元的侧壁表面。
本申请的实施例中，基底20包括排除区201和功能区202，功能区202位于排除区201远离导电插塞22的一侧，排除区201和功能区202内具有电容阵列24，排除区201的电容阵列24环绕导电插塞22的第二部分。通过在 排除区201的边缘处设置电容阵列24作为过渡，避免排除区201的元件排列密度与功能区202的元件排列密度差异过大，保证功能区202内能够布局元件排列密度较大的功能元件，以及保证功能区202的功能元件能够有效工作。
需要说明的是，图1所示结构中仅以功能区202内布局有电容阵列24作为示例，实际上功能区202内可布局任意功能元件；此外，为了表述上的简洁，后续将排除区201的电容阵列24称为第一电容阵列241，将功能区202的电容阵列24称为第二电容阵列242。
本申请的实施例中，排除区201的基底20内具有有源区203，第一电容阵列241与排除区201的有源区203电连接。如此，有利于保证第一电容阵列241可通过有源区203作动，进而使得第一电容阵列241可作为备用电容，在修补(fuse repair)时投入使用。
在本申请的一些实施例中，排除区201内还具有连接有源区203和第一电容阵列241的电容接触窗24d以及必要的位线(未图示)和字线(未图示)等结构，即排除区201的电学结构可与功能区202的电学结构完全相同，两者的区别仅在于位置差异以及排除区201的电学结构在进行修补之前不投入实际使用。
在本申请的一些实施例中，排除区201的基底20内还具有隔离相邻有源区203的隔离结构204，由于第一电容阵列241由多个电容单元24a排列而成，因此第一电容阵列241对应多个有源区203以及多个隔离结构204，多个隔离结构204的存在可使得形变应力在基底20内的传递衰减较大，从而避免形变应力穿过基底20而对介质层21内的功能元件造成较大的影响。
本申请的实施例中，第一电容阵列241与第二电容阵列242的排列方式相同。如此，第一电容阵列241与第二电容阵列242可在同一制作工艺下形成，有利于减小半导体结构的制备难度。
本申请的实施例中，在采用电容阵列24环绕导电插塞22时，选择同一制作工艺下处于结构边缘位置的电容阵列24作为环绕导电插塞22的电容阵列24，由于结构边缘位置的电容阵列24在形成过程中容易受到结构边缘效应的影响，例如，采用同一掩膜版刻蚀形成的多个沟槽中结构边缘位置的沟槽 顶部开口较小，因此结构边缘的电容阵列24的数据存储性能可能较差。
在结构边缘的电容阵列24的数据存储性能可能较差的情况下，将其作为过渡的位于排除区201的高排列密度功能元件，有利于实现结构边缘的电容阵列24的价值，且避免结构边缘的电容阵列24占据功能区202的空间，从而在功能区202内布局更多性能良好的电容阵列24，提高半导体结构的性能。
在本申请的一些实施例中，在采用电容阵列环绕导电插塞时，可以在整块电容阵列区域内镶入导电插塞预留空间区域，此时，靠近并包围该预留空间区域的部分区域的电容阵列较容易受到导电插塞的影响，可将该部分区域定义为排除区，以及将该部分区域的电容阵列定义为备用电容。
本申请的实施例中，在排除区201朝向功能区202的方向上，第一电容阵列241与第二电容阵列242之间具有第一预设间距d1。第一预设间距的d1的存在有利于避免受到导电插塞22影响的第一电容阵列241对第二电容阵列242造成影响，保证第二电容阵列242具有较优的性能。
其中，第一电容阵列241对第二电容阵列242的影响包括电位影响和结构影响。
关于电位影响：本申请的实施例中，为避免导电插塞22的电场对功能区202的功能元件的性能造成影响，第一电容阵列241自身接地，或者通过有源区203、电容接触窗24d、字线或位线接地，以形成静电屏蔽；相应地，接地后的第一电容阵列241处于低电位，而进行数据存储的第二电容阵列242至少有部分电容单元24a存储有电荷，即至少部分电容单元24a处于高电位，为避免电荷因为电位差而发生转移和泄露，采用第一预设间距d1进行隔离，能够有效阻断电荷的转移路径，从而保证第二电容阵列242的数据存储准确性和有效性。
其中，接地的第一电容阵列242可在后续投入使用时切断与地线的连接，从而进行数据存储。
关于结构影响：由于当前的电容阵列24的上电极24c通常是一体化形成的连续膜层，内部没有界面，因此形变应力可通过上电极24c以较小的传递衰减进行传递。如此，连续排列第一电容阵列241和第二电容阵列242，可能 会导致第二电容阵列242更容易受到形变应力的影响，而电容阵列24的电极通常为高高宽比结构，对形变应力较为敏感，受到形变应力时容易发生坍塌，因此，设置第一预设间距d1，对不同电容阵列24的上电极24c进行拆分，有利于保证第二电容阵列242承受的形变应力较小，以及保证第二电容阵列242具有较高的结构稳定性。
本申请的实施例中，第一预设间距d1为0.2μm～20μm，例如为1μm、5μm或10μm。第一预设间距d1过小，则第一电容阵列241会对第二电容阵列242的数据存储准确性以及结构稳定性造成影响；第一预设间距d1过大，则会压缩功能区202的预留空间。
在其他实施例中，参考图5和图6，电容阵列34为连续形成的整体，第一电容阵列341和第二电容阵列342连续排列。如此，可采用同一掩膜版连续形成第一电容阵列341和第二电容阵列342，降低半导体结构的制备难度。
本申请的实施例中，第二电容阵列242环绕导电插塞22的第二部分，第一电容阵列241的环绕形状与第二电容阵列242的环绕形状不同。
在本申请的一些实施例中，第一电容阵列241与第二电容阵列242均完整环绕导电插塞22，但环绕形状不同。如此，可使得在远离导电插塞22的不同方向上，第一电容阵列241与第二电容阵列242之间的间距不同，进一步地，可使得第二电容阵列242中对形变应力较敏感的部分处于距离第一电容阵列241较远的位置，从而保证第二电容阵列242的任意部分具有较高的结构稳定性。
在本申请的一些实施例中，第一电容阵列241可以为圆形，第二电容阵列242可以为椭圆形，椭圆形长轴端点对应的部分为第二电容阵列242中对形变应力敏感的部分；或者，第一电容阵列241为正方形，第二电容阵列242为圆形；或者，第一电容阵列241为圆形，第二电容阵列242为菱形等多边形。
在本申请的一些实施例中，第一电容阵列241不完全环绕导电插塞22，第二电容阵列242完全环绕导电插塞22。如此，可通过在部分区域布局第一电容阵列241，保护第二电容阵列242中的敏感部分，进而保证第二电容阵列 242整体具有较高的结构稳定性。
在本申请的一些实施例中，第一电容阵列241可以为圆弧形，第二电容阵列242可以为圆形；第一电容阵列241可以是直线形，第二电容阵列242可以是方形等等。
本申请的实施例中，半导体结构还包括：隔离环结构23，隔离环结构23至少环绕导电插塞22的第二部分，隔离环结构23位于导电插塞22与第一电容阵列241之间，第一电容阵列241的排列密度大于隔离环结构23的排列密度。如此，可在功能区202布局排列密度较大的功能元件。
在本申请的一些实施例中，隔离环结构23可接地，第一电容阵列241可不接地，隔离环结构23起到静电屏蔽的作用，第一电容阵列241起到阻隔形变应力的作用。如此，后续将第一电容阵列241投入使用时，无需断开第一电容阵列241的接地线，有利于提高半导体结构的实用性。
其中，隔离环结构23可包括与导电插塞22同向延伸的接触部，以及设置在接触部顶部的金属部。
在本申请的一些实施例中，参考图7，电容阵列44由多个不连续的电容子阵列构成，隔离环结构43包括多个不连续的隔离子环，每一隔离子环位于相邻两个电容子阵列之间，隔离环结构43与电容阵列44构成一环绕导电插塞42的图案，图案可以是方形、圆形、椭圆形或多边形等任意形状。
其中，隔离环结构43与电容阵列44电隔离，隔离环结构43接地，起到静电屏蔽的作用，电容阵列44不接地，起到阻隔形变应力的作用。
在本申请的一些实施例中，参考图8，包括多个电容子阵列的电容阵列54构成环绕导电插塞52的第一图案，包括多个隔离子环的隔离环结构53构成环绕导电插塞52的第二图案，第一图案与第二图案的形状相同，但位置不同，在导电插塞52朝向电容阵列54的方向上，第二图案的正投影可与第一图案互补，即构成一完整的封闭图案。
在本申请的一些实施例中，第一图案的形状和第二图案的形状还可以不同，第二图案的正投影还可以与第一图案部分重合或者与第一图案之间存在间隙。
本申请的实施例中，在导电插塞22朝向第一电容阵列241的方向上，导电插塞22与第一电容阵列241之间具有第二预设间距d2，第二预设间距d2为0.5μm～50μm，例如2μm、10μm或25μm。第二预设间距d2过小，则第一电容阵列241容易被导电插塞22的形变应力所破坏，进而导致第一电容阵列241无法起到形变隔离的效果，以及导致第一电容阵列241无法作为备用电容使用；第二预设间距d2过大，则会压缩功能区202的预留空间。
本申请的实施例中，在垂直于基底20表面的方向上，导电插塞22的第二部分的顶部表面低于或平齐于第一电容阵列241的顶部表面。如此，有利于使得导电插塞22产生的施加于介质层21的形变应力必须要穿过第一电容阵列241中的界面或者绕过第一电容阵列241，而无法直接对基底20表面的有源区203或者介质层21内的功能元件造成影响，即减小传递至功能元件或有源区203的形变应力，保证功能元件或有源区203具有良好性能。
本申请的实施例中，采用电容阵列作为形变隔离结构，电容阵列内可具有更多的界面，界面包括上电极与下电极的接触界面，当形变应力在电容阵列内传递时，形变应力需要不断穿过界面或者绕开界面，进而产生较大的传递衰减，如此，有利于保证形变应力对位于电容阵列远离导电插塞的一侧的元件造成的影响较小，进而保证半导体结构具有良好性能。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。
工业实用性
本申请实施例提供了一种半导体结构，其包括：基底和位于基底上的介质层；导电插塞，所述导电插塞的第一部分位于所述基底内，所述导电插塞的第二部分位于所述介质层内；电容阵列，所述电容阵列至少环绕所述导电插塞的第二部分。本申请实施例有利于减小导电插塞产生的形变应力对功能 元件的影响。

Claims (11)

  1. 一种半导体结构，包括：
    基底和位于基底上的介质层；
    导电插塞，所述导电插塞的第一部分位于所述基底内，所述导电插塞的第二部分位于所述介质层内；
    电容阵列，所述电容阵列至少环绕所述导电插塞的第二部分。
  2. 根据权利要求1所述的半导体结构，其中，所述基底包括功能区和排除区，所述功能区位于所述排除区远离所述导电插塞的一侧，所述排除区和所述功能区内具有所述电容阵列，所述排除区的所述电容阵列环绕所述导电插塞的第二部分。
  3. 根据权利要求2所述的半导体结构，其中，所述排除区的所述基底内具有有源区，所述排除区的所述电容阵列与所述排除区的所述有源区电连接。
  4. 根据权利要求2所述的半导体结构，其中，所述排除区的电容阵列与所述功能区的电容阵列的排列方式相同。
  5. 根据权利要求2所述的半导体结构，其中，在所述排除区朝向所述功能区的方向上，所述排除区的所述电容阵列与所述功能区的所述电容阵列之间具有预设间距。
  6. 根据权利要求2所述的半导体结构，其中，所述功能区的所述电容阵列环绕所述导电插塞的第二部分，所述排除区的所述电容阵列的环绕形状与所述功能区的所述电容阵列的环绕形状不同。
  7. 根据权利要求1所述的半导体结构，其中，还包括：隔离环结构，所述隔离环结构至少环绕所述导电插塞的第二部分，所述隔离环结构位于所述导电插塞与所述电容阵列之间。
  8. 根据权利要求1所述的半导体结构，其中，所述电容阵列由多个不连续的电容子阵列构成；还包括：隔离环结构，所述隔离环结构由多个不连续 的隔离子环构成，每一隔离子环位于相邻所述电容子阵列之间，所述隔离环结构与所述电容阵列构成一环绕所述导电插塞的图案，且所述隔离环结构与所述电容阵列电隔离。
  9. 根据权利要求1所述的半导体结构，其中，所述电容阵列接地。
  10. 根据权利要求1所述的半导体结构，其中，在所述导电插塞朝向所述电容阵列的方向上，所述导电插塞与所述电容阵列之间的间距为0.05μm～50μm。
  11. 根据权利要求1所述的半导体结构，其中，在垂直于所述基底表面的方向上，所述导电插塞的第二部分的顶部表面低于或平齐于所述电容阵列的顶部表面。
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