WO2022061719A1 - 一种芯片封装结构、电子设备及芯片封装结构的制备方法 - Google Patents

一种芯片封装结构、电子设备及芯片封装结构的制备方法 Download PDF

Info

Publication number
WO2022061719A1
WO2022061719A1 PCT/CN2020/117768 CN2020117768W WO2022061719A1 WO 2022061719 A1 WO2022061719 A1 WO 2022061719A1 CN 2020117768 W CN2020117768 W CN 2020117768W WO 2022061719 A1 WO2022061719 A1 WO 2022061719A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
blocking block
resin material
blocking
package substrate
Prior art date
Application number
PCT/CN2020/117768
Other languages
English (en)
French (fr)
Inventor
张童龙
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2020/117768 priority Critical patent/WO2022061719A1/zh
Priority to CN202080104879.8A priority patent/CN116134613A/zh
Publication of WO2022061719A1 publication Critical patent/WO2022061719A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device

Definitions

  • the present application relates to the technical field of chip packaging, and in particular, to a chip packaging structure, an electronic device and a method for preparing the chip packaging structure.
  • FCBGA Flip-Chip Ball Grid Array
  • Fig. 1 shows a structure diagram of heat dissipation of the chip at present.
  • the chip 1-1 is integrated on the package substrate 1-2 through the FCBGA process, and the heat sink 1-3 is covered on the back of the chip 1-1 (Fig. 1). side B shown). In this way, the heat dissipated by the chip 1-1 can be conducted to the heat sink 1-3, and the heat is diffused out through the heat sink 1-3.
  • radiator 1-3 When installing the radiator 1-3 in FIG. 1, it is difficult to ensure that the radiator 1-3 vertically covers the chip 1-1 along the L direction in the figure, but may appear as shown in the figure. Radiator 1-3 bias phenomenon. In this case, the heat sink 1-3 will exert greater pressure on the edge of the backside of the chip 1-1, so that the chip 1-1 may be fractured, thereby increasing the failure rate of the product.
  • Embodiments of the present application provide a chip packaging structure, an electronic device, and a method for preparing the chip packaging structure, the main purpose of which is to reduce the risk of chips being fractured.
  • the present application provides a chip packaging structure
  • the chip packaging structure includes: a packaging substrate, a first chip and a plurality of blocking blocks; the first chip and the plurality of blocking blocks are arranged on the same surface of the packaging substrate, and The plurality of blocking blocks are arranged close to the first chip, the plurality of blocking blocks are symmetrically arranged relative to the first chip, and the surface of the blocking blocks away from the packaging substrate is used for abutting with the heat sink; wherein, the height of the blocking blocks is greater than or equal to the height of the first chip. high.
  • a plurality of blocking blocks are provided on the surface of the packaging substrate on which the first chip is integrated, and the plurality of blocking blocks are close to the first chip and are symmetrically arranged with respect to the first chip.
  • the heat sink when the heat sink is biased and cannot vertically cover the upper surface of the first chip, since the height of the blocking block is greater than or equal to the height of the first chip, the heat sink will abut on the blocking block. Therefore, by limiting the block to the heat sink, the heat sink can be prevented from generating pressure on the first chip, the risk of the first chip being cracked by the heat sink is reduced, and the packaging reliability is improved.
  • the blocking block is disposed close to a corner of the first chip.
  • the internal stress of the corner of the first chip is larger than that of other positions, and it is easily fractured when subjected to external force, so the blocking block is arranged close to the corner of the first chip.
  • a plurality of corners of the first chip are provided with blocking blocks, and the blocking blocks on each of two adjacent corners are connected by a connection structure.
  • blocking blocks are arranged at the corners of the first chip, a plurality of blocking blocks can be connected together through a connection structure to facilitate fixing these blocking blocks at one time and improve packaging efficiency.
  • the blocking block is integrally formed with a resin material. If a resin material is used to form the blocking block, in the specific preparation process, the resin material can be coated on the packaging substrate to directly form the blocking block with the resin material, which can simplify the manufacturing process.
  • the blocking block is made of metal, silicon, glass or ceramic material, and is connected to the package substrate through an adhesive layer.
  • a second chip is further integrated on the packaging substrate, the first chip and the second chip are integrated in a first area on the surface of the packaging substrate, and a plurality of blocking blocks are arranged along the edge of the first area .
  • the difference between the height of the blocking block and the height of the first chip is less than or equal to 200 microns. If the difference between the height of the blocking block and the height of the first chip is large, a large gap may exist between the heat sink and the upper surface of the first chip, thereby affecting the heat dissipation effect of the first chip.
  • the embodiments of the present application further provide a method for preparing a chip package, the preparation method comprising:
  • a plurality of blocking blocks are arranged symmetrically about the first chip, and the height of the blocking blocks is greater than or equal to the height of the first chip, and the blocking blocks are far from the package.
  • the surface of the substrate is used for abutting with the heat sink.
  • a plurality of blocking blocks are arranged on the surface of the packaging substrate integrated with the first chip, and the plurality of blocking blocks are close to the chip and are symmetrically arranged relative to the first chip.
  • the height of the block is greater than or equal to the height of the first chip.
  • disposing a plurality of blocking blocks on the surface of the package substrate integrated with the first chip includes: on the surface of the package substrate integrated with the first chip, at a position close to the first chip coating the first resin material, and making the upper surface of the first resin material higher than the upper surface of the first chip; flattening the upper surface of the first resin material; curing the first resin material, so that the cured first resin material form a blocking block.
  • the blocking block can be formed directly after the first resin material is cured.
  • the process for preparing the blocking block is simple and easy to implement.
  • disposing a plurality of blocking blocks on the surface of the package substrate integrated with the first chip includes: on the surface of the package substrate integrated with the first chip, at a position close to the first chip coating the second resin material; covering the blocking block on the second resin material, and making the upper surface of the blocking block higher than the upper surface of the first chip; flattening the upper surface of the blocking block; curing the second resin material so that the The blocking block is disposed on the package substrate by the cured second resin material. That is, the blocking block is bonded on the package substrate through the second resin material.
  • flattening the upper surface of the first resin material or the upper surface of the blocking block includes: pressing the first plane of the pressing plate on the blocking block or the upper surface of the first resin material, and the first Two planes are pressed on the upper surface of the first chip, wherein the first plane and the second plane are parallel, and the second plane is far away from the upper surface of the first chip relative to the first plane, so that the upper surface of the first resin material or The upper surface of the blocking block is parallel to the upper surface of the first chip.
  • the upper surface of the first resin material or the top surface of the blocking block may not be flat and not parallel to the top surface of the chip. In this case, by pressing the pressing plate on the blocking block surface or the upper surface of the first resin material, so that the upper surface of the blocking block and the upper surface of the first resin material are parallel to the upper surface of the chip.
  • the preparation method before pressing the first plane of the pressing plate on the blocking block or the upper surface of the first resin material, and pressing the second plane on the upper surface of the first chip, the preparation method further comprises: The method includes: forming a separation layer on the first plane, and the separation layer is used to remove the pressing plate after the pressing plate presses the first resin material or the blocking block. By coating the separation layer on the first plane, the pressing plate is prevented from sticking with the first resin material and cannot be easily removed.
  • the preparation method before disposing a plurality of blocking blocks on the surface of the packaging substrate integrated with the first chip, the preparation method further includes: filling adhesive between the first chip and the packaging substrate to form Primer layer. By filling the adhesive, the connection strength between the chip and the package substrate is increased.
  • the present application further provides an electronic device, comprising a printed circuit board and the chip packaging structure in any implementation manner of the above-mentioned first aspect, or the manufacturing method of the chip packaging structure in any implementation manner of the second aspect.
  • the printed circuit board is electrically connected to the chip package structure
  • the heat sink covers the top of the first chip and the blocking block, and abuts the surface of the blocking block away from the package substrate, and the heat sink is connected to the printed circuit Board fixed connection.
  • the electronic device provided by the embodiment of the present application includes the chip package structure obtained by the first aspect embodiment or the second aspect embodiment. Therefore, when the heat sink is packaged, even if the heat sink is biased, it cannot vertically cover the first chip. On the upper surface, the risk of fracturing the first chip by the heat sink is reduced by a plurality of blocking blocks arranged symmetrically.
  • a surface of the first chip away from the packaging substrate and a surface of the blocking block away from the packaging substrate are provided with a thermally conductive interface material layer, and the heat sink is covered on the first chip by the thermally conductive interface material layer.
  • the thermally conductive interface material layer on the first chip and the thermally conductive interface material layer on the blocking block are in an integrated structure.
  • FIG. 1 is a schematic diagram of the connection relationship between a chip packaging structure and a heat sink in the prior art
  • Fig. 2 is the partial structure schematic diagram in the electronic equipment
  • 3a is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application.
  • 3b is a schematic diagram of the connection relationship between the chip packaging structure and the heat sink according to an embodiment of the application;
  • FIG. 4 is a schematic diagram of a connection relationship between a chip packaging structure and a heat sink according to an embodiment of the present application
  • 5a is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application.
  • 5b is a schematic diagram of the connection relationship between the chip packaging structure and the heat sink according to an embodiment of the present application
  • 5c is a schematic diagram of the connection relationship between the chip packaging structure and the heat sink according to an embodiment of the present application.
  • 5d is a schematic structural diagram of a heat sink according to an embodiment of the present application.
  • 6a is a schematic structural diagram of a heat sink when biased according to an embodiment of the present application.
  • 6b is a schematic structural diagram of a heat sink when biased according to an embodiment of the present application.
  • FIG. 7 is a top view of a chip packaging structure according to an embodiment of the present application.
  • FIG. 8 is a top view of a chip packaging structure according to an embodiment of the present application.
  • FIG. 9 is a top view of a chip packaging structure according to an embodiment of the present application.
  • FIG. 10 is a top view of a chip packaging structure according to an embodiment of the application.
  • FIG. 11 is a top view of a chip packaging structure according to an embodiment of the application.
  • FIG. 12 is a top view of a chip packaging structure according to an embodiment of the application.
  • FIG. 13 is a top view of a chip package structure according to an embodiment of the application.
  • FIG. 14 is a flowchart of a method for preparing a chip package structure according to an embodiment of the present application.
  • 15 is a flowchart of a method for preparing a chip packaging structure according to an embodiment of the present application.
  • FIG. 16 is a schematic structural diagram corresponding to each step in the preparation method of the chip packaging structure according to the embodiment of the present application.
  • FIG. 17 is a flowchart of a method for preparing a chip package structure according to an embodiment of the present application.
  • FIG. 18 is a schematic structural diagram corresponding to each step in the manufacturing method of the chip packaging structure according to the embodiment of the present application after completion of each step.
  • 01-chip package structure 02-PCB; 03-electrical connection structure; 04-radiator; 041-fin; 042-groove; 05-fastener;
  • Embodiments of the present application provide an electronic device.
  • the electronic device may include a mobile phone (mobile phone), a tablet computer (pad), a smart wearable product (eg, a smart watch, a smart bracelet), a virtual reality (VR) device, an augmented reality (AR), It can also be household appliances and other equipment.
  • the embodiments of the present application do not specifically limit the specific form of the above electronic device.
  • the above-mentioned electronic device may include a chip package structure 01 and a printed circuit board (printed circuit board, PCB) 02 .
  • the chip package structure 01 is electrically connected to the PCB 02 through the electrical connection structure 03 , so that the chip package structure 01 can be interconnected with other chips or other modules on the PCB 02 .
  • the electrical connection structure 03 may be a ball grid array (BGA). In an alternative embodiment, if the size of the chip package structure is relatively large. In order to ensure the reliability of the electrical connection between the chip package structure 01 and the PCB 02, the electrical connection structure 03 may also use a socket with a socket-type connection structure, and the connection terminal may also be called a connector, a plug, etc. .
  • BGA ball grid array
  • the electronic device When the chip in the chip package structure 01 is working, it will emit heat, especially as the number of cores and the speed of the chips increase, more and more heat will be emitted.
  • the electronic device In order to diffuse the heat dissipated by the chip in time, as shown in FIG. 2 , the electronic device further includes a heat sink 04 , and the heat sink 04 covers the chip package structure 01 and is fixedly connected to the PCB 02 . In this way, the heat dissipated by the chip package structure 01 will be conducted to the heat sink 04, and the heat will be dissipated through the heat sink 04 with a larger heat conduction area, so as to cool the chip and ensure the normal operation of the chip.
  • the heat sink 04 is relatively fixed to the PCB 02 by fasteners 05 (eg, bolts, rivets).
  • the heat sink 04 shown in FIG. 2 is a heat sink with a fin structure, that is, the side of the heat sink 04 away from the chip has a plurality of fins 041 .
  • the heat sink 04 can also exist in other structures.
  • the structure shown in FIG. 3 a shows the relative positional relationship between the chip package structure 01 and the heat sink 04 .
  • the chip package structure 01 includes a first chip 1 and a package substrate 2 for carrying the first chip 1 .
  • FIG. 3 a is only an embodiment, only one first chip 1 is shown, and there may be multiple chips or other electronic devices (eg, transistors, resistors, inductors, etc.).
  • the structures including the first chip 1 and other electronic devices are all fixed on the packaging substrate 2, and metal traces are formed on the packaging substrate 2, and the metal traces form a wiring structure between the chips or between the chips and other electronic devices. A signal path is established, and the first chip and other electronic devices are electrically connected to the electrical connection structure.
  • the chip involved in this application may be a single die (die), or may be a plurality of stacked dies.
  • any of the chips in the embodiments of the present application may include a substrate and a metal layer.
  • the first chip 1 includes a substrate 101 and a metal layer 102 , and the metal layer 102 is provided with a circuit structure. And the first chip 1 electrically connects the metal layer 102 to the packaging substrate 2 through the BGA through the flip-chip packaging process.
  • the base 101 can also be arranged close to the packaging substrate 2 .
  • a conductive channel needs to pass through the base 101 , one end of the conductive channel is electrically connected to the metal layer 102 , and the other end is connected to a bump.
  • the bump is electrically connected to the package substrate 2 .
  • a reinforcement ring (Ring) 10 is further provided on the package substrate 2 , and the reinforcement ring 10 is arranged along the edge of the package substrate 2 . Under the action of the reinforcement ring 10 on the package substrate 2 , the degree of warpage can be suppressed.
  • a glue dispensing process may be used to fill an underfill layer 5 between the first chip 1 and the package substrate 2 .
  • the heat sink 04 involved in the present application is covered on the upper surface of the first chip 1 (that is, the surface of the first chip 1 away from the package substrate 2 ) through a thermal interface material (thermal interface material, TIM) layer.
  • the first chip 1 is not covered with a heat dissipation cover (Lid), and then the heat sink 04 is covered on the Lid through TIM. Therefore, compared with the existing package structure including Lid, the Lid is removed, and the TIM between the Lid and the first chip is removed. In this way, the heat dissipation path between the first chip 1 and the heat sink 04 is shortened. Significantly improve the heat dissipation effect, especially for chips with high power consumption, the heat dissipation efficiency is improved more obviously.
  • the TIM 9 on the upper surface of the first chip 1 has a certain buffering effect, because the height of the TIM is small and the buffering effect is limited, the risk of the first chip being fractured is still high.
  • the chip package structure 01 involved in the present application further includes a plurality of stoppers 4 , and the plurality of stoppers 4 and the first chip 1 are arranged on the same surface of the package substrate 2 , and there are many stoppers 4 .
  • a plurality of blocking blocks 4 are disposed close to the first chip 1 , and a plurality of blocking blocks 4 are symmetrically arranged relative to the first chip 1 .
  • the heat sink 04 also covers the upper surface of the blocking block 4 , and the surface of the blocking block 4 away from the package substrate 2 is in contact with the heat sink 04 .
  • the relationship between the height of the blocking block 4 and the height of the first chip 1 may be that, as shown in FIG. 3 a , the height of the blocking block 4 is equal to the height of the first chip 1 .
  • the height of the blocking block 4 is greater than the height of the first chip 1, and the height dimension of the blocking block here refers to the size perpendicular to the package substrate.
  • the height size of the first chip refers to is the dimension perpendicular to the package substrate.
  • the vertical distance h1 between the surface of the blocking block 4 that is combined with the package substrate 2 and the surface of the blocking block 4 that is combined with the heat sink 04 is the height of the blocking block 4 .
  • the sum h2 of the thickness of the Die and the height of the bump 3 is the height of the first chip.
  • the height of the blocking block 4 is equal to the height of the first chip 1 .
  • the height of the blocking block 4 is greater than that of the first chip 1 .
  • TIM9 can be set on both the upper surface of the first chip 1 and the upper surface of the blocking block 4, and because the distance between the blocking block 4 The first chip 1 is relatively close, so the TIM9 on the first chip 1 and the TIM9 on the blocking block 4 are arranged in an integrated structure, and then the heat dissipation cover 04 is covered above the first chip 1 and the blocking block 4 through the TIM9.
  • TIM9 can also be provided on the upper surface of the first chip 1 and the upper surface of the blocking block 4, and the first chip 1
  • the TIM9 on the block 4 and the TIM9 on the blocking block 4 are in an integrated structure, but the thickness of the TIM9 on the blocking block 4 is thinner than the thickness of the TIM9 on the first chip 1, and then the heat dissipation cover 04 is covered by the TIM9 on the first chip 1 and the blocking block. 4 above.
  • the structures shown in FIG. 5c and FIG. 5d can also be used to open a groove 042 at the position of the heat dissipation cover 04 relative to the first chip 1 , the TIM9 is arranged on the upper surface of the first chip 1, but the TIM is not arranged on the upper surface of the blocking block 4.
  • the TIM9 on the first chip 1 will be embedded in the groove. 042, and the blocking block 4 is in contact with the heat dissipation cover 04.
  • the structures shown in FIG. 6a and FIG. 6b include a first blocking block 41 and a second blocking block 42 symmetrically arranged with respect to the first chip 1.
  • a first blocking block 41 when the heat sink 04 is packaged, if it is along the S1 direction During biasing, due to the existence of the first blocking block 41 , the biased inclined heat sink 04 will abut on the first blocking block 41 .
  • the biased heat sink 04 when the heat sink 04 is packaged, if it is along the S1 direction During biasing, due to the existence of the first blocking block 41 , the biased inclined heat sink 04 will abut on the first blocking block 41 .
  • the biased heat sink 04 when the heat sink 04 is biased in the S2 direction, due to the existence of the second blocking block 42 , the biased heat sink 04 will abut on the second blocking block 42 .
  • the thickness of the TIM9 between the first chip 1 and the heat sink 04 will be larger, although this structure can prevent the first chip 1
  • the heat dissipation path between the upper surface of the first chip 1 and the heat sink 04 is relatively large, which will affect the heat dissipation effect of the first chip.
  • the difference between h1 and h2 is less than or equal to 200 microns. In another alternative embodiment, the difference between h1 and h2 is less than or equal to 100 microns. In another alternative embodiment, the difference between h1 and h2 is about 10 microns.
  • the blocking block 4 is made, for example, metals (copper, aluminum, stainless steel, etc.). Silicon, glass, ceramics, etc. may also be used. A resin material may also be used.
  • the resin material when a resin material is selected to make the blocking block 4, the resin material can be directly coated on the packaging substrate 2, and after the resin material is cured, the blocking block 4 can be formed.
  • the formed The stopper 4 is integrally formed by a resin material.
  • the blocking block 4 when a blocking block made of materials such as silicon, glass or ceramics is selected, the blocking block 4 is bonded to the package substrate 2 through an adhesive layer.
  • the arrangement of the blocking block 4 on the package substrate 2 may have many situations, which will be described in detail below.
  • FIG. 7 shows an arrangement of the blocking blocks 4 , and the blocking blocks 4 are arranged close to the corners of the first chip 1 .
  • the cross-section of the first chip 1 is rectangular, that is, the first chip 1 has four sides, and the position near the connection between the two adjacent sides is regarded as the corner of the first chip 1 .
  • the position in the first chip 1 and near the corner has larger internal stress and lower strength than other positions, and it is easy to be fractured when a pressing force is applied to this position. Therefore, the blocking block 4 is placed close to the first chip The corner setting of a chip 1 will effectively prevent the chip corner from being fractured.
  • FIG. 8 shows another arrangement of the blocking blocks 4 .
  • the blocking blocks 4 are arranged close to the corners of the first chip 1 , and the blocking blocks 4 located at the adjacent corners are connected by the connecting structures 11 .
  • the connecting structures 11 can be made of the same material as the blocking block 1, or it can be different.
  • connection structure 11 does not limit the height of the connection structure 11 , which can be equal to the height of the blocking block 1 or smaller than the height of the blocking block.
  • the height of the connection structure 11 here is also perpendicular to the package substrate.
  • the blocking blocks 4 located at adjacent corners are connected by the connecting structure 11, in terms of the manufacturing process, a plurality of blocking blocks 4 can be arranged at one time to improve the packaging efficiency.
  • the blocking block When block 4 is a metal block, firstly apply adhesive glue at the positions near the four corners of the first chip, and then cover multiple metal blocks in an integrated structure on the adhesive glue at the same time. block, will significantly improve the efficiency.
  • the heat sink 04 when the heat sink 04 is biased, it is usually pressed at two positions on the first chip 1, one is at a position close to the corner of the first chip, and the other may be pressed at two positions of the first chip 1. It will be pressed close to the side of the first chip. If the height of the connecting structure 11 is equal to the height of the blocking block 4, it will not only prevent the corner of the first chip from being cracked, but also prevent the side of the first chip from being pressed. The risk of blocking the chip from being fractured is further increased.
  • the shape of the blocking block may exist in various forms.
  • the cross-section of the blocking block 4 is a rectangle.
  • the cross section of the blocking block 4 is circular.
  • the cross section of the blocking block 4 is oval.
  • the cross-section of the blocking block 4 can also be of other shapes. The application does not specifically limit the specific formation of the blocking block.
  • a second chip 12 or even more chips are integrated on the package substrate 2, as shown in FIG. 11, the first chip 1 and the second chip 12 are integrated; as shown in FIG. 12 , including a first chip 1, a second chip 12, and a third chip 13; as shown in FIG. 13, including a first chip 1 and a second chip 12, and a third chip 13 and a fourth chip 14.
  • These chips can be integrated on the package substrate 2 respectively, and are electrically connected to the package substrate 2 through BGA respectively. Alternatively, these chips are integrated on an interconnection substrate to form a combo die, and the interconnection substrate is further integrated on the packaging substrate 2 and electrically connected to the packaging substrate 2 .
  • the interconnect substrate can use a redistribution layer (RDL) or an interposer.
  • RDL redistribution layer
  • interposer an interposer
  • a plurality of blocking blocks 4 are provided at positions of the first region near the corners of the chip.
  • the embodiment of the present application also provides a method for preparing a chip packaging structure, as shown in FIG. 14 , the preparation method includes the following steps:
  • S2 On the surface of the package substrate integrated with the first chip, and close to the first chip, a plurality of blocking blocks are symmetrically arranged with respect to the first chip, and the height of the blocking blocks is greater than or equal to the height of the first chip.
  • the surface away from the package substrate is used for abutment with the heat sink.
  • a plurality of blocking blocks are symmetrically arranged near the first chip, because the height of the blocking blocks is greater than or equal to that of the first chip.
  • the limit of the blocking block can prevent the heat sink from affecting the first chip.
  • the edge of the chip creates a larger squeezing force to reduce the risk of the chip being fractured.
  • the above-mentioned blocking block can be made of different materials.
  • the blocking block can be directly made of coated resin material, or can be made of metal, or can be made of silicon, glass, or the like.
  • the preparation method When the blocking block is directly made of resin material, the preparation method will also be different, and the preparation method will be described in detail below.
  • the preparation method specifically includes the following steps:
  • step S101 of FIG. 15 and (a) of FIG. 16 the first resin material 71 is coated on the surface of the package substrate 2 in which the first chip 1 is integrated, and at a position close to the first chip 1 , and the first The upper surface of a resin material 71 is higher than the upper surface of the first chip 1 .
  • the upper surface Q surface of the first resin material 71 refers to the surface of the first resin material 71 away from the package substrate 2 .
  • a cofferdam (Dam) can be formed by using a resin material (Epoxy) with high viscosity and poor fluidity first, and then fill the cofferdam with a resin material (Epoxy) with high fluidity. Resin material, which can avoid the Epoxy flowing on the package substrate when the epoxy with higher fluidity is directly applied.
  • the shape of the cofferdam Dam determines the shape of the final cross-section of the block when coating a higher viscosity, less fluid resin material.
  • only the corners of the first chip 1 may be coated with the first resin material.
  • the edges of the first chip 1 other than the corners of the first chip 1 may also be coated with the first resin material.
  • step (b) in FIG. 16 can be completed before (a), that is, firstly, glue is dispensed between the first chip 1 and the packaging substrate 2 to form the primer layer 5, and then the first chip is close to the first chip.
  • the first resin material 71 is coated at the position of 1 .
  • the first resin material shown in FIG. 16 can be applied first, and then the glue is dispensed.
  • the reason is: if the glue is dispensed between the first chip 1 and the package substrate 2 first, the glue may flow to the The position where the blocking block is to be arranged will affect the coating of the first resin material. Therefore, the first resin material 71 can be coated at a position close to the first chip 1 first, and then glue is dispensed between the first chip 1 and the package substrate 2 .
  • the upper surface of the first resin material 71 needs to be higher than the upper surface of the first chip 1 , because the first resin material needs to be cured later, during the curing process During the process, the first resin material will shrink. If the upper surface of the first resin material 71 is lower than the upper surface of the first chip 1 or flush with the upper surface of the first chip 1, after curing, the upper surface of the formed blocking block will The surface will be lower than the upper surface of the first chip, so that the blocking block cannot prevent the heat sink from pressing the first chip.
  • step S102 of FIG. 15 and (c) of FIG. 16 the upper surface of the first resin material is flattened.
  • the first surface P1 of the pressing plate 6 is pressed against the upper surface of the first resin material 71
  • the second surface P2 is pressed against the upper surface of the first chip 1
  • the first plane P1 and the second plane P2 are parallel, and the second plane P2 is far from the upper surface of the first chip 1 relative to the first plane P1. That is, the first plane P1 and the second plane P2 are not on the same plane, but have a distance d1 between them as shown in (c) of FIG. 16 .
  • the protrusion 61 is formed at the position of the pressing plate 6 opposite to the first chip 1 .
  • step S103 of FIG. 15 and (d) of FIG. 16 the first resin material is cured, so that the cured first resin material forms the blocking block 4 .
  • the first resin material When the upper surface of the first resin material is pressed with a pressing plate in the above step S102, the first resin material still has a certain fluidity. When the first resin material is heated and cured in the step S103, the first resin material will shrink Therefore, before heating and curing, there is a gap between the first plane P1 and the second plane P2 of the pressing plate, so that the height of the blocking block formed after curing can be equal to or greater than that of the first chip.
  • a pressing plate When a pressing plate is used to flatten the upper surface of the first resin material, due to the high viscosity of the first resin material, the pressing plate and the first resin material may be bonded together. In order to facilitate the removal of the pressing plate, the pressing plate can be pressed On the upper surface of the first resin material and before pressing on the upper surface of the first chip, in conjunction with (c) in FIG. 16 , a detachment layer (detach) 8 is formed on the first plane P1 of the pressing plate 6, or A detachment layer 8 is also formed on the second surface P2. The function of the detachment layer 8 is to facilitate the removal of the pressing plate after the pressing plate presses the first resin material.
  • the material of the separation layer 8 can be selected from a material whose viscosity decreases as the temperature increases. In this case, when the first resin material is heated and cured, the adhesive force of the separation layer will gradually decrease with the increase of temperature, and then the adhesive force of the separation layer will gradually decrease. The pressing plate 6 is released from the first resin material and the first chip.
  • the pressing plate 6 is still fixed above the first resin material and the first chip, so that the surface abutting against the pressing plate will not form an uneven surface due to the shrinkage of the first resin material. , so as to ensure that the upper surface of the final blocking block is parallel to the upper surface of the first chip.
  • the following also provides another preparation method for preparing a chip package structure, and the preparation method specifically includes the following steps:
  • step S201 of FIG. 17 and (a) of FIG. 18 a second resin material 72 is coated on the surface of the package substrate 2 on which the first chip 1 is integrated, and at a position close to the first chip 1 .
  • the second resin material 72 here serves as a bonding structure for bonding the blocking block on the package substrate.
  • a cofferdam (Dam) may be formed by using a resin material with relatively high viscosity and poor fluidity, and then a resin material with relatively high fluidity is filled in the cofferdam.
  • the multiple blocking blocks are correspondingly arranged at multiple corners of the first chip, and the multiple blocking blocks are connected through the connection structure, then the multiple blocking blocks need to be located at multiple corners of the first chip. Both are coated with the second resin material, so as to fix the plurality of blocking blocks connected together at one time.
  • step S202 of FIG. 17 and (c) of FIG. 18 the blocking block 4 is covered on the second resin material 72 , and the upper surface of the blocking block 4 is made higher than the top surface of the first chip 1 .
  • the blocking block 4 can be a prepared structure, and the structure can be a metal block made of a metal material, a silicon block made of a silicon material, a glass block, or a ceramic block.
  • step S203 of FIG. 17 , and (d) of FIG. 18 the upper surface of the blocking block 4 is flattened.
  • the upper surface of the blocking block is inclined, so the upper surface of the blocking block 4 needs to be flattened.
  • the first surface P1 of the pressing plate 6 can be pressed on the upper surface of the second resin material 72, and the second surface P2 can be pressed on the upper surface of the first chip 1, and the first plane P1 and the second plane P2 are not They are on the same plane, but there is a distance d2 between them as shown in (d) of FIG. 18 .
  • the distance d2 between the first plane and the second plane P2 may be smaller than d1
  • the blocking block is made of metal, glass, ceramics and other materials, and there is only a layer of resin material between the blocking block and the packaging substrate, after the resin material is heated and cured, the shrinkage range is very small, so , d2 can be designed to be smaller.
  • the blocking block is integrally formed by the resin material. After the resin material is heated and cured, the shrinkage range is very large. That is, the design of d1 is larger to prevent the blocking block formed after the heating and curing process.
  • the upper surface is lower than the upper surface of the first chip.
  • the pressing plate 6 can be removed.
  • step S204 of FIG. 17 and (e) of FIG. 18 the second resin material is cured, so that the blocking block 4 is disposed on the package substrate 2 through the cured second resin material.
  • the blocking block can be formed according to the above-mentioned manufacturing process.
  • the manufacturing method may further include: disposing a reinforcement ring (Ring) at a position close to the edge of the package substrate.
  • a reinforcement ring Ring
  • the preparation method may further include: disposing the heat sink 04, and making the heat sink 04 cover the upper surface of the blocking block 4 and the upper surface of the first chip 1, and is connected with the chip packaging structure Electrically connected PCB fixed connections.
  • TIM Before disposing the heat sink 04, TIM can be coated on the upper surface of the first chip 1 and the upper surface of the blocking block 4, and the TIM on the upper surface of the first chip 1 and the TIM on the upper surface of the blocking block 4 can be integrally formed, and then packaged for heat dissipation cover.

Abstract

本申请实施例提供一种芯片封装结构、电子设备及芯片封装结构的制备方法，涉及芯片封装技术领域。该芯片封装结构包括：封装基板、第一芯片和多个阻挡块；第一芯片和多个阻挡块设置在封装基板的同一表面上，且多个阻挡块靠近第一芯片设置，多个阻挡块相对第一芯片对称布设，阻挡块的远离封装基板的表面用于与散热器相抵接；其中，阻挡块的高度大于或等于第一芯片的高度。

Description

一种芯片封装结构、电子设备及芯片封装结构的制备方法 技术领域
本申请涉及芯片封装技术领域，尤其涉及一种芯片封装结构、电子设备及芯片封装结构的制备方法。
背景技术
随着芯片核数和速度的提升，芯片的功耗是越来越高，那么芯片散热问题就尤为的突出。
目前，对芯片进行封装时，一般采用倒装芯片球阵列封装(Flip-Chip Ball Grid Array，FCBGA)。也就是，将芯片的有源面通过球阵列(ball grid array，BGA)集成在封装基板上，芯片的背面位于远离封装基板的一侧。
图1所示的是目前对芯片进行散热的一种结构图，芯片1-1通过FCBGA工艺集成在封装基板1-2上，散热器1-3覆盖在芯片1-1的背面(图1所示的B面)。这样，芯片1-1散发的热量可以传导至散热器1-3，通过散热器1-3将热量扩散出去。
在对图1中的散热器1-3进行安装时，很难保障散热器1-3沿图中的L方向垂直的覆盖在芯片1-1的上方，而是可能会出现图中所示的散热器1-3偏压现象。这样的话，散热器1-3会对芯片1-1背面的边缘产生较大的压力，从而可能会出现芯片1-1被压裂，进而增加产品的不合格率。
发明内容
本申请的实施例提供一种芯片封装结构、电子设备及芯片封装结构的制备方法，主要目的是降低芯片被压裂的风险。
为达到上述目的，本申请的实施例采用如下技术方案：
第一方面，本申请提供了一种芯片封装结构，该芯片封装结构包括：封装基板、第一芯片和多个阻挡块；第一芯片和多个阻挡块设置在封装基板的同一表面上，且多个阻挡块靠近第一芯片设置，多个阻挡块相对第一芯片对称布设，阻挡块的远离封装基板的表面用于与散热器相抵接；其中，阻挡块的高度大于或等于第一芯片的高度。
本申请实施例提供的芯片封装结构，由于在封装基板的集成有第一芯片的表面上设置有多个阻挡块，且多个阻挡块靠近第一芯片并关于第一芯片对称设置。这样的话，当散热器出现偏压而不能垂直的覆盖在第一芯片上表面时，由于阻挡块的高度大于或等于第一芯片的高度，散热器就会抵接在阻挡块上。从而，通过阻挡块对散热器的限位阻挡，就可以阻止散热器对第一芯片产生压力，降低第一芯片被散热器压裂的风险，进而提高封装可靠性。
在第一方面可能的实现方式中，阻挡块靠近第一芯片的角落设置。通常，第一芯片的角落的内应力相比其他位置的内应力大，在受到外部作用力时，很容易被压裂，所以，将阻挡块靠近第一芯片的角落设置。
在第一方面可能的实现方式中，第一芯片的多个角落均设置有阻挡块，每相邻两个角落上的阻挡块之间通过连接结构相连接。当在第一芯片的角落均设置阻挡块时， 可以将多个阻挡块通过连接结构连接在一起，以方便一次性固定这些阻挡块，提高封装效率。
在第一方面可能的实现方式中，阻挡块由树脂材料一体成型。若采用树脂材料形成阻挡块时，在具体制备过程中，可以在封装基板上涂布树脂材料，直接使该树脂材料形成阻挡块，可简化制备工艺。
在第一方面可能的实现方式中，阻挡块由金属、硅、玻璃或者陶瓷材料制得，并通过粘结层与封装基板连接。
在第一方面可能的实现方式中，封装基板上还集成有第二芯片，第一芯片和第二芯片集成在封装基板表面上的第一区域内，多个阻挡块沿第一区域的边缘设置。通过将多个阻挡块沿第一区域的边缘设置，就可以对第一芯片和第二芯片均进行保护。
在第一方面可能的实现方式中，阻挡块的高度与第一芯片的高度的差值小于或等于200微米。若阻挡块的高度与第一芯片的高度的差值较大时，散热器与第一芯片的上表面之间可能会存在较大的间隙，进而会影响对第一芯片的散热效果。
第二方面，本申请实施例还提供了一种芯片封装的制备方法，该制备方法包括：
在封装基板的表面上集成第一芯片；
在集成有第一芯片的封装基板的表面上，且靠近第一芯片，并关于第一芯片对称设置多个阻挡块，且阻挡块的高度大于或等于第一芯片的高度，阻挡块的远离封装基板的表面用于与散热器相抵接。
本申请实施例提供的芯片封装的制备方法中，在集成有第一芯片的封装基板的表面上设置多个阻挡块，且多个阻挡块靠近芯片并相对第一芯片对称设置，还有，阻挡块的高度大于或等于第一芯片的高度，这样制得的芯片封装结构中，在封装散热器时，不会因为散热器的偏压，对第一芯片施加较大的挤压力，从而会降低第一芯片被压裂的风险。
在第二方面可能的实现方式中，在集成有第一芯片的封装基板的表面上设置多个阻挡块，包括：在集成第一芯片的封装基板的表面上，且靠近第一芯片的位置处涂覆第一树脂材料，并使第一树脂材料的上表面高于第一芯片的上表面；压平第一树脂材料的上表面；固化第一树脂材料，以使固化后的第一树脂材料形成阻挡块。这样的话，直接就可使该第一树脂材料固化后形成阻挡块。制备该阻挡块的工艺简单，便于实施。
在第二方面可能的实现方式中，在集成有第一芯片的封装基板的表面上设置多个阻挡块，包括：在集成第一芯片的封装基板的表面上，且靠近第一芯片的位置处涂覆第二树脂材料；将阻挡块覆盖在第二树脂材料上，并使阻挡块的上表面高于第一芯片的上表面；压平阻挡块的上表面；固化第二树脂材料，以使阻挡块通过固化后的第二树脂材料设置在封装基板上。也就是说，将阻挡块通过第二树脂材料粘结在封装基板上。
在第二方面可能的实现方式中，压平第一树脂材料的上表面或者阻挡块的上表面，包括：将压板的第一平面压在阻挡块或第一树脂材料的上表面上，以及第二平面压在第一芯片的上表面上，其中，第一平面和第二平面相平行，且第二平面相对第一平面远离第一芯片的上表面，以使得第一树脂材料的上表面或阻挡块的上表面与第一芯片的上表面相平行。在涂覆第一树脂材料或者设置阻挡块之后，第一树脂材料的上表面 或者阻挡块的上表面可能不是平面，不与芯片的上表面平行，这样的话，通过将压板压在阻挡块的上表面上或者第一树脂材料的上表面上，以使阻挡块的上表面和第一树脂材料的上表面与芯片的上表面相平行。
在第二方面可能的实现方式中，在将压板的第一平面压在阻挡块或第一树脂材料的上表面上，以及第二平面压在第一芯片的上表面上，之前，制备方法还包括：在第一平面上形成分离层，分离层用于使压板对第一树脂材料或者阻挡块施压后，将压板取下。通过在第一平面上涂覆分离层，防止压板与第一树脂材料粘结，不能轻松的取下。
在第二方面可能的实现方式中，在集成有第一芯片的封装基板的表面上设置多个阻挡块之前，制备方法还包括：在第一芯片和封装基板之间填充粘结胶，以形成底胶层。通过填充粘结胶，增加芯片与封装基板的连接强度。
第三方面，本申请还提供了一种电子设备，包括印制电路板和上述第一方面任一实现方式中的芯片封装结构，或者第二方面任一实现方式中的芯片封装结构制备方法制得的芯片封装结构，印制电路板与芯片封装结构电连接，散热器覆盖在第一芯片和阻挡块的上方，并与阻挡块的远离封装基板的表面相抵接，且散热器与印制电路板固定连接。
本申请实施例提供的电子设备包括第一方面实施例或者第二方面实施例制得的芯片封装结构，因此，在封装散热器时，即使散热器出现偏压不能垂直的覆盖在第一芯片的上表面上，通过对称布设的多个阻挡块，降低散热器将第一芯片压裂的风险。
在第三方面可能的实现方式中，第一芯片的远离封装基板的表面上，和阻挡块的远离封装基板的表面上均设置有导热界面材料层，散热器通过导热界面材料层覆盖在第一芯片和阻挡块的上方，且第一芯片上的导热界面材料层，和阻挡块上的导热界面材料层呈一体结构。
附图说明
图1为现有技术中芯片封装结构和散热器的连接关系示意图；
图2为电子设备中的部分结构示意图；
图3a为本申请实施例的芯片封装结构的结构示意图；
图3b为本申请实施例的芯片封装结构和散热器的连接关系示意图；
图4为本申请实施例的芯片封装结构和散热器的连接关系示意图；
图5a为本申请实施例的芯片封装结构的结构示意图；
图5b为本申请实施例的芯片封装结构和散热器的连接关系示意图；
图5c为本申请实施例的芯片封装结构和散热器的连接关系示意图；
图5d为本申请实施例的散热器的结构示意图；
图6a为本申请实施例的散热器偏压时的结构示意图；
图6b为本申请实施例的散热器偏压时的结构示意图；
图7为本申请实施例的芯片封装结构的俯视图；
图8为本申请实施例的芯片封装结构的俯视图；
图9为本申请实施例的芯片封装结构的俯视图；
图10为本申请实施例的芯片封装结构的俯视图；
图11为本申请实施例的芯片封装结构的俯视图；
图12为本申请实施例的芯片封装结构的俯视图；
图13为本申请实施例的芯片封装结构的俯视图；
图14为本申请实施例制得芯片封装结构的方法的流程框图；
图15为本申请实施例制得芯片封装结构的方法的流程框图；
图16为本申请实施例芯片封装结构的制备方法中各步骤完成后相对应的结构示意图；
图17为本申请实施例制得芯片封装结构的方法的流程框图；
图18为本申请实施例芯片封装结构的制备方法中各步骤完成后相对应的结构示意图。
附图标记：
1-1-芯片；1-2-封装基板；1-3-散热器；
01-芯片封装结构；02-PCB；03-电连接结构；04-散热器；041-翅片；042-凹槽；05-紧固件；
1-第一芯片；101-基底；102-金属层；2-封装基板；3-凸点紧固件；4-阻挡块；41-第一阻挡块；42-第二阻挡块；5-底胶层；6-压板；61-凸起；71-第一树脂材料；72-第二树脂材料；8-分离层；9-导热界面材料层；10-加固环；11-连接结构；12-第二芯片；13-第三芯片；14-第四芯片。
具体实施方式
本申请实施例提供一种电子设备。该电子设备可以包括手机(mobile phone)、平板电脑(pad)、智能穿戴产品(例如，智能手表、智能手环)、虚拟现实(virtual reality，VR)设备、增强现实(augmented reality，AR)，还可以是家用电器等设备。本申请实施例对上述电子设备的具体形式不做特殊限制。
如图2所示，上述电子设备可以包括芯片封装结构01以及印制电路板(printed circuit board，PCB)02。芯片封装结构01通过电连接结构03与PCB02电连接，从而使得芯片封装结构01能够与PCB02上的其他芯片或者其他模块实现互连。
该电连接结构03可以是球阵列(ball grid array，BGA)。在可选择的实施方式中，如果芯片封装结构的尺寸比较大。为了保障该芯片封装结构01与PCB02电连接的可靠性，电连接结构03也可以采用带有插槽式连接结构的连接端子(socket)，该连接端子也可以称为连接器、插接器等。
芯片封装结构01中的芯片在工作时，会散发出热量，尤其是随着芯片核数和速度的提升，散发的热量越来越多。为了及时将芯片散发的热量扩散出现，如图2所示，电子设备还包括散热器04，且散热器04覆盖在芯片封装结构01的上方，并与PCB02固定连接。这样的话，芯片封装结构01散发的热量会传导至散热器04，通过具有较大热传导面积的散热器04将热量扩散出去，实现对芯片的降温，保证芯片的正常运行。
在可选择的实施方式中，散热器04通过紧固件05(比如，螺栓，铆钉)与PCB02相对固定。
图2给出的散热器04是一种翅片型结构的散热器，即散热器04的远离芯片的一侧具有多个翅片041。当然，散热器04也可以以其他结构存在。
以下对上述芯片封装结构01的结构进行详细的说明。
如图3a所示的结构中，体现了芯片封装结构01和散热器04的相对位置关系，该芯片封装结构01包括：第一芯片1，用于承载第一芯片1的封装基板2。图3a仅是一种实施例，仅示出了一个第一芯片1，也可能会具有多个芯片，或者具有其他电子器件(比如，晶体管、电阻、电感等)。包括第一芯片1和其他电子器件的结构均被固定在封装基板2上，封装基板2上形成有金属走线，该金属走线形成布线结构，在芯片之间或者芯片与其他电子器件之间建立信号通路，以及将第一芯片和其他电子器件电连接至所述电连接结构。
需要说明的是，本申请涉及的芯片可以是一个裸片(die)，也可以是堆叠的多个die。
本申请实施例中的任一个芯片可以包括基底和金属层。比如，如图4所示，第一芯片1包括基底101和金属层102，金属层102设置有电路结构。且第一芯片1通过倒装封装工艺，将金属层102通过BGA与封装基板2电连接。
在可选择的实施方式中，也可以是基底101靠近封装基板2设置，这样，就需要在基底101内贯通导电通道，导电通道的一端与金属层102电连接，另一端与凸点(bump)电连接，凸点与封装基板2电连接。
除此之外，在将第一芯片或者其他电子器件与封装基板焊接时，由于第一芯片或者其他电子器件与封装基板之间存在热膨胀系数(coefficient of thermal expansion，CTE)失配现象，进而会出现封装后的结构出现翘曲。所以，结合图4，封装基板2上还设置有加固环(Ring)10，且加固环10沿封装基板2的边缘设置。在加固环10对封装基板2的作用下，可抑制翘曲程度。
为了提升第一芯片1与封装基板2之间连接的可靠性，如图4，可以采用点胶工艺，在第一芯片1与封装基板2之间填充底胶层(Underfill)5。
本申请涉及的散热器04是通过导热界面材料(thermal interface material，TIM)层覆盖在第一芯片1的上表面(即第一芯片1的远离封装基板2的表面)上。相比现有技术，没有在第一芯片1上覆盖散热盖(Lid)，再将散热器04通过TIM覆盖在Lid上。所以，相比现有的包含Lid的封装结构，去掉了Lid，以及去掉了Lid与第一芯片之间的TIM，这样的话，就缩短了第一芯片1至散热器04之间的散热路径，明显的提高散热效果，尤其对于功耗较大的芯片，散热效率提升的更加明显。
但是，在封装散热器04时，虽然处于第一芯片1上表面的TIM9具有一定的缓冲效果，由于TIM的高度较小，缓冲效果有限，出现第一芯片被压裂的风险依然很高。
所以，如图3a所示，本申请涉及的该芯片封装结构01还包括多个阻挡块(stopper)4，多个阻挡块4与第一芯片1设置在封装基板2的同一表面上，且多个阻挡块4靠近第一芯片1设置，还有，多个阻挡块4相对第一芯片1对称布设。另外，散热器04也覆盖在阻挡块4的上表面的上方，并且阻挡块4的远离封装基板2的表面与散热器04相抵接。
阻挡块4与第一芯片1的高度之间的关系可以是，如图3a所示，阻挡块4的高度与第一芯片1的高度相等。也可以是，如图5a所示，阻挡块4的高度大于第一芯片1的高度，这里的阻挡块的高度尺寸指的是垂直于封装基板的尺寸，同样的，第一芯片 的高度尺寸指的是垂直于封装基板的尺寸。
也可以这样理解，结合图3a，阻挡块4的与封装基板2相接合的表面，与阻挡块4的与散热器04相结合的表面之间的垂直间距h1为阻挡块4的高度。Die的厚度和凸点3的高度之和h2为第一芯片的高度。如图3a，当h1与h2相等时，则阻挡块4的高度与第一芯片1的高度相等。结合图5a，当h1大于h2时，则阻挡块4的高度大于第一芯片1的高度。
结合图3b，当h1与h2相等时，在芯片封装结构01上覆盖散热盖04之前，可以在第一芯片1的上表面和阻挡块4的上表面上均设置TIM9，又因为阻挡块4距离第一芯片1较近，所以将第一芯片1上的TIM9和阻挡块4上的TIM9呈一体结构布设，再将散热盖04通过TIM9覆盖在第一芯片1和阻挡块4的上方。
结合图5b，当h1大于h2时，在芯片封装结构01上覆盖散热盖04之前，也可以在第一芯片1的上表面和阻挡块4的上表面上均设置TIM9，且第一芯片1上的TIM9和阻挡块4上的TIM9呈一体结构，只是阻挡块4上的TIM9的厚度比第一芯片1上的TIM9的厚度薄，再将散热盖04通过TIM9覆盖在第一芯片1和阻挡块4的上方。
在一些可选择的实施方式中，当h1与h2的差值较大时，也可以采用图5c和图5d所示的结构，在散热盖04的相对第一芯片1的位置处开设凹槽042，在第一芯片1的上表面上设置TIM9，但是，阻挡块4的上表面上不设置TIM，这样的话，在覆盖散热盖04时，位于第一芯片1上的TIM9就会镶嵌在凹槽042内，且阻挡块4与散热盖04抵接。
图6a和图6b所示的结构中，包括了关于第一芯片1对称布设的第一阻挡块41和第二阻挡块42，如图6a所示，散热器04在封装时，若沿S1方向偏压时，由于第一阻挡块41的存在，偏压倾斜的散热器04会抵接在第一阻挡块41上。如图6b所示，若散热器04沿S2方向偏压时，由于第二阻挡块42的存在，偏压倾斜的散热器04会抵接在第二阻挡块42上。所以，不论散热器04沿S1方向偏压，还是沿S2方向偏压，都不会对第一芯片1的局部施加较大的压力，相比现有技术，有效的降低了第一芯片1被压裂的风险，提高芯片封装的可靠性。
当阻挡块4高度h1如图5b所示的大于第一芯片1的高度h2时，会出现第一芯片1与散热器04之间的TIM9的厚度较大，虽然该结构能够阻止第一芯片1被压裂，但是，第一芯片1的上表面与散热器04之间的散热路径较大，会影响对第一芯片的散热效果。
所以，在可选择的实施方式中，h1与h2的差值小于或等于200微米。在另外可选择的实施方式中，h1与h2的差值小于或等于100微米。在另外可选择的实施方式中，h1与h2的差值在10微米左右。
制得阻挡块4的材料具有多种，例如，金属(铜、铝、不锈钢等)。也可以是硅、玻璃、陶瓷等。也可以是树脂材料。
在一些可选择的实施方式中，当选择树脂材料制得阻挡块4时，可以直接在封装基板2上涂覆树脂材料，待树脂材料固化后，就可形成阻挡块4，这样的话，形成的阻挡块4是通过树脂材料一体成型的。
在另外一些可选择的实施方式中，当选择硅、玻璃或者陶瓷等材料制得的阻挡块 时，阻挡块4通过粘结层粘结在封装基板2上。
阻挡块4在封装基板2上的布设方式会具有许多情况，下述分别详细介绍。
图7示出了阻挡块4的一种布设方式，阻挡块4靠近第一芯片1的角落设置。
一般，第一芯片1的横断面为矩形，也就是第一芯片1具有四个侧面，靠近相邻两个侧面的连接处的位置认为是第一芯片1的角落。
第一芯片1内的且靠近角落的位置相比其他位置具有较大的内应力，强度较低，在对该位置施加挤压力时，很容易被压裂，所以，将阻挡块4靠近第一芯片1的角落设置，会有效的阻止芯片角落被压裂。
图8示出了阻挡块4的另一种布设方式，阻挡块4靠近第一芯片1的角落设置，且位于相邻角落的阻挡块4之间通过连接结构11相连接。比如，若阻挡块是由金属材料制得时，可以采用金属片将位于相邻角落的阻挡块4连接。该连接结构11可以与阻挡块1的材料相同，也可以不同。
还有，本申请对连接结构11的高度尺寸不做限定，可以与阻挡块1的高度相等，也可以小于阻挡块的高度，这里的连接结构11的高度尺寸也是垂直于封装基板的尺寸。
如图8所示的将位于相邻角落的阻挡块4之间通过连接结构11相连接时，从制造工艺上讲，可以将多个阻挡块4一次性布设，提高封装效率，比如，该阻挡块4为金属块时，首先在靠近第一芯片四个角落的位置处分别涂覆粘结胶，再将呈一体结构的多个金属块同时覆盖在粘结胶上，相比逐个粘结金属块，会明显的提高效率。
另外，从对芯片的防压裂效果上讲，散热器04在偏压时，通常会压在第一芯片1的两个位置，一个是压在靠近第一芯片角落的位置处，另一个可能会压在靠近第一芯片侧边的位置处，若连接结构11的高度与阻挡块4的高度相等时，不仅防止第一芯片的角落被压裂，也会防止第一芯片的侧边被压裂，阻挡芯片被压裂的风险被进一步提升。
阻挡块的形状会以多种形式存在，示例的，参照图8，阻挡块4的横断面为矩形。再示例的，参照图9，阻挡块4的横断面为圆形。参照图10，阻挡块4的横断面为椭圆形。除上述的这几种结构之外，阻挡块4的横断面还可以是其他形状。本申请对阻挡块的具体形成不做特殊限定。
在可选择的实施方式中，在封装基板2上还会集成第二芯片12，甚至更多的芯片，如图11所示，集成了第一芯片1和第二芯片12；如图12所示，包括第一芯片1和第二芯片12，以及第三芯片13；如图13所示，包括第一芯片1和第二芯片12，以及第三芯片13和第四芯片14。
这些芯片可以分别集成在封装基板2上，且分别通过BGA与封装基板2电连接。也可以是，将这些芯片集成在互连基底上，以形成组合芯片(Combo die)，互连基底再集成在封装基底2上，并与封装基底2电连接。
互连基底可以采用重新布线层(redistribution layer，RDL)，也可以采用转接板(Interposer)。
在如图11、图12和图13所示的结构中，当芯片具有多个时，这些芯片集成在封装基板表面上的第一区域(如图的T区域)内，这样的话，多个阻挡块4靠近第一区域的边缘设置。
在可选择的实施方式中，结合图11至图13，多个阻挡块4设置在第一区域的靠近芯片角落的位置处。
本申请实施例还提供了一种芯片封装结构的制备方法，如图14，该制备方法包括下述步骤：
S1：在封装基板的表面上集成第一芯片；
S2：在集成有第一芯片的封装基板的表面上，且靠近第一芯片，并关于第一芯片对称设置多个阻挡块，且阻挡块的高度大于或等于第一芯片的高度，阻挡块的远离封装基板的表面用于与散热器相抵接。
也就是说，除在封装基板上集成第一芯片之外，还在靠近第一芯片的位置处对称布设多个阻挡块，由于阻挡块的高度大于或等于第一芯片的高度。这样的话，在封装散热器时，即使散热器不能沿着垂直第一芯片上表面的方向设置在芯片的上方，而出现倾斜偏压时，通过阻挡块的限位，可以防止散热器对第一芯片的边缘造成较大的挤压力，以降低芯片被压裂的风险。
上述所述的阻挡块可以是不同的材料制得，比如，该阻挡块可以直接通过涂覆的树脂材料制得，也可以是金属制得，也可以是硅、玻璃等制得。
当阻挡块直接采用树脂材料制得时，制备方法也会不同，下述对该制备方法详细介绍。
当阻挡块为树脂材料一体成型时，制备方法具体包括下述步骤：
[根据细则91更正 24.11.2020]　
如图15的步骤S101，以及图16的(a)，在集成有第一芯片1的封装基板2的表面上，且靠近第一芯片1的位置处涂覆第一树脂材料71，并使第一树脂材料71的上表面高于第一芯片1的上表面。
[根据细则91更正 24.11.2020]　
需要说明的是：结合图16的(a)，第一树脂材料71的上表面Q面指的是：第一树脂材料71的远离封装基板2的面。
在涂覆第一树脂材料71的过程中，可以先采用粘度较高、流动性较差的树脂材料(Epoxy)形成围堰(Dam)，再在围堰内填充(fill)流动性较高的树脂材料，这样可以避免直接涂覆流动性较高的Epoxy时，该Epoxy在封装基板上流动。
在涂覆粘度较高、流动性较差的树脂材料时，围堰Dam的形状决定了最终的阻挡块的横断面的形状。
在可选择的实施方式中，可以仅在第一芯片1的角落涂覆第一树脂材料。在另外可选择的实施方式中，也可以在除第一芯片1的角落之外的，第一芯片的边缘也涂覆第一树脂材料。
[根据细则91更正 24.11.2020]　
在靠近第一芯片1的位置处涂覆第一树脂材料71之后，如图16的(b)，在第一芯片1与封装基板2之间采用点胶工艺，形成底胶层5。
[根据细则91更正 24.11.2020]　
当然，图16中的(b)的工艺步骤可以在(a)之前完成，也就是，先在第一芯片1与封装基板2之间点胶，形成底胶层5，再在靠近第一芯片1的位置处涂覆第一树脂材料71。
在具体实施时，可以优先选用图16所示的先涂覆第一树脂材料，再点胶，原因是：若先在第一芯片1与封装基板2之间点胶，则胶可能会流动至待设置阻挡块的位置处，进而影响第一树脂材料的涂覆。所以，可以先在靠近第一芯片1的位置处涂覆第一树 脂材料71，再在第一芯片1与封装基板2之间点胶。
还有，在涂覆第一树脂材料时，结合图16，需要第一树脂材料71的上表面高于第一芯片1的上表面，因为后续还需要对第一树脂材料固化，在固化的过程中，第一树脂材料会收缩，若第一树脂材料71的上表面低于第一芯片1的上表面或者与第一芯片1的上表面相齐平，在固化后，形成的阻挡块的上表面就会低于第一芯片的上表面，这样，阻挡块就无法起到阻止散热器对第一芯片施压。
[根据细则91更正 24.11.2020]　
如图15的步骤S102，以及图16的(c)，压平第一树脂材料的上表面。
因为在点滴第一树脂材料后，第一树脂材料的上表面不是平面，所以，需要将第一树脂材料的上表面压平。
[根据细则91更正 24.11.2020]　
在可选择的实施方式中，参照图16的(c)，将压板6的第一表面P1压在第一树脂材料71的上表面上，以及第二表面P2压在第一芯片1的上表面上，第一平面P1和第二平面P2相平行，第二平面P2相对第一平面P1远离所述第一芯片1的上表面。即第一平面P1和第二平面P2不处于同一平面上，而是他们之间具有如图16的(c)的间距d1。也可以这样理解，在压板6的相对第一芯片1的位置处形成凸起61。
[根据细则91更正 24.11.2020]　
如图15的步骤S103，以及图16的(d)，固化第一树脂材料，以使固化后的第一树脂材料形成阻挡块4。
上述进行步骤S102的采用压板对第一树脂材料的上表面压平时，该第一树脂材料还具有一定的流动性，在进行步骤S103的对第一树脂材料加热固化时，第一树脂材料会收缩，所以，在加热固化前，采用的压板的第一平面P1和第二平面P2之间具有间距，才可实现固化后形成的阻挡块的高度等于或大于第一芯片的高度。
[根据细则91更正 24.11.2020]　
在采用压板压平第一树脂材料的上表面时，由于第一树脂材料的粘度较高，有可能使压板与第一树脂材料粘结在一起，为了便于将压板取下，可以在使压板压在第一树脂材料的上表面上，以及压在第一芯片的上表面上之前，结合图16中的(c)，在压板6的第一平面P1上形成分离层(detach)8，也可以在第二表面P2上也形成分离层(detach)8，分离层8的作用是在压板在对第一树脂材料施压后，便于将压板取下。
分离层8的材料可以选择随着温度升高，粘性降低的材料，这样的话，在对第一树脂材料加热固化时，分离层随着温度的升高，粘结力会逐渐减小，进而就会使压板6脱离第一树脂材料和第一芯片。
上述在对第一树脂材料加热固化时，压板6仍然固定在第一树脂材料和第一芯片的上方，这样不会因为第一树脂材料的收缩，造成与压板抵接的表面形成凹凸不平的面，以保障最终的阻挡块的上表面与第一芯片上表面相平行。
下述还给出了另外一种制备芯片封装结构的制备方法，该制备方法具体包括下述步骤：
[根据细则91更正 24.11.2020]　
如图17的步骤S201，以及图18的(a)，在集成有第一芯片1的封装基板2的表面上，且靠近第一芯片1的位置处涂覆第二树脂材料72。
此处的第二树脂材料72是作为粘结结构，用于将阻挡块粘结在封装基板上。
在涂覆第二树脂材料72时，也可以先采用粘度较高、流动性较差的树脂材料形成围堰(Dam)，再在围堰内填充(fill)流动性较高的树脂材料。
[根据细则91更正 24.11.2020]　
在靠近第一芯片1的位置处涂覆第二树脂材料72之后，如图18的(b)，在第一 芯片1与封装基板2之间采用点胶工艺，形成底胶层5。
若阻挡块是多个，多个阻挡块是相对应的设置在第一芯片的多个角落的，且多个阻挡块是通过连接结构相连接的，那么，需要在第一芯片的多个角落均涂覆第二树脂材料，以便于将连接在一起的多个阻挡块一次性固定。
[根据细则91更正 24.11.2020]　
如图17的步骤S202，以及图18的(c)，将阻挡块4覆盖在第二树脂材料72上，并使阻挡块4的上表面高于第一芯片1的上表面。
该阻挡块4可以是已经制备好的结构，该结构可以是金属材料制得的金属块，也可以是硅材料制得硅块，也可以是玻璃块，也可以是陶瓷块。
[根据细则91更正 24.11.2020]　
如图17的步骤S203，以及图18的(d)，压平阻挡块4的上表面。
再将阻挡块4覆盖在第二树脂材料上之后，阻挡块的上表面是倾斜的，所以，需要将阻挡块4的上表面压平。
[根据细则91更正 24.11.2020]　
同样的，可以将压板6的第一表面P1压在第二树脂材料72的上表面上，以及第二表面P2压在第一芯片1的上表面上，第一平面P1和第二平面P2不处于同一平面上，而是他们之间具有如图18的(d)的间距d2。
[根据细则91更正 24.11.2020]　
图16的(c)和图18的(d)相比，当阻挡块是由金属、陶瓷、玻璃等材料制得时，第一平面与第二平面P2之间的间距d2可以比d1小，因为在图18中，阻挡块是由金属、玻璃、陶瓷等材料制得，阻挡块和封装基板之间仅有一层树脂材料，在树脂材料被加热固化后，收缩的范围是很小的，所以，可以将d2设计的较小。在图16中，阻挡块是由树脂材料一体成型的，在树脂材料被加热固化后，收缩的范围是很大的，即将d1设计的较大，防止经加热固化工艺后，形成的阻挡块的上表面低于第一芯片的上表面。
在完成上述的步骤S203后，就可以将压板6移除。
[根据细则91更正 24.11.2020]　
如图17的步骤S204，以及图18的(e)，固化第二树脂材料，以使阻挡块4通过固化后的第二树脂材料设置在封装基板2上。
在图16和图18所示的制备方法中，当集成在封装基板上的芯片还包括第二芯片或者更多的芯片时，可以按照上述制备过程形成阻挡块。
设置阻挡块之后，该制备方法还可以包括：在封装基板的靠近边缘的位置处设置加固环(Ring)。
在设置阻挡块之后，该制备方法还可以包括：设置散热器04，并使散热器04覆盖在阻挡块4的上表面的上方，和第一芯片1的上表面的上方，并与芯片封装结构电连接的PCB固定连接。
在设置散热器04的过程中，即使散热器04不能垂直的覆盖在第一芯片1的上方，而是倾斜的压在阻挡块4上方，这样一来，散热器04不会压在强度较低的芯片上，从而阻止芯片被压裂，提高芯片封装的可靠性。
在设置散热器04之前，可以在第一芯片1上表面和阻挡块4上表面涂覆TIM，并使得第一芯片1上表面的TIM和阻挡块4上表面的TIM一体成型，然后再封装散热盖。
在本说明书的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任 何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (14)

  1. 一种芯片封装结构，其特征在于，包括：
    封装基板；
    第一芯片；
    多个阻挡块，所述第一芯片和所述多个阻挡块设置在所述封装基板的同一表面上，所述多个阻挡块靠近所述第一芯片设置，且所述多个阻挡块相对所述第一芯片对称布设，所述阻挡块的远离所述封装基板的表面用于与散热器相抵接；其中，所述阻挡块的高度大于或等于所述第一芯片的高度。
  2. 根据权利要求1所述的芯片封装结构，其特征在于，所述阻挡块靠近所述第一芯片的角落设置。
  3. 根据权利要求1或2所述的芯片封装结构，其特征在于，所述第一芯片的多个角落均设置有所述阻挡块，每相邻两个角落上的所述阻挡块之间通过连接结构相连接。
  4. 根据权利要求1-3中任一项所述的芯片封装结构，其特征在于，所述阻挡块由金属、硅、玻璃或者陶瓷材料制得，并通过粘结层与所述封装基板连接。
  5. 根据权利要求1-3中任一项所述的芯片封装结构，其特征在于，所述阻挡块由树脂材料一体成型。
  6. 根据权利要求1-5中任一项所述的芯片封装结构，其特征在于，所述封装基板上还集成有第二芯片，所述第一芯片和所述第二芯片集成在所述封装基板表面上的第一区域内，所述多个阻挡块沿所述第一区域的边缘设置。
  7. 一种芯片封装结构的制备方法，其特征在于，包括：
    在封装基板的表面上集成第一芯片；
    在集成有所述第一芯片的封装基板的表面上，且靠近所述第一芯片，并关于所述第一芯片对称设置多个阻挡块，且所述阻挡块的高度大于或等于所述第一芯片的高度，所述阻挡块的远离所述封装基板的表面用于与散热器相抵接。
  8. 根据权利要求7所述的芯片封装结构的制备方法，其特征在于，在集成有所述第一芯片的封装基板的表面上设置多个阻挡块，包括：
    在集成有所述第一芯片的所述封装基板的表面上，且靠近所述第一芯片的位置处涂覆第一树脂材料，并使所述第一树脂材料的上表面高于所述第一芯片的上表面；
    压平所述第一树脂材料的上表面；
    固化所述第一树脂材料，以使固化后的所述第一树脂材料形成所述阻挡块。
  9. 根据权利要求7所述的芯片封装结构的制备方法，其特征在于，在集成有所述第一芯片的封装基板的表面上设置多个阻挡块，包括：
    在集成有所述第一芯片的所述封装基板的表面上，且靠近所述第一芯片的位置处涂覆第二树脂材料；
    将所述阻挡块覆盖在所述第二树脂材料上，并使所述阻挡块的上表面高于所述第一芯片的上表面；
    压平所述阻挡块的上表面；
    固化所述第二树脂材料，以使所述阻挡块通过固化后的所述第二树脂材料设置在所述封装基板上。
  10. 根据权利要求8或9所述的芯片封装结构的制备方法，其特征在于，压平所述第一树脂材料的上表面或者阻挡块的上表面，包括：
    将压板的第一平面压在所述阻挡块或所述第一树脂材料的上表面上，以及第二平面压在所述第一芯片的上表面上，其中，所述第一平面和所述第二平面相平行，且所述第二平面相对所述第一平面远离所述第一芯片的上表面，以使得所述第一树脂材料的上表面或所述阻挡块的上表面与所述第一芯片的上表面相平行。
  11. 根据权利要求10所述的芯片封装结构的制备方法，其特征在于，在将所述压板的第一平面压在所述阻挡块或所述第一树脂材料的上表面上，以及第二平面压在所述第一芯片的上表面上，之前，所述制备方法还包括：
    在所述第一平面上形成分离层，所述分离层用于使所述压板对所述第一树脂材料或者阻挡块施压后，将所述压板取下。
  12. 根据权利要求7-11中任一项所述的芯片封装结构的制备方法，其特征在于，在集成有所述第一芯片的封装基板的表面上设置所述多个阻挡块之前，所述制备方法还包括：
    在所述第一芯片和所述封装基板之间填充粘结胶，以形成底胶层。
  13. 一种电子设备，其特征在于，包括：
    印制电路板；
    如权利要求1～6中任一项所述的芯片封装结构，或者如权利要求7～12中任一项所述的芯片封装结构的制备方法制得的芯片封装结构，所述芯片封装结构与所述印制电路板电连接；
    所述散热器覆盖在所述第一芯片和所述阻挡块的上方，并与所述阻挡块的远离所述封装基板的表面相抵接，且所述散热器与所述印制电路板固定连接。
  14. 根据权利要求13所述的电子设备，其特征在于，所述第一芯片的远离所述封装基板的表面上，和所述阻挡块的远离所述封装基板的表面上均设置有导热界面材料层，所述散热器通过所述导热界面材料层覆盖在所述第一芯片和所述阻挡块的上方，且所述第一芯片上的所述导热界面材料层，和所述阻挡块上的所述导热界面材料层呈一体结构。
PCT/CN2020/117768 2020-09-25 2020-09-25 一种芯片封装结构、电子设备及芯片封装结构的制备方法 WO2022061719A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2020/117768 WO2022061719A1 (zh) 2020-09-25 2020-09-25 一种芯片封装结构、电子设备及芯片封装结构的制备方法
CN202080104879.8A CN116134613A (zh) 2020-09-25 2020-09-25 一种芯片封装结构、电子设备及芯片封装结构的制备方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/117768 WO2022061719A1 (zh) 2020-09-25 2020-09-25 一种芯片封装结构、电子设备及芯片封装结构的制备方法

Publications (1)

Publication Number Publication Date
WO2022061719A1 true WO2022061719A1 (zh) 2022-03-31

Family

ID=80846002

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/117768 WO2022061719A1 (zh) 2020-09-25 2020-09-25 一种芯片封装结构、电子设备及芯片封装结构的制备方法

Country Status (2)

Country Link
CN (1) CN116134613A (zh)
WO (1) WO2022061719A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1374693A (zh) * 2001-03-09 2002-10-16 矽品精密工业股份有限公司 具有散热结构的半导体封装件
CN1387252A (zh) * 2001-05-21 2002-12-25 矽品精密工业股份有限公司 具散热结构的半导体封装件
US6753602B2 (en) * 2001-04-18 2004-06-22 Siliconware Precision Industries Co., Ltd. Semiconductor package with heat-dissipating structure and method of making the same
US7030484B1 (en) * 2004-04-14 2006-04-18 Sun Microsystems, Inc. Lidless chip package effectively having co-planar frame and semiconductor die surfaces
CN210040197U (zh) * 2019-05-08 2020-02-07 青岛海信电器股份有限公司 一种芯片封装结构

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1374693A (zh) * 2001-03-09 2002-10-16 矽品精密工业股份有限公司 具有散热结构的半导体封装件
US6753602B2 (en) * 2001-04-18 2004-06-22 Siliconware Precision Industries Co., Ltd. Semiconductor package with heat-dissipating structure and method of making the same
CN1387252A (zh) * 2001-05-21 2002-12-25 矽品精密工业股份有限公司 具散热结构的半导体封装件
US7030484B1 (en) * 2004-04-14 2006-04-18 Sun Microsystems, Inc. Lidless chip package effectively having co-planar frame and semiconductor die surfaces
CN210040197U (zh) * 2019-05-08 2020-02-07 青岛海信电器股份有限公司 一种芯片封装结构

Also Published As

Publication number Publication date
CN116134613A (zh) 2023-05-16

Similar Documents

Publication Publication Date Title
US8378480B2 (en) Dummy wafers in 3DIC package assemblies
TWI529878B (zh) 集成電路封裝件及其裝配方法
US7843058B2 (en) Flip chip packages with spacers separating heat sinks and substrates
US7566591B2 (en) Method and system for secure heat sink attachment on semiconductor devices with macroscopic uneven surface features
TWM572570U (zh) 積體電路封裝及其之蓋子
US8901732B2 (en) Semiconductor device package and method
JP5983032B2 (ja) 半導体パッケージ及び配線基板ユニット
US7906857B1 (en) Molded integrated circuit package and method of forming a molded integrated circuit package
US9633978B2 (en) Semiconductor device and method of manufacturing the same
TW202127591A (zh) 半導體結構及其製造方法
US20230238302A1 (en) Semiconductor package having liquid-cooling lid
US20060273467A1 (en) Flip chip package and method of conducting heat therefrom
TWI658549B (zh) 散熱型封裝結構
TW587325B (en) Semiconductor chip package and method for manufacturing the same
WO2022061719A1 (zh) 一种芯片封装结构、电子设备及芯片封装结构的制备方法
CN114823573B (zh) 一种散热型封装结构及其形成方法
TWI721898B (zh) 半導體封裝結構
CN108281398B (zh) 半导体封装件及其制造方法
WO2022061682A1 (zh) 一种封装结构及封装方法、电子装置及其制造方法
US20230048302A1 (en) Package structure and manufacturing method thereof
WO2023184414A1 (zh) 芯片封装结构、电子设备及芯片封装结构的制备方法
WO2022193133A1 (zh) 封装结构及其制作方法、终端设备
TWI735398B (zh) 電子封裝件及其製法
US20230024043A1 (en) Semiconductor Packages with Thermal Lid and Methods of Forming the Same
TWI806343B (zh) 半導體封裝及其製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20954571

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20954571

Country of ref document: EP

Kind code of ref document: A1