WO2022057382A1 - 半导体器件及其制备方法、存储装置 - Google Patents

半导体器件及其制备方法、存储装置 Download PDF

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WO2022057382A1
WO2022057382A1 PCT/CN2021/103745 CN2021103745W WO2022057382A1 WO 2022057382 A1 WO2022057382 A1 WO 2022057382A1 CN 2021103745 W CN2021103745 W CN 2021103745W WO 2022057382 A1 WO2022057382 A1 WO 2022057382A1
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layer
semiconductor substrate
isolation
wire
semiconductor device
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PCT/CN2021/103745
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English (en)
French (fr)
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舒月姣
蔡明蒲
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长鑫存储技术有限公司
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Priority to US17/468,793 priority Critical patent/US11985810B2/en
Publication of WO2022057382A1 publication Critical patent/WO2022057382A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines

Definitions

  • the present disclosure relates to the technical field of semiconductors, and in particular, to a semiconductor device and a method for fabricating the semiconductor device, and a storage device including the semiconductor device.
  • DRAM Dynamic Random Access Memory
  • Each memory cell usually includes a capacitor and a transistor; the gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor; the voltage signal on the word line can control the opening or closing of the transistor, and then through the bit line The data information stored in the capacitor is read, or the data information is written into the capacitor through the bit line for storage.
  • the purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art, and to provide a semiconductor device, a method for manufacturing the semiconductor device, and a storage device including the semiconductor device.
  • a semiconductor device comprising a semiconductor substrate, a plurality of strip-shaped stacked structures and a spacer structure covering the periphery of the stacked structures are provided on the semiconductor substrate, A conductive structure is provided on a side of the stacked structure away from the semiconductor substrate;
  • the stacked structure includes:
  • a wire layer disposed on the semiconductor substrate, and the wire layer is used for transmitting data signals
  • an isolation layer disposed on the side of the wire layer away from the semiconductor substrate
  • the isolation layer is a low dielectric constant material
  • a dielectric layer is provided on the side of the isolation layer away from the semiconductor substrate, and the dielectric layer is used for isolating the isolation layer and the conductive structure.
  • the material of the isolation layer is methylsilsesquioxane, the dielectric constant thereof is 2.6, and the thickness of the isolation layer is greater than or equal to 8 nm and less than or equal to 12 nm.
  • the thickness of the insulating layer is greater than or equal to 8 nm and less than or equal to 12 nm, and the material thereof is silicon nitride.
  • the thickness of the dielectric layer is greater than or equal to 120 nm and less than or equal to 160 nm, and the material thereof is silicon nitride.
  • the stacked structure further includes:
  • the wire adhesion layer is arranged between the wire layer and the semiconductor substrate.
  • the wire adhesion layer is made of polysilicon, and its thickness is greater than or equal to 60 nm and less than or equal to 70 nm.
  • the conductive structure includes:
  • a conductive layer disposed on the side of the stacked structure away from the semiconductor substrate, the conductive layer is connected to the capacitive contact;
  • the capacitor structure is arranged on the side of the conductive layer away from the semiconductor substrate, and the capacitor structure is connected to the conductive layer.
  • a method for fabricating a semiconductor device comprising:
  • a wire material layer, an isolation material layer, an isolation material layer and a dielectric material layer are sequentially formed on the semiconductor substrate;
  • a conductive structure is formed on a side of the stacked structure remote from the semiconductor substrate.
  • forming the isolation material layer includes:
  • the methylsilsesquioxane and n-tetradecane of the set ratio are mixed to form a mixed solution;
  • the films were dried in a protective atmosphere.
  • the protective atmosphere is nitrogen.
  • the preparation method before forming the wire material layer, the preparation method further includes:
  • the wire adhesion material layer is etched to form a wire adhesion layer.
  • a storage device comprising: the semiconductor device described in any one of the above.
  • the present disclosure has at least one of the following advantages and positive effects:
  • an isolation layer is provided on the side of the wire layer away from the semiconductor substrate, an isolation layer is provided on the side of the isolation layer away from the semiconductor substrate, and an isolation layer is provided on the side of the isolation layer away from the semiconductor substrate
  • the conductor layer and the isolation layer can be isolated by the isolation layer, and the isolation layer can be isolated from the conductive structure through the dielectric layer.
  • the isolation layer is a material with low dielectric constant. Reduce the impact of parasitic capacitance on the quality and life of semiconductor device use.
  • FIG. 1 is a schematic structural diagram of an exemplary embodiment of a semiconductor device of the present disclosure
  • FIG. 2 is a schematic flow diagram of an exemplary embodiment of a method for fabricating a semiconductor device of the present disclosure
  • FIG. 3 is a schematic structural diagram of a semiconductor substrate of the semiconductor device of the present disclosure.
  • FIG. 4 is a schematic structural diagram after forming a wire material layer, an insulating material layer, an insulating material layer and a dielectric material layer on the basis of FIG. 3;
  • FIG. 5 is a schematic structural diagram of forming a stacked structure on the basis of FIG. 4;
  • FIG. 6 is a schematic structural diagram of forming a sidewall material layer on the basis of FIG. 5 .
  • word line 31, word line trench; 32, inter-gate dielectric layer; 33, first conductive layer; 34, second conductive layer; 35, insulating layer;
  • wire adhesion material layer 51, wire adhesion material layer; 52, wire material layer; 53, insulating material layer; 54, insulating material layer; 55, dielectric material layer;
  • the bit line contacts the trench; 9. The bit line.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • the parasitic capacitance between the bit line (BL) and the BL is widely concerned, but the bit line and the conductive structure above it will also generate parasitic capacitance.
  • the existence of the parasitic capacitance will affect the performance of the semiconductor device. performance, affecting the running speed and refresh rate, etc.
  • the semiconductor device may include a semiconductor substrate 1 on which a plurality of strip-shaped stacked structures 6 are arranged and covered on the semiconductor substrate 1 .
  • word lines 3 and shallow trench isolation structures 4 are provided in the semiconductor substrate 1 , and the shallow trench isolation structures 4 divide the semiconductor substrate 1 into a plurality of active regions 2 .
  • a word line trench 31 is provided in the semiconductor substrate 1, an inter-gate dielectric layer 32 is provided in the word line trench 31, and the inter-gate dielectric layer 32 covers the sidewalls and the bottom of the word line trench 31; the inter-gate dielectric layer
  • the material of 32 can include but not limited to at least one of silicon oxide and silicon nitride; can adopt atomic layer deposition process (Atomic Layer Deposition), plasma vapor deposition process (Chemical Vapor Deposition) or rapid thermal oxidation process (Rapid Thermal Oxidation) ) to form the inter-gate dielectric layer 32 .
  • a first conductive layer 33 and a second conductive layer 34 are disposed in the word line trench 31 .
  • the first conductive layer 33 covers the sidewall of the inter-gate dielectric layer 32 and the bottom of the inter-gate dielectric layer 32
  • the second conductive layer 34 fills the Filling the gap inside the first conductive layer 33
  • the upper surfaces of the first conductive layer 33 and the second conductive layer 34 are both lower than the upper surface of the semiconductor substrate 1, and the upper surface of the second conductive layer 34 is higher than the first conductive layer.
  • the upper surface of 33; the material of the first conductive layer 33 may include any one of As or B-doped silicon, P or As-doped germanium, W, Ti, TiN and Ru, and the material of the second conductive layer 34 It can include any one of W, Ti, Ni, Al and Pt, and the materials of the first conductive layer 33 and the second conductive layer 34 are different; the first conductive layer 33 and the second conductive layer 34 can adopt the atomic layer deposition process or plasma vapor deposition process.
  • a filled insulating layer 35 is arranged in the word line trench 31, the filled insulating layer 35 covers the upper surface of the first conductive layer 33 and the upper surface of the second conductive layer 34, and fills the word line trench 31; the filled insulating layer 35
  • the material can include any suitable insulating material including oxides (eg, silicon oxide, aluminum oxide, hafnium oxide, etc.), silicon nitride, silicon oxynitride, and the like.
  • a bit line contact trench 8 may also be provided on the semiconductor substrate 1 , and the bit line 9 is provided in the bit line contact trench 8 and protrudes from the bit line contact trench 8 .
  • a plurality of strip-shaped stacked structures 6 are provided on the semiconductor substrate 1 , and the outer periphery of the stacked structures 6 is covered with a spacer structure 71 , and the stacked structure 6 and the spacer structure 71 form the position of the semiconductor device.
  • the laminated structure 6 may include a wire adhesion layer 61 , a wire layer 62 , an isolation layer 63 , an isolation layer 64 and a dielectric layer 65 .
  • the wire adhesion layer 61 can be disposed on the semiconductor substrate 1 , and the wire adhesion layer 61 can be made of polysilicon (Polysilicon), and its thickness is greater than or equal to 60 nm and less than or equal to 70 nm.
  • the wire layer 62 is disposed on the side of the wire adhesion layer 61 away from the semiconductor substrate 1 .
  • the wire layer 62 can be made of titanium, tungsten, etc., and its thickness is greater than or equal to 25 nm and less than or equal to 30 nm.
  • the insulating layer 63 is disposed on the side of the wire layer 62 away from the semiconductor substrate 1 .
  • the insulating layer 63 can be made of silicon nitride, and its thickness is greater than or equal to 8 nm and less than or equal to 12 nm, preferably 10 nm.
  • the isolation layer 64 is disposed on the side of the isolation layer 63 away from the semiconductor substrate 1 .
  • the isolation layer 64 can be made of methylsilsesquioxane (SiLK), and its thickness is greater than or equal to 8 nm and less than or equal to 12 nm, preferably 10 nm.
  • the dielectric layer 65 is disposed on the side of the isolation layer 64 away from the semiconductor substrate 1 .
  • the dielectric layer 65 can be made of silicon nitride, and its thickness is greater than or equal to 120 nm and less than or equal to 160 nm, preferably 140 nm.
  • the dielectric constant of methylsilsesquioxane is relatively low, about 2.6, and methylsilsesquioxane is relatively easy to control its pore size by introducing microvoids with a diameter of 2-5 nm and making it They are closed to each other, so that they have high mechanical modulus and mechanical strength; a certain external force may be applied during the subsequent chemical mechanical polishing (CMP) and packaging operations, and the isolation layer with high mechanical strength will protect the bit line structure This in turn protects the entire semiconductor structure.
  • CMP chemical mechanical polishing
  • the chemical properties of the material are relatively stable, and can still maintain stable properties at high temperatures. Therefore, even if there is a high temperature requirement in the subsequent process, the performance of the semiconductor device will not be affected.
  • the material of the isolation layer 64 may also be silicon dioxide, and the dielectric constant of silicon dioxide is about 3.9, and other low-dielectric constant materials may also be used, which may be Methylsilsesquioxane (MSQ) or porous HSQ (porous hydrogenated silsesquioxane).
  • MSQ Methylsilsesquioxane
  • HSQ porous hydrogenated silsesquioxane
  • the spacer structure 71 is not only provided on the periphery of the stacked structure 6 but also covers the semiconductor substrate 1 where the stacked structure 6 is not provided.
  • the sidewall structure 71 may cover the entire laminated structure 6 .
  • the height of the spacer structure 71 is at least higher than the height of the isolation layer 64 , that is, the distance between the side of the spacer structure 71 away from the semiconductor substrate 1 and the semiconductor substrate 1 is greater than that of the isolation layer
  • the distance between the side of the 64 away from the semiconductor substrate 1 and the semiconductor substrate 1 enables the spacer structure 71 to completely cover the isolation layer 64 to prevent the isolation layer 64 from being exposed to subsequent processes.
  • the stacked structure 6 and the spacer structure 71 form the bit line 9 .
  • a conductive structure is provided on the side of the bit line 9 away from the semiconductor substrate 1 , and the conductive structure may include a capacitance structure and a conductive layer, and the conductive layer is located on a side of the bit line 9 away from the semiconductor substrate 1 .
  • the conductive layer is connected to the capacitive contact, the capacitive structure is located on the side of the conductive layer away from the semiconductor substrate 1, the conductive layer is connected to the capacitive structure, and the capacitive structure is connected to the capacitive contact.
  • an isolation layer 63 is provided on the side of the wire layer 62 away from the semiconductor substrate 1
  • an isolation layer 64 is provided on the side of the isolation layer 63 away from the semiconductor substrate 1
  • an isolation layer 64 is provided on the side of the isolation layer 63 away from the semiconductor substrate 1
  • a dielectric layer 65 is provided on one side of the semiconductor substrate 1
  • a conductive structure is provided on the side of the dielectric layer 65 away from the semiconductor substrate 1 .
  • the conductor layer 62 and the isolation layer 64 can be isolated by the isolation layer 63, and the isolation layer 64 can be isolated from the conductive structure by the dielectric layer 65.
  • the isolation layer 64 is a low dielectric constant material.
  • the parasitic capacitance generated by the structure can reduce the RC delay, crosstalk and power consumption of the semiconductor device, avoid affecting the operating speed and refresh frequency, etc., thereby effectively reducing the impact of the parasitic capacitance on the quality and life of the semiconductor device.
  • the present exemplary embodiment also provides a method for fabricating a semiconductor device.
  • the method for fabricating a semiconductor device may include the following steps:
  • step S10 a semiconductor substrate 1 is provided.
  • Step S20 a wire material layer 52 , an isolation material layer 53 , an isolation material layer 54 and a dielectric material layer 55 are sequentially formed on the semiconductor substrate 1 .
  • Step S30 etching the dielectric material layer 55 , the isolation material layer 54 , the isolation material layer 53 and the wire material layer 52 to form a plurality of strip-shaped stacked structures 6 .
  • Step S40 forming a sidewall structure 71 on the periphery of the stacked structure 6 .
  • Step S50 forming a conductive structure on the side of the stacked structure 6 away from the semiconductor substrate 1 .
  • step S10 a semiconductor substrate 1 is provided.
  • the semiconductor substrate 1 may include, but is not limited to, a single crystal silicon substrate, a polycrystalline silicon substrate, a gallium nitride substrate or a sapphire substrate.
  • the semiconductor substrate 11 When it is a single crystal substrate or a polycrystalline substrate, it can also be an intrinsic silicon substrate or a lightly doped silicon substrate, and further, it can be an N-type polysilicon substrate or a P-type polysilicon substrate.
  • Step S20 a wire material layer 52 , an isolation material layer 53 , an isolation material layer 54 and a dielectric material layer 55 are sequentially formed on the semiconductor substrate 1 .
  • a wire adhesion material layer 51 is formed on the semiconductor substrate 1 by a CVD (Chemical Vapor Deposition) process.
  • the deposition gas can be Si 2 H 6 , SiH 4 , PH 3 , LTO520 ( Precursor: one or more of SiH3N(C3H7)2).
  • the wire material layer 52 is formed by a PVD (Physical Vapor Deposition, physical vapor deposition) process on the side of the wire adhesion material layer 51 away from the semiconductor substrate 1.
  • the target material can be tungsten, titanium, etc.
  • the insulating material layer 53 is formed on the side of the wire material layer 52 away from the semiconductor substrate 1 by a low pressure chemical vapor deposition (Low Pressure Chemical Vapour Deposition, LPCVD) or an atomic layer deposition (Atomic layer deposition, ALD) process, and the deposition material is Silicon Nitride.
  • the main deposition gases were SiCl 2 H 2 and NH 3 .
  • the isolation material layer 54 is formed on the side of the isolation material layer 53 away from the semiconductor substrate 1 .
  • the protective atmosphere can be nitrogen, of course, helium can be used as the protective atmosphere.
  • the set ratio may be 30% to 50% of n-tetradecane to methylsilsesquioxane.
  • a dielectric material layer 55 is formed on the side of the isolation material layer 54 away from the semiconductor substrate 1 by LPCVD or atomic layer deposition (Atomic layer deposition, ALD) process, and the deposition material is silicon nitride.
  • the main deposition gases were SiCl 2 H 2 and NH 3 .
  • Step S30 etching the dielectric material layer 55 , the isolation material layer 54 , the isolation material layer 53 and the wire material layer 52 to form a plurality of strip-shaped stacked structures 6 .
  • a photoresist layer may be formed on the side of the dielectric material layer 55 away from the semiconductor substrate 1 , and a mask plate may be arranged on the photoresist layer, and the photoresist Then, the photoresist layer that is not covered by the mask plate is removed, and then the remaining photoresist layer is used as a mask, and the dielectric material layer 55, the isolation material layer 54, the isolation material layer 53, the wire material layer 52 And the wire adhesion material layer 51 is dry etched to form a plurality of strip-shaped dielectric layers 65 , isolation layers 64 , isolation layers 63 , wire layers 62 and wire adhesion layers 61 , ie, to form a plurality of strip-shaped laminated structures 6 .
  • Step S40 forming a sidewall structure 71 on the periphery of the stacked structure 6 .
  • a spacer material layer 7 can be formed on the semiconductor substrate 1 and on the side of the stacked structure 6 away from the semiconductor substrate 1 by low pressure chemical vapor deposition, and the spacer The height of the material layer 7 is higher than that of the dielectric layer 65 . Then, the sidewall material layer 7 is etched to retain the sidewall material layer 7 of the sidewall of the stacked structure 6 and a part of the sidewall material layer 7 on the semiconductor substrate 1 to form a sidewall structure 71 .
  • the thickness of the material layer 7 is basically the same, which is greater than or equal to 7 nm and less than or equal to 9 nm, that is, a schematic structural diagram of the semiconductor device shown in FIG. 1 is formed.
  • the stacked structure 6 and the spacer structure 71 form the bit line 9 of the semiconductor device.
  • Step S50 forming a conductive structure on the side of the stacked structure 6 away from the semiconductor substrate 1 .
  • the conductive structure may include a capacitive structure and a conductive layer.
  • the specific structure of the conductive structure has been described in detail above, so it will not be repeated here.
  • the beneficial effects of the method for fabricating a semiconductor device provided by the exemplary embodiments of the present disclosure are the same as those of the semiconductor device provided by the above-described exemplary embodiments, which are not repeated here.
  • the present exemplary embodiment further provides a storage device, and the storage device may include the semiconductor device described in any one of the above.
  • the specific structure of the semiconductor device has been described in detail above, so it will not be repeated here.
  • the beneficial effects of the storage device provided by the exemplary embodiments of the present disclosure are the same as the beneficial effects of the semiconductor device provided by the above-described exemplary embodiments, which will not be repeated here.
  • the terms “a”, “an”, “the” and “said” are used to indicate the presence of one or more elements/components/etc.; the terms “comprising”, “including” and “having” are used for Indicates an open-ended inclusive meaning and means that additional elements/components/etc may be present in addition to the listed elements/components/etc; the terms “first”, “second” and “third” ”, etc. are used only as markers, not as restrictions on the number of objects.

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Abstract

一种半导体器件及其制备方法、存储装置。该半导体器件包括半导体衬底（1），在半导体衬底（1）之上设有多个条状的层叠结构（6）及覆盖于层叠结构（6）外围的侧墙结构（71），在层叠结构（6）的远离半导体衬底（1）的一侧设有导电结构；层叠结构（6）包括导线层（62）、隔绝层（63）、隔离层（64）及介质层（65）；导线层（62）设于半导体衬底（1）之上，导线层（62）用于传输数据信号；隔绝层（63）设于导线层（62）的远离半导体衬底（1）的一侧；隔离层（64）设于隔绝层（63）的远离半导体衬底（1）的一侧，隔离层（64）是低介电常数材料；介质层（65）设于隔离层（64）的远离半导体衬底（1）的一侧，介质层（65）用于隔离隔离层（64）与导电结构。通过隔离层（64）可以有效降低导线层（62）与导电结构产生的寄生电容，从而有效降低寄生电容对半导体器件使用的质量和寿命的影响。

Description

半导体器件及其制备方法、存储装置
交叉引用
本公开要求于2020年9月15日提交的申请号为202010969793.3名称为“半导体器件及其制备方法、存储装置”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体技术领域，尤其涉及一种半导体器件及半导体器件的制备方法、包括该半导体器件的存储装置。
背景技术
动态随机存储器(Dynamic Random Access Memory，简称：DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。每个存储单元通常包括电容器和晶体管；晶体管的栅极与字线相连、漏极与位线相连、源极与电容器相连；字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或者通过位线将数据信息写入到电容器中进行存储。
上述这些结构导致动态随机存储器中存在众多的寄生电容，这些寄生电容严重影响芯片使用的质量和寿命。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
本公开的目的在于克服上述现有技术的不足，提供一种半导体器件及半导体器件的制备方法、包括该半导体器件的存储装置。
根据本公开的一个方面，提供一种半导体器件，包括半导体衬底，在所述半导体衬底之上设置有多个条状的层叠结构以及覆盖于所述层叠结构外围的侧墙结构，在所述层叠结构的远离所述半导体衬底的一侧设置有导电结构；
所述层叠结构包括：
导线层，设于所述半导体衬底之上，所述导线层用于传输数据信号；
隔绝层，设于所述导线层的远离所述半导体衬底的一侧；
隔离层，设于所述隔绝层的远离所述半导体衬底的一侧，所述隔离层是低介电常数材料；
介质层，设于所述隔离层的远离所述半导体衬底的一侧，所述介质层用于隔离所述隔离层与所述导电结构。
在本公开的一种示例性实施例中，所述隔离层的材质是甲基硅倍半氧烷，其介电常数为2.6，所述隔离层的厚度大于等于8nm且小于等于12nm。
在本公开的一种示例性实施例中，所述隔绝层的厚度大于等于8nm且小于等于12nm，其材质是氮化硅。
在本公开的一种示例性实施例中，所述介质层的厚度大于等于120nm且小于等于160nm，其材质是氮化硅。
在本公开的一种示例性实施例中，所述层叠结构还包括：
导线黏附层，设于所述导线层与所述半导体衬底之间，所述导线黏附层的材质是多晶硅，其厚度大于等于60nm且小于等于70nm。
在本公开的一种示例性实施例中，所述导电结构包括：
导电层，设于所述层叠结构的远离半导体衬底的一侧，所述导电层连接于电容触点；
电容结构，设于所述导电层的远离半导体衬底的一侧，所述电容结构连接于所述导电层。
根据本公开的一个方面，提供一种半导体器件的制备方法，包括：
提供一半导体衬底；
在所述半导体衬底之上依次形成导线材料层、隔绝材料层、隔离材料层以及介质材料层；
对所述介质材料层、所述隔离材料层、所述隔绝材料层以及所述导线材料层刻蚀形成多个条状的层叠结构；
在所述层叠结构外围形成侧墙结构；
在所述层叠结构的远离所述半导体衬底的一侧形成导电结构。
在本公开的一种示例性实施例中，形成所述隔离材料层，包括：
将设定比例的甲基硅倍半氧烷与正十四烷混合形成混合液；
将所述混合液通过旋转离心法旋涂于所述隔绝材料层的远离所述半导体衬底的一侧形成薄膜；
在保护性气氛中对所述薄膜进行烘干。
在本公开的一种示例性实施例中，所述保护性气氛为氮气。
在本公开的一种示例性实施例中，在形成所述导线材料层之前，所述制备方法还包括：
在所述半导体衬底之上形成导线黏附材料层；
对所述介质材料层刻蚀的同时，对所述导线黏附材料层进行刻蚀形成导线黏附层。
根据本公开的一个方面，提供一种存储装置，包括：上述任意一项所述的半导体器件。
由上述技术方案可知，本公开具备以下优点和积极效果中的至少之一：
本公开的半导体器件，在导线层的远离半导体衬底的一侧设置有隔绝层，在隔绝层的远离半导体衬底的一侧设置有隔离层，在隔离层的远离半导体衬底的一侧设置有介质层，在介质层的远离半导体衬底的一侧设置有导电结构。通过隔绝层能够隔离导线层和隔离层，通过介质层能够将隔离层与导电结构隔离，隔离层是低介电常数材料，通过隔离层可以有效降低导线层与导电结构产生的寄生电容，从而有效降低寄生电容对半导体器件使用的质量和寿命的影响。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开半导体器件一示例实施方式的结构示意图；
图2是本公开半导体器件的制备方法一示例实施方式的流程示意框图；
图3是本公开半导体器件的半导体衬底的结构示意图；
图4是在图3的基础上形成导线材料层、隔绝材料层、隔离材料层以及介质材料层后的结构示意图；
图5是在图4的基础上形成层叠结构的结构示意图；
图6是在图5的基础上形成侧墙材料层的结构示意图。
图中主要元件附图标记说明如下：
1、半导体衬底；2、有源区；
3、字线；31、字线沟槽；32、栅间介质层；33、第一导电层；34、第二导电层；35、绝缘层；
4、浅沟槽隔离结构；
51、导线黏附材料层；52、导线材料层；53、隔绝材料层；54、隔离材料层；55、介质材料层；
6、层叠结构；61、导线黏附层；62、导线层；63、隔绝层；64、隔离层；65、介质层；
7、侧墙材料层；71、侧墙结构；
8、位线接触沟槽；9、位线。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
在相关技术中，受到广泛关注的是位线(Bit line，BL)与BL之间的寄生电容，但是位线与其上方的导电结构也会产生寄生电容，寄生电容的存在，会影响半导体器件的性能，影响运行速度和刷新频率等。
本示例实施方式首先提供了一种半导体器件，参照图1所示，该半导体器件可以包括半导体衬底1，在所述半导体衬底1之上设置有多个条状的层叠结构6以及覆盖于所述层叠结构6外围的侧墙结构71，以及设于所 述层叠结构6的远离所述半导体衬底1一侧的导电结构(图中未示出)；所述层叠结构6可以包括导线层62、隔绝层63、隔离层64以及介质层65；导线层62设于所述半导体衬底1之上，所述导线层62用于传输数据信号；隔绝层63设于所述导线层62的远离所述半导体衬底1的一侧；隔离层64设于所述隔绝层63的远离所述半导体衬底1的一侧，所述隔离层64是低介电常数材料；介质层65设于所述隔离层64的远离所述半导体衬底1的一侧，所述介质层65用于隔离所述隔离层64与所述导电结构。
在本示例实施方式中，在半导体衬底1内设置有字线3和浅沟槽隔离结构4，浅沟槽隔离结构4将半导体衬底1分割成多个有源区2。
在半导体衬底1内设置有字线沟槽31，在字线沟槽31内设置有栅间介质层32，栅间介质层32覆盖字线沟槽31的侧壁及底部；栅间介质层32的材料可以包括但不仅限于氧化硅及氮化硅中的至少一种；可以采用原子层沉积工艺(Atomic Layer Deposition)、等离子蒸汽沉积工艺(Chemical Vapor Deposition)或快速热氧化工艺(Rapid Thermal Oxidation)形成栅间介质层32。
在字线沟槽31内设置有第一导电层33及第二导电层34，第一导电层33覆盖栅间介质层32的侧壁及栅间介质层32的底部，第二导电层34填满第一导电层33内侧的间隙，第一导电层33及第二导电层34的上表面均低于半导体衬底1的上表面，且第二导电层34的上表面高于第一导电层33的上表面；第一导电层33的材料可以包括As或B掺杂的硅、P或As掺杂的锗、W、Ti、TiN及Ru中的任一种，第二导电层34的材料可以包括W、Ti、Ni、Al及Pt中的任意一种，且第一导电层33与第二导电层34的材料不同；第一导电层33与第二导电层34可以采用原子层沉积工艺或等离子体蒸汽沉积工艺形成。
在字线沟槽31内设置有填充绝缘层35，填充绝缘层35覆盖第一导电层33的上表面及第二导电层34的上表面，且填满字线沟槽31；填充绝缘层35的材料可以包括氧化物(譬如，氧化硅、氧化铝或氧化铪等等)、氮化硅及氮氧化硅等在内的任何合适的绝缘材料。
在半导体衬底1上还可以设置位线接触沟槽8，位线9设置在位线接触沟槽8内，并突出于位线接触沟槽8。
在本示例实施方式中，在半导体衬底1之上设置有多个条状的层叠结构6，在层叠结构6外围覆盖有侧墙结构71，层叠结构6和侧墙结构71形成半导体器件的位线9。
具体而言，层叠结构6可以包括导线黏附层61、导线层62、隔绝层63、隔离层64以及介质层65。导线黏附层61可以设置在半导体衬底1之上，导线黏附层61的材质可以是多晶硅(Polysilicon)，其厚度大于等于60nm且小于等于70nm。导线层62设置在导线黏附层61的远离半导体衬底1的一侧，导线层62的材质可以是钛、钨等，其厚度大于等于25nm且小于等于30nm。隔绝层63设置在导线层62的远离半导体衬底1的一侧，隔绝层63的材质可以是氮化硅，其厚度大于等于8nm且小于等于12nm，优选为10nm。隔离层64设置在隔绝层63的远离半导体衬底1的一侧，隔离层64的材质可以是甲基硅倍半氧烷(SiLK)，其厚度大于等于8nm且小于等于12nm，优选为10nm。介质层65设置在隔离层64的远离半导体衬底1的一侧，介质层65的材质可以是氮化硅，其厚度大于等于120nm且小于等于160nm，优选为140nm。
甲基硅倍半氧烷(SiLK)的介电常数较低，约为2.6，甲基硅倍半氧烷比较容易控制它的孔径大小，通过引入直径为2-5纳米的微空洞并使其相互封闭，从而使其具有较高的力学模量和机械强度；在后续进行的化学机械抛光(CMP)和封装操作等过程中可能施加一定的外力，机械强度高的隔离层会保护位线结构进而保护整个半导体结构。且该材料的化学性能也较稳定，在高温下仍然能保持稳定的性能，因此，在后续的工艺中即使有高温要求也不会影响半导体器件的性能。当然，在本公开的其他示例实施方式中，隔离层64的材质还可以是二氧化硅，二氧化硅的介电常数大约为3.9，还可以采用其他低介电常数材料，可以是甲基倍半硅氧烷(methylsilsesquioxane，MSQ)或porous HSQ(多孔氢化倍半硅氧烷)。
在本示例实施方式中，侧墙结构71不仅设置在层叠结构6的外围，还覆盖在未设置层叠结构6的半导体衬底1之上。侧墙结构71可以覆盖整个层叠结构6。在本公开的其他示例实施方式中，侧墙结构71的高度至少高于隔离层64的高度，即侧墙结构71的远离半导体衬底1的一面与半导体衬底1之间的距离大于隔离层64的远离半导体衬底1的一面与半导 体衬底1之间的距离，使侧墙结构71将隔离层64完全覆盖，避免隔离层64暴露于后续工序中。层叠结构6与侧墙结构71形成位线9。
在本示例实施方式中，在位线9的远离半导体衬底1的一侧设置有导电结构，该导电结构可以包括电容结构和导电层，导电层位于位线9的远离半导体衬底1的一侧，导电层连接于电容触点，电容结构位于导电层的远离半导体衬底1的一侧，导电层与电容结构连接，将电容结构连接于电容触点。
本公开的半导体器件，在导线层62的远离半导体衬底1的一侧设置有隔绝层63，在隔绝层63的远离半导体衬底1的一侧设置有隔离层64，在隔离层64的远离半导体衬底1的一侧设置有介质层65，在介质层65的远离半导体衬底1的一侧设置有导电结构。通过隔绝层63能够隔离导线层62和隔离层64，通过介质层65能够将隔离层64与导电结构隔离，隔离层64是低介电常数材料，通过隔离层64可以有效降低导线层62与导电结构产生的寄生电容，从而可以减少半导体器件的RC延迟、串扰和功耗，避免影响运行速度和刷新频率等，从而有效降低寄生电容对半导体器件使用的质量和寿命的影响。
进一步的，本示例实施方式还提供了一种半导体器件的制备方法，参照图2所示，该半导体器件的制备方法可以包括以下步骤：
步骤S10，提供一半导体衬底1。
步骤S20，在所述半导体衬底1之上依次形成导线材料层52、隔绝材料层53、隔离材料层54以及介质材料层55。
步骤S30，对所述介质材料层55、所述隔离材料层54、所述隔绝材料层53以及所述导线材料层52刻蚀形成多个条状的层叠结构6。
步骤S40，在所述层叠结构6外围形成侧墙结构71。
步骤S50，在所述层叠结构6的远离所述半导体衬底1的一侧形成导电结构。
下面对半导体器件的制备方法的各个步骤进行详细说明。
步骤S10，提供一半导体衬底1。
在本示例实施方式中，参照图3所示，半导体衬底1可以包括但不限于单晶硅衬底、多晶硅衬底、氮化镓衬底或蓝宝石衬底，另外，所述半导 体衬底11为单晶衬底或多晶衬底时，还可以是本征硅衬底或者是轻微掺杂的硅衬底，进一步，可以为N型多晶硅衬底或P型多晶硅衬底。
步骤S20，在所述半导体衬底1之上依次形成导线材料层52、隔绝材料层53、隔离材料层54以及介质材料层55。
在本示例实施方式中，参照图4所示。
在半导体衬底1之上通过CVD(Chemical Vapor Deposition，化学气相沉积)工艺形成导线黏附材料层51，在化学气相沉积工艺过程中沉积气体可以是Si 2H 6、SiH 4、PH 3、LTO520(前驱物：SiH3N(C3H7)2)中的一种或多种。
在导线黏附材料层51的远离半导体衬底1的一侧通过PVD(Physical Vapor Deposition，物理气相沉积)工艺形成导线材料层52，在物理气相沉积工艺过程中靶材可以采用钨、钛等等。
在导线材料层52的远离半导体衬底1的一侧通过低压力化学气相沉积(Low Pressure Chemical Vapour Deposition，LPCVD)或者原子层沉积(Atomic layer deposition，ALD)工艺形成隔绝材料层53，沉积材料为氮化硅。主要沉积气体为SiCl 2H 2和NH 3。
在隔绝材料层53的远离半导体衬底1的一侧形成隔离材料层54。具体为：将设定比例的甲基硅倍半氧烷与正十四烷混合形成混合液；将混合液通过旋转离心法旋涂于隔绝材料层53的远离半导体衬底1的一侧形成薄膜，薄膜的厚度大约为10nm；在保护性气氛中对薄膜进行烘干。保护性气氛可以为氮气，当然，可以将氦气作为保护性气氛。设定比例可以为正十四烷占甲基硅倍半氧烷30％至50％。
在隔离材料层54的远离半导体衬底1的一侧通过LPCVD或者原子层沉积(Atomic layer deposition，ALD)工艺形成介质材料层55，沉积材料为氮化硅。主要沉积气体为SiCl 2H 2和NH 3。
步骤S30，对所述介质材料层55、所述隔离材料层54、所述隔绝材料层53以及所述导线材料层52刻蚀形成多个条状的层叠结构6。
在本示例实施方式中，参照图5所示，可以在介质材料层55的远离半导体衬底1的一侧形成光刻胶层，在光刻胶层之上设置掩膜板，对光刻胶层进行曝光，然后去除未被掩膜板覆盖的光刻胶层，然后以剩余的光刻 胶层作为掩膜，对介质材料层55、隔离材料层54、隔绝材料层53、导线材料层52以及导线黏附材料层51进行干刻对应形成多个条状的介质层65、隔离层64、隔绝层63、导线层62以及导线黏附层61，即形成多个条状的层叠结构6。
步骤S40，在所述层叠结构6外围形成侧墙结构71。
在本示例实施方式中，参照图6所示，在半导体衬底1之上和层叠结构6的远离半导体衬底1的一侧可以通过低压力化学气相沉积形成侧墙材料层7，且侧墙材料层7的高度高于介质层65的高度。然后，对侧墙材料层7进行刻蚀以保留层叠结构6侧壁的侧墙材料层7和半导体衬底1之上的部分侧墙材料层7形成侧墙结构71，这两处的侧墙材料层7的厚度基本相同，为大于等于7nm且小于等于9nm，即形成图1所示的半导体器件的结构示意图。
层叠结构6与侧墙结构71形成半导体器件的位线9。
步骤S50，在所述层叠结构6的远离所述半导体衬底1的一侧形成导电结构。
在本示例实施方式中，导电结构可以包括电容结构和导电层。导电结构的具体结构上述已经进行了详细说明，因此，此处不再赘述。
与现有技术相比，本公开示例实施方式提供的半导体器件的制备方法的有益效果与上述示例实施方式提供的半导体器件的有益效果相同，在此不做赘述。
进一步的，本示例实施方式还提供了一种存储装置，该存储装置可以包括上述任意一项所述的半导体器件。半导体器件的具体结构上述已经进行了详细说明，因此，此处不再赘述。
与现有技术相比，本公开示例实施方式提供的存储装置的有益效果与上述示例实施方式提供的半导体器件的有益效果相同，在此不做赘述。
上述所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中，如有可能，各实施例中所讨论的特征是可互换的。在上面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而没有所述特定细节中的一个或更多，或者可以采用其它的方法、组件、材料等。在 其它情况下，不详细示出或描述公知结构、材料或者操作以避免模糊本公开的各方面。
本说明书中使用“约”“大约”的用语通常表示在一给定值或范围的20％之内，较佳是10％之内，且更佳是5％之内。在此给定的数量为大约的数量，意即在没有特定说明的情况下，仍可隐含“约”“大约”“大致”“大概”的含义。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。其他相对性的用语，例如“高”“低”“顶”“底”等也作具有类似含义。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
本说明书中，用语“一个”、“一”、“该”和“所述”用以表示存在一个或多个要素/组成部分/等；用语“包含”、“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
应可理解的是，本公开不将其应用限制到本说明书提出的部件的详细结构和布置方式。本公开能够具有其他实施方式，并且能够以多种方式实现并且执行。前述变形形式和修改形式落在本公开的范围内。应可理解的是，本说明书公开和限定的本公开延伸到文中和/或附图中提到或明显的两个或两个以上单独特征的所有可替代组合。所有这些不同的组合构成本公开的多个可替代方面。本说明书所述的实施方式说明了已知用于实现本公开的最佳方式，并且将使本领域技术人员能够利用本公开。

Claims (11)

  1. 一种半导体器件，其中，包括半导体衬底，在所述半导体衬底之上设置有多个条状的层叠结构以及覆盖于所述层叠结构外围的侧墙结构，在所述层叠结构的远离所述半导体衬底的一侧设置有导电结构；
    所述层叠结构包括：
    导线层，设于所述半导体衬底之上，所述导线层用于传输数据信号；
    隔绝层，设于所述导线层的远离所述半导体衬底的一侧；
    隔离层，设于所述隔绝层的远离所述半导体衬底的一侧，所述隔离层是低介电常数材料；
    介质层，设于所述隔离层的远离所述半导体衬底的一侧，所述介质层用于隔离所述隔离层与所述导电结构。
  2. 根据权利要求1所述的半导体器件，其中，所述隔离层的材质是甲基硅倍半氧烷，其介电常数为2.6，所述隔离层的厚度大于等于8nm且小于等于12nm。
  3. 根据权利要求1所述的半导体器件，其中，所述隔绝层的厚度大于等于8nm且小于等于12nm，其材质是氮化硅。
  4. 根据权利要求1所述的半导体器件，其中，所述介质层的厚度大于等于120nm且小于等于160nm，其材质是氮化硅。
  5. 根据权利要求1所述的半导体器件，其中，所述层叠结构还包括：
    导线黏附层，设于所述导线层与所述半导体衬底之间，所述导线黏附层的材质是多晶硅，其厚度大于等于60nm且小于等于70nm。
  6. 根据权利要求1所述的半导体器件，其中，所述导电结构包括：
    导电层，设于所述层叠结构的远离半导体衬底的一侧，所述导电层连接于电容触点；
    电容结构，设于所述导电层的远离半导体衬底的一侧，所述电容结构连接于所述导电层。
  7. 一种半导体器件的制备方法，其中，包括：
    提供一半导体衬底；
    在所述半导体衬底之上依次形成导线材料层、隔绝材料层、隔离材料层以及介质材料层；
    对所述介质材料层、所述隔离材料层、所述隔绝材料层以及所述导线材料层刻蚀形成多个条状的层叠结构；
    在所述层叠结构外围形成侧墙结构；
    在所述层叠结构的远离所述半导体衬底的一侧形成导电结构。
  8. 根据权利要求7所述的半导体器件的制备方法，其中，形成所述隔离材料层，包括：
    将设定比例的甲基硅倍半氧烷与正十四烷混合形成混合液；
    将所述混合液通过旋转离心法旋涂于所述隔绝材料层的远离所述半导体衬底的一侧形成薄膜；
    在保护性气氛中对所述薄膜进行烘干。
  9. 根据权利要求8所述的半导体器件的制备方法，其中，所述保护性气氛为氮气。
  10. 根据权利要求9所述的半导体器件的制备方法，其中，在形成所述导线材料层之前，所述制备方法还包括：
    在所述半导体衬底之上形成导线黏附材料层；
    对所述介质材料层刻蚀的同时，对所述导线黏附材料层进行刻蚀形成导线黏附层。
  11. 一种存储装置，其中，包括：权利要求1～6任意一项所述的半导体器件。
PCT/CN2021/103745 2020-09-15 2021-06-30 半导体器件及其制备方法、存储装置 WO2022057382A1 (zh)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150111360A1 (en) * 2013-10-17 2015-04-23 Samsung Electronics Co., Ltd. Method of manufacturing a semiconductor device
CN110364529A (zh) * 2018-03-26 2019-10-22 爱思开海力士有限公司 包括超低k间隔件的半导体器件及其制造方法
CN110718550A (zh) * 2018-07-12 2020-01-21 三星电子株式会社 半导体器件及制造其的方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6187624B1 (en) * 1999-06-04 2001-02-13 Taiwan Semiconductor Manufacturing Company Method for making closely spaced capacitors with reduced parasitic capacitance on a dynamic random access memory (DRAM) device
KR20090097362A (ko) * 2008-03-11 2009-09-16 삼성전자주식회사 저항 메모리 소자 및 그 형성 방법
KR102232766B1 (ko) * 2015-01-05 2021-03-26 삼성전자주식회사 반도체 소자 및 이의 제조방법
CN108269758B (zh) * 2016-12-29 2019-08-23 联华电子股份有限公司 半导体元件的制作方法
KR102427397B1 (ko) * 2017-11-29 2022-08-02 삼성전자주식회사 반도체 메모리 장치 및 이의 제조 방법
CN210272359U (zh) * 2019-10-09 2020-04-07 长鑫存储技术有限公司 半导体存储器

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150111360A1 (en) * 2013-10-17 2015-04-23 Samsung Electronics Co., Ltd. Method of manufacturing a semiconductor device
CN110364529A (zh) * 2018-03-26 2019-10-22 爱思开海力士有限公司 包括超低k间隔件的半导体器件及其制造方法
CN110718550A (zh) * 2018-07-12 2020-01-21 三星电子株式会社 半导体器件及制造其的方法

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