WO2022056992A1 - Goa 驱动电路及显示面板 - Google Patents

Goa 驱动电路及显示面板 Download PDF

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Publication number
WO2022056992A1
WO2022056992A1 PCT/CN2020/122024 CN2020122024W WO2022056992A1 WO 2022056992 A1 WO2022056992 A1 WO 2022056992A1 CN 2020122024 W CN2020122024 W CN 2020122024W WO 2022056992 A1 WO2022056992 A1 WO 2022056992A1
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WIPO (PCT)
Prior art keywords
transistor
drain
source
gate
control
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Ceased
Application number
PCT/CN2020/122024
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English (en)
French (fr)
Inventor
李艳
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US17/056,717 priority Critical patent/US11756497B2/en
Publication of WO2022056992A1 publication Critical patent/WO2022056992A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/001—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background
    • G09G3/003—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background to produce spatial visual effects
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Definitions

  • the present application relates to the field of display technology, and in particular, to a GOA driving circuit and a display panel.
  • the GOA (row drive on array substrate) technology utilizes the existing thin film transistor process of the liquid crystal display array to fabricate the gate row scan drive circuit on the array substrate, so as to realize the drive method of scanning the gate lines row by row.
  • the GOA circuit in the prior art can only display on a full screen, so even if only a part of the area or a low-resolution image needs to be displayed in a standby state, full-screen display is still required, resulting in high power consumption.
  • the full-screen display of the GOA circuit in the prior art can only display the left eye image and the right eye image at the same position, and the human brain is synthesizing the left eye image and the right eye image. Discomfort such as dizziness and vomiting is easy to appear when taking eye images.
  • the application proposes a GOA driving circuit and a display panel, which can selectively output scanning signals to achieve the function of part of the display screen, so as to reduce power consumption. At the same time, it can also be applied to 3D display.
  • the pixel positions of the left eye image and the right eye image are different to help the left and right eye images of the human brain to synthesize and improve the 3D display effect.
  • the embodiment of the present application provides a GOA drive circuit, including:
  • a plurality of cascaded GOA drive units wherein the GOA drive unit of this level includes: a pull-up module, a pull-up control module, a pull-down module, a pull-down maintenance module and a selection module;
  • the pull-up module includes:
  • the eleventh transistor the source of which is connected to the clock signal, the gate of which is connected to the first node, and the drain of which is used to output the start signal of this stage to the next-stage GOA drive unit;
  • the pull-up control module is used for receiving the start signal of the GOA driving unit of the previous stage and controlling the opening and closing of the first transistor and the eleventh transistor through the first node;
  • the selection module is used for receiving a first control signal and a second control signal to control whether the clock signal is input to the source of the first transistor.
  • the pull-up control module includes a start transistor, the source and gate of which are connected to the start signal of the upper-level GOA driving unit, and the drain is connected to to the first node.
  • the selection module includes a first control transistor and a second control transistor, a source of the first control transistor is connected to the clock signal, and a source of the first control transistor is connected to the clock signal.
  • the gate is connected to the first control signal
  • the drain of the first control transistor is connected to the source of the second control transistor
  • the gate of the second control transistor is connected to the second control signal, so The drain of the second control transistor is connected to a reference low level
  • the first transistor is connected to the clock signal through the first control transistor
  • the first transistor is connected to the clock signal through the second control transistor Reference low.
  • the phase of the second control signal is completely opposite to the phase of the first control signal.
  • the pull-down module includes:
  • a second transistor the source of which is connected to the drain of the first transistor, the gate of which is connected to the start signal of the next-stage GOA driving unit, and the drain of which is connected to the second low level;
  • the twelfth transistor has a source connected to the first node, a gate connected to the start signal of the next-stage GOA driving unit, and a drain connected to a first low level.
  • the pull-down maintaining module includes:
  • a third transistor the source of which is connected to the first node, the gate of which is connected to the second node, and the drain of which is connected to the first low level;
  • a fourth transistor the source of which is connected to the scanning signal of the current stage, the gate of which is connected to the second node, and the drain of which is connected to the second low level;
  • a fifth transistor the source of which is connected to the start signal of the current stage, the gate of which is connected to the second node, and the drain of which is connected to the first low level;
  • the sixth transistor the source and the gate of which are connected to the first switch signal
  • a seventh transistor the source of which is connected to the drain of the sixth transistor, the gate of which is connected to the first node, and the drain of which is connected to the first low level;
  • an eighth transistor the source of which is connected to the first switch signal, and the gate of which is connected to the drain of the sixth transistor;
  • the ninth transistor has its source connected to the drain of the eighth transistor, its gate connected to the first node, and its drain connected to the first low level.
  • the pull-down maintaining module further includes:
  • a thirteenth transistor the source of which is connected to the scan signal, the gate of which is connected to the third node, and the drain of which is connected to the second low level;
  • a fourteenth transistor the source of which is connected to the first node, the gate of which is connected to the third node, and the drain of which is connected to the first low level;
  • a fifteenth transistor the source of which is connected to the start signal of the current stage, the gate of which is connected to the third node, and the drain of which is connected to the first low level;
  • the sixteenth transistor, the source and the gate of which are connected to the second switch signal
  • a seventeenth transistor the source of which is connected to the drain of the sixteenth transistor, the gate of which is connected to the first node, and the drain of which is connected to the first low level;
  • An eighteenth transistor the source of which is connected to the second switch signal, and the gate of which is connected to the drain of the sixteenth transistor;
  • the source of the nineteenth transistor is connected to the drain of the eighteenth transistor, the gate is connected to the first node, and the drain is connected to the first low level.
  • the present application further provides a display panel, which is characterized by comprising a GOA drive circuit, an array substrate and a selection circuit, wherein the GOA drive circuit includes a plurality of cascaded GOA drive units, wherein the GOA drive unit of the current level Including: pull-up module, pull-up control module, pull-down module, pull-down maintenance module and selection module;
  • the pull-up module includes:
  • the eleventh transistor the source of which is connected to the clock signal, the gate of which is connected to the first node, and the drain of which is used to output the start signal of this stage to the next-stage GOA drive unit;
  • the pull-up control module is used for receiving the start signal of the GOA driving unit of the previous stage and controlling the opening and closing of the first transistor and the eleventh transistor through the first node;
  • the selection module is used for receiving a first control signal and a second control signal to control whether the clock signal is input to the source of the first transistor;
  • the selection circuit includes a first enable line and a second enable line, the first enable line is used to provide a part of the first control signal of the GOA driving unit, and the second enable line is used to provide Another part of the first control signal of the GOA driving unit.
  • each of the GOA driving units includes an inverter for inverting the first control signal to generate the corresponding second control signal.
  • the GOA driving units of odd-numbered stages are connected to the first enable line, and the GOA driving units of even-numbered stages are connected to the second enable line.
  • the pull-up control module includes a start transistor, the source and gate of which are connected to the start signal of the upper-level GOA driving unit, and the drain of which is connected to first node.
  • the selection module includes a first control transistor and a second control transistor, the source of the first control transistor is connected to the clock signal, and the gate of the first control transistor is connected to the clock signal.
  • the first control signal is connected to the first control signal
  • the drain of the first control transistor is connected to the source of the second control transistor
  • the gate of the second control transistor is connected to the second control signal
  • the The drain of the second control transistor is connected to the reference low level
  • the first transistor is connected to the clock signal through the first control transistor
  • the first transistor is connected to the reference through the second control transistor low level.
  • the phase of the second control signal is completely opposite to the phase of the first control signal.
  • the pull-down module includes:
  • a second transistor the source of which is connected to the drain of the first transistor, the gate of which is connected to the start signal of the next-stage GOA driving unit, and the drain of which is connected to the second low level;
  • the twelfth transistor has a source connected to the first node, a gate connected to the start signal of the next-stage GOA driving unit, and a drain connected to a first low level.
  • the pull-down maintaining module includes:
  • a third transistor the source of which is connected to the first node, the gate of which is connected to the second node, and the drain of which is connected to the first low level;
  • a fourth transistor the source of which is connected to the scanning signal of the current stage, the gate of which is connected to the second node, and the drain of which is connected to the second low level;
  • a fifth transistor the source of which is connected to the start signal of the current stage, the gate of which is connected to the second node, and the drain of which is connected to the first low level;
  • the sixth transistor the source and the gate of which are connected to the first switch signal
  • a seventh transistor the source of which is connected to the drain of the sixth transistor, the gate of which is connected to the first node, and the drain of which is connected to the first low level;
  • an eighth transistor the source of which is connected to the first switch signal, and the gate of which is connected to the drain of the sixth transistor;
  • the ninth transistor has its source connected to the drain of the eighth transistor, its gate connected to the first node, and its drain connected to the first low level.
  • the pull-down maintaining module further includes:
  • a thirteenth transistor the source of which is connected to the scan signal, the gate of which is connected to the third node, and the drain of which is connected to the second low level;
  • a fourteenth transistor the source of which is connected to the first node, the gate of which is connected to the third node, and the drain of which is connected to the first low level;
  • a fifteenth transistor the source of which is connected to the start signal of the current stage, the gate of which is connected to the third node, and the drain of which is connected to the first low level;
  • the sixteenth transistor, the source and the gate of which are connected to the second switch signal
  • a seventeenth transistor the source of which is connected to the drain of the sixteenth transistor, the gate of which is connected to the first node, and the drain of which is connected to the first low level;
  • An eighteenth transistor the source of which is connected to the second switch signal, and the gate of which is connected to the drain of the sixteenth transistor;
  • the source of the nineteenth transistor is connected to the drain of the eighteenth transistor, the gate is connected to the first node, and the drain is connected to the first low level.
  • the present application further provides a display panel, which is characterized by comprising a GOA drive circuit, an array substrate and a selection circuit, wherein the GOA drive circuit includes a plurality of cascaded GOA drive units, wherein the GOA drive unit of the current level Including: pull-up module, pull-up control module, pull-down module, pull-down maintenance module and selection module;
  • the pull-up module includes:
  • a first transistor the source of which is connected to the selection module, the gate of which is connected to the pull-up control module through the first node, and the drain of which outputs the scan signal of the current stage;
  • the eleventh transistor the source of which is connected to the clock signal, the gate of which is connected to the first node, and the drain of which is used to output the start signal of this stage to the next-stage GOA drive unit;
  • the pull-up control module includes a start transistor, the source and gate of which are connected to the start signal of the upper-level GOA driving unit, and the drain is connected to the first node;
  • the pull-up control module is used for receiving the start signal of the GOA driving unit of the previous stage and controlling the opening and closing of the first transistor and the eleventh transistor through the first node;
  • the selection module is used for receiving a first control signal and a second control signal to control whether the clock signal is input to the source of the first transistor;
  • the selection circuit includes a first enable line and a second enable line, wherein the first enable line is used to provide a part of the first control signal of the GOA driving unit;
  • the second enable line is used to provide another part of the first control signal of the GOA driving unit.
  • the selection module includes a first control transistor and a second control transistor, a source of the first control transistor is connected to the clock signal, and a source of the first control transistor is connected to the clock signal.
  • the gate is connected to the first control signal
  • the drain of the first control transistor is connected to the source of the second control transistor
  • the gate of the second control transistor is connected to the second control signal, so The drain of the second control transistor is connected to a reference low level
  • the first transistor is connected to the clock signal through the first control transistor
  • the first transistor is connected to the clock signal through the second control transistor Reference low.
  • the GOA driving circuit and the display panel of the embodiments of the present application provide the selection module, which can selectively output the scanning signal Gn without affecting the staging function of the GOA driving unit, and can pass the first control signal and the level of the second control signal to control the output of the scan signal Gn.
  • FIG. 1 is a schematic diagram of a GOA driving circuit provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a display panel provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a display panel according to another embodiment of the present application.
  • FIG. 4 is a signal timing diagram when the GOA drive circuit of the embodiment of the present application provides a low-potential scanning signal
  • FIG. 5 is a signal timing diagram when the GOA driving circuit according to the embodiment of the present application provides a high-potential scan signal.
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature defined as “first” or “second” may expressly or implicitly include one or more of that feature. In the description of this application, unless stated otherwise, “plurality” means two or more. Additionally, the term “comprising” and any variations thereof are intended to cover non-exclusive inclusion.
  • the terms “installed”, “connected” and “connected” should be understood in a broad sense, for example, it may be a support connection or a detachable connection Connection, or integral connection; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium, can be internal communication between two elements.
  • installed should be understood in a broad sense, for example, it may be a support connection or a detachable connection Connection, or integral connection; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium, can be internal communication between two elements.
  • the GOA drive circuit includes a plurality of cascaded GOA drive units 20 and 20 ′, wherein the GOA drive units 20 and 20 ′ of the current stage include: a pull-up module 21 , a pull-up control module 22 , a pull-down module 23 , and a pull-down maintenance module 24 and selection module 25.
  • the pull-up module 21 includes: a first transistor T11 and an eleventh transistor T12, the source of the first transistor T11 is connected to the selection module 25, and the gate of the first transistor T11 is connected to the pull-up control module through the first node Q 22, its drain outputs the scanning signal Gn of the current stage.
  • the source of the eleventh transistor is connected to the clock signal CK, the gate of the eleventh transistor is connected to the first node Q, and the drain of the eleventh transistor is used to output the start signal STn of the current stage to the next-stage GOA driving unit.
  • the pull-up control module 22 is used for receiving the start signal STn-1 of the GOA driving unit of the previous stage and controlling the opening and closing of the first transistor T11 and the eleventh transistor T12 through the first node Q.
  • the selection module 25 is used for receiving the first control signal EN1 and the second control signal EN2 to control whether the clock signal CK is input to the source of the first transistor T11.
  • the pull-up control module 22 includes a start transistor T1, the source and gate of which are connected to the start signal STn-1 of the previous GOA driving unit, and the drain is connected to the first node Q.
  • the selection module 25 includes a first control transistor T2 and a second control transistor T3. The source of the first control transistor T2 is connected to the clock signal CK, and the gate of the first control transistor T2 is connected to the clock signal CK.
  • the first control signal EN1 the drain of the first control transistor T2 is connected to the source of the second control transistor T3, the gate of the second control transistor T3 is connected to the second control signal EN2, the The drain of the second control transistor T3 is connected to the reference low level VGL, the first transistor T11 is connected to the clock signal CK through the first control transistor T2, and the first transistor T1 is controlled by the second Transistor T3 is connected to the reference low level VGL.
  • the phase of the second control signal EN2 is completely opposite to that of the first control signal EN1 .
  • the pull-down module 23 includes: a second transistor T21 and a twelfth transistor T22.
  • the source of the second transistor T21 is connected to the drain of the first transistor T11, the gate of the second transistor T21 is connected to the start signal STn+1 of the next-stage GOA driving unit, and the drain is connected to the second low level VSS2.
  • the twelfth transistor T22 has its source connected to the first node Q, its gate connected to the start signal STn+1 of the next-stage GOA driving unit, and its drain connected to the first low level VSS1.
  • the pull-down maintaining module 24 includes: a third transistor T31, a fourth transistor T41, a fifth transistor T51, a sixth transistor T61, a seventh transistor T71, an eighth transistor T81, and a ninth transistor T91.
  • the gates of the third transistor T31, the fourth transistor T41 and the fifth transistor T51 are all connected to the second node P, the source of the third transistor T31 is connected to the first node Q, and the drain is connected to the first low level VSS1 , the source of the fourth transistor T41 is connected to the scan signal Gn of the current stage, the drain of the fourth transistor T41 is connected to the second low level VSS2, the source of the fifth transistor T51 is connected to the start signal STn of the current stage, and the fifth transistor T51 is connected to the start signal STn of the current stage.
  • the drain of the transistor T51 is connected to the first low level VSS1.
  • the gate of the sixth transistor T61 is connected to the source and connected to the first switching signal LC1, the gate of the seventh transistor T71 is connected to the first node Q, and the source of the seventh transistor T71 is connected to the drain of the sixth transistor T61 , the drain of the seventh transistor T71 is connected to the first low level VSS1, the gate of the eighth transistor T81 is connected to the drain of the sixth transistor T61, that is, the gate of the eighth transistor T81 and the source of the seventh transistor T71 connected, the source of the eighth transistor T81 is connected to the gate of the sixth transistor T61, that is, the source of the eighth transistor T81 is connected to the first switching signal LC1, the drain of the eighth transistor T81 is connected to the second node P, the The source of the nine transistor T91 is connected to the second node P, that is, the source of the ninth transistor T91 is connected to the drain of the eighth transistor T81, the gate of the ninth transistor T91 is connected to the first node Q, and the The drain is connected to the first low level VSS1.
  • the GOA driving unit of this stage may further include a reset module 26, the reset module 26 includes a tenth transistor T10, the source of the tenth transistor T10 is connected to the drain of the starting transistor T1, and the gate of the tenth transistor T10 is connected to With the reset signal reset, the drain of the tenth transistor T10 is connected to the first low level VSS1.
  • the reset module 26 is used for receiving the reset signal reset to pull the potential of the first node Q to a low level to reset the GOA driving unit of the current stage.
  • the pull-down maintaining module 24 further includes a thirteenth transistor T32, a fourteenth transistor T42, a fifteenth transistor T52, a sixteenth transistor T62, a seventeenth transistor T72, an eighteenth transistor T82 and a nineteenth transistor T92.
  • the gates of the thirteenth transistor T32, the fourteenth transistor T42 and the fifteenth transistor T52 are all connected to the third node K, the source of the thirteenth transistor T32 is connected to the scanning signal Gn of the current stage, and the source of the thirteenth transistor T32
  • the drain is connected to the second low level VSS2
  • the source of the fourteenth transistor T42 is connected to the first node Q
  • the drain of the fourteenth transistor T42 is connected to the first low level VSS1
  • the source of the fifteenth transistor T52 The pole is connected to the start signal STn of the current stage
  • the drain of the fifteenth transistor T52 is connected to the first low level VSS1.
  • the gate of the sixteenth transistor T62 is connected to the source and connected to the second switching signal LC2, the gate of the seventeenth transistor T72 is connected to the first node Q, and the source of the seventeenth transistor T72 is connected to the sixteenth transistor
  • the drain of T62, the drain of the seventeenth transistor T72 is connected to the first low level VSS1
  • the gate of the eighteenth transistor T82 is connected to the drain of the sixteenth transistor T62, that is, the gate of the eighteenth transistor T82 It is connected to the source of the seventeenth transistor T72, the source of the eighteenth transistor T82 is connected to the gate of the sixteenth transistor T62, that is, the source of the eighteenth transistor T82 is connected to the second switch signal LC2, and the eighteenth transistor T82 is connected to the second switch signal LC2.
  • the drain of the transistor T82 is connected to the third node K
  • the source of the nineteenth transistor T92 is connected to the third node K, that is, the source of the nineteenth transistor T92 is connected to the drain of the eighteenth transistor T82
  • the nineteenth transistor T92 is connected to the drain of the eighteenth transistor T82.
  • the gate of the transistor T92 is connected to the first node Q
  • the drain of the nineteenth transistor T92 is connected to the first low level VSS1.
  • the pull-up control module 22 starts The initial transistor T1 is turned on, and the first node Q is pulled up to a first high level to turn on the first transistor T11 and the eleventh transistor T12 of the pull-up module 21, but because the clock signal CK is at a low level, at this time The scanning signal Gn of the current stage and the start signal STn of the current stage are still at low level.
  • the pull-down maintaining module 24 ends the pull-down maintaining operation at this time, and the seventh transistor T71, the ninth transistor T91, the seventeenth transistor T72 and the nineteenth transistor T92 are turned on due to the high potential of the Q point, and the pull-down second transistor T71, the ninth transistor T91, the seventeenth transistor T72, and the nineteenth transistor T92 are turned on.
  • the potentials of the node P and the third node K go to a low level so that the third transistor T31, the fourth transistor T41, the fifth transistor T51, the thirteenth transistor T32, the fourteenth transistor T42 and the fifteenth transistor T52 are not turned on, In order to prevent the subsequent third transistor T31, fourth transistor T41, fifth transistor T51, thirteenth transistor T32, fourteenth transistor T42 and fifteenth transistor T52 from causing the first node Q, the scan signal Gn of this stage and the start of this stage The potential of the signal STn is pulled low.
  • the start signal STn-1 of the previous stage is at a low level
  • the clock signal CK is at a high level
  • the start transistor T1 of the pull-up control module 22 is turned off
  • the first node Q is at In the floating state
  • the bootstrap capacitor C produces a coupling effect due to the change of the clock signal CK from a low level to a high level, so that the potential of the first node Q is bootstrapped to the second high level, and the first transistor T11 and the eleventh transistor T12 are completely turned on, and the current-stage scan signal Gn and the current-stage start signal STn output a high level.
  • the start signal STn-1 of the previous stage is still low level
  • the clock signal CK turns to low level
  • the start signal STn+1 of the next stage GOA drive unit turns to high level
  • the second transistor T21 and the twelfth transistor T22 in the pull-down module 23 are thus turned on, so that the scanning signal Gn and the first node Q of the current stage are both pulled down to a low level.
  • the seventh transistor T71, the ninth transistor T91, the seventeenth transistor T72 and the nineteenth transistor T92 in the pull-down maintaining module 24 are not turned on, that is, the second node P and the third node K are no longer pulled to the low level, So that the pull-down of the next clock maintains the activation of the module 24 .
  • the first switch signal LC1 or the second switch signal LC2 is at a high level.
  • the phases of the first switch signal LC1 and the second switch signal LC2 are opposite, so that the right half circuit and the left half circuit of the pull-down maintaining module 24 can work alternately, that is, when the first switch signal LC1 is at a high level, the second switch The signal LC2 is at a low level, the sixth transistor T61 and the eighth transistor T81 on the right half of the pull-down maintaining module 24 are turned on, so that the second node P is pulled up to a high level, so the third transistor T31, the fourth transistor T41 and the fifth transistor The transistor T51 is turned on to maintain the level of the first node Q, the scanning signal Gn of the current stage, and the start signal STn of the current stage to be continuously pulled down, that is, the right half circuit of the pull-down maintaining module 24 operates to maintain the low level of the signal of the current stage.
  • the second switch signal LC2 is at a high level
  • the first switch signal LC1 is at a low level
  • the sixteenth transistor T62 and the eighteenth transistor T82 on the left half of the pull-down maintaining module 24 are turned on so that the third node K is turned on.
  • Pulled to a high level so the thirteenth transistor T32, the fourteenth transistor T42 and the fifteenth transistor T52 are turned on to maintain the levels of the first node Q, the current-stage scan signal Gn and the current-stage start signal STn respectively keep pulling down.
  • the phases of the first switch signal LC1 and the second switch signal LC2 are opposite, so that the transistors of the right half circuit of the pull-down maintaining module 24 and the transistors of the left half circuit can work alternately, so as to avoid the transistor threshold voltage drift due to long-term bias voltage of the transistors .
  • the present application further includes a first control signal EN1 and a second control signal EN2 to control the gate of the first control transistor T2 and the gate of the second control transistor T3 respectively.
  • the first control signal EN1 is at a high level
  • the second control signal EN2 is at a low level, so that the clock signal CK can pass through the first transistor T11 to make the scan signal of the current stage Gn outputs a high level, as shown in Figure 5.
  • the first control signal EN1 is at a low level
  • the second control signal EN2 is at a high level, so that the clock signal CK is always pulled low and the first transistor T11 is output
  • the low-level scanning signal Gn of this stage is shown in FIG. 4 .
  • the present invention further provides a display panel 100 , which is characterized by comprising any of the above-mentioned GOA driving circuits, an array substrate 10 and a selection circuit 40 , wherein the selection circuit 40 includes a first enable line EN ⁇ R and the second enable line EN-L, the first enable line EN-R is used to provide a part of the first control signal EN1 of the GOA driving unit 20, and the second enable line EN-L is used for to provide another part of the first control signal EN1 of the GOA driving unit 20 ′.
  • the selection circuit 40 includes a first enable line EN ⁇ R and the second enable line EN-L
  • the first enable line EN-R is used to provide a part of the first control signal EN1 of the GOA driving unit 20
  • the second enable line EN-L is used for to provide another part of the first control signal EN1 of the GOA driving unit 20 ′.
  • the GOA driving circuit is disposed on the array substrate 10 .
  • the display panel 100 further includes a plurality of source driving circuits 30 , a plurality of gate lines GL and a plurality of data lines DL disposed on the array substrate 10 .
  • a pixel circuit (not shown) is provided at the intersection of each gate line GL and the data line DL, and the GOA driving units 20 and 20' correspond to the gate line GL one-to-one for providing scan signals.
  • the selection circuit 40 controls the display panel 100 to display the right half and the left half of the display panel 100 through the first enable line EN-R and the second enable line EN-L, or display the left half and not display the right half .
  • the display panel 100 can be suitable for some kinds of 3D stereoscopic display, so that the left-eye image and the right-eye image can be displayed separately.
  • the stage transmission function of the GOA driving units 20 and 20 ′ is to pass the start signal, that is, the start signal STn-1 of the previous stage, the start signal STn of the current stage, and the start signal STn of the next stage. Therefore, even if the selection circuit 40 controls the scanning signals of some GOA driving units 20 and 20' to be pulled down to a low level, the stage transmission function of the GOA driving units 20 and 20' is not affected.
  • each of the GOA driving units 20, 20' includes an inverter 50 for inverting the first control signal EN1 to generate the corresponding second control signal EN2.
  • the GOA driving units 20 of the odd-numbered stages of the display panel 100 ′ are connected to the first enable line EN-R, and the GOA driving units 20 ′ of the even-numbered stages are connected to the first enable line EN-R Connected to the second enable line EN-L.
  • the selection circuit 40 controls the display panel 100 ′ to display the GOA driving units 20 in odd-numbered stages and drive the GOAs in even-numbered stages through the first enable line EN-R and the second enable line EN-L.
  • Cells 20' are not shown, or even-numbered stages of the GOA drive cells 20' are shown and odd-numbered stages of the GOA drive cells 20 are not shown.
  • the display panel 100' can be applied to some 3D stereoscopic displays with prism plates, so that the left-eye image and the right-eye image can be displayed separately.
  • the display panel 100' is also applicable to some usage scenarios requiring energy saving, so that only half of the pixels of the display panel 100' are displayed to save power.
  • the above are just a few ways of configuring the selection circuit 40 and the GOA driving units 20 and 20 ′.
  • the present invention is not limited thereto.
  • the selection circuit 40 and the GOA driving units 20 and 20 ′ can also be configured according to actual needs.
  • Two GOA drive units are interactively activated and deactivated as a group, or every three GOA drive units are in a group, etc.
  • the GOA driving circuit and the display panel of the embodiments of the present application provide the selection module, which can selectively output scanning signals without affecting the staging function of the GOA driving unit, and can pass the level of the first control signal and the second control signal High and low to control the output of the scan signal.

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Abstract

一种GOA驱动电路（30）及显示面板(100，100')，GOA驱动电路（30）包含多个级联的GOA驱动单元(20，20')。本级的GOA驱动单元(20，20')包括：上拉模块（21）、上拉控制模块（22）、以及选择模块（25）。上拉模块（21）包括第一晶体管（T11），其源极连接至选择模块（25），其栅极通过第一节点（Q）连接至上拉控制模块（22），其漏极输出本级扫描信号（Gn）。选择模块（25）用以接收第一控制信号（EN1）与第二控制信号（EN2）以控制时钟信号（CK）是否输入至第一晶体管（T11）的源极。

Description

GOA驱动电路及显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种GOA驱动电路及显示面板。
 背景技术
GOA (阵列基板行驱动)技术利用现有液晶显示器阵列的薄膜晶体管制程将栅极行扫描驱动电路制作在阵列基板上，实现对栅极线逐行扫描的驱动方式。
现有技术中的GOA电路只能全屏幕显示，因此即使在待机状态下只需要显示部分区域或是显示低分辨率的图像时，仍需全屏幕显示，使得功耗较大。另外，在通过倍频分时技术显示左右眼影像以实现3D显示效果时，现有技术中的GOA电路的全屏幕显示只能在同一位置显示左眼图像及右眼图像，人脑在合成左右眼图像时容易出现头晕呕吐等不适感。
 技术问题
申请提出一种GOA驱动电路及显示面板，可选择性输出扫描信号，达到部份显示画面的功能，以降低功耗。同时也可以应用在3D显示，在显示左右图像时，使左眼图像及右眼图像的像素位置不同以帮助人脑的左右眼图像合成，改善3D显示效果。
 技术解决方案
本申请实施例提供一种GOA驱动电路，包括：
多个级联的GOA驱动单元，其中，本级的GOA驱动单元包括：上拉模块、上拉控制模块、下拉模块、下拉维持模块以及选择模块；
其中，所述上拉模块包括：
第一晶体管，其源极连接至所述选择模块，其栅极通过第一节点连接至所述上拉控制模块，其漏极输出本级扫描信号；以及
第十一晶体管，其源极接入时钟信号，其栅极连接所述第一节点，其漏极用以向下一级GOA驱动单元输出本级起始信号；
所述上拉控制模块用以接收上一级GOA驱动单元的起始讯号并通过第一节点控制所述第一晶体管与第十一晶体管的启闭；
所述选择模块用以接收第一控制信号与第二控制信号以控制所述时钟信号是否输入至所述第一晶体管的所述源极。
本发明实施例所述GOA驱动电路中，其中所述上拉控制模块包括起始晶体管，其源极与栅极接入所述上一级GOA驱动单元的所述起始信号，其漏极连接至第一节点。
本发明实施例所述GOA驱动电路中，其中所述选择模块包括第一控制晶体管以及第二控制晶体管，所述第一控制晶体管的源极接入所述时钟信号，所述第一控制晶体管的栅极接入所述第一控制信号，所述第一控制晶体管的漏极连接所述第二控制晶体管的源极，所述第二控制晶体管的栅极接入所述第二控制信号，所述第二控制晶体管的漏极连接至参考低电平，所述第一晶体管通过所述第一控制晶体管接入所述时钟信号，所述第一晶体管通过所述第二控制晶体管连接至所述参考低电平。
本发明实施例所述GOA驱动电路中，其中所述第二控制信号的相位与所述第一控制信号的相位完全相反。
本发明实施例所述GOA驱动电路中，其中所述下拉模块包括：
第二晶体管，其源极连接所述第一晶体管的漏极，其栅极接入下一级GOA驱动单元的起始信号，其漏极连接第二低电平；以及
第十二晶体管，其源极连接所述第一节点，其栅极连接所述下一级GOA驱动单元的所述起始信号，其漏极连接第一低电平。
本发明实施例所述GOA驱动电路中，其中所述下拉维持模块包括：
第三晶体管，其源极连接所述第一节点，其栅极连接第二节点，其漏极连接所述第一低电平；
第四晶体管，其源极接入所述本级扫描信号，其栅极连接所述第二节点，其漏极连接第二低电平；
第五晶体管，其源极接入所述本级起始信号，其栅极连接所述第二节点，其漏极连接第一低电平；
第六晶体管，其源极与栅极接入第一开关信号；
第七晶体管，其源极连接所述第六晶体管的漏极，其栅极连接所述第一节点，其漏极连接所述第一低电平；
第八晶体管，其源极接入所述第一开关信号，其栅极连接所述第六晶体管的漏极；以及
第九晶体管，其源极连接所述第八晶体管的漏极，其栅极连接所述第一节点，其漏极连接所述第一低电平。
本发明实施例所述GOA驱动电路中，其中所述下拉维持模块还包括：
第十三晶体管，其源极接入所述扫描信号，其栅极连接第三节点，其漏极连接所述第二低电平；
第十四晶体管，其源极连接所述第一节点，其栅极连接所述第三节点，其漏极连接所述第一低电平；
第十五晶体管，其源极接入所述本级起始信号，其栅极连接所述第三节点，其漏极连接所述第一低电平；
第十六晶体管，其源极与栅极接入第二开关信号；
第十七晶体管，其源极连接所述第十六晶体管的漏极，其栅极连接第一节点，其漏极连接所述第一低电平；
第十八晶体管，其源极接入所述第二开关信号，其栅极连接所述第十六晶体管的漏极；以及
第十九晶体管，其源极连接所述第十八晶体管的漏极，其栅极连接第一节点，其漏极连接所述第一低电平。
本申请尚提供一种显示面板，其特征在于，包括GOA驱动电路、阵列基板及选择电路，其中，所述GOA驱动电路，包括多个级联的GOA驱动单元，其中，本级的GOA驱动单元包括：上拉模块、上拉控制模块、下拉模块、下拉维持模块以及选择模块；
其中，所述上拉模块包括：
第一晶体管，其源极连接至所述选择模块，其栅极通过第一节点连接至所述上拉控制模块，其漏极输出本级扫描信号；以及
第十一晶体管，其源极接入时钟信号，其栅极连接所述第一节点，其漏极用以向下一级GOA驱动单元输出本级起始信号；
所述上拉控制模块用以接收上一级GOA驱动单元的起始讯号并通过第一节点控制所述第一晶体管与第十一晶体管的启闭；
所述选择模块用以接收第一控制信号与第二控制信号以控制所述时钟信号是否输入至所述第一晶体管的所述源极；
所述选择电路包含第一致能线与第二致能线，所述第一致能线用以提供一部分所述GOA驱动单元所述第一控制信号，所述第二致能线用以提供另一部分所述GOA驱动单元所述第一控制信号。
本发明实施例所述显示面板中，其中每一所述GOA驱动单元包括反向器，用以反转所述第一控制信号以产生对应的所述第二控制信号。
本发明实施例所述显示面板中，其中单数级的所述GOA驱动单元连接至所述第一致能线，偶数级的所述GOA驱动单元连接至所述第二致能线。
本发明实施例所述显示面板中，其中所述上拉控制模块包括起始晶体管，其源极与栅极接入所述上一级GOA驱动单元的所述起始信号，其漏极连接至第一节点。
本发明实施例所述显示面板中，其中所述选择模块包括第一控制晶体管以及第二控制晶体管，所述第一控制晶体管的源极接入所述时钟信号，所述第一控制晶体管的栅极接入所述第一控制信号，所述第一控制晶体管的漏极连接所述第二控制晶体管的源极，所述第二控制晶体管的栅极接入所述第二控制信号，所述第二控制晶体管的漏极连接至参考低电平，所述第一晶体管通过所述第一控制晶体管接入所述时钟信号，所述第一晶体管通过所述第二控制晶体管连接至所述参考低电平。
本发明实施例所述显示面板中，其中所述第二控制信号的相位与所述第一控制信号的相位完全相反。
本发明实施例所述显示面板中，其中所述下拉模块包括：
第二晶体管，其源极连接所述第一晶体管的漏极，其栅极接入下一级GOA驱动单元的起始信号，其漏极连接第二低电平；以及
第十二晶体管，其源极连接所述第一节点，其栅极连接所述下一级GOA驱动单元的所述起始信号，其漏极连接第一低电平。
本发明实施例所述显示面板中，其中所述下拉维持模块包括：
第三晶体管，其源极连接所述第一节点，其栅极连接第二节点，其漏极连接所述第一低电平；
第四晶体管，其源极接入所述本级扫描信号，其栅极连接所述第二节点，其漏极连接第二低电平；
第五晶体管，其源极接入所述本级起始信号，其栅极连接所述第二节点，其漏极连接第一低电平；
第六晶体管，其源极与栅极接入第一开关信号；
第七晶体管，其源极连接所述第六晶体管的漏极，其栅极连接所述第一节点，其漏极连接所述第一低电平；
第八晶体管，其源极接入所述第一开关信号，其栅极连接所述第六晶体管的漏极；以及
第九晶体管，其源极连接所述第八晶体管的漏极，其栅极连接所述第一节点，其漏极连接所述第一低电平。
本发明实施例所述显示面板中，其中所述下拉维持模块还包括：
第十三晶体管，其源极接入所述扫描信号，其栅极连接第三节点，其漏极连接所述第二低电平；
第十四晶体管，其源极连接所述第一节点，其栅极连接所述第三节点，其漏极连接所述第一低电平；
第十五晶体管，其源极接入所述本级起始信号，其栅极连接所述第三节点，其漏极连接所述第一低电平；
第十六晶体管，其源极与栅极接入第二开关信号；
第十七晶体管，其源极连接所述第十六晶体管的漏极，其栅极连接第一节点，其漏极连接所述第一低电平；
第十八晶体管，其源极接入所述第二开关信号，其栅极连接所述第十六晶体管的漏极；以及
第十九晶体管，其源极连接所述第十八晶体管的漏极，其栅极连接第一节点，其漏极连接所述第一低电平。
本申请尚提供一种显示面板，其特征在于，包括GOA驱动电路、阵列基板及选择电路，其中，所述GOA驱动电路，包括多个级联的GOA驱动单元，其中，本级的GOA驱动单元包括：上拉模块、上拉控制模块、下拉模块、下拉维持模块以及选择模块；
其中，所述上拉模块包括：
第一晶体管，其源极连接至所述选择模块，其栅极通过第一节点连接至所述上拉控制模块，其漏极输出本级扫描信号；以及
第十一晶体管，其源极接入时钟信号，其栅极连接所述第一节点，其漏极用以向下一级GOA驱动单元输出本级起始信号；
所述上拉控制模块包括起始晶体管，其源极与栅极接入所述上一级GOA驱动单元的所述起始信号，其漏极连接至第一节点；
所述上拉控制模块用以接收上一级GOA驱动单元的起始讯号并通过第一节点控制所述第一晶体管与第十一晶体管的启闭；
所述选择模块用以接收第一控制信号与第二控制信号以控制所述时钟信号是否输入至所述第一晶体管的所述源极；
所述选择电路包含第一致能线与第二致能线，其中，所述第一致能线用以提供一部分所述GOA驱动单元所述第一控制信号；
所述第二致能线用以提供另一部分所述GOA驱动单元所述第一控制信号。
本发明实施例所述显示面板中，其中，所述选择模块包括第一控制晶体管以及第二控制晶体管，所述第一控制晶体管的源极接入所述时钟信号，所述第一控制晶体管的栅极接入所述第一控制信号，所述第一控制晶体管的漏极连接所述第二控制晶体管的源极，所述第二控制晶体管的栅极接入所述第二控制信号，所述第二控制晶体管的漏极连接至参考低电平，所述第一晶体管通过所述第一控制晶体管接入所述时钟信号，所述第一晶体管通过所述第二控制晶体管连接至所述参考低电平。
 有益效果
本申请的有益效果为：本申请实施例的GOA驱动电路及显示面板提供所述选择模块，可以选择性输出扫描信号Gn，不会影响GOA驱动单元的级传功能，即可通过第一控制信号以及第二控制信号的电平高低来控制扫描信号Gn的输出。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果清楚呈现。
图1为本申请实施例提供的GOA驱动电路示意图；
图2为本申请实施例提供的显示面板示意图；
图3为本申请另一实施例提供的显示面板示意图；
图4为本申请实施例的GOA驱动电路提供低电位扫描信号时的信号时序图；
图5为本申请实施例的GOA驱动电路提供高电位扫描信号时的信号时序图。
 本发明的实施方式
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是支撑连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
下面结合附图和实施例对本申请作进一步说明。
具体的，请参阅图1至图2，本申请实施例提供一种GOA驱动电路。GOA驱动电路包含多个级联的GOA驱动单元20、20’，其中，本级的GOA驱动单元20、20’包括：上拉模块21、上拉控制模块22、下拉模块23、下拉维持模块24以及选择模块25。所述上拉模块21包括：第一晶体管T11以及第十一晶体管T12，第一晶体管T11的源极连接至所述选择模块25，其栅极通过第一节点Q连接至所述上拉控制模块22，其漏极输出本级扫描信号Gn。第十一晶体管的源极接入时钟信号CK，其栅极连接所述第一节点Q，其漏极用以向下一级GOA驱动单元输出本级起始信号STn。所述上拉控制模块22用以接收上一级GOA驱动单元的起始讯号STn-1并通过第一节点Q控制所述第一晶体管T11与第十一晶体管T12的启闭。所述选择模块25用以接收第一控制信号EN1与第二控制信号EN2以控制所述时钟信号CK是否输入至所述第一晶体管T11的所述源极。
所述上拉控制模块22包括起始晶体管T1，其源极与栅极接入所述上一级GOA驱动单元的所述起始信号STn-1，其漏极连接至第一节点Q。所述选择模块25包括第一控制晶体管T2以及第二控制晶体管T3，所述第一控制晶体管T2的源极接入所述时钟信号CK，所述第一控制晶体管T2的栅极接入所述第一控制信号EN1，所述第一控制晶体管T2的漏极连接所述第二控制晶体管T3的源极，所述第二控制晶体管T3的栅极接入所述第二控制信号EN2，所述第二控制晶体管T3的漏极连接至参考低电平VGL，所述第一晶体管T11通过所述第一控制晶体管T2接入所述时钟信号CK，所述第一晶体管T1通过所述第二控制晶体管T3连接至所述参考低电平VGL。
参照图4、图5，所述第二控制信号EN2的相位与所述第一控制信号EN1的相位完全相反。
参照图1、图2，所述下拉模块23包括：第二晶体管T21以及第十二晶体管T22。第二晶体管T21的源极连接所述第一晶体管T11的漏极，其栅极接入下一级GOA驱动单元的起始信号STn+1，其漏极连接第二低电平VSS2。第十二晶体管T22，其源极连接所述第一节点Q，其栅极连接所述下一级GOA驱动单元的所述起始信号STn+1，其漏极连接第一低电平VSS1。
所述下拉维持模块24包括：第三晶体管T31、第四晶体管T41、第五晶体管T51、第六晶体管T61、第七晶体管T71、第八晶体管T81、以及第九晶体管T91。第三晶体管T31、第四晶体管T41以及第五晶体管T51的栅极均连接至第二节点P，第三晶体管T31的源极连接至第一节点Q，其漏极连接至第一低电平VSS1，第四晶体管T41的源极接入本级扫描信号Gn，第四晶体管T41的漏极连接至第二低电平VSS2，第五晶体管T51的源极接入本级起始信号STn，第五晶体管T51的漏极连接至第一低电平VSS1。
第六晶体管T61的栅极与源极相连并接入第一开关信号LC1，第七晶体管T71的栅极连接至第一节点Q，第七晶体管T71的源极连接至第六晶体管T61的漏极，第七晶体管T71的漏极连接至第一低电平VSS1，第八晶体管T81的栅极连接至第六晶体管T61的漏极，即第八晶体管T81的栅极与第七晶体管T71的源极相连，第八晶体管T81的源极连接至第六晶体管T61的栅极，即第八晶体管T81的源极接入第一开关信号LC1，第八晶体管T81的漏极连接至第二节点P，第九晶体管T91的源极连接至第二节点P，即第九晶体管T91的源极与第八晶体管T81的漏极相连，第九晶体管T91的栅极连接至第一节点Q，第九晶体管T91的漏极连接至第一低电平VSS1。
本级的GOA驱动单元还可包括重置模块26，重置模块26包含第十晶体管T10，第十晶体管T10的源极与起始晶体管T1的漏极相连，第十晶体管T10的栅极接入重置信号reset，第十晶体管T10的漏极连接至第一低电平VSS1。重置模块26用以接收重置信号reset将第一节点Q的电位拉至低电位以重置本级的GOA驱动单元。
所述下拉维持模块24还包含第十三晶体管T32、第十四晶体管T42、第十五晶体管T52、第十六晶体管T62、第十七晶体管T72、第十八晶体管T82以及第十九晶体管T92。第十三晶体管T32、第十四晶体管T42以及第十五晶体管T52的栅极均连接至第三节点K，第十三晶体管T32的源极接入本级扫描信号Gn，第十三晶体管T32的漏极连接至第二低电平VSS2，第十四晶体管T42的源极连接至第一节点Q，第十四晶体管T42的漏极连接至第一低电平VSS1，第十五晶体管T52的源极接入本级起始信号STn，第十五晶体管T52的漏极连接至第一低电平VSS1。
第十六晶体管T62的栅极与源极相连并接入第二开关信号LC2，第十七晶体管T72的栅极连接至第一节点Q，第十七晶体管T72的源极连接至第十六晶体管T62的漏极，第十七晶体管T72的漏极连接至第一低电平VSS1，第十八晶体管T82的栅极连接至第十六晶体管T62的漏极，即第十八晶体管T82的栅极与第十七晶体管T72的源极相连，第十八晶体管T82的源极连接至第十六晶体管T62的栅极，即第十八晶体管T82的源极接入第二开关信号LC2，第十八晶体管T82的漏极连接至第三节点K，第十九晶体管T92的源极连接至第三节点K，即第十九晶体管T92的源极与第十八晶体管T82的漏极相连，第十九晶体管T92的栅极连接至第一节点Q，第十九晶体管T92的漏极连接至第一低电平VSS1。
请一并参考图4及图5，本级的GOA驱动单元在上一级GOA驱动单元的起始信号STn-1为高电平、时钟信号CK为低电平时，上拉控制模块22的起始晶体管T1导通，第一节点Q上拉为第一高电平将上拉模块21的第一晶体管T11与第十一晶体管T12导通，但是因为时钟信号CK为低电平，所以此时本级的扫描信号Gn及本级起始信号STn仍为低电平。另外，下拉维持模块24此时结束下拉维持的工作，其第七晶体管T71、第九晶体管T91、第十七晶体管T72及第十九晶体管T92因为Q点的高电位而导通，拉下第二节点P及第三节点K的电位至低电平使得第三晶体管T31、第四晶体管T41、第五晶体管T51、第十三晶体管T32、第十四晶体管T42及第十五晶体管T52不导通，以免后续第三晶体管T31、第四晶体管T41、第五晶体管T51、第十三晶体管T32、第十四晶体管T42及第十五晶体管T52将第一节点Q、本级扫描信号Gn及本级起始信号STn的电位拉低。
参照图5，在下一个时脉中，上一级的起始信号STn-1为低电平、时钟信号CK为高电平，上拉控制模块22的起始晶体管T1关闭，第一节点Q处于浮动(floating)状态，自举电容C由于时钟信号CK由低电平转为高电平而产生耦合(coupling)效应，使得第一节点Q的电位自举至第二高电平，第一晶体管T11与第十一晶体管T12完全导通，本级扫描信号Gn及本级起始信号STn输出高电平。
接着在下一时脉中，上一级的起始信号STn-1仍然为低电平，时钟信号CK转为低电平，下一级GOA驱动单元的起始信号STn+1转为高电平，下拉模块23中的第二晶体管T21与第十二晶体管T22因而导通使得本级扫描信号Gn、第一节点Q均被下拉至低电平，由于第一节点Q被下拉至低电平，因此下拉维持模块24中的第七晶体管T71、第九晶体管T91、第十七晶体管T72及第十九晶体管T92不导通，即第二节点P与第三节点K不再被拉至低电平，以便下一时脉的下拉维持模块24的启动。
接着在下一时脉中，第一开关信号LC1或第二开关信号LC2为高电平。其中，第一开关信号LC1与第二开关信号LC2的相位相反，使得下拉维持模块24的右半边电路与左半边电路可以交替的工作，即当第一开关信号LC1为高电平时，第二开关信号LC2为低电平，下拉维持模块24右半边的第六晶体管T61及第八晶体管T81导通使得第二节点P上拉为高电平，因此第三晶体管T31、第四晶体管T41及第五晶体管T51导通，以分别维持第一节点Q、本级扫描信号Gn及本级起始信号STn的电平持续拉低，即下拉维持模块24的右半边电路运作以维持本级信号的低电位。同理，当第二开关信号LC2为高电平时，第一开关信号LC1为低电平，下拉维持模块24左半边的第十六晶体管T62及第十八晶体管T82导通使得第三节点K上拉为高电平，因此第十三晶体管T32、第十四晶体管T42及第十五晶体管T52导通，以分别维持第一节点Q、本级扫描信号Gn及本级起始信号STn的电平持续拉低。第一开关信号LC1与第二开关信号LC2的相位相反，使得下拉维持模块24的右半边电路的晶体管与左半边电路的晶体管可以交替的工作，以避免晶体管因长期偏压而造成晶体管阈值电压漂移。
参照图1、图4及图5，本申请尚有第一控制信号EN1及第二控制信号EN2分别控制第一控制晶体管T2的栅极及第二控制晶体管T3的栅极。当本级扫描信号Gn需输出高电位的扫描信号时，第一控制信号EN1为高电平，第二控制信号EN2为低电平使得时钟信号CK能通过第一晶体管T11而使本级扫描信号Gn输出高电平，如图5所示。当本级扫描信号Gn需输出低电平的扫描信号时，第一控制信号EN1为低电平，第二控制信号EN2为高电平使得时钟信号CK一律被拉低而使第一晶体管T11输出低电平的本级扫描信号Gn，如图4所示。
参照图2，本发明尚提供一种显示面板100，其特征在于，包括任一上述的GOA驱动电路、阵列基板10及选择电路40，其中，所述选择电路40包含第一致能线EN-R与第二致能线EN-L，所述第一致能线EN-R用以提供一部分所述GOA驱动单元20所述第一控制信号EN1，所述第二致能线EN-L用以提供另一部分所述GOA驱动单元20’所述第一控制信号EN1。
具体的，所述GOA驱动电路设置于所述阵列基板10上。所述显示面板100还包括多个源极驱动电路30、多条栅极线GL与多条资料线DL设置于所述阵列基板10上。每条栅极线GL与数据线DL交会处设有画素电路（图未绘示），所述GOA驱动单元20、20’与栅极线GL一一对应，用以提供扫描信号。
具体的，所述选择电路40透过第一致能线EN-R与第二致能线EN-L控制显示面板100右半边显示而左半边不显示，或是左半边显示而右半边不显示。显示面板100可适用于某些种类的3D立体显示，使得左眼影像与右眼影像可以分别显示。
具体的，参照图1与图2，所述GOA驱动单元20、20’的级传功能是透过起始信号，即上一级启始信号STn-1、本级起始信号STn、下一级启始信号STn+1等传递，因此，即使选择电路40控制某些GOA驱动单元20、20’的扫描信号下拉至低电平，也不影响GOA驱动单元20、20’的级传功能。
于本发明的一实施例中，每一所述GOA驱动单元20、20’包括反向器50，用以反转所述第一控制信号EN1以产生对应的所述第二控制信号EN2。
参照图3，于本发明的一实施例中，显示面板100’ 的单数级的所述GOA驱动单元20连接至所述第一致能线EN-R，偶数级的所述GOA驱动单元20’连接至所述第二致能线EN-L。具体的，所述选择电路40透过第一致能线EN-R与第二致能线EN-L控制显示面板100’单数级的所述GOA驱动单元20显示而偶数级的所述GOA驱动单元20’不显示，或是偶数级的所述GOA驱动单元20’显示而单数级的所述GOA驱动单元20不显示。显示面板100’可适用于某些具有棱镜板的3D立体显示，使得左眼影像与右眼影像可以分别显示。显示面板100’还可适用于某些需要节能的使用情境，使得显示面板100’仅有一半的画素进行显示以节省电能。
以上仅为选择电路40与 GOA驱动单元20、20’的几种配置方式，本发明不限于此，还可依实际需求进行选择电路40与 GOA驱动单元20、20’的配置，例如依序每两个GOA驱动单元为一组进行交互启动与关闭，或是每三个GOA驱动单元为一组等。
本申请实施例的GOA驱动电路及显示面板提供所述选择模块，可以选择性输出扫描信号，不会影响GOA驱动单元的级传功能，即可通过第一控制信号以及第二控制信号的电平高低来控制扫描信号的输出。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种电子装置进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (18)

  1. 一种GOA驱动电路，包括：
    多个级联的GOA驱动单元，其中，本级的GOA驱动单元包括：上拉模块、上拉控制模块、下拉模块、下拉维持模块以及选择模块；
    其中，所述上拉模块包括：
    第一晶体管，其源极连接至所述选择模块，其栅极通过第一节点连接至所述上拉控制模块，其漏极输出本级扫描信号；以及
    第十一晶体管，其源极接入时钟信号，其栅极连接所述第一节点，其漏极用以向下一级GOA驱动单元输出本级起始信号；
    所述上拉控制模块用以接收上一级GOA驱动单元的起始讯号并通过第一节点控制所述第一晶体管与第十一晶体管的启闭；
    所述选择模块用以接收第一控制信号与第二控制信号以控制所述时钟信号是否输入至所述第一晶体管的所述源极。
  2. 如权利要求1所述的GOA驱动电路，其中，所述上拉控制模块包括起始晶体管，其源极与栅极接入所述上一级GOA驱动单元的所述起始信号，其漏极连接至第一节点。
  3. 如权利要求2所述的GOA驱动电路，其中，所述选择模块包括第一控制晶体管以及第二控制晶体管，所述第一控制晶体管的源极接入所述时钟信号，所述第一控制晶体管的栅极接入所述第一控制信号，所述第一控制晶体管的漏极连接所述第二控制晶体管的源极，所述第二控制晶体管的栅极接入所述第二控制信号，所述第二控制晶体管的漏极连接至参考低电平，所述第一晶体管通过所述第一控制晶体管接入所述时钟信号，所述第一晶体管通过所述第二控制晶体管连接至所述参考低电平。
  4. 如权利要求3所述的GOA驱动电路，其中，所述第二控制信号的相位与所述第一控制信号的相位完全相反。
  5. 如权利要求3所述的GOA驱动电路，其中，所述下拉模块包括：
    第二晶体管，其源极连接所述第一晶体管的漏极，其栅极接入下一级GOA驱动单元的起始信号，其漏极连接第二低电平；以及
    第十二晶体管，其源极连接所述第一节点，其栅极连接所述下一级GOA驱动单元的所述起始信号，其漏极连接第一低电平。
  6. 如权利要求3所述的GOA驱动电路，其中，所述下拉维持模块包括：
    第三晶体管，其栅极连接第二节点，其源极连接所述第一节点，其漏极连接第一低电平；
    第四晶体管，其源极接入所述本级扫描信号，其栅极连接所述第二节点，其漏极连接第二低电平；
    第五晶体管，其源极接入所述本级起始信号，其栅极连接所述第二节点，其漏极连接第一低电平；
    第六晶体管，其源极与栅极接入第一开关信号；
    第七晶体管，其源极连接所述第六晶体管的漏极，其栅极连接所述第一节点，其漏极连接所述第一低电平；
    第八晶体管，其源极接入所述第一开关信号，其栅极连接所述第六晶体管的漏极；以及
    第九晶体管，其源极连接所述第八晶体管的漏极，其栅极连接所述第一节点，其漏极连接所述第一低电平。
  7. 如权利要求6所述的GOA驱动电路，其中，所述下拉维持模块包括：
    第十三晶体管，源极接入所述本级扫描信号，其栅极连接第三节点，其漏极连接所述第二低电平；
    第十四晶体管，其源极连接所述第一节点，其栅极连接所述第三节点，其漏极连接所述第一低电平；
    第十五晶体管，其源极接入所述本级起始信号，其栅极连接所述第三节点，其漏极连接所述第一低电平；
    第十六晶体管，其源极与栅极接入第二开关信号；
    第十七晶体管，其源极连接所述第十六晶体管的漏极，其栅极连接第一节点，其漏极连接所述第一低电平；
    第十八晶体管，其源极接入所述第二开关信号，其栅极连接所述第十六晶体管的漏极；以及
    第十九晶体管，其源极连接所述第十八晶体管的漏极，其栅极连接第一节点，其漏极连接所述第一低电平。
  8. 一种显示面板，包括GOA驱动电路、阵列基板及选择电路，其中，所述GOA驱动电路，包括多个级联的GOA驱动单元，其中，本级的GOA驱动单元包括：上拉模块、上拉控制模块、下拉模块、下拉维持模块以及选择模块；
    其中，所述上拉模块包括：
    第一晶体管，其源极连接至所述选择模块，其栅极通过第一节点连接至所述上拉控制模块，其漏极输出本级扫描信号；以及
    第十一晶体管，其源极接入时钟信号，其栅极连接所述第一节点，其漏极用以向下一级GOA驱动单元输出本级起始信号；
    所述上拉控制模块用以接收上一级GOA驱动单元的起始讯号并通过第一节点控制所述第一晶体管与第十一晶体管的启闭；
    所述选择模块用以接收第一控制信号与第二控制信号以控制所述时钟信号是否输入至所述第一晶体管的所述源极；
    所述选择电路包含第一致能线与第二致能线，其中，所述第一致能线用以提供一部分所述GOA驱动单元所述第一控制信号；
    所述第二致能线用以提供另一部分所述GOA驱动单元所述第一控制信号。
  9. 如权利要求8所述的显示面板，其中，每一所述GOA驱动单元包括反向器，用以反转所述第一控制信号以产生对应的所述第二控制信号。
  10. 如权利要求8所述的显示面板，其中，单数级的所述GOA驱动单元连接至所述第一致能线，偶数级的所述GOA驱动单元连接至所述第二致能线。
  11. 如权利要求10所述的显示面板，其中，所述上拉控制模块包括起始晶体管，其源极与栅极接入所述上一级GOA驱动单元的所述起始信号，其漏极连接至第一节点。
  12. 如权利要求11所述的显示面板，其中，所述选择模块包括第一控制晶体管以及第二控制晶体管，所述第一控制晶体管的源极接入所述时钟信号，所述第一控制晶体管的栅极接入所述第一控制信号，所述第一控制晶体管的漏极连接所述第二控制晶体管的源极，所述第二控制晶体管的栅极接入所述第二控制信号，所述第二控制晶体管的漏极连接至参考低电平，所述第一晶体管通过所述第一控制晶体管接入所述时钟信号，所述第一晶体管通过所述第二控制晶体管连接至所述参考低电平。
  13. 如权利要求12所述的显示面板，其中，所述第二控制信号的相位与所述第一控制信号的相位完全相反。
  14. 如权利要求12所述的显示面板，其中，所述下拉模块包括：
    第二晶体管，其源极连接所述第一晶体管的漏极，其栅极接入下一级GOA驱动单元的起始信号，其漏极连接第二低电平；以及
    第十二晶体管，其源极连接所述第一节点，其栅极连接所述下一级GOA驱动单元的所述起始信号，其漏极连接第一低电平。
  15. 如权利要求12所述的显示面板，其中，所述下拉维持模块包括：
    第三晶体管，其栅极连接第二节点，其源极连接所述第一节点，其漏极连接第一低电平；
    第四晶体管，其源极接入所述本级扫描信号，其栅极连接所述第二节点，其漏极连接第二低电平；
    第五晶体管，其源极接入所述本级起始信号，其栅极连接所述第二节点，其漏极连接第一低电平；
    第六晶体管，其源极与栅极接入第一开关信号；
    第七晶体管，其源极连接所述第六晶体管的漏极，其栅极连接所述第一节点，其漏极连接所述第一低电平；
    第八晶体管，其源极接入所述第一开关信号，其栅极连接所述第六晶体管的漏极；以及
    第九晶体管，其源极连接所述第八晶体管的漏极，其栅极连接所述第一节点，其漏极连接所述第一低电平。
  16. 如权利要求15所述的显示面板，其中，所述下拉维持模块包括：
    第十三晶体管，源极接入所述本级扫描信号，其栅极连接第三节点，其漏极连接所述第二低电平；
    第十四晶体管，其源极连接所述第一节点，其栅极连接所述第三节点，其漏极连接所述第一低电平；
    第十五晶体管，其源极接入所述本级起始信号，其栅极连接所述第三节点，其漏极连接所述第一低电平；
    第十六晶体管，其源极与栅极接入第二开关信号；
    第十七晶体管，其源极连接所述第十六晶体管的漏极，其栅极连接第一节点，其漏极连接所述第一低电平；
    第十八晶体管，其源极接入所述第二开关信号，其栅极连接所述第十六晶体管的漏极；以及
    第十九晶体管，其源极连接所述第十八晶体管的漏极，其栅极连接第一节点，其漏极连接所述第一低电平。
  17. 一种显示面板，包括GOA驱动电路、阵列基板及选择电路，其中，所述GOA驱动电路，包括多个级联的GOA驱动单元，其中，本级的GOA驱动单元包括：上拉模块、上拉控制模块、下拉模块、下拉维持模块以及选择模块；
    其中，所述上拉模块包括：
    第一晶体管，其源极连接至所述选择模块，其栅极通过第一节点连接至所述上拉控制模块，其漏极输出本级扫描信号；以及
    第十一晶体管，其源极接入时钟信号，其栅极连接所述第一节点，其漏极用以向下一级GOA驱动单元输出本级起始信号；
    所述上拉控制模块包括起始晶体管，其源极与栅极接入所述上一级GOA驱动单元的所述起始信号，其漏极连接至第一节点；
    所述上拉控制模块用以接收上一级GOA驱动单元的起始讯号并通过第一节点控制所述第一晶体管与第十一晶体管的启闭；
    所述选择模块用以接收第一控制信号与第二控制信号以控制所述时钟信号是否输入至所述第一晶体管的所述源极；
    所述选择电路包含第一致能线与第二致能线，其中，所述第一致能线用以提供一部分所述GOA驱动单元所述第一控制信号；
    所述第二致能线用以提供另一部分所述GOA驱动单元所述第一控制信号。
  18. 如权利要求17所述的显示面板，其中，所述选择模块包括第一控制晶体管以及第二控制晶体管，所述第一控制晶体管的源极接入所述时钟信号，所述第一控制晶体管的栅极接入所述第一控制信号，所述第一控制晶体管的漏极连接所述第二控制晶体管的源极，所述第二控制晶体管的栅极接入所述第二控制信号，所述第二控制晶体管的漏极连接至参考低电平，所述第一晶体管通过所述第一控制晶体管接入所述时钟信号，所述第一晶体管通过所述第二控制晶体管连接至所述参考低电平。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114743482A (zh) * 2022-03-28 2022-07-12 Tcl华星光电技术有限公司 基于goa的显示面板
CN115862514A (zh) * 2022-12-16 2023-03-28 Tcl华星光电技术有限公司 栅极驱动电路及显示面板

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114974114B (zh) * 2022-05-26 2024-10-25 合肥京东方卓印科技有限公司 显示驱动电路、方法、显示面板及其制备方法、装置
CN115641803B (zh) 2022-11-02 2025-07-25 惠州华星光电显示有限公司 栅极驱动电路及显示面板
CN116364015A (zh) * 2023-04-12 2023-06-30 云谷（固安）科技有限公司 扫描驱动电路、显示装置及其驱动方法
CN117475950B (zh) * 2023-08-28 2026-01-13 Tcl华星光电技术有限公司 栅极驱动电路及显示面板
CN119626179B (zh) * 2025-01-20 2025-09-16 广州华星光电半导体显示技术有限公司 显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130301793A1 (en) * 2010-05-10 2013-11-14 Mitsubishi Electric Corporation Shift register circuit
CN106104665A (zh) * 2014-03-10 2016-11-09 乐金显示有限公司 显示装置
CN106683631A (zh) * 2016-12-30 2017-05-17 深圳市华星光电技术有限公司 一种igzo薄膜晶体管的goa电路及显示装置
CN106875911A (zh) * 2017-04-12 2017-06-20 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及其驱动方法
CN107564477A (zh) * 2016-06-30 2018-01-09 乐金显示有限公司 有机发光显示器
CN108231029A (zh) * 2018-01-29 2018-06-29 京东方科技集团股份有限公司 栅极驱动电路、显示装置及驱动方法
CN111312190A (zh) * 2020-04-01 2020-06-19 深圳市华星光电半导体显示技术有限公司 Goa驱动电路及其正负极性充电补偿方法、显示面板

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101573460B1 (ko) * 2009-04-30 2015-12-02 삼성디스플레이 주식회사 게이트 구동회로
CN105047158B (zh) * 2015-08-21 2017-11-10 深圳市华星光电技术有限公司 一种goa电路及液晶显示器
CN106782395B (zh) * 2016-12-30 2019-02-26 深圳市华星光电技术有限公司 Goa电路的驱动方法和驱动装置
US10484577B1 (en) * 2017-08-15 2019-11-19 Facebook Technologies, Llc Real-time interleaved multi-scan-out
CN107424554B (zh) * 2017-09-26 2020-06-02 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN108648711B (zh) * 2018-06-08 2020-10-02 厦门天马微电子有限公司 一种阵列基板、显示面板及显示装置
CN110178174B (zh) * 2018-09-28 2020-05-08 华为技术有限公司 一种栅极驱动电路及其控制方法、移动终端
CN109671386B (zh) * 2019-03-01 2021-11-23 合肥鑫晟光电科技有限公司 栅极驱动单元及其驱动方法、栅极驱动电路、显示装置
CN110021279A (zh) * 2019-03-05 2019-07-16 深圳市华星光电技术有限公司 Goa电路

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130301793A1 (en) * 2010-05-10 2013-11-14 Mitsubishi Electric Corporation Shift register circuit
CN106104665A (zh) * 2014-03-10 2016-11-09 乐金显示有限公司 显示装置
CN107564477A (zh) * 2016-06-30 2018-01-09 乐金显示有限公司 有机发光显示器
CN106683631A (zh) * 2016-12-30 2017-05-17 深圳市华星光电技术有限公司 一种igzo薄膜晶体管的goa电路及显示装置
CN106875911A (zh) * 2017-04-12 2017-06-20 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及其驱动方法
CN108231029A (zh) * 2018-01-29 2018-06-29 京东方科技集团股份有限公司 栅极驱动电路、显示装置及驱动方法
CN111312190A (zh) * 2020-04-01 2020-06-19 深圳市华星光电半导体显示技术有限公司 Goa驱动电路及其正负极性充电补偿方法、显示面板

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114743482A (zh) * 2022-03-28 2022-07-12 Tcl华星光电技术有限公司 基于goa的显示面板
CN114743482B (zh) * 2022-03-28 2024-06-11 Tcl华星光电技术有限公司 基于goa的显示面板
CN115862514A (zh) * 2022-12-16 2023-03-28 Tcl华星光电技术有限公司 栅极驱动电路及显示面板
CN115862514B (zh) * 2022-12-16 2024-03-15 Tcl华星光电技术有限公司 栅极驱动电路及显示面板

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