WO2022052927A1 - 发光二极管外延片及其制备方法 - Google Patents

发光二极管外延片及其制备方法 Download PDF

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WO2022052927A1
WO2022052927A1 PCT/CN2021/117073 CN2021117073W WO2022052927A1 WO 2022052927 A1 WO2022052927 A1 WO 2022052927A1 CN 2021117073 W CN2021117073 W CN 2021117073W WO 2022052927 A1 WO2022052927 A1 WO 2022052927A1
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hole injection
layer
type gan
emitting diode
epitaxial wafer
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PCT/CN2021/117073
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English (en)
French (fr)
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洪威威
王倩
梅劲
董彬忠
张奕
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华灿光电（浙江）有限公司
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Publication of WO2022052927A1 publication Critical patent/WO2022052927A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure

Definitions

  • the present disclosure relates to the field of light-emitting diode fabrication, in particular to a light-emitting diode epitaxial wafer and a preparation method thereof.
  • a light-emitting diode is a semiconductor electronic component that emits light.
  • Embodiments of the present disclosure provide a light-emitting diode epitaxial wafer and a method for fabricating the same, which can increase the number of holes entering the multiple quantum well layer to ultimately improve the light-emitting efficiency of the light-emitting diode.
  • the technical solution is as follows:
  • An embodiment of the present disclosure provides a light-emitting diode epitaxial wafer, the light-emitting diode epitaxial wafer includes a substrate and an n-type GaN layer, a multiple quantum well layer, an AlGaN electron blocking layer, and a p-type GaN layer sequentially stacked on the substrate layer,
  • the p-type GaN layer has a plurality of hole injection grooves distributed at intervals, each of the hole injection grooves extends from the p-type GaN layer to the multiple quantum well layer, and the light emitting diode epitaxial wafer is further It includes a plurality of GaN hole injection structures, and the plurality of GaN hole injection structures are distributed in the plurality of hole injection grooves in a one-to-one correspondence.
  • the material of the GaN hole injection structure is undoped GaN material.
  • the GaN hole injection structure fills the corresponding hole injection groove.
  • each hole injection groove gradually decreases from an end close to the p-type GaN layer to an end close to the n-type GaN layer.
  • each of the hole injection grooves is close to one end of the n-type GaN layer, and extends to the quantum well in the multiple quantum well layer that is closest to the p-type GaN layer.
  • the top surface of the hole injection groove is circular, and the diameter of the top surface of the hole injection groove ranges from 400 nm to 600 nm.
  • a plurality of the hole injection grooves are evenly distributed on the light emitting diode epitaxial wafer, and the minimum distance between two adjacent hole injection grooves is in the range of 1000 nm ⁇ 2000 nm.
  • the light emitting diode epitaxial wafer further includes a p-type GaN fill-in layer, and the p-type GaN fill-in layer is stacked on the p-type GaN layer and the plurality of GaN hole injection structures.
  • the thickness of the p-type GaN fill-in layer ranges from 20 nm to 50 nm.
  • an end face of each of the GaN hole injection structures close to one end of the p-type GaN layer is a convex conical face.
  • the thickness of the p-type GaN ranges from 70 nm to 100 nm.
  • An embodiment of the present disclosure provides a method for preparing a light-emitting diode epitaxial wafer, and the preparation method includes:
  • a plurality of hole injection grooves are formed in the p-type GaN layer, each of the hole injection grooves extends from the p-type GaN layer to the multi-quantum well layer, and in each of the hole injection grooves A GaN hole injection structure is grown.
  • a plurality of hole injection grooves are formed in the p-type GaN layer, each of the hole injection grooves extends from the p-type GaN layer to the multiple quantum well layer, and each of the hole injection grooves extends from the p-type GaN layer to the multiple quantum well layer.
  • a GaN hole injection structure is grown in the hole injection groove, including:
  • the SiO2 layer is removed.
  • the material of the GaN hole injection structure is undoped GaN material.
  • the GaN hole injection structure fills the corresponding hole injection groove.
  • FIG. 1 is a schematic structural diagram of a light-emitting diode epitaxial wafer provided by an embodiment of the present disclosure
  • FIG. 2 is a top view of a light-emitting diode epitaxial wafer provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of another light-emitting diode epitaxial wafer provided by an embodiment of the present disclosure
  • FIG. 4 is a flowchart of a method for preparing a light-emitting diode epitaxial wafer provided by an embodiment of the present disclosure
  • FIG. 5 is a flowchart of another method for fabricating a light-emitting diode epitaxial wafer provided by an embodiment of the present disclosure.
  • an epitaxial wafer of a light emitting diode generally includes a substrate and an n-type GaN layer, a multiple quantum well layer, an AlGaN electron blocking layer and a p-type GaN layer sequentially grown on the substrate.
  • the AlGaN electron blocking layer between the multiple quantum well layer and the p-type GaN layer can block the overflow of electrons in the multiple quantum well layer, but at the same time, the AlGaN electron blocking layer will also block the entry of the multiple quantum well from the p-type GaN layer.
  • the holes in the layer make it more difficult for holes whose mobility is lower than that of electrons to enter the quantum well layer.
  • the number of holes entering the multi-quantum well layer is much less than that of electrons, and the number of holes that can recombine with electrons in the multi-quantum well layer is less, and the luminous efficiency of the finally obtained light-emitting diode is not high.
  • FIG. 1 is a schematic structural diagram of a light-emitting diode epitaxial wafer provided by an embodiment of the present disclosure.
  • an embodiment of the present disclosure provides a light-emitting diode epitaxial wafer.
  • the light-emitting diode epitaxial wafer includes a substrate 1 and is sequentially stacked on the substrate.
  • the p-type GaN layer 5 has a plurality of hole injection grooves 6 distributed at intervals. Each hole injection groove 6 extends from the p-type GaN layer 5 to the multiple quantum well layer 3.
  • the light-emitting diode epitaxial wafer also includes a plurality of GaN holes. In the injection structure 7 , the plurality of GaN hole injection structures 7 are distributed in the plurality of hole injection grooves 6 in a one-to-one correspondence.
  • the light-emitting diode epitaxial wafer includes a substrate 1 and an n-type GaN layer 2, a multiple quantum well layer 3, an AlGaN electron blocking layer 4 and a p-type GaN layer 5 sequentially stacked on the substrate 1, and can realize the normal light-emitting function of the light-emitting diode.
  • the p-type GaN layer 5 has a plurality of hole injection grooves 6 distributed at intervals, and each hole injection groove 6 and the GaN hole injection structure 7 filling the hole injection groove 6 extend from the p-type GaN layer 5 at most Quantum well layer 3.
  • the GaN hole injection structure 7 can function as a channel.
  • the GaN hole injection structure 7 crosses the AlGaN electron blocking layer 4 and guides the holes in the p-type GaN layer 5 directly into the multiple quantum well layer 3 .
  • the resistance of holes entering the multiple quantum well layer 3 through the GaN hole injection structure 7 is relatively small compared to the resistance of passing through the AlGaN electron blocking layer 4 into the multiple quantum well layer 3 . Therefore, more holes can enter the multiple quantum well layer 3 through the GaN hole injection structure 7 to combine with electrons to emit light. As the number of holes entering the multiple quantum well layer 3 increases, the luminous efficiency of the finally obtained light-emitting diode will also be improved.
  • the GaN hole injection structure 7 may be an undoped GaN material.
  • the GaN hole injection structure 7 may be a p-type doped GaN material.
  • the GaN hole injection structure 7 itself can also act as a provider of holes.
  • the GaN hole injection structures 7 fill the corresponding hole injection grooves 6 . Filling here may mean that the proportion of the GaN hole injection structure 7 in the hole injection groove 6 exceeds a predetermined value, eg, 95%.
  • the light emitting diode epitaxial wafer may further include a p-type GaN fill-in layer 8 , and the p-type GaN fill-in layer 8 is stacked on the p-type GaN layer 5 and the plurality of GaN hole injection structures 7 .
  • the p-type GaN leveling layer 8 can cover one end of the GaN hole injection structure 7 close to the p-type layer, that is, the upper end of the GaN hole injection structure 7 shown in FIG. 1 .
  • the holes provided by the p-type GaN leveling layer 8 It is also possible to directly enter the GaN hole injection structure 7 from the end of the GaN hole injection structure 7 close to the p-type layer, and the holes provided by the p-type GaN filling layer 8 can also enter the GaN hole from the peripheral wall of the GaN hole injection structure 7.
  • the hole injection structure 7 enables more holes to enter the multiple quantum well layer 3 through the GaN hole injection structure 7, which can further improve the luminous efficiency of the finally obtained light-emitting diode.
  • the thickness of the p-type GaN levelling layer 8 may range from 20 nm to 50 nm.
  • the thickness of the p-type GaN leveling layer 8 is within the above range, holes can be provided stably without excessively increasing the fabrication cost of the light-emitting diode epitaxial wafer.
  • the thickness of the p-type GaN may range from 70 to 100 nm.
  • each hole injection groove 6 close to the n-type GaN layer 2 that is, the lower end of the hole injection groove 6 shown in FIG. 1 , can extend to the nearest p-type in the multiple quantum well layer 3 . in the quantum well of the GaN layer 5 .
  • the hole injection groove 6 adopts this structure, and the GaN hole injection structure 7 filling the hole injection groove 6 also extends to the quantum well closest to the p-type GaN layer 5, and holes can pass through the GaN hole injection structure 7 Transmission into the quantum wells of the multiple quantum well layer 3 facilitates the direct recombination of holes with electrons.
  • the hole injection groove 6 will not cause excessive damage and influence to the multiple quantum well layer 3 itself.
  • holes can more easily enter the multi-quantum well layer 3, and a part of the multi-quantum well layer 3 that is closer to the n-type GaN layer 2 can also play a role in blocking electrons, leaving more holes for holes. injection time.
  • the hole injection groove 6 may be in the shape of a truncated cone.
  • the frustum-shaped hole injection groove 6 is easy to manufacture, and the GaN hole injection structure 7 in the hole injection groove 6 is also easy to form.
  • the hole injection groove 6 may also be cylindrical, polygonal, or trapezoidal, which is not limited in the present disclosure.
  • each hole injection groove 6 can gradually decrease from the end close to the p-type GaN layer 5 to the end close to the n-type GaN layer 2 , that is, the hole injection groove 6 can be large at the top and small at the bottom. Conical shape.
  • the cross-section of the hole injection groove 6 gradually decreases from the end close to the p-type GaN layer 5 to the end close to the n-type GaN layer 2
  • the cross-section of the GaN hole injection structure 7 also decreases from the end close to the p-type GaN layer 5 to the end close to the n-type GaN layer 2 .
  • the end close to the n-type GaN layer 2 is gradually reduced.
  • the GaN hole injection structure 7 of this shape can facilitate the entry of holes into the multi-quantum well layer 3, ensure the stable injection of holes into the multi-quantum well layer 3, and reduce the possibility of There is a possibility that electrons enter the GaN hole injection structure 7 from the multiple quantum well layer 3 .
  • the movement of electrons and holes requires migration time, and holes can directly enter the multi-quantum well layer 3 from the GaN hole injection structure 7, and the multi-quantum well layer 3 itself will The electrons are blocked, so that a large number of electrons will not pass through the GaN hole injection structure 7 at this time, and the GaN hole injection structure 7 is mainly used as a flow channel of holes.
  • each GaN hole injection structure 7 close to one end of the p-type GaN layer 5 may be a convex conical face.
  • the end face of the GaN hole injection structure 7 close to one end of the p-type GaN layer 5 is controlled to be a convex conical surface, and the GaN hole injection structure 7 is connected to the p-type GaN layer 5 .
  • the direct contact surface will be larger, which facilitates the entry of more holes into the GaN hole injection structure 7 .
  • FIG. 2 is a top view of a light-emitting diode epitaxial wafer provided by an embodiment of the present disclosure.
  • the top surface of the hole injection groove 6 is circular, and the diameter of the top surface of the hole injection groove 6 may range from 400 nm to 600 nm.
  • the hole diameter d of the hole injection groove 6 is within this range, the stable injection of holes can be achieved, and the structure of the multiple quantum well layer 3 is not greatly affected.
  • the bottom surface of the hole injection groove 6 may be circular, and the range of the diameter of the bottom surface of the hole injection groove 6 may be in the range of 400 nm to 600 nm.
  • a plurality of hole injection grooves 6 may be uniformly distributed on the light emitting diode epitaxial wafer, and the minimum distance L between two adjacent hole injection grooves 6 ranges from 1000 nm to 2000 nm.
  • the minimum distance L between two adjacent hole injection grooves 6 is 1000 nm to 2000 nm, which can maximize the number of holes entering the multi-quantum well layer 3 through the GaN hole injection structure 7 in the hole injection groove 6 , while not increasing the production cost too much.
  • FIG. 3 is a schematic structural diagram of another light-emitting diode epitaxial wafer provided by an embodiment of the present disclosure.
  • the light-emitting diode epitaxial wafer may include a substrate 1 and a substrate grown on the substrate. Buffer layer 9 on bottom 1, undoped GaN layer 10, n-type GaN layer 2, multiple quantum well layer 3, p-type AlGaN layer 11, AlGaN electron blocking layer 4, p-type GaN layer 5, p-type GaN filling layer 8 and p-type contact layer 12 .
  • the structure of the GaN hole injection structure 7 shown in FIG. 3 is the same as that of the GaN hole injection structure 7 shown in FIG. 1 , and details are not repeated here.
  • the substrate 1 may be a sapphire substrate 1 . Easy to make and obtain.
  • the buffer layer 9 may be an AlN buffer layer 9 , which can ensure the crystal quality of the epitaxial thin film grown on the low-temperature buffer layer 9 .
  • the thickness of the buffer layer 9 may range from 10 nm to 30 nm, which can reduce the lattice mismatch between the n-type GaN layer 2 and the substrate 1 and ensure the growth quality of the epitaxial layer.
  • the thickness of the undoped GaN layer 10 may be 1 ⁇ m ⁇ 3.5 ⁇ m.
  • the quality of the light-emitting diode epitaxial wafer obtained at this time is good.
  • the thickness of the undoped GaN layer 10 is 1 ⁇ m.
  • the doping element of the n-type GaN layer 2 may be Si, and the doping concentration range of the Si element may be 1 ⁇ 10 18 cm ⁇ 3 to 1 ⁇ 10 19 cm ⁇ 3 , so that the n-type GaN layer 2 The overall quality is good.
  • the thickness of the n-type GaN layer 2 may range from 2 to 3 ⁇ m, and the overall quality of the obtained n-type GaN layer 2 is good.
  • the thickness of the n-type GaN layer 2 is 2 ⁇ m.
  • the multiple quantum well layer 3 includes a plurality of alternately stacked InGaN well layers 31 and GaN barrier layers 32 , the thickness of the InGaN well layers 31 may range from 2 nm to 3 nm, and the thickness of the GaN barrier layers 32 may range from 9 nm to 20 nm. .
  • the number of InGaN well layers and the number of GaN barrier layers can both be 5 to 11, and the obtained multiple quantum well layer 3 has a good structure.
  • the light-emitting diode epitaxial wafer may further include a p-type AlGaN layer 11 disposed between the multiple quantum well layer 3 and the AlGaN electron blocking layer 4, and both the hole injection groove 6 and the GaN hole injection structure 7 pass through the p-type AlGaN layer 11 .
  • the p-type AlGaN layer 11 can also serve as a carrier for providing holes, further ensuring the number of holes entering the multiple quantum well layer 3, and at the same time, it can also play a certain role in blocking electrons.
  • the thickness of the p-type AlGaN layer 11 may range from 20 nm to 100 nm, and the concentration range of the doped Mg element may range from 5 ⁇ 10 19 cm ⁇ 3 to 1 ⁇ 10 21 cm ⁇ 3 .
  • the p-type AlGaN layer 11 designed according to the above can provide sufficient holes and ensure that the overall cost of the light-emitting diode epitaxial wafer is not too high.
  • the Al composition in the AlGaN electron blocking layer 4 may be 0.15-0.25, so that the layer has a better effect of blocking electrons.
  • the p-type GaN layer 5 may be doped with Mg, and the thickness of the p-type GaN layer 5 may be the same as that of the structure shown in FIG. 1 , which will not be repeated here.
  • the thickness of the p-type contact layer may be 15 nm.
  • the epitaxial wafer structure shown in FIG. 3 is added between the buffer layer 9 and the n-type GaN layer 2 .
  • the GaN layer 10 is doped and a p-type contact layer is grown on the p-type GaN layer 5, the quality and luminous efficiency of the obtained epitaxial wafer will be better.
  • FIG. 4 is a flowchart of a method for preparing a light-emitting diode epitaxial wafer provided by an embodiment of the present disclosure. As shown in FIG. 4 , the preparation method for a light-emitting diode epitaxial wafer includes:
  • S102 sequentially growing an n-type GaN layer, a multiple quantum well layer, and a p-type GaN layer on the substrate.
  • growing the multiple quantum well layer includes: alternately growing a plurality of InGaN well layers and GaN barrier layers on the n-type GaN layer to form the multiple quantum well layer.
  • the light-emitting diode epitaxial wafer includes a substrate and an n-type GaN layer, a multiple quantum well layer, an AlGaN electron blocking layer and a p-type GaN layer stacked on the substrate in sequence, and can realize the normal light-emitting function of the light-emitting diode.
  • the p-type GaN layer has a plurality of hole injection grooves distributed at intervals, and each hole injection groove and the GaN hole injection structure filling the hole injection groove extend from the p-type GaN layer to the multiple quantum well layer.
  • the GaN hole injection structure can act as a channel.
  • the GaN hole injection structure crosses the AlGaN electron blocking layer and guides the holes in the p-type GaN layer directly into the multiple quantum well layer.
  • the resistance of holes entering the multiple quantum well layer through the GaN hole injection structure is relatively small compared with that of passing through the AlGaN electron blocking layer into the multiple quantum well layer. Therefore, more holes can enter the multiple quantum well layer through the GaN hole injection structure to combine with electrons to emit light. As the number of holes entering the multiple quantum well layer increases, the luminous efficiency of the resulting light-emitting diode will also increase.
  • step S103 includes:
  • a SiO2 layer is spin-coated on the surface of the p-type GaN layer; a plurality of spaced hole injection grooves are formed on the p-type GaN layer using a photolithography process, and each hole injection groove extends to the multiple quantum well layer.
  • the SiO 2 layer can form protection for the p-type GaN layer where etching is not required, ensuring the stable formation of multiple hole injection grooves.
  • the thickness of the SiO 2 layer spin-coated on the surface of the p-type GaN layer may range from 200 nm to 500 nm.
  • the p-type GaN layer can be reasonably protected without causing excessive material waste.
  • forming a plurality of spaced-apart hole injection grooves on the p-type GaN layer using a photolithography process may include:
  • the thickness of the photoresist may range from 1000 nm to 3000 nm.
  • Step S103 may include: growing a GaN hole injection structure in each hole injection groove under the premise that the temperature is 850-1000° C. and the pressure is 100-300 torr. The quality of the obtained GaN hole injection structure is good.
  • Step S103 may further include: after obtaining the hole injection groove, using a cleaning solution to remove the SiO 2 layer. The preparation of the light-emitting diode epitaxial wafer is completed.
  • the epitaxial wafer structure of the light emitting diode after step S103 is performed may refer to FIG. 1 .
  • FIG. 5 is a flowchart of another method for preparing a light-emitting diode epitaxial wafer provided by an embodiment of the present disclosure. As shown in FIG. 5 , the preparation method for a light-emitting diode epitaxial wafer includes:
  • the substrate can be a sapphire substrate. Easy to implement and make.
  • step S201 may further include: under a hydrogen atmosphere, treating the surface of the substrate for growing the epitaxial layer for 5-6 minutes.
  • the temperature of the reaction chamber may be 1000 ⁇ 1100° C.
  • the pressure of the reaction chamber may be 200 ⁇ 500 torr.
  • the buffer layer may be an AlN buffer layer.
  • the AlN layer can be obtained by magnetron sputtering.
  • the deposition temperature of the AlN layer may be 400 ⁇ 800° C.
  • the sputtering power may be 3000 ⁇ 5000 W
  • the pressure may be 2 ⁇ 20 mtorr.
  • the quality of the obtained AlN layer is good.
  • the thickness of the undoped GaN layer may be 0.5-3um.
  • the growth temperature of the undoped GaN layer may be 1000 ⁇ 1100° C., and the growth pressure is controlled at 100 ⁇ 300 torr.
  • the quality of the obtained undoped GaN layer is good.
  • the n-type GaN layer may be an n-type GaN layer
  • the growth temperature of the n-type GaN layer may be 1000 ⁇ 1100° C.
  • the growth pressure of the n-type GaN layer may be 100 ⁇ 300 Torr.
  • the thickness of the n-type GaN layer may be 0.5 ⁇ 3 ⁇ m.
  • the multiple quantum well layer includes alternately stacked InGaN well layers and GaN barrier layers, the thickness of the InGaN well layer may be 2-3 nm, and the thickness of the GaN barrier layer may be 9-20 nm.
  • the growth temperature of the InGaN well layer and the growth temperature of the InGaN well layer can both be 700 to 830° C., the growth temperature of the GaN barrier layer, the growth temperature of the GaN barrier layer, and the growth temperature of the third GaN barrier layer.
  • the growth temperature can be 800 ⁇ 960 °C.
  • the quality of the multiple quantum well layer grown under this condition is good, and the luminous efficiency of the light emitting diode can be guaranteed.
  • step S205 the growth conditions, growth method and structure of the multiple quantum well layer in step S205 are the same as the growth conditions, growth method and structure of the multiple quantum well layer in step S103 in FIG. 4 . It will not be repeated here.
  • the growth temperature of the p-type AlGaN layer may be 600 ⁇ 800° C., and the growth pressure may be 200 ⁇ 500 Torr.
  • S207 growing an AlGaN electron blocking layer on the p-type AlGaN layer.
  • the growth temperature of the AlGaN electron blocking layer may be 800 ⁇ 1000° C., and the growth pressure of the AlGaN electron blocking layer may be 100 ⁇ 300 Torr.
  • the quality of the AlGaN electron blocking layer grown under this condition is good, which is beneficial to improve the luminous efficiency of the light emitting diode.
  • S208 growing a p-type GaN layer on the electron blocking layer.
  • the growth pressure of the p-type GaN layer may be 200-600 Torr, and the growth temperature of the p-type GaN layer may be 800-1000°C.
  • step S208 For the implementation of step S208, reference may be made to the implementation of step S103 in FIG. 4 , which will not be repeated here.
  • S210 growing a p-type GaN filling layer covering the p-type GaN layer and the GaN hole injection structure on the p-type GaN layer.
  • the growth pressure of the p-type GaN leveling layer may be 200-600 Torr, and the growth temperature of the p-type GaN leveling layer may be 800-1000°C.
  • the quality of the obtained p-type GaN levelling layer is good.
  • the growth pressure of the p-type contact layer may be 100-300 Torr, and the growth temperature of the p-type contact layer may be 800-1000°C.
  • the preparation method of the light emitting diode epitaxial wafer shown in FIG. 5 provides a more detailed growth method of the light emitting diode epitaxial wafer compared with the preparation method of the light emitting diode shown in FIG. 4 .
  • step S211 The structure of the light emitting diode epitaxial wafer after step S211 is performed can be seen in FIG. 3 .
  • Veeco K465i or C4 or RB MOCVD Metal Organic Chemical Vapor Deposition, metal organic compound chemical vapor deposition
  • high-purity H2 hydrogen or high-purity N2 (nitrogen) or a mixture of high-purity H2 and high-purity N2 as carrier gas
  • high-purity NH3 as N source
  • trimethylindium (TMIn) as the indium source
  • silane (SiH4) as the N-type dopant
  • trimethylaluminum (TMAl) as the aluminum source
  • dicocene (CP 2 Mg) dicocene

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Abstract

本公开公开了发光二极管外延片及其制备方法，属于发光二极管制作领域。所述发光二极管外延片包括衬底及依次层叠在所述衬底上的n型GaN层、多量子阱层、AlGaN电子阻挡层与p型GaN层，所述p型GaN层上具有多个间隔分布的空穴注入槽，每个所述空穴注入槽均由所述p型GaN层延伸至所述多量子阱层，所述发光二极管外延片还包括多个GaN空穴注入结构，多个所述GaN空穴注入结构一一对应分布在多个所述空穴注入槽内。

Description

发光二极管外延片及其制备方法
本公开要求于2020年9月10日提交的申请号为202010946042.X、发明名称为“发光二极管外延片及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及发光二极管制作领域，特别涉及发光二极管外延片及其制备方法。
背景技术
发光二极管是一种能发光的半导体电子元件。作为一种高效、环保、绿色新型固态照明光源，正在被迅速广泛地应用在各个领域，如交通信号灯、汽车内外灯、城市景观照明、手机背光源等，提高发光二极管芯片的发光效率是发光二极管行业内不断追求的目标。
发明内容
本公开实施例提供了发光二极管外延片及其制备方法，能够提高进入多量子阱层中的空穴的数量以最终提高发光二极管的发光效率。所述技术方案如下：
本公开实施例提供了一种发光二极管外延片，所述发光二极管外延片包括衬底及依次层叠在所述衬底上的n型GaN层、多量子阱层、AlGaN电子阻挡层与p型GaN层，
所述p型GaN层上具有多个间隔分布的空穴注入槽，每个所述空穴注入槽均由所述p型GaN层延伸至所述多量子阱层，所述发光二极管外延片还包括多个GaN空穴注入结构，多个所述GaN空穴注入结构一一对应分布在多个所述空穴注入槽内。
可选地，所述GaN空穴注入结构的材料为未掺杂的GaN材料。
可选地，所述GaN空穴注入结构充满对应的所述空穴注入槽。
可选地，每个所述空穴注入槽的横截面由靠近所述p型GaN层的一端至靠近所述n型GaN层的一端逐渐减小。
可选地，每个所述空穴注入槽靠近所述n型GaN层的一端，均延伸至所述多量子阱层中最靠近所述p型GaN层的量子阱中。
可选地，所述空穴注入槽的顶面为圆形，所述空穴注入槽的顶面直径的范围为400nm～600nm。
可选地，多个所述空穴注入槽均匀分布在所述发光二极管外延片上，且相邻的两个所述空穴注入槽之间的最小距离的范围为1000nm～2000nm。
可选地，所述发光二极管外延片还包括p型GaN填平层，所述p型GaN填平层层叠在所述p型GaN层与多个所述GaN空穴注入结构上。
可选地，所述p型GaN填平层的厚度的范围为20nm～50nm。
可选地，每个所述GaN空穴注入结构靠近所述p型GaN层的一端的端面为凸起的圆锥面。
可选地，所述p型GaN的厚度的范围为70nm～100nm。
本公开实施例提供了一种发光二极管外延片的制备方法，所述制备方法包括：
提供一衬底；
在所述衬底上依次生长n型GaN层、多量子阱层、p型GaN层；
在所述p型GaN层形成多个空穴注入槽，每个所述空穴注入槽均由所述p型GaN层延伸至所述多量子阱层，在每个所述空穴注入槽内生长一个GaN空穴注入结构。
可选地，在所述p型GaN层形成多个空穴注入槽，每个所述空穴注入槽均由所述p型GaN层延伸至所述多量子阱层，在每个所述空穴注入槽内生长一个GaN空穴注入结构，包括：
在所述p型GaN层的表面上旋涂SiO 2层；
使用光刻工艺在所述p型GaN层上形成多个间隔分布的空穴注入槽，且每个所述空穴注入槽均延伸至所述多量子阱层；
在每个所述空穴注入槽内生长所述GaN空穴注入结构；
去除所述SiO 2层。
可选地，所述GaN空穴注入结构的材料为未掺杂的GaN材料。
可选地，所述GaN空穴注入结构充满对应的所述空穴注入槽。
附图说明
图1是本公开实施例提供的一种发光二极管外延片的结构示意图；
图2是本公开实施例提供的发光二极管外延片的俯视图；
图3是本公开实施例提供的另一种发光二极管外延片的结构示意图；
图4是本公开实施例提供的一种发光二极管外延片的制备方法流程图；
图5是本公开实施例提供的另一种发光二极管外延片的制备方法流程图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
相关技术中，发光二极管的外延片通常包括衬底及在衬底上依次生长的n型GaN层、多量子阱层、AlGaN电子阻挡层及p型GaN层。多量子阱层与p型GaN层之间的AlGaN电子阻挡层可以起到阻挡多量子阱层中的电子溢流的作用，但同时AlGaN电子阻挡层也会阻挡从p型GaN层进入多量子阱层的空穴，使得原本迁移能力就低于电子的空穴更难以进入量子阱层中。进入多量子阱层中空穴的数量相对电子少很多，可以在多量子阱层中与电子复合的空穴较少，最终得到的发光二极管的发光效率不高。
图1是本公开实施例提供的一种发光二极管外延片的结构示意图，参考图1可知，本公开实施例提供了一种发光二极管外延片，发光二极管外延片包括衬底1及依次层叠在衬底1上的n型GaN层2、多量子阱层3、AlGaN电子阻挡层4与p型GaN层5。
p型GaN层5上具有多个间隔分布的空穴注入槽6，每个空穴注入槽6均由p型GaN层5延伸至多量子阱层3，发光二极管外延片还包括多个GaN空穴注入结构7，多个GaN空穴注入结构7一一对应分布在多个空穴注入槽6内。
发光二极管外延片包括衬底1及依次层叠在衬底1上的n型GaN层2、多量子阱层3、AlGaN电子阻挡层4与p型GaN层5，能够实现发光二极管的正常发光功能。p型GaN层5上具有多个间隔分布的空穴注入槽6，且每个空穴注入槽6与填满空穴注入槽6的GaN空穴注入结构7均由p型GaN层5延伸至多量子阱层3。GaN空穴注入结构7可到通道的作用，GaN空穴注入结构7越过AlGaN电子阻挡层4，将p型GaN层5中的空穴直接引导至多量子阱层3中。空穴通过GaN空穴注入结构7进入多量子阱层3时受到阻力，相对穿过AlGaN 电子阻挡层4进入多量子阱层3中的阻力较小。因此更多的空穴可以通过GaN空穴注入结构7进入多量子阱层3中与电子复合发光。进入多量子阱层3中的空穴数量增多，最终得到的发光二极管的发光效率也会提高。
在本公开一种实现方式中，GaN空穴注入结构7可为未掺杂的GaN材料。
在本公开另一种实现方式中，GaN空穴注入结构7可为p型掺杂的GaN材料。GaN空穴注入结构7本身也可作为空穴的提供体。
在本公开实施例中，GaN空穴注入结构7充满对应的空穴注入槽6。这里的充满可以是指GaN空穴注入结构7在空穴注入槽6中的比例超过预定值，例如95％。
参考图1可知，发光二极管外延片还可包括p型GaN填平层8，p型GaN填平层8层叠在p型GaN层5与多个GaN空穴注入结构7上。
p型GaN填平层8可以覆盖GaN空穴注入结构7靠近p型层的一端，也即图1中示出的GaN空穴注入结构7的上端，p型GaN填平层8提供的空穴还可以从GaN空穴注入结构7靠近p型层的一端直接进入GaN空穴注入结构7内，p型GaN填平层8提供的空穴还可以从GaN空穴注入结构7的周壁进入GaN空穴注入结构7，使得通过GaN空穴注入结构7进入多量子阱层3的空穴数量更多，可以进一步提高最终得到的发光二极管的发光效率。
可选地，p型GaN填平层8的厚度的范围可为20nm～50nm。
p型GaN填平层8的厚度在以上范围内时，可以稳定提供空穴，并不会过多地增加发光二极管外延片的制备成本。
示例性地，在存在p型GaN填平层8的前提下，p型GaN的厚度的范围可为70～100nm。
参考图1可知，每个空穴注入槽6靠近n型GaN层2的一端，也即图1中示出的空穴注入槽6的下端，均可延伸至多量子阱层3中最靠近p型GaN层5的量子阱中。
空穴注入槽6采用这种结构，填满空穴注入槽6的GaN空穴注入结构7也会延伸至最靠近p型GaN层5的量子阱中，空穴可以通过GaN空穴注入结构7传输进入多量子阱层3的量子阱中，便于空穴直接与电子复合。空穴注入槽6不会对多量子阱层3本身造成过多的破坏与影响。并且采用以上结构，空穴可以更容易进入多量子阱层3中，而多量子阱层3较为靠近n型GaN层2的一部分结构还可起到阻挡电子的作用，为空穴留出更多的注入时间。
示例性地，空穴注入槽6可呈圆台形。
圆台形的空穴注入槽6便于制备，空穴注入槽6内的GaN空穴注入结构7也容易制备形成。
在本公开所提供的其他实现方式中，空穴注入槽6也可为圆柱状、多棱柱状或梯形状，本公开对此不做限制。
可选地，每个空穴注入槽6的横截面可由靠近p型GaN层5的一端至靠近n型GaN层2的一端逐渐减小，也即空穴注入槽6可以呈上大下小的圆台形。
空穴注入槽6的横截面由靠近p型GaN层5的一端至靠近n型GaN层2的一端逐渐减小，GaN空穴注入结构7的横截面也由靠近p型GaN层5的一端至靠近n型GaN层2的一端逐渐减小，这种形状的GaN空穴注入结构7能够便于空穴进入多量子阱层3中，保证空穴稳定注入多量子阱层3中，同时减小可能有电子从多量子阱层3内进入GaN空穴注入结构7的可能。
需要说明的是，发光二极管通电时，电子与空穴的移动均需要迁移时间，空穴可以从GaN空穴注入结构7直接进入多量子阱层3中，而此时多量子阱层3本身会对电子进行阻挡，因此此时不会有大量电子通过GaN空穴注入结构7，GaN空穴注入结构7主要是作为空穴的流动通道。
可选地，每个GaN空穴注入结构7靠近p型GaN层5的一端的端面可为凸起的圆锥面。
在具有p型GaN填平层8的前提下，将GaN空穴注入结构7靠近p型GaN层5的一端的端面控制为凸起的圆锥面，GaN空穴注入结构7与p型GaN层5直接的接触面会更大，便于更多的空穴进入GaN空穴注入结构7内。
图2是本公开实施例提供的发光二极管外延片的俯视图，参考图2可知，空穴注入槽6的顶面为圆形，空穴注入槽6的顶面直径的范围可以为400nm～600nm。
空穴注入槽6的孔径d在此范围内时，可以实现空穴的稳定注入，而对多量子阱层3的结构不产生过大影响。
需要说明的是，空穴注入槽6的底面也可以为圆形，空穴注入槽6的底面直径的范围也可位于400nm～600nm的范围内。
可选地，多个空穴注入槽6可均匀分布在发光二极管外延片上，且相邻的两个空穴注入槽6之间的最小距离L的范围为1000nm～2000nm。
相邻的两个空穴注入槽6之间的最小距离L为1000nm～2000nm，可以使得 通过空穴注入槽6内的GaN空穴注入结构7进入多量子阱层3中的空穴数量最大化，同时又不会过多地提升制作成本。
需要说明的是，图2中为便于观察GaN空穴注入结构7，省略了p型GaN填平层8的结构。
图3是本公开实施例提供的另一种发光二极管外延片的结构示意图，参考图3可知，在本公开提供的另一种实现方式中，发光二极管外延片可包括衬底1及生长在衬底1上的缓冲层9、非掺杂GaN层10、n型GaN层2、多量子阱层3、p型AlGaN层11、AlGaN电子阻挡层4、p型GaN层5、p型GaN填平层8及p型接触层12。
需要说明的是，图3中所示的GaN空穴注入结构7与图1中所示的GaN空穴注入结构7的结构相同，此处不再赘述。
可选地，衬底1可为蓝宝石衬底1。易于制作与获取。
示例性地，缓冲层9可为AlN缓冲层9，能够保证在低温缓冲层9上生长的外延薄膜的晶体质量。
可选地，缓冲层9的厚度范围可为10nm～30nm，能够减小n型GaN层2与衬底1之间的晶格失配，保证外延层的生长质量。
示例性地，非掺杂GaN层10的厚度可为1μm～3.5μm。此时得到的发光二极管外延片的质量较好。
例如，非掺杂GaN层10的厚度为1μm。
可选地，n型GaN层2的掺杂元素可为Si，且Si元素的掺杂浓度范围可为1×10 18cm -3～1×10 19cm -3，从而使得n型GaN层2整体的质量较好。
示例性地，n型GaN层2的厚度范围可为2～3μm，得到的n型GaN层2整体的质量较好。
例如，n型GaN层2的厚度为2μm。
示例性地，多量子阱层3包括多个交替层叠的InGaN阱层31及GaN垒层32，InGaN阱层31的厚度范围可为2nm～3nm，GaN垒层32的厚度范围可为9nm～20nm。
InGaN阱层的层数与GaN垒层的层数均可为5～11，得到的多量子阱层3的结构较好。
示例性地，发光二极管外延片还可包括设置在多量子阱层3与AlGaN电子阻挡层4之间的p型AlGaN层11，空穴注入槽6与GaN空穴注入结构7均穿 过p型AlGaN层11。
p型AlGaN层11也可以作为空穴的提供载体，进一步保证进入多量子阱层3的空穴数量，同时还可以起到一定的阻挡电子的作用。
可选地，p型AlGaN层11的厚度范围可为20nm～100nm，掺杂的Mg元素的浓度范围可为5×10 19cm -3～1×10 21cm -3。
按照上述设计的p型AlGaN层11能够提供足够的空穴，并保证发光二极管外延片整体的成本不会过高。
可选地，AlGaN电子阻挡层4中Al组分可为0.15～0.25，使得该层阻挡电子的效果较好。
可选地，p型GaN层5可掺Mg，p型GaN层5的厚度可与图1中所示结构相同，此处不再赘述。
示例性地，p型接触层的厚度可为15nm。
需要说明的是，图3中所示的外延片结构相对图1中所示的外延片结构，在缓冲层9与n型GaN层2之间增加了缓解晶格失配的缓冲层9与非掺杂GaN层10，并在p型GaN层5上还生长有p型接触层，得到的外延片的质量及发光效率会更好。
图4是本公开实施例提供的一种发光二极管外延片的制备方法流程图，如图4所示，该发光二极管外延片制备方法包括：
S101：提供一衬底。
S102：在衬底上依次生长n型GaN层、多量子阱层、p型GaN层。
其中，生长多量子阱层包括：在n型GaN层上交替生长多个InGaN阱层与GaN垒层以形成多量子阱层。
S103：在p型GaN层形成多个空穴注入槽，每个空穴注入槽均由p型GaN层延伸至多量子阱层，在每个空穴注入槽内生长一个GaN空穴注入结构。
发光二极管外延片包括衬底及依次层叠在衬底上的n型GaN层、多量子阱层、AlGaN电子阻挡层与p型GaN层，能够实现发光二极管的正常发光功能。p型GaN层上具有多个间隔分布的空穴注入槽，且每个空穴注入槽与填满空穴注入槽的GaN空穴注入结构均由p型GaN层延伸至多量子阱层。GaN空穴注入结构可到通道的作用，GaN空穴注入结构越过AlGaN电子阻挡层，将p型GaN层中的空穴直接引导至多量子阱层中。空穴通过GaN空穴注入结构进入多量子 阱层时受到阻力，相对穿过AlGaN电子阻挡层进入多量子阱层中的阻力较小。因此更多的空穴可以通过GaN空穴注入结构进入多量子阱层中与电子复合发光。进入多量子阱层中的空穴数量增多，最终得到的发光二极管的发光效率也会提高。
可选地，步骤S103，包括：
在p型GaN层的表面上旋涂SiO 2层；使用光刻工艺在p型GaN层上形成多个间隔分布的空穴注入槽，且每个空穴注入槽均延伸至多量子阱层。
SiO 2层可以对p型GaN层不需要刻蚀的地方形成保护，保证多个空穴注入槽的稳定形成。
可选地，在p型GaN层的表面上旋涂的SiO 2层的厚度范围可为200nm～500nm。可以合理保护p型GaN层的同时，不造成过多材料浪费。
示例性地，使用光刻工艺在p型GaN层上形成多个间隔分布的空穴注入槽，可包括：
在SiO 2层的表面旋涂光刻胶；对光刻胶进行曝光处理；去除曝光软化的光刻胶；在没有光刻胶覆盖的SiO 2层与p型GaN层的位置刻蚀出空穴注入槽。
可选地，光刻胶厚度范围可为1000nm～3000nm。
步骤S103可包括：在温度为850～1000℃且压力为100～300torr的前提下，在每个空穴注入槽内生长GaN空穴注入结构。得到的GaN空穴注入结构的质量较好。
步骤S103还可包括：得到空穴注入槽之后，使用清洗液去除SiO 2层。完成发光二极管外延片的制备。
执行完步骤S103之后的发光二极管的外延片结构可参考图1。
图5是本公开实施例提供的另一种发光二极管外延片的制备方法流程图，如图5所示，该发光二极管外延片制备方法包括：
S201：提供一衬底。
其中，衬底可为蓝宝石衬底。易于实现与制作。
可选地，步骤S201还可包括：在氢气气氛下，处理衬底用于生长外延层的表面5～6min。
示例性地，处理衬底用于生长外延层的表面时，反应腔的温度可为1000～1100℃，反应腔的压力可为200～500torr。
S202：在衬底上生长缓冲层。
缓冲层可为AlN缓冲层。AlN层可通过磁控溅射得到。
示例性地，AlN层的沉积温度可为400～800℃，溅射功率可为3000～5000W，压力可为2～20mtorr。得到的AlN层的质量较好。
S203：在缓冲层上生长非掺杂GaN层。
非掺杂GaN层的厚度可为0.5～3um。
示例性地，非掺杂GaN层的生长温度可为1000～1100℃，生长压力控制在100～300torr。得到的非掺杂GaN层的质量较好。
S204：在非掺杂GaN层上生长n型GaN层。
可选地，n型GaN层可为n型GaN层，n型GaN层的生长温度可为1000～1100℃，n型GaN层的生长压力可为100～300Torr。
可选地，n型GaN层的厚度可为0.5～3um。
S205：在n型GaN层上生长多量子阱层。
多量子阱层包括交替层叠的InGaN阱层与GaN垒层，InGaN阱层的厚度可为2～3nm，GaN垒层的厚度可为9～20nm。
可选地，多量子阱层中，InGaN阱层的生长温度与InGaN阱层的生长温度均可为700～830℃，GaN垒层的生长温度、GaN垒层的生长温度及第三GaN垒层的生长温度均可为800～960℃。在此条件下生长得到的多量子阱层的质量较好，能够保证发光二极管的发光效率。
需要说明的是，步骤S205中多量子阱层的生长条件、生长方式及结构，与图4的步骤S103中多量子阱层的生长条件、生长方式及结构相同。此处不再赘述。
S206：在多量子阱层上生长p型AlGaN层。
p型AlGaN层的生长温度可为600～800℃，生长压力可为200～500Torr。
S207：在p型AlGaN层上生长AlGaN电子阻挡层。
AlGaN电子阻挡层的生长温度可为800～1000℃，AlGaN电子阻挡层的生长压力可为100～300Torr。在此条件下生长得到的AlGaN电子阻挡层的质量较好，有利于提高发光二极管的发光效率。
S208：在电子阻挡层上生长p型GaN层。
可选地，p型GaN层的生长压力可为200～600Torr，p型GaN层的生长温度可为800～1000℃。
S209：在p型GaN层形成多个空穴注入槽，每个空穴注入槽均由p型GaN 层延伸至多量子阱层，在每个空穴注入槽内生长一个GaN空穴注入结构。
步骤S208的实现方式可参考图4中步骤S103的实现方式，此处不再赘述。
S210：在p型GaN层上生长覆盖p型GaN层与GaN空穴注入结构的p型GaN填平层。
可选地，p型GaN填平层的生长压力可为200～600Torr，p型GaN填平层的生长温度可为800～1000℃。得到的p型GaN填平层的质量较好。
S211：在p型GaN填平层上生长p型接触层。
可选地，p型接触层的生长压力可为100～300Torr，p型接触层的生长温度可为800～1000℃。
需要说明的是，图5中所示的发光二极管外延片的制备方法，相对图4中所示的发光二极管的制备方法，提供了一种更为详细的发光二极管外延片的生长方式。
执行完步骤S211后的发光二极管外延片的结构可参见图3。
需要说明的是，在本公开实施例中，采用Veeco K465i or C4 or RB MOCVD(Metal Organic Chemical Vapor Deposition，金属有机化合物化学气相沉淀)设备实现发光二极管的生长方法。采用高纯H 2(氢气)或高纯N 2(氮气)或高纯H 2和高纯N 2的混合气体作为载气，高纯NH 3作为N源，三甲基镓(TMGa)及三乙基镓(TEGa)作为镓源，三甲基铟(TMIn)作为铟源，硅烷(SiH4)作为N型掺杂剂，三甲基铝(TMAl)作为铝源，二茂镁(CP 2Mg)作为P型掺杂剂。
以上所述仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (15)

  1. 一种发光二极管外延片，所述发光二极管外延片包括衬底及依次层叠在所述衬底上的n型GaN层、多量子阱层、AlGaN电子阻挡层与p型GaN层，
    所述p型GaN层上具有多个间隔分布的空穴注入槽，每个所述空穴注入槽均由所述p型GaN层延伸至所述多量子阱层，所述发光二极管外延片还包括多个GaN空穴注入结构，多个所述GaN空穴注入结构一一对应分布在多个所述空穴注入槽内。
  2. 根据权利要求1所述的发光二极管外延片，其中，所述GaN空穴注入结构的材料为未掺杂的GaN材料。
  3. 根据权利要求1或2所述的发光二极管外延片，其中，所述GaN空穴注入结构充满对应的所述空穴注入槽。
  4. 根据权利要求1至3任一项所述的发光二极管外延片，其中，每个所述空穴注入槽的横截面由靠近所述p型GaN层的一端至靠近所述n型GaN层的一端逐渐减小。
  5. 根据权利要求1至4任一项所述的发光二极管外延片，其中，每个所述空穴注入槽靠近所述n型GaN层的一端，均延伸至所述多量子阱层中最靠近所述p型GaN层的量子阱中。
  6. 根据权利要求1至5任一项所述的发光二极管外延片，其中，所述空穴注入槽的顶面为圆形，所述空穴注入槽的顶面直径的范围为400nm～600nm。
  7. 根据权利要求1至6任一项所述的发光二极管外延片，其中，多个所述空穴注入槽均匀分布在所述发光二极管外延片上，且相邻的两个所述空穴注入槽之间的最小距离的范围为1000nm～2000nm。
  8. 根据权利要求1至7任一项所述的发光二极管外延片，其中，所述发光二 极管外延片还包括p型GaN填平层，所述p型GaN填平层层叠在所述p型GaN层与多个所述GaN空穴注入结构上。
  9. 根据权利要求8所述的发光二极管外延片，其中，所述p型GaN填平层的厚度的范围为20nm～50nm。
  10. 根据权利要求1至9任一项所述的发光二极管外延片，其中，每个所述GaN空穴注入结构靠近所述p型GaN层的一端的端面为凸起的圆锥面。
  11. 根据权利要求1至10任一项所述的发光二极管外延片，所述p型GaN的厚度的范围为70nm～100nm。
  12. 一种发光二极管外延片的制备方法，所述制备方法包括：
    提供一衬底；
    在所述衬底上依次生长n型GaN层、多量子阱层、p型GaN层；
    在所述p型GaN层形成多个空穴注入槽，每个所述空穴注入槽均由所述p型GaN层延伸至所述多量子阱层，在每个所述空穴注入槽内生长一个GaN空穴注入结构。
  13. 根据权利要求12所述的制备方法，其中，在所述p型GaN层形成多个空穴注入槽，每个所述空穴注入槽均由所述p型GaN层延伸至所述多量子阱层，在每个所述空穴注入槽内生长一个GaN空穴注入结构，包括：
    在所述p型GaN层的表面上旋涂SiO 2层；
    使用光刻工艺在所述p型GaN层上形成多个间隔分布的空穴注入槽，且每个所述空穴注入槽均延伸至所述多量子阱层；
    在每个所述空穴注入槽内生长所述GaN空穴注入结构；
    去除所述SiO 2层。
  14. 根据权利要求12或13所述的制备方法，其中，所述GaN空穴注入结构的材料为未掺杂的GaN材料。
  15. 根据权利要求12至14任一项所述的制备方法，其中，所述GaN空穴注入结构充满对应的所述空穴注入槽。
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