WO2022052763A1 - 光电检测电路及其驱动方法、显示装置及其制作方法 - Google Patents

光电检测电路及其驱动方法、显示装置及其制作方法 Download PDF

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Publication number
WO2022052763A1
WO2022052763A1 PCT/CN2021/113287 CN2021113287W WO2022052763A1 WO 2022052763 A1 WO2022052763 A1 WO 2022052763A1 CN 2021113287 W CN2021113287 W CN 2021113287W WO 2022052763 A1 WO2022052763 A1 WO 2022052763A1
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Prior art keywords
layer
light
substrate
electrode
line
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PCT/CN2021/113287
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English (en)
French (fr)
Inventor
张振宇
肖丽
刘冬妮
陈亮
陈昊
郑皓亮
玄明花
赵蛟
Original Assignee
京东方科技集团股份有限公司
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Priority to US17/789,661 priority Critical patent/US11721287B2/en
Publication of WO2022052763A1 publication Critical patent/WO2022052763A1/zh
Priority to US18/338,577 priority patent/US20230351968A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/13—Active-matrix OLED [AMOLED] displays comprising photosensors that control luminance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/042—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by opto-electronic means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/042—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by opto-electronic means
    • G06F3/0421—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by opto-electronic means by interrupting or reflecting a light beam, e.g. optical touch-screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/14—Detecting light within display terminals, e.g. using a single or a plurality of photosensors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/14—Detecting light within display terminals, e.g. using a single or a plurality of photosensors
    • G09G2360/145—Detecting light within display terminals, e.g. using a single or a plurality of photosensors the light originating from the display screen
    • G09G2360/147—Detecting light within display terminals, e.g. using a single or a plurality of photosensors the light originating from the display screen the originated light output being determined for each pixel
    • G09G2360/148—Detecting light within display terminals, e.g. using a single or a plurality of photosensors the light originating from the display screen the originated light output being determined for each pixel the light being detected by light detection means within each pixel
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/40—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/47—Image sensors with pixel address output; Event-driven image sensors; Selection of pixels to be read out based on image data

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a photodetection circuit and a driving method thereof, a display device and a manufacturing method thereof.
  • OLED Organic Light Emitting Diode
  • the embodiments of the present disclosure provide a photoelectric detection circuit and a driving method thereof, a display device and a manufacturing method thereof.
  • an embodiment of the present disclosure provides a photoelectric detection circuit, including: a first reset subcircuit, a second reset subcircuit, a first storage subcircuit, a data readout subcircuit, and a photosensitive device, wherein the data readout subcircuit The first end of the fetch sub-circuit, the first end of the first storage sub-circuit, the first pole of the photosensitive device, and the first end of the first reset sub-circuit are connected to the first node; the photosensitive device The second pole is connected to the common voltage line;
  • the photosensitive device is configured to generate an induced electrical signal according to the sensed optical signal
  • the data read sub-circuit is configured to transmit the voltage of the first node to the data read line in response to the control of the signal of the scan line;
  • the first reset subcircuit is configured to reset the voltage of the first node in response to the control of the signal of the reset line;
  • the first storage subcircuit is configured to store the voltage between the first node and the common voltage line;
  • the second reset subcircuit is configured to reset the voltage on the scan line in response to the control of the signal of the reset line.
  • the photodetection circuit further includes a second storage sub-circuit configured to store the voltage between the scan line and the common voltage line.
  • the first reset sub-circuit includes: a first reset transistor, a gate of the first reset transistor is connected to the reset line, and a first electrode of the first reset transistor is connected to a common voltage line, The second pole of the first reset transistor forms the first end of the first reset sub-circuit;
  • the data reading sub-circuit includes: a data reading transistor, the gate of the data reading transistor is connected to the scan line, the first electrode of the data reading transistor is connected to the data reading line, the data reading The second pole of the read transistor is formed as the first end of the data read sub-circuit.
  • the data read lines and the scan lines are located in different layers of insulating spacers, the scan lines extend in a first direction, the data read lines extend in a second direction, and the first one direction intersects the second direction,
  • the gate of the data read transistor is a part of the scan line, and the orthographic projections of the first electrode and the second electrode of the data read transistor on the first substrate are respectively located on the scan line on the first substrate. on both sides of the orthographic projection along the second direction.
  • the first pole and the second pole of the first reset transistor and the first pole and the second pole of the data readout transistor are all disposed in the same layer as the data readout line
  • a first insulating layer is provided between the layer where the first pole of the first reset transistor is located and the layer where the common voltage line is located, a first via hole is provided on the first insulating layer, and the first via hole is exposed A part of the common voltage line is output, and the first electrode of the first reset transistor is connected to the common voltage line through the first via hole.
  • the second reset sub-circuit includes: a second reset transistor, a gate of the second reset transistor is connected to the reset line, and a first pole of the second reset transistor is connected to the first
  • the first electrode of the reset transistor forms an integrated structure, and the second electrode of the second reset transistor is connected to the scan line.
  • the first insulating layer is further provided with a second via hole, the second via hole exposes a part of the scan line, and the second electrode of the second reset transistor passes through the first Two via holes are connected to the scan lines.
  • the first storage sub-circuit includes: a first capacitor, the first plate of the first capacitor and the common voltage line are formed into an integrated structure, the second plate of the first capacitor, The second electrode of the data read transistor and the second electrode of the first reset transistor form an integrated structure.
  • the photosensitive device is located on the side of the second electrode plate of the first capacitor away from the first electrode plate, and the layer where the first electrode of the photosensitive device is located is connected to the second electrode of the first capacitor.
  • a second insulating layer is arranged between the layers where the plates are located, and a third via hole is arranged on the second insulating layer, and the third via hole exposes a part of the second plate of the first capacitor, and the photosensitive
  • the first pole of the device is connected to the second pole plate of the first capacitor through the third via hole to form the first node; the second poles of the photosensitive devices of the plurality of photodetection circuits are connected to form an integral layer structure.
  • the orthographic projection of the first pole of the photosensitive device on the first substrate at least covers the orthographic projection of the first capacitor on the first substrate.
  • the second storage sub-circuit includes a second capacitor, the first plate of the second capacitor is a part of the scan line, and the second plate of the second capacitor is the first plate of the second capacitor. A portion of the first pole of a reset transistor.
  • an embodiment of the present disclosure provides a display device, including:
  • the display substrate comprising: a second substrate and a plurality of pixel structures disposed on the second substrate, the pixel structures comprising light emitting devices;
  • a photoelectric detection substrate includes: a first base and a plurality of photoelectric detection circuits arranged on the first base, the photoelectric detection circuits adopt the above-mentioned photoelectric detection circuits; wherein, the display substrate includes a relative On the display side and the non-display side, the photodetection substrate is located on the non-display side of the display substrate, and the orthographic projection of each of the photosensitive devices on the second substrate is located on the yth pixel structure on the second substrate. In the orthographic projection range on the two substrates, to receive the light of the y light-emitting devices, 1 ⁇ y ⁇ 100, and y is an integer.
  • the material of the second substrate is glass or polyimide.
  • the extension direction of the common voltage line and the extension direction of the reset line are the same as the extension direction of the scan line, and both the common voltage line and the reset line are the same as the scan line same layer settings,
  • the scan line is located between the common electrode line and the reset line.
  • the pixel structure further includes a pixel driving circuit
  • the pixel driving circuit includes: a driving transistor, a data writing transistor and a third capacitor
  • the gate of the data writing transistor is connected to the gate line
  • the first pole of the data writing transistor is connected to the data line
  • the second pole of the data writing transistor is connected to the gate of the driving transistor
  • the driving transistor The first pole of the third capacitor is connected to the first power line
  • the second pole of the driving transistor is connected to the first electrode of the light-emitting device
  • the two ends of the third capacitor are respectively connected to the gate and the first pole of the driving transistor.
  • the first plate of the third capacitor is at least a part of the gate of the driving transistor, and the second plate of the third capacitor is located away from the first plate of the third electrode one side of the second substrate.
  • the active layer, the first electrode and the second electrode of the driving transistor are arranged in the same layer, and a first gate insulating layer is arranged between the layer where the gate electrode of the driving transistor is located and the layer where the active layer is located , a second gate insulating layer is arranged between the layer where the gate of the driving transistor is located and the layer where the second plate of the third capacitor is located, and the first power line is located at the second plate of the third capacitor
  • the layer where the layer is located is away from the side of the second substrate, and an interlayer dielectric layer is provided between the layer where the first power line is located and the layer where the second plate of the third capacitor is located,
  • the first power line is connected to the second electrode plate of the third capacitor through a fourth via hole, and is connected to the first electrode of the driving transistor through a fifth via hole, wherein the fourth via hole passes through the interlayer dielectric layer, and exposes a part of the second plate of the third capacitor; the fifth via hole simultaneously penetrates the interlayer dielectric layer, the second gate insulating layer and the first a gate insulating layer, and a part of the first electrode of the driving transistor is exposed.
  • the second electrode and the active layer of the data writing transistor are both disposed in the same layer as the active layer of the driving transistor
  • the pixel structure further includes a bridge piece, the bridge piece and the first power line are arranged in the same layer, one end of the bridge piece is connected to the gate of the driving transistor through a sixth via hole, and the bridge piece is The other end is connected to the second pole of the data writing transistor through the seventh via hole,
  • the sixth via hole penetrates both the interlayer dielectric layer and the second gate insulating layer, and exposes a part of the gate of the driving transistor; the seventh via hole simultaneously penetrates the interlayer a dielectric layer, the second gate insulating layer and the first gate insulating layer, exposing a part of the second electrode of the data writing transistor.
  • the data line is located on a side of the layer where the first power line is located away from the second substrate, and passivation is provided between the layer where the data line is located and the layer where the first power line is located layer, the first electrode of the light-emitting device is located on the side of the layer where the data line is located away from the second substrate, and a planarization is provided between the layer where the first electrode of the light-emitting device is located and the layer where the data line is located Floor;
  • the pixel structure also includes:
  • the first adapter is arranged on the same layer as the bridge, the first adapter is connected to the second pole of the driving transistor through an eighth via hole, and the eighth via hole also penetrates between the layers a dielectric layer, the second gate insulating layer and the first gate insulating layer, exposing a part of the second electrode of the driving transistor;
  • a second adapter the second adapter is disposed on the same layer as the data line, and the second adapter is connected to the first adapter through a ninth via on the passivation layer , the first electrode of the light emitting device is connected to the second adapter through a tenth via hole penetrating the planarization layer.
  • the orthographic projection of the first electrode of the light emitting device on the second substrate overlaps the orthographic projection of the data line on the second substrate.
  • a plurality of the pixel structures are arranged in multiple rows and columns, and two adjacent pixel driving circuits in the same column are respectively connected to two adjacent data lines;
  • the pixel driving circuits in the same row are connected to the same first power line.
  • the virtual structure obtained by moving the pixel driving circuit in the i-th row and the j-th column along the column direction is mirror-symmetrical with the pixel driving circuit in the i+1-th row and the j+2-th column, wherein 1 ⁇ i ⁇ m-1, 1 ⁇ j ⁇ n-2, m is the total number of rows of the pixel driving circuit, and n is the total number of columns of the pixel driving circuit.
  • the light-emitting device further includes a light-emitting layer, the light-emitting layer is located on a side of the first electrode of the light-emitting device away from the second substrate, and the pixel structure further includes a light-emitting layer that is located between the light-emitting layer and the second substrate.
  • the light-passing portion between the second substrates is used for light-passing, so that a part of the light emitted by the light-emitting layer is directed to the second substrate.
  • the light-passing portion includes a first light-passing hole, and the first light-passing hole passes through the pixel driving circuit; or,
  • the light passing portion includes a light passing slit in the pixel driving circuit.
  • the first electrode is a reflective electrode
  • the light passing portion further includes a second light passing hole passing through the first electrode
  • the display device further includes:
  • a lens layer is provided between the display substrate and the photodetection substrate, the lens layer includes a plurality of lenses, and the lenses are used for condensing light.
  • the display device further includes:
  • a compensation circuit connected to the data reading line, for determining the compensation parameter of the light-emitting device according to the difference between the actual voltage and the theoretical voltage on the data reading line;
  • a display driving circuit connected with the compensation circuit and the pixel structure, is used for determining the driving signal of the light-emitting device according to the compensation parameters of the light-emitting device and the target light-emitting brightness of the light-emitting device, and driving the A signal is output to the pixel structure.
  • embodiments of the present disclosure provide a method for driving a photoelectric detection circuit, where the photoelectric detection circuit adopts the photoelectric detection circuit described in the above embodiments, wherein the driving method includes:
  • an active level signal is applied to the reset line and an inactive level signal is applied to the scan line, so that the first reset subcircuit resets the voltage of the first node, and the second reset subcircuit resets the voltage of the first node.
  • the reset subcircuit resets the voltage of the scan line;
  • both the reset line and the scan line are loaded with an inactive level signal, so that the photodetection device performs charge accumulation;
  • an inactive level signal is applied to the scan line and the reset line, so that the data read sub-circuit disconnects the first node from the data read line.
  • an embodiment of the present disclosure provides a method for fabricating a display device, including:
  • a plurality of photoelectric detection circuits are formed on the first substrate to form a photoelectric detection substrate; wherein, the photoelectric detection circuits adopt the photoelectric detection circuits in the above embodiments;
  • the display substrate includes opposite display sides and non-display sides, and the pixel structures include light emitting devices;
  • each of the pixel structures is within the orthographic projection range on the second substrate to receive light from the y light-emitting devices, 1 ⁇ y ⁇ 100, and y is an integer.
  • the light emitting device includes: a first electrode, a second electrode, and a light emitting layer located between the first electrode and the second electrode, the light emitting layer being located on the first part of the light emitting device a side of the electrode away from the second substrate, the pixel structure further includes a light-passing part located between the light-emitting layer and the second substrate, the light-passing part is used for light-passing, so that the light is emitted A portion of the light emitted by the layer is directed towards the second substrate.
  • the light-passing portion includes a first light-passing hole, and the first light-passing hole passes through the pixel driving circuit; or,
  • the light passing portion includes a light passing slit in the pixel driving circuit.
  • the first electrode is a reflective electrode
  • the light passing portion further includes a second light passing hole passing through the first electrode
  • the manufacturing method further includes: manufacturing a lens layer, the lens layer includes a plurality of lenses, and the lenses are used for condensing light;
  • Fixing the display substrate and the photoelectric detection substrate together includes:
  • the lens layer is fixed on the non-display side of the display substrate, and the photodetection substrate is fixed on the side of the lens layer away from the display substrate.
  • FIG. 1 is a schematic circuit diagram of a photoelectric detection circuit provided in an embodiment of the present disclosure.
  • FIG. 2 is a schematic structural diagram of a photosensitive device provided in an embodiment of the present disclosure.
  • FIG. 3 is a schematic circuit diagram of another photoelectric detection circuit provided in an embodiment of the present disclosure.
  • FIG. 4 is a working timing diagram of the photoelectric detection circuit shown in FIG. 3 .
  • 5a is a plan view of a semiconductor layer of a photodetection circuit provided in an embodiment of the present disclosure.
  • 5b is a plan view of a semiconductor layer and a first metal layer of a photodetection circuit provided in an embodiment of the present disclosure.
  • FIG. 5c is a schematic diagram of a via hole on the first insulating layer provided in an embodiment of the present disclosure.
  • Figure 5d is a cross-sectional view taken along line AA' in Figure 5c.
  • FIG. 5e is a plan view of the second metal layer of the photodetection circuit provided in the embodiment of the present disclosure.
  • FIG. 5f is a semiconductor layer of a photodetection circuit provided in an embodiment of the present disclosure.
  • Fig. 5g is a cross-sectional view taken along line BB' in Fig. 5f.
  • 5h is a schematic diagram of a semiconductor layer, a first metal layer, a second metal layer, and a first pole of a photosensitive device of a photodetection circuit provided in an embodiment of the present disclosure.
  • FIG. 5i is a plan view of a plurality of photodetection circuits provided in an embodiment of the present disclosure.
  • FIG. 6 is a flowchart of a driving method of a photodetection circuit provided in an embodiment of the present disclosure.
  • FIG. 7a is a schematic structural diagram of a display device provided in an embodiment of the disclosure.
  • FIG. 7b is a schematic diagram of the photodetection circuit in FIG. 7a detecting light.
  • FIG. 8a is a schematic structural diagram of another display device provided in an embodiment of the present disclosure.
  • FIG. 8b is a schematic diagram of light detection by the photoelectric detection circuit in FIG. 8a.
  • FIG. 9a is a schematic diagram of the working principle of the display device provided in the embodiment of the present disclosure.
  • Figure 9b is a graph showing the relationship between the intensity of the electrical signal generated by the photosensitive device and the brightness of the light when the duration of the charge accumulation phase is constant.
  • FIG. 9c is a relationship curve between the intensity of the electrical signal and the brightness of the light after adjustment by the duration.
  • FIG. 10 is a schematic diagram of the arrangement of a photoelectric detection circuit provided in an embodiment of the present disclosure.
  • FIG. 11 is a schematic circuit diagram of a pixel driving circuit provided in an embodiment of the present disclosure.
  • 12a is a plan view of a semiconductor layer of a display substrate provided in an embodiment of the present disclosure.
  • 12b is a plan view of a first gate metal layer of a display substrate provided in an embodiment of the present disclosure.
  • 12c is a plan view of a semiconductor layer and a first gate metal layer of a display substrate provided in an embodiment of the present disclosure.
  • FIG. 12d is a plan view of the second gate metal layer of the display substrate provided in the embodiment of the present disclosure.
  • 12e is a plan view of a semiconductor layer, a first gate metal layer and a second gate metal layer of a display substrate provided in an embodiment of the present disclosure.
  • FIG. 12f is a schematic diagram of a via hole on an interlayer dielectric layer provided in an embodiment of the present disclosure.
  • Figure 12g is a cross-sectional view taken along line CC' in Figure 12f.
  • FIG. 12h is a plan view of a first source-drain metal layer provided in an embodiment of the present disclosure.
  • 12i is a plan view of a semiconductor layer, a first gate metal layer, a second gate metal layer, and a first source-drain metal layer of a display substrate provided in an embodiment of the present disclosure.
  • FIG. 12j is a schematic diagram of a via hole on the passivation layer provided in the embodiment of the present disclosure.
  • FIG. 12k is a plan view of the second source-drain metal layer of the display substrate provided in the embodiment of the present disclosure.
  • 13a is a plan view of a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer of a display substrate provided in an embodiment of the present disclosure.
  • Figure 13b is a cross-sectional view taken along line DD' in Figure 13a.
  • FIG. 13c is a positional relationship diagram of the tenth via hole and the second source-drain metal layer provided in the embodiment of the present disclosure.
  • FIG. 13d is a plan view of the first electrode layer and the second source-drain metal layer of the display substrate provided in the embodiment of the present disclosure.
  • FIG. 13e is a schematic diagram of the connection between the first electrode layer and the second source-drain metal layer of the display substrate provided in the embodiment of the present disclosure.
  • FIG. 14 is a flowchart of a method for fabricating a display device according to an embodiment of the present disclosure.
  • the transistors used in all the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. Since the source and drain of the used transistor are symmetrical, there is no difference between the source and the drain. To distinguish the source and drain of the transistor, one of the electrodes is called the first electrode, and the other is called the second electrode.
  • transistors can be divided into N-type transistors and P-type transistors, and each transistor in the present disclosure can be independently selected from N-type transistors or P-type transistors; in the following embodiments, it will be shown that each transistor in the driving circuit is an N-type transistor.
  • a type transistor is taken as an example for illustrative description, and in this case, the transistors in the display driving circuit can be fabricated simultaneously by using the same fabrication process.
  • the valid level signal is a high level signal
  • the invalid level signal is a low level signal.
  • FIG. 1 is a schematic circuit diagram of a photoelectric detection circuit provided in an embodiment of the present disclosure.
  • the photoelectric detection circuit includes: a first reset sub-circuit 11 , a second reset sub-circuit 12 , and a first storage sub-circuit 14 , the data reading sub-circuit 16 and the photosensitive device 13 .
  • the first end of the data reading sub-circuit 16, the first end of the first storage sub-circuit 14, the first pole of the photosensitive device 13, and the first end of the first reset sub-circuit 11 are connected to the first node N1;
  • the second pole of the device 13 is connected to the common voltage line.
  • FIG. 2 is a schematic structural diagram of a photosensitive device provided in an embodiment of the present disclosure.
  • the photosensitive device 13 may use a PIN photodiode, which specifically includes: a first pole 131 , a P-type semiconductor layer 133 , a layered first pole 131 , a P-type semiconductor layer 133 , a The sign layer 134 , the N-type semiconductor layer 135 and the second pole 132 are formed.
  • the data read sub-circuit 16 is also connected to the scan line Scan and the data read line DataRead, and the data read line DataRead is configured to transmit the voltage of the first node N1 to the data read line in response to the control of the signal of the scan line Scan DataRead.
  • the first reset sub-circuit 11 is also connected to the reset line Reset and the common voltage line Vcom, and the first reset sub-circuit 11 is configured to, in response to the control of the signal of the reset line Reset, transmit the reference signal of the common voltage line Vcom to the first node N1, thereby resetting the voltage of the first node N1.
  • the first storage sub-circuit 14 is connected between the first node N1 and the common voltage line Vcom, and the first storage sub-circuit 14 is configured to store the voltage between the first node N1 and the common voltage line Vcom.
  • the second reset sub-circuit 12 is connected to the reset line Reset, the scan line Scan and the common voltage line Vcom, and the second reset sub-circuit 12 is configured to transmit the reference signal on the common voltage line Vcom in response to the control of the signal of the reset line Reset to the scan line Scan to reset the voltage on the scan line Scan.
  • the working stages of the photodetection circuit in the embodiment of the present disclosure may include: a reset stage, a charge accumulation stage, and a data reading stage.
  • the voltage of the first node N1 is reset, and at the same time, the second reset sub-circuit 12 resets the voltage on the scan line Scan; in the charge accumulation stage, the photosensitive device 13 performs charge accumulation according to the light signal it receives; in the reading stage, By loading a valid level signal to the scan line Scan, the read sub-circuit transmits the voltage of the first node N1 to the data read line DataRead, so that the external processing circuit can read the voltage according to the data read line DataRead Determine the light intensity received by the photosensitive device 13 .
  • the photodetection circuit in the embodiment of the present disclosure can be applied to an OLED display device.
  • the photosensitive device 13 can be used to receive at least a part of the light emitted by the light-emitting device in the OLED display device, so that the external compensation circuit can The difference between the actual voltage read by the reading line DataRead and the theoretical voltage determines the compensation parameter of the light-emitting device; then the driving circuit can determine the driving signal of the light-emitting device according to the compensation parameter of the light-emitting device and the target light-emitting brightness of the light-emitting device, and The driving signal is output to the pixel structure, so that the light-emitting device can achieve the target light-emitting brightness, so that the light-emitting brightness of different light-emitting devices is consistent.
  • the photodetection circuit further includes: a second storage sub-circuit 15, the second storage sub-circuit 15 is connected between the scan line Scan and the common voltage line Vcom, and is configured to store the scan line Scan The voltage between it and the common voltage line Vcom.
  • the second storage sub-circuit 15 can maintain the stability of the voltage on the scan line Scan to prevent the voltage on the scan line Scan from being affected in the charge accumulation stage The data reads the state of the sub-circuit 16, thereby ensuring the stability of the voltage output.
  • FIG. 3 is a schematic circuit diagram of another photoelectric detection circuit provided in an embodiment of the present disclosure. As shown in FIG. 3 , the photoelectric detection circuit is a specific implementation of the photoelectric detection circuit shown in FIG. 1 .
  • the first reset sub-circuit 11 includes: a first reset transistor T1, the gate of the first reset transistor T1 is connected to the reset line Reset, and the first electrode of the first reset transistor T1 is connected to the common The voltage line Vcom, the second pole of the first reset transistor T1 forms the first end of the first reset sub-circuit 11, that is, the second pole of the first reset transistor T1 is connected to the first node N1.
  • the data reading sub-circuit 16 includes: a data reading transistor T3, the gate of the data reading transistor T3 is connected to the scan line Scan, the first pole of the data reading transistor T3 is connected to the data reading line DataRead, and the first pole of the data reading transistor T3 is connected to the data reading line DataRead.
  • the diode is formed as the first terminal of the data reading sub-circuit 16, that is, the second terminal of the data reading transistor T3 is connected to the first node N1.
  • the second reset sub-circuit 12 includes: a second reset transistor T2, the gate of the second reset transistor T2 is connected to the reset line Reset, the first electrode of the second reset transistor T2 is connected to the common voltage line Vcom, the second reset transistor T2 The second electrode of the reset transistor T2 is connected to the scan line Scan.
  • the first storage sub-circuit 14 includes: a first capacitor C1, the first capacitor C1 is connected to the common voltage line Vcom and the first node N1.
  • the second storage sub-circuit 15 includes: a second capacitor C2 connected between the scan line Scan and the common voltage line Vcom.
  • FIG. 4 is a working timing diagram of the photoelectric detection circuit shown in FIG. 3 .
  • the operation process of the photoelectric detection circuit shown in FIG. 3 will be described below with reference to the accompanying drawings.
  • the working process of the photodetection circuit includes a reset phase t1 , a charge accumulation phase t2 , a scan phase t3 and a redundancy phase t4 .
  • the voltage of the common voltage line Vcom is a low level voltage.
  • the reset line Reset is loaded with an active level signal
  • the scan line Scan is loaded with an inactive level signal.
  • both the first reset transistor T1 and the second reset transistor T2 are in an on state, and the data writing transistor is in an off state.
  • the first node N1 receives the voltage of the common voltage line Vcom, and the scan line Scan is turned on with the common voltage line Vcom, thereby maintaining a low-level voltage.
  • the reset line Reset and the scan line Scan are loaded with inactive level signals, and at this time, the first reset transistor T1, the second reset transistor T2 and the data read transistor T3 are all turned off.
  • the voltage on the scan line Scan remains the same as that in the reset phase, thereby ensuring that the data reading transistor T3 is in an off state.
  • the photoelectric conversion effect of the photosensitive device 13 the voltage of the first node N1 gradually increases.
  • the reset line Reset is loaded with an inactive level signal
  • the scan line Scan is loaded with an active level signal.
  • the first reset transistor T1 and the second reset transistor T2 are both kept off, and the data read transistor T3 is in In the on state, the voltage of the first node N1 is transmitted to the data read line DataRead, so that the external processing circuit can read the voltage of the first node N1, and then determine according to the voltage of the first node N1 that the photosensitive device 13 receives of light intensity.
  • an inactive level signal is applied to the scan line Scan and the reset line Reset, so that the first reset transistor T1, the second reset transistor T2, and the data read transistor T3 are all kept in an off state, and the first node N1 and the The data read line DataRead is disconnected.
  • the duration of the charge accumulation phase can be set according to actual needs to prevent the light-emitting device when the brightness is low.
  • the intensity of the detected signal is too small, or the brightness of the light-emitting device is high, the detected signal is saturated.
  • the duration of the working cycle of the photosensitive device 13 ie, the total duration of the reset phase t1 , the charge accumulation phase t2 , the scanning phase t3 and the redundancy phase t4 .
  • the duration of the charge accumulation stage t2 needs to be increased, the duration of the redundant stage t4 can be reduced; when the duration of the charge accumulation stage t2 needs to be reduced, the duration of the redundant stage t4 can be increased, so that the photosensitive device 13
  • the duration of the duty cycle remains unchanged.
  • the data read line DataRead, the scan line Scan, the common voltage line Vcom, each transistor in the photodetection circuit, the capacitor and the photosensitive device 13 are all disposed on the first substrate.
  • the data read line DataRead and the scan line Scan are located in different layers of insulating spacers, the scan line Scan extends along a first direction, the data read line DataRead extends along a second direction, and the first direction and the second direction intersect. .
  • the active layers of the transistors in the photodetection circuit are arranged in the same layer, the reset line Reset, the scan line Scan and the common voltage line Vcom are arranged in the same layer, and the reset line Reset is arranged with the first and second electrodes of the transistors.
  • Very homogenous settings It should be noted that “same layer arrangement” means that the two structures are formed by the same material layer through the patterning process, so the two are in the same layer in terms of stacking relationship; this does not mean that the two structures are in the same layer. The distance between the first base and the first base must be the same.
  • the active layer of each transistor is located in the semiconductor layer
  • the reset line Reset, the scan line Scan and the common voltage line Vcom are located in the first metal layer
  • the data read line DataRead and the first and second electrodes of the transistors are located in the first metal layer.
  • two metal layers The structure of each layer and the connection relationship between the layers of the photodetection circuit in the embodiments of the present disclosure will be introduced below with reference to the accompanying drawings.
  • the semiconductor layer poly1 may be made of polysilicon or metal oxide, which is not specifically limited in the embodiment of the present disclosure.
  • the semiconductor layer poly1 includes: an active layer T1_p of the first reset transistor T1, an active layer T2_p of the second reset transistor T2, and an active layer T3_p of the data read transistor T3.
  • the active layer T1_p of the first reset transistor T1 and the active layer T2_p of the second reset transistor T2 may be connected as a whole.
  • the first metal layer M1 may be made of metal materials such as silver, aluminum, molybdenum, or copper. The disclosed embodiments do not specifically limit this.
  • the first metal layer M1 is located on the side of the semiconductor layer poly1 away from the first substrate, and the first metal layer M1 and the semiconductor layer poly1 are separated by an insulating layer.
  • the first metal layer M1 includes: a common voltage line Vcom, a scan line Scan, a reset line Reset, gates of each transistor, and a first plate C1_1 of the first capacitor C1.
  • the common voltage line Vcom, the scan line Scan and the reset line Reset all extend along the first direction, and the scan line Scan is located between the common voltage line Vcom and the reset line Reset.
  • the gate of the data reading transistor T3 is a part of the scan line Scan, and the gate of the first reset transistor T1, the gate of the second reset transistor T2 and the reset line Reset form an integrated structure, that is, the gate of the first reset transistor T1,
  • the gate of the second reset transistor T2 and the reset line Reset are formed as a whole, or the gate of the first reset transistor T1, the gate of the second reset transistor T2 and the reset line Reset are respectively three conductive structures, and the three The conductive structures are electrically connected.
  • the first plate of the first capacitor C1 and the common voltage line Vcom form an integral structure, that is, the first plate of the first capacitor C1 and the common voltage line Vcom are formed as a whole, or the first electrode of the first capacitor C1
  • the board and the common voltage line Vcom are respectively two conductive structures, and the two conductive structures are electrically connected.
  • FIG. 5c is a schematic diagram of a via hole on the first insulating layer provided in an embodiment of the present disclosure
  • FIG. 5d is a cross-sectional view along the line AA' in FIG. 5c.
  • the first metal layer M1 and A third insulating layer Ins3 is provided between the semiconductor layers poly1
  • a first insulating layer Ins1 is provided on the side of the first metal layer M1 away from the first substrate 17 .
  • both the first insulating layer Ins1 and the third insulating layer Ins3 may be a single layer or multiple layers of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer.
  • the first insulating layer Ins1 is provided with a plurality of via holes.
  • the via holes on the first insulating layer Ins1 include a first via hole V1, a second via hole V2, a source via hole V_s and a drain via hole V_d, the first via hole V1 exposes a part of the common voltage line Vcom, the second via hole V1 The via hole V2 exposes a part of the scan line Scan.
  • the active layer of each transistor corresponds to a source via hole V_s and a drain via hole V_d.
  • FIG. 5e is a plan view of the second metal layer of the photodetection circuit provided in the embodiment of the disclosure
  • FIG. 5f is a plan view of the semiconductor layer, the first metal layer and the second metal layer of the photodetection circuit provided in the embodiment of the disclosure.
  • the fabrication material of the second metal layer M2 may be a metal material such as silver, aluminum, molybdenum, or copper, which is not specifically limited in this embodiment of the present disclosure. As shown in FIG. 5c to FIG.
  • the second metal layer M2 is located on the side of the first insulating layer Ins1 away from the semiconductor layer poly1, and the second metal layer M2 includes: a data read line DataRead, a second plate of the first capacitor C1 C1_2, the first pole and the second pole of each transistor.
  • the first electrodes of each transistor are connected to the active layer through the corresponding source via holes V_s, and the second electrodes of each transistor are connected to the active layer through the corresponding drain via holes V_d.
  • the orthographic projections of the first electrode T3_1 and the second electrode T3_2 of the data reading transistor T3 on the first substrate are respectively located on two sides along the second direction of the orthographic projection of the scan line Scan on the first substrate.
  • the first pole T1_1 of the first reset transistor T1 is connected to the common voltage line Vcom through the first via hole V1.
  • the second pole T2_2 of the second reset transistor T2 is connected to the scan line Scan through the second via hole V2.
  • the first electrode T3_1 of the data read transistor T3 and the data read line DataRead form an integrated structure
  • the lines DataRead are respectively two conductive structures, and the two conductive structures are electrically connected; the second electrode plate C1_2 of the first capacitor C1, the second electrode T1_2 of the first reset transistor T1, and the second electrode T3_2 of
  • the first pole T1_1 of the first reset transistor T1 and the first pole T2_1 of the second reset transistor T2 form an integral structure, and here, the first pole T1_1 of the first reset transistor T1 and the first pole T2_1 of the second reset transistor T2 form an integral structure It is an integral electrode block, which can be used as the first electrode T1_1 of the first reset transistor T1 or the first electrode T2_1 of the second reset transistor T2; or, the first electrode T1_1 of the first reset transistor T1 and the The first electrodes T2_1 of the second reset transistor T2 are respectively two electrode blocks, and the two electrode blocks are electrically connected.
  • the first electrode T1_1 of the first reset transistor T1 (ie, the first electrode T2_1 of the second reset transistor T2 ) is insulated and intersected with the scan line Scan, and the intersecting portion forms a second capacitor C2 . That is, the first electrode plate of the second capacitor C2 is a part of the scan line Scan, and the second electrode plate of the second capacitor C2 is a part of the first electrode T1_1 of the first reset transistor T1.
  • FIG. 5g is a cross-sectional view along the line BB' in FIG. 5f.
  • a second insulating layer Ins2 is provided on the side of the layer where the second plate C1_2 of the first capacitor C1 is located away from the first substrate 17, which can
  • the second insulating layer Ins2 may be a single layer or multiple layers of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer.
  • a third via hole V3 is provided on the second insulating layer Ins2. As shown in FIG. 5f and FIG. 5g, the third via hole V3 exposes a part of the second electrode plate C1_2 of the first capacitor C1.
  • the photosensitive device 13 is disposed on the side of the second insulating layer Ins2 away from the first substrate 17 , and FIG. 5h is the semiconductor layer, the first metal layer, and the second metal layer of the photodetection circuit provided in the embodiment of the disclosure.
  • FIG. 5h Schematic diagram of the layer and the first pole of the photosensitive device, combined with FIGS. 5f to 5h, the first pole of the photosensitive device 13 is connected to the second plate C1_2 of the first capacitor C1 through the third via V3 to form FIG. 3 The first node N1 in .
  • the orthographic projection of the first pole 131 of the photosensitive device 13 on the first substrate does not overlap with the orthographic projection of the data read line DataRead on the first substrate.
  • the orthographic projection of the second pole 132 of the photosensitive device 13 on the first substrate exceeds the orthographic projection of the first pole 131 of the photosensitive device 13 on the first substrate, so as to prevent the second pole 132 from interacting with the first pole when the common voltage line Vcom is connected.
  • the pole 131 is short-circuited.
  • the second electrode 132 of the photosensitive device 13 is a transparent electrode made of a transparent conductive material (eg, indium tin oxide, etc.), so that the photosensitive device 13 can receive the light emitted by the light-emitting device.
  • transparent in the embodiments of the present disclosure may mean that the light transmittance is above 80%.
  • FIG. 5i is a plan view of a plurality of photodetection circuits provided in an embodiment of the present disclosure.
  • the P-type semiconductor layer 133, the intrinsic layer 134, and the N-type semiconductor layer 135 of the photosensitive device 13 are omitted in FIG. 5i.
  • the P-type semiconductor layer 133 , the intrinsic layer 134 , and the N-type semiconductor layer 135 of the photosensitive device 13 and the first pole 131 of the photosensitive device 13 can be formed by the same photolithography patterning process.
  • the photosensitive device 13 The range of the orthographic projection of the P-type semiconductor layer 133 , the intrinsic layer 134 , and the N-type semiconductor layer 135 and the first pole 131 of the photosensitive device 13 on the first substrate may be the same. As shown in Figure 5i, a plurality of photodetection circuits can be set on the first substrate, and the plurality of photodetection circuits can be arranged in an array.
  • the photodetection circuits in the same column can be connected to the same data read line DataRead, and the photodetection circuits in the same row
  • the connected scan lines Scan are the same
  • the common voltage lines Vcom connected to the photodetection circuits in the same row are the same
  • the reset lines Reset connected to the photodetection circuits in the same row are the same.
  • the second poles 132 of the photosensitive devices 13 in the plurality of photodetection circuits may be connected to form a whole-layer structure. Therefore, for one of the photosensitive devices 13, the orthographic projection of the second pole 132 of the photosensitive device 13 on the first substrate exceeds the orthographic projection of the first pole 131 on the first substrate.
  • the portion of the second pole 132 beyond the first pole 131 is connected to the common voltage line Vcom through a via hole penetrating the first insulating layer and the second insulating layer.
  • a common voltage bus may be provided, the common voltage bus is connected to each common voltage line Vcom, and the second pole 132 is connected to the common voltage through vias penetrating the first insulating layer and the second insulating layer. bus connection.
  • the orthographic projection of the first pole 131 of the photosensitive device 13 on the first substrate at least covers the orthographic projection of the first capacitor C1 on the first substrate.
  • the orthographic projection of the first pole 131 of the photosensitive device 13 on the first substrate covers the positive projection of the first capacitor C1 on the first substrate in the photodetection circuit where it is located.
  • the projection is overlapped with the orthographic projection of the data reading transistor T3 in the photodetection circuit where it is located on the first substrate, and at the same time, it overlaps with the data reading transistor T3, the first reset transistor T1, the first reset transistor T1, the third
  • the orthographic projections of the two reset transistors T2 on the first substrate both overlap.
  • the orthographic projection of the first electrode 131 of the photosensitive device 13 on the first substrate can also cover the first capacitor C1, the data reading transistor T3, the first capacitor C1, the data reading transistor T3, the first capacitor in the photodetecting circuit where it is located Orthographic projections of the reset transistor T1 and the second reset transistor T2 on the first substrate.
  • FIG. 6 is a flowchart of the driving method for the photoelectric detection circuit provided in the embodiment of the disclosure. As shown in FIG. 6 , the driving method includes:
  • FIG. 7 a is a schematic structural diagram of a display device provided in an embodiment of the present disclosure.
  • the display device includes a display substrate 2 and a photoelectric detection substrate 1 .
  • the display substrate 2 includes opposing display sides and non-display sides.
  • the photodetection substrate 1 includes: a first substrate 17 and a plurality of photodetection circuits 10 disposed on the first substrate 17 , and the photodetection circuits 10 use the photodetection circuits 10 in any of the above embodiments.
  • the photodetection substrate 1 is located on the non-display side of the display substrate 2 , and the photosensitive device of the photodetection circuit 10 faces at least one light-emitting device 22 so as to receive light from the light-emitting device 22 .
  • the display substrate 2 includes: a second substrate 20 and a plurality of pixel structures disposed on the second substrate 20 , and the pixel structures include a light emitting device 22 and a pixel driving circuit 21 .
  • the light-emitting device 22 in the embodiment of the present disclosure may be a current-driven light-emitting device 22 including an LED (Light Emitting Diode, light-emitting diode) or an OLED (Organic Light Emitting Diode, organic light-emitting diode). The description is given by taking an OLED as an example.
  • the display side of the display substrate 2 is the side where the viewer is when the display substrate 2 is displaying; the non-display side of the display substrate 2 is the side opposite to the display side.
  • FIG. 7b is a schematic diagram of the photodetection circuit in FIG. 7a detecting light.
  • the arrows in FIG. 7b indicate light.
  • the light-emitting device 22 is disposed on the side of the pixel driving circuit 21 away from the second substrate 20.
  • the light-emitting device 22 includes : arranged in sequence along the direction away from the second substrate 20 : a first electrode 221 , a hole injection layer 222 , a hole transport layer 223 , a light emitting layer 224 , an electron transport layer 225 , an electron injection layer 226 , and a second electrode 227 .
  • the first electrode 221 is an anode
  • the second electrode 227 is a cathode.
  • the pixel structure further includes a light-passing portion located between the light-emitting layer 224 and the second substrate 20, the light-passing portion is The portion is used to pass light, so that a part of the light emitted by the light emitting layer 224 is directed to the second substrate 20 and then irradiated to the non-display side through the second substrate 20 .
  • the photodetection circuit 10 includes a photosensitive device 13 and a photosensitive device driving structure 13t, and the photosensitive device driving structure 13t includes the first reset transistor T1, the second reset transistor T2, the data reading transistor T3, the first capacitor C1 and the first reset transistor T2 in the above embodiment. Two capacitors C2..
  • the photosensitive device 13 is disposed between the photosensitive device driving structure 13t and the second substrate 20 to receive a part of the light emitted by the light emitting device 22 .
  • the pixel driving circuit 21 includes conductive layers such as a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer. Spaced by an insulating layer (eg, a first gate insulating layer, a second gate insulating layer, etc.).
  • Each conductive film layer includes a plurality of opaque conductive patterns.
  • the first gate metal layer includes gate lines, gates of a plurality of transistors, etc.
  • the semiconductor layer includes active layers of a plurality of transistors. The details will be described below. describe.
  • the light passing portion may include a first light passing hole Vt1 passing through the pixel driving circuit 21 .
  • the first light-passing hole Vt1 passes through the insulating layer, and the orthographic projection of the first light-passing hole Vt1 on the second substrate 20 does not overlap with the orthographic projection of the conductive pattern in the pixel driving circuit 21 on the second substrate 20 .
  • the light passing portion includes a light passing slit in the pixel driving circuit 21 .
  • the insulating layer between the conductive film layers is made of transparent material, and the light-transmitting slit is the gap between the conductive patterns.
  • the first light-transmitting hole Vt1 may not be provided, and the light emitted by the light-emitting device 22 may pass through the gaps between the conductive patterns and directly pass through the insulating layer, thereby irradiating the photosensitive device 13.
  • the first electrode 221 of the light emitting device 22 in the embodiment of the present disclosure may adopt a reflective electrode.
  • the light-passing portion further includes a second light-passing hole Vt2 passing through the first electrode 221 .
  • the orthographic projection of the hole Vt2 on the second substrate 20 overlaps with the orthographic projection of the first light-transmitting hole Vt1 (or the light-transmitting slit) on the second substrate 20 .
  • the first electrode 221 may also be a transparent electrode. In this case, the first electrode 221 may be provided with a second light-transmitting hole Vt2 or not.
  • each photosensitive device 13 may be opposite to one light-emitting device 22 , or may be opposite to a plurality of photosensitive devices 13 .
  • the photosensitive device 13 receives light from one light-emitting device 22;
  • the plurality of light-emitting devices 22 can be controlled to emit light in different light-emitting stages , so as to ensure that the photosensitive device 13 receives the light emitted by different light-emitting devices 22 in different light-emitting stages.
  • the orthographic projection of each photosensitive device 13 on the second substrate 20 is located within the orthographic projection range of the y pixel structures on the second substrate 20 .
  • 1 ⁇ y ⁇ 100, and y is an integer, so as to ensure the detection accuracy and prevent the manufacturing process from being too difficult.
  • the orthographic projection of each photosensitive device 13 on the second substrate 20 is located within the orthographic projection range of the y pixel structures on the second substrate 20 , and may be: each photosensitive device 13 is disposed directly opposite to the y pixel structures to The light emitted by the y light-emitting devices 22 is received.
  • the orthographic projection area of each pixel structure on the second substrate 20 may be 70 square microns.
  • each pixel structure is on the second substrate 20.
  • the orthographic projected area on it is less than 70 square microns.
  • the orthographic projection area of a single pixel structure on the second substrate 20 changes, the orthographic projection area of each photosensitive device 13 on the second substrate 20 also changes correspondingly, but the positive projection area of each photosensitive device 13 on the second substrate 20 changes accordingly.
  • the proportional relationship between the projection and the orthographic projection of the pixel structure on the second substrate 20 may be fixed.
  • each photosensitive device 13 on the second substrate 20 is located at 4*4 (ie, 16) pixel structures on the first Within the orthographic projection range on the two substrates 20, and each photosensitive device 13 is directly opposite to the 4*4 pixel structure.
  • an optical adhesive layer 3 is further disposed between the display substrate 2 and the photodetection substrate, so that the display substrate 2 and the photodetection substrate 1 are bonded by the optical adhesive layer 3 .
  • FIG. 8a is a schematic structural diagram of another display device provided in an embodiment of the present disclosure
  • FIG. 8b is a schematic diagram of the photoelectric detection circuit in FIG. 8a detecting light
  • the arrows in FIG. 8b represent light.
  • the display device further includes: a lens layer, and the lens layer is disposed between the display substrate 2 and the photodetection substrate.
  • the lens layer includes a plurality of lenses 4 .
  • An optical adhesive layer 3 is disposed between the lens layer and the display substrate 2 and between the lens layer and the photoelectric detection substrate.
  • the plurality of lenses 4 of the lens layer are arranged in multiple rows and columns, and each lens 4 may be directly opposite to one or more light emitting devices 22 .
  • the lens 4 can be a convex lens for condensing light. Similar to FIG. 7b, in FIG. 8b, a part of the light from the light-emitting device 22 is irradiated to the photosensitive device 13 through the light-transmitting part. The difference from FIG. 7b is that in FIG. lens 4, thereby converging.
  • the second substrate 20 can be a glass substrate, for example, the thickness of the glass substrate is between 100 ⁇ m and 500 ⁇ m, or a flexible substrate with a thinner thickness, for example, the flexible substrate is polyimide (PI) ), the thickness is between 3 ⁇ m and 20 ⁇ m.
  • the second substrate 20 adopts a glass substrate with a larger thickness, the light irradiated by the light-emitting device 22 to the non-display side will be seriously divergent, and the convergence effect of the lens 4 can reduce the divergence angle, so as to improve the electrical signal generated by the photosensitive device 13 accuracy.
  • the second substrate 20 is a flexible substrate with a smaller thickness, the degree of divergence of the light irradiated by the light emitting device 22 to the non-display side is smaller, therefore, a lens layer may or may not be provided.
  • FIG. 9a is a schematic diagram of the working principle of the display device provided in the embodiment of the disclosure.
  • the display device further includes a compensation circuit 4 and a display driving circuit 5.
  • the compensation circuit 4 is connected to the above-mentioned data read line DataRead for use in According to the difference between the actual voltage on the data read line DataRead and the theoretical voltage, the compensation parameter of the light emitting device 22 is determined.
  • the compensation circuit 4 may include a signal reading sub-circuit and a signal processing sub-circuit, the signal reading sub-circuit can read the voltage on the data reading line DataRead, and the signal processing sub-circuit is used to read the voltage output by the signal reading sub-circuit Signal processing such as analog-to-digital conversion.
  • the display driving circuit 5 is connected to the compensation circuit 4 and the pixel driving circuit 21 of the pixel structure, and is used to determine the driving signal of the light-emitting device 22 according to the compensation parameters of the light-emitting device 22 and the target luminous brightness of the light-emitting device 22, and output the driving signal to
  • the pixel driving circuit 21 of the pixel structure can achieve the target brightness when the light emitting device 22 emits light under the driving of the pixel driving circuit 21 .
  • the actual voltage can be the voltage signal actually read by the data reading line DataRead when the display substrate displays the test image; the theoretical voltage is the data when the display substrate displays the test image and the light emitted by the light-emitting device 22 reaches the ideal brightness.
  • the voltage signal that the read line DataRead should read theoretically. It can be understood that due to the aging of the light emitting device 22 and the threshold shift of the transistors in the pixel driving circuit 21, the actual voltage on the data read line DataRead may be different from the theoretical voltage.
  • the display driving circuit 5 can determine the target brightness of the light-emitting device 22 according to the target image to be displayed, thereby determining the initial driving signal corresponding to the target brightness, and according to the compensation parameter of the light-emitting device 22.
  • the signal is adjusted to obtain a compensated driving signal, and then the driving signal is provided to the pixel driving circuit 21 to drive the light-emitting device 22 to emit light.
  • Figure 9b is a relationship curve between the electrical signal intensity and light brightness generated by the photosensitive device when the duration of the charge accumulation phase is constant
  • Figure 9c is a relationship curve between the electrical signal intensity and light brightness after adjustment by the duration. It can be seen from FIG. 9b that when the duration of the charge accumulation phase of the photoelectric detection circuit 10 is a certain value, the greater the light intensity detected by the photosensitive device 13, the greater the intensity of the generated electrical signal; and when the intensity of the electrical signal is greater When it is lower than the threshold V0, the compensation circuit 4 may not recognize the electrical signal at this time.
  • the intensity of the electrical signal generated by the photosensitive device can be changed.
  • the duration is adjusted so that when the light-emitting brightness of the light-emitting device 22 is high, the duration of the charge accumulation phase of the photodetection circuit 10 is reduced; when the light-emitting brightness of the light-emitting device 22 is low, the duration of the charge accumulation phase of the photodetection circuit 10 is increased. , so that the intensity of the electrical signal generated by the photosensitive device 13 is consistent under each luminous intensity, and the intensity of the electrical signal is higher than V0, as shown in FIG. 9c .
  • the voltage that should be read by the data read line DataRead is Vd
  • the actual brightness of the light-emitting device 22 is L2
  • the charge accumulation duration of the photoelectric sensing circuit is time2
  • the voltage that the data reading line DataRead should read is Vd
  • the display substrate is displaying a certain frame of test screen, and the test screen needs a light-emitting device
  • the duration of the charge accumulation phase of the control photodetection circuit 10 is time1.
  • the compensation value of the light-emitting device 22 can be determined according to the difference between Vd' and Vd, so that when the display substrate subsequently displays the target image, the compensation value of the light-emitting device 22 is provided to the light-emitting device 22.
  • the drive voltage of device 22 is compensated.
  • the light emitting devices 22 may be arranged in an array, and correspondingly, the plurality of photodetection circuits 10 of the photodetection substrate 1 are also arranged in an array.
  • FIG. 10 is a schematic diagram of the arrangement of the photodetection circuits provided in the embodiment of the present disclosure. As shown in FIG. 10 , the photodetection circuits 10 in the same column can be connected to the same data read line DataRead, and the photodetection circuits 10 connected to the same row
  • the scan lines Scan are the same, the common voltage lines Vcom connected to the photodetection circuits 10 in the same row are the same, and the reset lines Reset connected to the photodetection circuits 10 in the same row are the same.
  • the second poles of the plurality of photosensitive devices 13 can be connected into an integral structure, that is, the second poles of the plurality of photosensitive devices 13 can be connected into an integral structure, and can be connected to a common voltage line through via holes in the edge region of the first substrate 17 . Vcom connection.
  • FIG. 11 is a schematic circuit diagram of a pixel driving circuit provided in an embodiment of the present disclosure.
  • the pixel driving circuit 21 may adopt a simple 2T1C (ie, two transistors and one capacitor) structure to simplify the display substrate 2 . structure, and is conducive to improving the resolution of the display device.
  • the pixel driving circuit 21 includes: a driving transistor Td, a data writing transistor T1', and a third capacitor C3.
  • the gate of the data writing transistor T1' is connected to the gate line Gate, the first pole of the data writing transistor T1' is connected to the data line Data, the second pole of the data writing transistor T1' is connected to the gate of the driving transistor Td, and the driving transistor Td
  • the first electrode of the driving transistor Td is connected to the first power supply line VDD
  • the second electrode of the driving transistor Td is connected to the first electrode of the light emitting device 22
  • the second electrode of the light emitting device 22 is connected to the second power supply line VSS.
  • Two ends of the third capacitor C3 are respectively connected to the gate and the first electrode of the driving transistor Td.
  • the first power line VDD may be a high-level power line
  • the second power line VSS may be a low-level power line.
  • the gate line Gate is loaded with an active level signal.
  • the data writing transistor T1' is turned on, and the driving transistor Td is turned off, so that the data voltage on the data line Data is written into the third capacitor C3.
  • the gate line Gate is loaded with an inactive level signal.
  • the driving transistor Td is turned on, and sends the signal to the light-emitting device 22 according to the voltage between the gate and the first electrode. output drive current.
  • the pixel driving circuit 21 may also adopt circuits of other structures (eg, 7T1C, 9T1C, etc.), which is not limited here.
  • the active layer of each transistor of the pixel driving circuit 21 is arranged in the semiconductor layer, the gate of each transistor is arranged in the first gate metal layer, and the second plate of the third capacitor C3 is arranged in the semiconductor layer. is arranged in the second gate metal layer, the first power supply line VDD is arranged in the first source-drain metal layer, and the data line Data is arranged in the second source-drain metal layer. structure is introduced.
  • FIG. 12a is a plan view of a semiconductor layer of a display substrate provided in an embodiment of the present disclosure, and FIG. 12a shows a semiconductor layer poly2 of a pixel structure with two rows and three columns.
  • the semiconductor layer poly2 of the pixel structure includes the active layer of each transistor.
  • the fabrication material of the semiconductor layer poly2 may be polysilicon or metal oxide, which is not specifically limited in this embodiment of the present disclosure.
  • the first electrode Td_1 and the second electrode Td_2 of the driving transistor Td are arranged in the same layer as the active layer Td_p, and the second electrode T1'_2 of the data writing transistor T1' and the active layer T1'_p are also arranged in the same layer. , all located in the semiconductor layer poly2.
  • the first electrode Td_1 and the second electrode Td_2 of the driving transistor Td and the second electrode T1'_2 of the data writing transistor T1' can be formed by ion doping the semiconductor layer poly2.
  • FIG. 12b is a plan view of a first gate metal layer of a display substrate provided in an embodiment of the present disclosure
  • FIG. 12c is a plan view of a semiconductor layer and a first gate metal layer of the display substrate provided in an embodiment of the present disclosure, as shown in FIG. 12b and FIG.
  • the first gate metal layer G1 includes the gate T1'_g of the data writing transistor T1' and the gate Td_g of the driving transistor Td.
  • the first plate C3_1 of the third capacitor C3 is at least a part of the gate Td_g of the driving transistor Td, so as to simplify the overall structure of the pixel driving circuit 21 and simplify the manufacturing process.
  • a first gate insulating layer is disposed between the semiconductor layer poly2 and the first gate metal layer G1, and the first gate metal layer G1 is located on the side of the first gate insulating layer away from the semiconductor layer poly2.
  • the first gate insulating layer may be a single layer or multiple layers of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer.
  • FIG. 12d is a plan view of a second gate metal layer of a display substrate provided in an embodiment of the disclosure
  • FIG. 12e is a plan view of a semiconductor layer, a first gate metal layer, and a second gate metal layer of the display substrate provided in an embodiment of the disclosure 12d and 12e
  • the second gate metal layer G2 is located on the side of the first gate metal layer G1 away from the second substrate 20, and a second gate metal layer G2 and the first gate metal layer G1 are provided between the second gate metal layer G2 and the first gate metal layer G1.
  • the second plate C3_2 of each third capacitor C3 is located on the second gate metal layer G2.
  • the fabrication materials of the first gate metal layer G1 and the second gate metal layer G2 may be metal materials such as silver, aluminum, molybdenum, or copper, which are not specifically limited in this embodiment of the present disclosure.
  • interlayer dielectric layer is provided on the side of the second gate metal layer G2 away from the second substrate 20 .
  • the interlayer dielectric layer can be a single layer or multiple layers of silicon nitride layer, silicon oxide layer, and silicon oxynitride layer.
  • FIG. 12f is a schematic diagram of a via hole on the interlayer dielectric layer provided in the embodiment of the present disclosure
  • FIG. 12g is a cross-sectional view along the line CC' in FIG. 12f
  • a fourth via hole V4 a fifth via hole V5, a sixth via hole V6, a seventh via hole V7, an eighth via hole V8 and a source via hole V_s1 are provided, and the source via hole V_s1 is used to connect the data writing transistor
  • the second pole T1'_2 of T1' is connected to the data line.
  • the fourth via hole V4 penetrates through the interlayer dielectric layer ILD and exposes a part of the second electrode plate C3_2 of the third capacitor C3.
  • the fifth via hole V5 penetrates through the interlayer dielectric layer ILD, the second gate insulating layer GI2 and the first gate insulating layer GI1 simultaneously, and exposes a part of the first electrode Td_1 of the driving transistor Td.
  • the sixth via hole V6 penetrates both the interlayer dielectric layer ILD and the second gate insulating layer GI2, and exposes a part of the gate electrode Td_g of the driving transistor Td, wherein the orthographic projection of the sixth via hole V6 on the second substrate 20 is the same as that of the second substrate 20.
  • the orthographic projections of the second plate C3_2 of the third capacitor C3 on the second substrate 20 do not overlap.
  • the seventh via hole V7 penetrates through the interlayer dielectric layer ILD, the second gate insulating layer GI2 and the first gate insulating layer GI1 simultaneously, and exposes a part of the second electrode T1'_2 of the data writing transistor T1'.
  • the eighth via hole V8 penetrates through the interlayer dielectric layer ILD, the second gate insulating layer GI2 and the first gate insulating layer GI1 simultaneously, and exposes a part of the second electrode Td_2 of the driving transistor Td.
  • FIG. 12h is a plan view of a first source-drain metal layer provided in an embodiment of the present disclosure
  • FIG. 12i is a semiconductor layer, a first gate metal layer, a second gate metal layer, and a first source of a display substrate provided in an embodiment of the present disclosure Plan view of the drain metal layer. 12e to 12i, the first source-drain metal layer SD1 is located on the side of the second gate metal layer G2 away from the second substrate 20, and the interlayer dielectric layer ILD is disposed on the first source-drain metal layer SD1 and the second gate between the metal layers G2.
  • the first source-drain metal layer SD1 includes: a first power line VDD, the first power line VDD is connected to the second plate C3_2 of the third capacitor C3 through the fourth via V4, and is connected to the driving transistor Td through the fifth via V5
  • the first pole Td_1 is connected.
  • the pixel structure further includes a bridge member BR, and the bridge member BR and the first power supply line VDD are disposed in the same layer, and both are located in the first source-drain metal layer SD1.
  • One end of the bridge BR is connected to the gate Td_g of the driving transistor Td through the sixth via V6, and the other end of the bridge BR is connected to the second pole T1'_2 of the data writing transistor T1' through the seventh via V7.
  • the sixth via V6 is communicated with the seventh via V7 to improve the stability of the connection between the bridge BR and the gate Td_g of the driving transistor Td and the second pole T1'_2 of the data writing transistor T1'.
  • the pixel structure also includes a first adapter CT1 and a third adapter CT3.
  • the first adapter CT1 and the third adapter CT3 are arranged on the same layer as the bridge BR, and are located in the first source-drain metal layer SD1. middle.
  • the first transition piece CT1 is connected to the second pole Td_2 of the driving transistor Td through the eighth via hole V8.
  • the third transition piece CT3 is connected to the first electrode of the data writing transistor T1' through the source via V_s1.
  • FIG. 12j is a schematic diagram of a via hole on the passivation layer provided in an embodiment of the present disclosure. As shown in FIG. 12j , a ninth via hole V9 and an eleventh via hole V11 are provided on the passivation layer, and the ninth via hole V9 is exposed A part of the first adapter CT1 is exposed, and a part of the third adapter CT3 is exposed through the eleventh via hole V11.
  • FIG. 12k is a plan view of a second source-drain metal layer of a display substrate provided in an embodiment of the disclosure
  • FIG. 13a is a semiconductor layer, a first gate metal layer, a second gate metal layer, a semiconductor layer, a first gate metal layer, a second gate metal layer,
  • FIG. 13b is a cross-sectional view taken along the line D-D' in FIG. 13a.
  • the second source-drain metal layer SD2 is located on the side of the first source-drain metal layer SD1 away from the second substrate 20, and the passivation layer PVX is disposed on the second source-drain metal layer SD2 and the first source between the drain metal layers SD1.
  • the second source-drain metal layer SD2 includes the data line Data and the second transition piece CT2, and the second transition piece CT2 is connected to the first transition piece CT1 through the ninth via V9 on the passivation layer PVX.
  • the first pole T1'_1 of the data writing transistor T1' is integrated with the data line Data, and is connected to the third transition piece CT3 through the eleventh via V11, so as to write data through the third transition piece CT3.
  • the active layer of the transistor T1' is connected.
  • the fabrication materials of the first source-drain metal layer SD1 and the second source-drain metal layer SD2 may be metal materials such as silver, aluminum, molybdenum, or copper.
  • the gate line Gate and the first power line VDD extend along a third direction
  • the data line Data extends along a fourth direction
  • the third direction intersects the fourth direction, for example, the third direction is perpendicular to the fourth direction.
  • the third direction is the same as the first direction
  • the fourth direction is the same as the second direction.
  • a plurality of pixel structures of the display substrate 2 are arranged in rows and columns, and the fourth direction is the column direction.
  • the data writing transistors T1' of two adjacent pixel driving circuits 21 in the same column are respectively connected to the two adjacent data lines Data.
  • the virtual structure obtained by moving the pixel driving circuit 21 in the i-th row and the j-th column along the column direction is mirror-symmetrical with the pixel driving circuit 21 in the i+1-th row and the j+2-th column, where 1 ⁇ i ⁇ m ⁇ 1, 1 ⁇ j ⁇ n ⁇ 2, m is the total number of rows of the pixel driving circuit 21 , and n is the total number of columns of the pixel driving circuit 21 .
  • the dummy structure obtained by moving the pixel driving circuit 21 in the i-th row and the j-th column along the column direction is mirror-symmetrical with the pixel driving circuit 21 in the i+1-th row and the j+2-th column.
  • 1 ⁇ i ⁇ m-1, 1 ⁇ j ⁇ n-2, m is the total number of rows of the pixel driving circuit 21
  • n is the total number of columns of the pixel driving circuit 21 .
  • the pixel driving circuit 21 of the i-th row and the j-th column and the pixel driving circuit 21 of the i+1-th row and the j+2-th column are respectively connected to two adjacent data lines Data.
  • FIG. 13c is a positional relationship diagram of the tenth via hole and the second source-drain metal layer provided in the embodiment of the present disclosure. As shown in FIG. 13c, the tenth via hole V10 exposes at least a part of the second adapter CT2.
  • the layer where the first electrode 221 of the light-emitting device 22 is located is located on the side of the second source-drain metal layer SD2 away from the second substrate 20, and the planarization layer is disposed between the layer where the first electrode of the light-emitting device 22 is located and the second source-drain metal layer SD2.
  • between. 13d is a plan view of the first electrode layer and the second source-drain metal layer of the display substrate provided in the embodiment of the disclosure
  • FIG. 13e is the first electrode layer and the second source-drain metal layer of the display substrate provided in the embodiment of the disclosure
  • a schematic diagram of the connection of layers, as shown in FIG. 13d and FIG. 13e the first electrode layer includes the first electrodes 221 of the plurality of light emitting devices 22 .
  • the first electrode 221 is connected to the second transition piece CT2 through the tenth via V10 penetrating the planarization layer PLN, so as to be connected to the second electrode Td_2 of the driving transistor Td through the second transition piece CT2 and the first transition piece CT1.
  • the second adapter CT2 and the first adapter CT1 may not be provided, so that the first electrode 221 passes through the planarization layer PLN, the passivation layer PVX, the interlayer dielectric layer ILD, and the second gate insulating layer at the same time.
  • the via hole of GI2 and the first gate insulating layer GI1 is used to connect the driving transistor Td.
  • the arrangement of the second adapter CT2 and the first adapter CT1 can prevent the direct formation of deep via holes, thereby ensuring the reliability of the connection between the first electrode 221 and the driving transistor Td.
  • the orthographic projection of the first electrode 221 of the light-emitting device 22 on the second substrate 20 overlaps with the orthographic projection of the data line Data on the second substrate 20, so that when the resolution of the display substrate 2 is constant, The light-emitting area of the light-emitting device 22 is maximized.
  • a pixel defining layer may be provided on the side of the first electrode 221 away from the second substrate 20, and the pixel defining layer is provided with pixel openings corresponding to the first electrodes 221 one-to-one.
  • the hole injection layer of the light-emitting device 22, Film layers such as the hole transport layer, the light emitting layer, the electron transport layer, and the electron injection layer are all arranged in the pixel opening.
  • the orthographic projection of the pixel opening on the second substrate 20 may overlap with the orthographic projection of the data line Data on the second substrate 20 .
  • the region of the first electrode 221 exposed by the pixel opening can be used as the light-emitting region of the light-emitting device 22 .
  • the gap between the first poles 131 of the adjacent light-emitting devices 13 and the gap between the light-emitting regions of the adjacent light-emitting devices 22 are right.
  • FIG. 14 is a flowchart of a manufacturing method of a display device provided by an embodiment of the present disclosure. As shown in FIG. 14 , the manufacturing method includes:
  • the photoelectric detection circuit adopts the photoelectric detection circuit described in the above embodiments.
  • a sensing device driving structure of a plurality of photodetection circuits is formed on the first substrate, and the sensing device driving structure includes the first reset transistor T1, the second reset transistor T2, the data reading transistor T3, The first capacitor C1 and the second capacitor C2; after that, the photosensitive devices of a plurality of photodetection circuits are formed.
  • the pixel structures include a light-emitting device and a pixel driving circuit.
  • pixel driving circuits with a plurality of pixel structures are formed on the second substrate, and then light-emitting devices with a plurality of pixel structures are formed.
  • the specific structures of the pixel driving circuit and the light-emitting device refer to the above description.
  • the structures located in the same layer can be fabricated simultaneously.
  • the active layers of the transistors in the multiple pixel driving circuits are fabricated simultaneously.
  • the first electrode plates of the third capacitors in the plurality of pixel driving circuits are fabricated synchronously with the gate lines, the second electrode plates of the third capacitors in the plurality of pixel driving circuits are fabricated synchronously, and so on.
  • step S10 may be before step S20, or may be after step S20.
  • the display substrate and the photodetector substrate can be bonded together by an optical adhesive layer.
  • the method for fabricating the display device further includes: fabricating a lens layer, where the lens layer includes a plurality of lenses, and the lenses are used for condensing light.
  • step S30 may include: fixing the lens layer on the non-display side of the display substrate, and fixing the photodetection substrate on the side of the lens layer away from the display substrate.
  • an optical adhesive layer is used to bond the lens layer on the non-display side of the display substrate, and an optical adhesive layer is used to bond the photodetection substrate to the side of the lens layer away from the display substrate.

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Abstract

公开一种光电检测电路及其驱动方法、显示装置及其制作方法，所述光电检测电路包括：第一复位子电路、第二复位子电路、第一存储子电路、数据读取子电路和感光器件，数据读取子电路的第一端、第一存储子电路的第一端、感光器件的第一极、第一复位子电路的第一端连接于第一节点；感光器件的第二极连接公共电压线；数据读取子电路配置为，响应于扫描线的信号的控制，将第一节点的电压传输至数据读取线；第一复位子电路配置为，对第一节点的电压进行复位；第一存储子电路配置为，存储所述第一节点与公共电压线之间的电压；第二复位子电路配置为，响应于复位线的信号的控制，对扫描线上的电压进行复位。

Description

光电检测电路及其驱动方法、显示装置及其制作方法 技术领域
本公开涉及显示技术领域，具体涉及一种光电检测电路及其驱动方法、显示装置及其制作方法。
背景技术
OLED(Organic Light Emitting Diode有机电致发光二极管)是一种电流驱动型显示器件，因其具有自发光、快速响应、宽视角、以及可以制作在柔性衬底上等优点，被广泛应用于显示相关领域。
发明内容
本公开实施例提出了一种光电检测电路及其驱动方法、显示装置及其制作方法。
第一方面，本公开实施例提供一种光电检测电路，包括：第一复位子电路、第二复位子电路、第一存储子电路、数据读取子电路和感光器件，其中，所述数据读取子电路的第一端、所述第一存储子电路的第一端、所述感光器件的第一极、所述第一复位子电路的第一端连接于第一节点；所述感光器件的第二极连接公共电压线；
其中，所述感光器件配置为，根据感应到的光信号生成感应电信号；
所述数据读取子电路配置为，响应于扫描线的信号的控制，将所述第一节点的电压传输至数据读取线；
所述第一复位子电路配置为，响应于复位线的信号的控制，对所述第一节点的电压进行复位；
所述第一存储子电路配置为，存储所述第一节点与所述公共电压线之间的电压；
所述第二复位子电路配置为，响应于所述复位线的信号的控制， 对所述扫描线上的电压进行复位。
在一些实施例中，所述光电检测电路还包括第二存储子电路，所述第二存储子电路配置为，存储所述扫描线与所述公共电压线之间的电压。
在一些实施例中，所述第一复位子电路包括：第一复位晶体管，所述第一复位晶体管的栅极连接所述复位线，所述第一复位晶体管的第一极连接公共电压线，所述第一复位晶体管的第二极形成所述第一复位子电路的第一端；
所述数据读取子电路包括：数据读取晶体管，所述数据读取晶体管的栅极连接所述扫描线，所述数据读取晶体管的第一极连接所述数据读取线，所述数据读取晶体管的第二极形成为所述数据读取子电路的第一端。
在一些实施例中，所述数据读取线和所述扫描线位于绝缘间隔的不同层中，所述扫描线沿第一方向延伸，所述数据读取线沿第二方向延伸，所述第一方向与所述第二方向相交叉，
所述数据读取晶体管的栅极为所述扫描线的一部分，所述数据读取晶体管的第一极和第二极在第一基底上的正投影分别位于所述扫描线在所述第一基底上的正投影沿所述第二方向的两侧。
在一些实施例中，所述第一复位晶体管的第一极和第二极、所述数据读取晶体管的第一极和第二极均与所述数据读取线同层设置，
所述第一复位晶体管的第一极所在层与所述公共电压线所在层之间设置有第一绝缘层，所述第一绝缘层上设置有第一过孔，所述第一过孔暴露出所述公共电压线的一部分，所述第一复位晶体管的第一极通过所述第一过孔连接所述公共电压线。
在一些实施例中，所述第二复位子电路包括：第二复位晶体管，所述第二复位晶体管的栅极连接所述复位线，所述第二复位晶体管的 第一极与所述第一复位晶体管的第一极形成为一体结构，所述第二复位晶体管的第二极连接所述扫描线。
在一些实施例中，所述第一绝缘层上还设置有第二过孔，所述第二过孔暴露出所述扫描线的一部分，所述第二复位晶体管的第二极通过所述第二过孔连接所述扫描线。
在一些实施例中，所述第一存储子电路包括：第一电容，所述第一电容的第一极板与所述公共电压线形成为一体结构，所述第一电容的第二极板、所述数据读取晶体管的第二极、所述第一复位晶体管的第二极形成为一体结构。
在一些实施例中，所述感光器件位于所述第一电容的第二极板远离第一极板的一侧，所述感光器件的第一极所在层与所述第一电容的第二极板所在层之间设置有第二绝缘层，所述第二绝缘层上设置有第三过孔，所述第三过孔暴露出所述第一电容的第二极板的一部分，所述感光器件的第一极通过所述第三过孔与所述第一电容的第二极板连接，以形成所述第一节点；多个所述光电检测电路的感光器件的第二极连接为整层结构。
在一些实施例中，所述感光器件的第一极在第一基底上的正投影至少覆盖所述第一电容在所述第一基底上的正投影。
在一些实施例中，所述第二存储子电路包括第二电容，所述第二电容的第一极板为所述扫描线的一部分，所述第二电容的第二极板为所述第一复位晶体管的第一极的一部分。
第二方面，本公开实施例提供一种显示装置，包括：
显示基板，所述显示基板包括：第二基底和设置在所述第二基底上的多个像素结构，所述像素结构包括发光器件；
光电检测基板，所述光电检测基板包括：第一基底和设置在所述第一基底上的多个光电检测电路，所述光电检测电路采用上述的光电 检测电路；其中，所述显示基板包括相对的显示侧和非显示侧，所述光电检测基板位于所述显示基板的非显示侧，每个所述感光器件在所述第二基底上的正投影位于y个所述像素结构在所述第二基底上的正投影范围内，以接收y个所述发光器件的光线，1≤y≤100，且y为整数。
在一些实施例中，所述第二基底的材料为玻璃或聚酰亚胺。
在一些实施例中，所述公共电压线的延伸方向和所述复位线的延伸方向均与所述扫描线的延伸方向相同，且所述公共电压线和所述复位线均与所述扫描线同层设置，
所述扫描线位于所述公共电极线与所述复位线之间。
在一些实施例中，所述像素结构还包括像素驱动电路，所述像素驱动电路包括：驱动晶体管、数据写入晶体管和第三电容，
所述数据写入晶体管的栅极连接栅线，所述数据写入晶体管的第一极连接数据线，所述数据写入晶体管的第二极连接所述驱动晶体管的栅极，所述驱动晶体管的第一极连接第一电源线，所述驱动晶体管的第二极连接所述发光器件的第一电极，所述第三电容的两端分别连接所述驱动晶体管的栅极和第一极。
在一些实施例中，所述第三电容的第一极板为所述驱动晶体管的栅极的至少一部分，所述第三电容的第二极板位于所述第三电极的第一极板远离所述第二基底的一侧。
在一些实施例中，所述驱动晶体管的有源层、第一极和第二极同层设置，所述驱动晶体管的栅极所在层与有源层所在层之间设置有第一栅绝缘层，所述驱动晶体管的栅极所在层与所述第三电容的第二极板所在层之间设置有第二栅绝缘层，所述第一电源线位于所述第三电容的第二极板所在层远离所述第二基底的一侧，所述第一电源线所在层与所述第三电容的第二极板所在层之间设置有层间介质层，
所述第一电源线通过第四过孔与所述第三电容的第二极板连接，并通过第五过孔与所述驱动晶体管的第一极连接，其中，所述第四过孔贯穿所述层间介质层，并暴露出所述第三电容的第二极板的一部分；所述第五过孔同时贯穿所述层间介质层、所述第二栅绝缘层和所述第一栅绝缘层，并暴露出所述驱动晶体管的第一极的一部分。
在一些实施例中，所述数据写入晶体管的第二极和有源层均与所述驱动晶体管的有源层同层设置，
所述像素结构还包括桥接件，所述桥接件与所述第一电源线同层设置，所述桥接件的一端通过第六过孔与所述驱动晶体管的栅极连接，所述桥接件的另一端通过第七过孔与所述数据写入晶体管的第二极连接，
其中，所述第六过孔同时贯穿所述层间介质层和所述第二栅绝缘层，并暴露出所述驱动晶体管的栅极的一部分；所述第七过孔同时贯穿所述层间介质层、所述第二栅绝缘层和所述第一栅绝缘层，并暴露出所述数据写入晶体管的第二极的一部分。
在一些实施例中，所述数据线位于所述第一电源线所在层远离所述第二基底的一侧，所述数据线所在层与所述第一电源线所在层之间设置有钝化层，所述发光器件的第一电极位于所述数据线所在层远离所述第二基底的一侧，所述发光器件的第一电极所在层与所述数据线所在层之间设置有平坦化层；
所述像素结构还包括：
第一转接件，与所述桥接件同层设置，所述第一转接件通过第八过孔与所述驱动晶体管的第二极连接，所述第八过孔同时贯穿所述层间介质层、所述第二栅绝缘层和所述第一栅绝缘层，并暴露出所述驱动晶体管的第二极的一部分；
第二转接件，所述第二转接件与所述数据线同层设置，所述第二 转接件通过所述钝化层上的第九过孔与所述第一转接件连接，所述发光器件的第一电极通过贯穿所述平坦化层的第十过孔与所述第二转接件连接。
在一些实施例中，所述发光器件的第一电极在所述第二基底上的正投影与所述数据线在所述第二基底上的正投影存在交叠。
在一些实施例中，多个所述像素结构排成多行多列，同一列中的相邻两个所述像素驱动电路分别连接两条相邻的所述数据线；
同一行所述像素驱动电路连接同一条所述第一电源线。
在一些实施例中，第i行第j列所述像素驱动电路沿列方向移动后得到的虚拟结构与第i+1行第j+2列像素驱动电路呈镜像对称，其中，1≤i≤m-1，1≤j≤n-2，m为所述像素驱动电路的总行数，n为所述像素驱动电路的总列数。
在一些实施例中，所述发光器件还包括发光层，所述发光层位于所述发光器件的第一电极远离所述第二基底的一侧，所述像素结构还包括位于所述发光层与所述第二基底之间的通光部，所述通光部用于通光，以使所述发光层所发射的光线的一部分射向所述第二基底。
在一些实施例中，所述通光部包括第一通光孔，所述第一通光孔穿过所述像素驱动电路；或者，
所述通光部包括位于所述像素驱动电路中的通光狭缝。
在一些实施例中，所述第一电极为反射电极，所述通光部还包括穿过所述第一电极的第二通光孔。
在一些实施例中，所述显示装置还包括：
设置在所述显示基板与所述光电检测基板之间的透镜层，所述透镜层包括多个透镜，所述透镜用于对光线进行汇聚。
在一些实施例中，所述显示装置还包括：
补偿电路，与所述数据读取线连接，用于根据所述数据读取线上 的实际电压与理论电压的差异，确定所述发光器件的补偿参数；
显示驱动电路，与所述补偿电路和所述像素结构连接，用于根据所述发光器件的补偿参数以及所述发光器件的目标发光亮度，确定所述发光器件的驱动信号，并将所述驱动信号输出至所述像素结构。
第三方面，本公开实施例提供一种光电检测电路的驱动方法，所述光电检测电路采用上述实施例所述的光电检测电路，其中，所述驱动方法包括：
在复位阶段，向所述复位线加载有效电平信号、向所述扫描线加载无效电平信号，以使所述第一复位子电路对所述第一节点的电压进行复位、所述第二复位子电路对所述扫描线的电压进行复位；
在电荷累积阶段，向所述复位线和所述扫描线均加载无效电平信号，以使所述光电检测器件进行电荷累积；
在读取阶段，向所述扫描线加载有效电平信号，以使所述第一节点的电压传输至数据读取线；
在冗余阶段，向所述扫描线和所述复位线加载无效电平信号，以使所述数据读取子电路将所述第一节点与所述数据读取线断开。
第四方面，本公开实施例提供一种显示装置的制作方法，包括：
在第一基底上形成多个光电检测电路，以形成光电检测基板；其中，所述光电检测电路采用上述实施例中的光电检测电路；
在第二基底上形成多个像素结构，以形成显示基板；所述显示基板包括相对的显示侧和非显示侧，所述像素结构包括发光器件；
将所述显示基板与所述光电检测基板固定在一起，其中，所述光电检测基板位于所述显示基板的非显示侧，每个所述感光器件在所述第二基底上的正投影位于y个所述像素结构在所述第二基底上的正投影范围内，以接收y个所述发光器件的光线，1≤y≤100，且y为整数。
在一些实施例中，所述发光器件包括：第一电极、第二电极和位 于所述第一电极与所述第二电极之间的发光层，所述发光层位于所述发光器件的第一电极远离所述第二基底的一侧，所述像素结构还包括位于所述发光层与所述第二基底之间的通光部，所述通光部用于通光，以使所述发光层所发射的光线的一部分射向所述第二基底。
在一些实施例中，所述通光部包括第一通光孔，所述第一通光孔穿过所述像素驱动电路；或者，
所述通光部包括位于所述像素驱动电路中的通光狭缝。
在一些实施例中，所述第一电极为反射电极，所述通光部还包括穿过所述第一电极的第二通光孔。
在一些实施例中，所述制作方法还包括：制作透镜层，所述透镜层包括多个透镜，所述透镜用于对光线进行汇聚；
将所述显示基板与所述光电检测基板固定在一起，包括：
将所述透镜层固定在所述显示基板的非显示侧，将所述光电检测基板固定在所述透镜层远离所述显示基板的一侧。
附图说明
附图是用来提供对本公开的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本公开，但并不构成对本公开的限制。在附图中：
图1为本公开实施例中提供的一种光电检测电路的电路示意图。
图2为本公开实施例中提供的感光器件的结构示意图。
图3为本公开实施例中提供的另一种光电检测电路的电路示意图。
图4为图3所示的光电检测电路的一种工作时序图。
图5a为本公开实施例中提供的光电检测电路的半导体层的平面图。
图5b为本公开实施例中提供的光电检测电路的半导体层和第一金属层的平面图。
图5c为本公开实施例中提供的第一绝缘层上的过孔示意图。
图5d为沿图5c中A-A'线的剖视图。
图5e为本公开实施例中提供的光电检测电路的第二金属层的平面图。
图5f为本公开实施例中提供的光电检测电路的半导体层。
图5g为沿图5f中B-B'线的剖视图。
图5h为本公开实施例中提供的光电检测电路的半导体层、第一金属层、第二金属层和感光器件的第一极的示意图。
图5i为本公开实施例提供的多个光电检测电路中的平面图。
图6为本公开实施例中提供的光电检测电路的驱动方法流程图。
图7a为本公开实施例中提供的一种显示装置的结构示意图。
图7b为图7a中的光电检测电路检测光线的示意图。
图8a为本公开实施例中提供的另一种显示装置的结构示意图。
图8b为图8a中的光电检测电路检测光线的示意图。
图9a为本公开实施例中提供的显示装置的工作原理示意图。
图9b为电荷累积阶段时长一定的情况下感光器件产生的电信号强度与光线亮度的关系曲线。
图9c为通过时长调整后的电信号强度与光线亮度的关系曲线。
图10为本公开实施例中提供的光电检测电路的排布示意图。
图11为本公开实施例中提供的像素驱动电路的电路示意图。
图12a为本公开实施例中提供的显示基板的半导体层的平面图。
图12b为本公开实施例中提供的显示基板的第一栅金属层的平面图。
图12c为本公开实施例中提供的显示基板的半导体层和第一栅金属层的平面图。
图12d为本公开实施例中提供的显示基板的第二栅金属层的平面图。
图12e为本公开实施例中提供的显示基板的半导体层、第一栅金属层和第二栅金属层的平面图。
图12f为本公开实施例中提供的层间介质层上的过孔示意图。
图12g为沿图12f中C-C'线的剖视图。
图12h为本公开实施例中提供的第一源漏金属层的平面图。
图12i为本公开实施例中提供的显示基板的半导体层、第一栅金属层、第二栅金属层和第一源漏金属层的平面图。
图12j为本公开实施例中提供的钝化层上的过孔示意图。
图12k为本公开实施例中提供的显示基板的第二源漏金属层的平面图。
图13a为本公开实施例中提供的显示基板的半导体层、第一栅金属层、第二栅金属层、第一源漏金属层和第二源漏金属层的平面图。
图13b为沿图13a中D-D'线的剖视图。
图13c为本公开实施例中提供的第十过孔与第二源漏金属层的位置关系图。
图13d为本公开实施例中提供的显示基板的第一电极层与第二源漏金属层的平面图。
图13e为本公开实施例中提供的显示基板的第一电极层与第二源漏金属层的连接示意图。
图14为本公开实施例提供的一种显示装置的制作方法流程图。
具体实施方式
以下结合附图对本公开的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本公开，并不用于限制本公开。
为使本公开的实施例的目的、技术方案和优点更加清楚，下面将结合本公开的实施例的附图，对本公开的实施例的技术方案进行清楚、 完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。由于采用的晶体管的源极和漏极是对称的，所以其源极、漏极是没有区别的。为区分晶体管的源极和漏极，将其中一极称为第一极，另一极称为第二极。
另外，晶体管可以划分为N型晶体管和P型晶体管，本公开中的各晶体管可分别独立选自N型晶体管或P型晶体管；在下述实施例中将以显示驱动电路中的各晶体管均为N型晶体管为例进行示例性描述，此时显示驱动电路中的晶体管可采用相同的制备工艺得以同时制备。相应地，有效电平信号为高电平信号，无效电平信号为低电平信号。
图1为本公开实施例中提供的一种光电检测电路的电路示意图，如图1所示，光电检测电路包括：第一复位子电路11、第二复位子电路12、第一存储子电路14、数据读取子电路16和感光器件13。其中，数据读取子电路16的第一端、第一存储子电路14的第一端、感光器件13的第一极、第一复位子电路11的第一端连接于第一节点N1；感 光器件13的第二极连接公共电压线。
感光器件13配置为根据感应到的光信号生成感应电信号。图2为本公开实施例中提供的感光器件的结构示意图，如图2所示，感光器件13可以采用PIN光电二极管，其具体包括：层叠设置的第一极131、P型半导体层133、本征层134、N型半导体层135和第二极132。
数据读取子电路16还与扫描线Scan和数据读取线DataRead连接，数据读取线DataRead配置为，响应于扫描线Scan的信号的控制，将第一节点N1的电压传输至数据读取线DataRead。
第一复位子电路11还与复位线Reset和公共电压线Vcom连接，第一复位子电路11配置为，响应于复位线Reset的信号的控制，将公共电压线Vcom的参考信号传输至第一节点N1，从而对第一节点N1的电压进行复位。
第一存储子电路14连接在第一节点N1与公共电压线Vcom之间，第一存储子电路14配置为，存储第一节点N1与公共电压线Vcom之间的电压。
第二复位子电路12与复位线Reset、扫描线Scan和公共电压线Vcom连接，第二复位子电路12配置为，响应于复位线Reset的信号的控制，将公共电压线Vcom上的参考信号传输至扫描线Scan，从而对扫描线Scan上的电压进行复位。
本公开实施例的光电检测电路的工作阶段可以包括：复位阶段、电荷累积阶段和数据读取阶段，在复位阶段，通过向复位线Reset加载有效电平信号，以使第一复位子电路11对第一节点N1的电压进行复位，同时第二复位子电路12对扫描线Scan上的电压进行复位；在电荷累积阶段，感光器件13根据其接收到的光信号进行电荷累积；在读取阶段，通过向扫描线Scan加载有效电平信号，以使读取子电路将第一节点N1的电压传输至数据读取线DataRead，从而使外部的处理 电路可以根据数据读取线DataRead读取到的电压确定感光器件13接收到的光强。
本公开实施例中的光电检测电路可以应用于OLED显示装置中，这种情况下，可以利用感光器件13来接收OLED显示装置中发光器件发出的至少一部分光线，从而使得外部的补偿电路可以根据数据读取线DataRead读取到的实际电压与理论电压的差异，确定发光器件的补偿参数；进而使驱动电路可以根据发光器件的补偿参数以及发光器件的目标发光亮度，确定发光器件的驱动信号，并将驱动信号输出至像素结构，以使发光器件能够达到目标发光亮度，从而使不同发光器件的发光亮度一致。
在一些实施例中，如图1所示，光电检测电路还包括：第二存储子电路15，第二存储子电路15连接在扫描线Scan与公共电压线Vcom之间，配置为存储扫描线Scan与公共电压线Vcom之间的电压。在光电检测电路的工作过程中，在对扫描线Scan上的电压进行复位后，第二存储子电路15可以保持扫描线Scan上电压的稳定性，防止扫描线Scan上的电压在电荷累积阶段影响数据读取子电路16的状态，从而保证电压输出的稳定性。
图3为本公开实施例中提供的另一种光电检测电路的电路示意图，如图3所示，该光电检测电路为图1所示的光电检测电路的一种具体化实施方案。
如图3所示，在一些实施例中，第一复位子电路11包括：第一复位晶体管T1，第一复位晶体管T1的栅极连接复位线Reset，第一复位晶体管T1的第一极连接公共电压线Vcom，第一复位晶体管T1的第二极形成第一复位子电路11的第一端，即，第一复位晶体管T1的第二极连接第一节点N1。
数据读取子电路16包括：数据读取晶体管T3，数据读取晶体管 T3的栅极连接扫描线Scan，数据读取晶体管T3的第一极连接数据读取线DataRead，数据读取晶体管T3的第二极形成为数据读取子电路16的第一端，即，数据读取晶体管T3的第二极连接第一节点N1。
在一些实施例中，第二复位子电路12包括：第二复位晶体管T2，第二复位晶体管T2的栅极连接复位线Reset，第二复位晶体管T2的第一极连接公共电压线Vcom，第二复位晶体管T2的第二极连接扫描线Scan。
在一些实施例中，第一存储子电路14包括：第一电容C1，第一电容C1连接公共电压线Vcom和第一节点N1。第二存储子电路15包括：第二电容C2，第二电容C2连接在扫描线Scan与公共电压线Vcom之间。
图4为图3所示的光电检测电路的一种工作时序图，下面结合附图对图3所示的光电检测电路的工作过程进行介绍。如图4所示，光电检测电路的工作过程包括复位阶段t1、电荷累积阶段t2、扫描阶段t3和冗余阶段t4。其中，公共电压线Vcom的电压为低电平电压。
在复位阶段t1，复位线Reset加载有效电平信号，扫描线Scan加载无效电平信号。此时，第一复位晶体管T1和第二复位晶体管T2均处于导通状态，数据写入晶体管处于关断状态。第一节点N1接收到公共电压线Vcom的电压，扫描线Scan与公共电压线Vcom导通，从而保持低电平电压。
在电荷累积阶段t2，复位线Reset和扫描线Scan加载无效电平信号，此时，第一复位晶体管T1、第二复位晶体管T2和数据读取晶体管T3均关断。在第二电容C2的稳压作用下，扫描线Scan上的电压保持与复位阶段相同，从而保证数据读取晶体管T3处于关断状态。随着感光器件13的光电转换作用，第一节点N1的电压逐渐升高。
在读取阶段t3，复位线Reset加载无效电平信号，扫描线Scan加 载有效电平信号，此时，第一复位晶体管T1和第二复位晶体管T2均保持关断状态，数据读取晶体管T3处于导通状态，以将第一节点N1的电压传输至数据读取线DataRead，从而使外部的处理电路读取到第一节点N1的电压，进而根据第一节点N1的电压确定感光器件13接收到的光强。
在冗余阶段t4，向扫描线Scan和复位线Reset加载无效电平信号，以使第一复位晶体管T1、第二复位晶体管T2、数据读取晶体管T3均保持关断状态，第一节点N1与数据读取线DataRead断开。
其中，当电荷累积时间相同时，感光器件13产生的电信号的强度与接收到的光强度正相关，因此，可以根据实际需要来设置电荷累积阶段的时长，以防止发光器件的亮度较低时检测到的信号强度过小，或发光器件亮度较高时，检测到的信号出现饱和。由于显示基板显示每帧图像的时长是一定的，因此，感光器件13的工作周期的时长(即，复位阶段t1、电荷累积阶段t2、扫描阶段t3和冗余阶段t4的总时长)是一定的，那么，当需要增加电荷累积阶段t2的时长时，则可以减少冗余阶段t4的时长；当需要减少电荷累积阶段t2的时长时，则可以增加冗余阶段t4的时长，从而使感光器件13的工作周期的时长保持不变。
在本公开实施例中，数据读取线DataRead、扫描线Scan、公共电压线Vcom、光电检测电路中的各晶体管、电容和感光器件13均设置在第一基底上。可选地，数据读取线DataRead和扫描线Scan位于绝缘间隔的不同层中，扫描线Scan沿第一方向延伸，数据读取线DataRead沿第二方向延伸，第一方向与第二方向相交叉。
在一些实施例中，光电检测电路中的各晶体管的有源层同层设置，复位线Reset、扫描线Scan和公共电压线Vcom同层设置，复位线Reset与各晶体管的第一极、第二极同层设置。需要说明的是，“同层设置” 是指两个结构是由同一个材料层经过构图工艺形成的，故二者在在层叠关系上是处于同一个层之中的；但这并不表示二者与第一基底之间的距离必定相同。例如，各晶体管的有源层位于半导体层中，复位线Reset、扫描线Scan和公共电压线Vcom位于第一金属层中，数据读取线DataRead与各晶体管的第一极和第二极位于第二金属层中。下面结合附图对本公开实施例中光电检测电路的各层结构以及层间的连接关系进行介绍。
图5a为本公开实施例中提供的光电检测电路的半导体层的平面图，可选地，半导体层poly1的制作材料可以为多晶硅或者金属氧化物，本公开实施例对此不作具体限定。如图5a所示，半导体层poly1包括：第一复位晶体管T1的有源层T1_p、第二复位晶体管T2的有源层T2_p和数据读取晶体管T3的有源层T3_p。其中，第一复位晶体管T1的有源层T1_p和第二复位晶体管T2的有源层T2_p可以连接为一体。
图5b为本公开实施例中提供的光电检测电路的半导体层和第一金属层的平面图，可选地，第一金属层M1的制作材料可以为银、铝、钼或铜等金属材料，本公开实施例对此不作具体限定。如图5b所示，第一金属层M1位于半导体层poly1远离第一基底的一侧，第一金属层M1与半导体层poly1之间被绝缘层间隔开。第一金属层M1包括：公共电压线Vcom、扫描线Scan、复位线Reset、各晶体管的栅极和第一电容C1的第一极板C1_1。
例如，公共电压线Vcom、扫描线Scan和复位线Reset均沿第一方向延伸，扫描线Scan位于公共电压线Vcom与复位线Reset之间。数据读取晶体管T3的栅极为扫描线Scan的一部分，第一复位晶体管T1的栅极、第二复位晶体管T2的栅极与复位线Reset形成为一体结构，即第一复位晶体管T1的栅极、第二复位晶体管T2的栅极与复位线Reset形成为一个整体，或者，第一复位晶体管T1的栅极、第二复位 晶体管T2的栅极与复位线Reset分别为三个导电结构，该三个导电结构电连接。第一电容C1的第一极板与公共电压线Vcom形成为一体结构，即，第一电容C1的第一极板与公共电压线Vcom形成为一个整体，或者，第一电容C1的第一极板与公共电压线Vcom分别为两个导电结构，该两个导电结构电连接。
图5c为本公开实施例中提供的第一绝缘层上的过孔示意图，图5d为沿图5c中A-A'线的剖视图，结合图5c和图5d所示，第一金属层M1与半导体层poly1之间设置有第三绝缘层Ins3，第一金属层M1远离第一基底17的一侧设置有第一绝缘层Ins1。可选地，第一绝缘层Ins1和第三绝缘层Ins3均可以采用氮化硅层、氧化硅层、氮氧化硅层中的单层或多层。第一绝缘层Ins1上设置有多个过孔。第一绝缘层Ins1上的过孔包括第一过孔V1、第二过孔V2、源极过孔V_s和漏极过孔V_d，第一过孔V1暴露出公共电压线Vcom的一部分，第二过孔V2暴露出扫描线Scan的一部分。各晶体管的有源层均对应一个源极过孔V_s和一个漏极过孔V_d。
图5e为本公开实施例中提供的光电检测电路的第二金属层的平面图，图5f为本公开实施例中提供的光电检测电路的半导体层、第一金属层和第二金属层的平面图。可选地，第二金属层M2的制作材料可以为银、铝、钼或铜等金属材料，本公开实施例对此不作具体限定。如图5c至图5f所示，第二金属层M2位于第一绝缘层Ins1远离半导体层poly1的一侧，第二金属层M2包括：数据读取线DataRead、第一电容C1的第二极板C1_2、各晶体管的第一极和第二极。各晶体管的第一极均通过相应的源极过孔V_s连接有源层，各晶体管的第二极通过相应的漏极过孔V_d连接有源层。数据读取晶体管T3的第一极T3_1和第二极T3_2在第一基底上的正投影分别位于扫描线Scan在第一基底上的正投影沿第二方向的两侧。第一复位晶体管T1的第一极 T1_1通过第一过孔V1连接公共电压线Vcom。第二复位晶体管T2的第二极T2_2通过第二过孔V2连接扫描线Scan。可选地，数据读取晶体管T3的第一极T3_1与数据读取线DataRead形成为一体结构，第一电容C1的第二极板C1_2、第一复位晶体管T1的第二极T1_2、数据读取晶体管T3的第二极T3_2形成为一体结构，即，数据读取晶体管T3的第一极T3_1与数据读取线DataRead形成为一个整体，或者，数据读取晶体管T3的第一极T3_1与数据读取线DataRead分别为两个导电结构，该两个导电结构电连接；第一电容C1的第二极板C1_2、第一复位晶体管T1的第二极T1_2、数据读取晶体管T3的第二极T3_2形成为一个整体，或者，第一电容C1的第二极板C1_2、第一复位晶体管T1的第二极T1_2、数据读取晶体管T3的第二极T3_2分别为三个导电结构，该三个导电结构电连接。第一复位晶体管T1的第一极T1_1与第二复位晶体管T2的第一极T2_1形成为一体结构，这里，第一复位晶体管T1的第一极T1_1与第二复位晶体管T2的第一极T2_1形成为一个整体的电极块，该电极块可以作为第一复位晶体管T1的第一极T1_1，也可以作为第二复位晶体管T2的第一极T2_1；或者，第一复位晶体管T1的第一极T1_1与第二复位晶体管T2的第一极T2_1分别为两个电极块，该两个电极块电连接。
另外，如图5f所示，第一复位晶体管T1的第一极T1_1(也即第二复位晶体管T2的第一极T2_1)与扫描线Scan绝缘交叉设置，交叉部分形成第二电容C2。即，第二电容C2的第一极板为扫描线Scan的一部分，第二电容C2的第二极板为第一复位晶体管T1的第一极T1_1的一部分。
图5g为沿图5f中B-B'线的剖视图，如图5g所示，第一电容C1的第二极板C1_2所在层远离第一基底17的一侧设置有第二绝缘层Ins2，可选地，第二绝缘层Ins2可以采用氮化硅层、氧化硅层、氮氧 化硅层中的单层或多层。第二绝缘层Ins2上设置有第三过孔V3。如图5f和图5g所示，第三过孔V3暴露出第一电容C1的第二极板C1_2的一部分。
在一些实施例中，感光器件13设置在第二绝缘层Ins2远离第一基底17的一侧，图5h为本公开实施例中提供的光电检测电路的半导体层、第一金属层、第二金属层和感光器件的第一极的示意图，结合图5f至图5h所示，感光器件13的第一极通过第三过孔V3与第一电容C1的第二极板C1_2连接，以形成图3中的第一节点N1。
其中，感光器件13的第一极131在第一基底上的正投影与数据读取线DataRead在第一基底上的正投影无交叠。感光器件13的第二极132在第一基底上的正投影超出感光器件13的第一极131在第一基底上的正投影，以防止第二极132在连接公共电压线Vcom时与第一极131发生短路。感光器件13的第二极132采用透明导电材料(例如，氧化铟锡等)制作的透明电极，从而有利于感光器件13接收发光器件所发射的光线。其中，本公开实施例中的“透明”可以为，透光率在80％以上。
图5i为本公开实施例提供的多个光电检测电路中的平面图，为了示意清楚，在图5i中省去了感光器件13的P型半导体层133、本征层134、N型半导体层135，需要说明的是，感光器件13的P型半导体层133、本征层134、N型半导体层135可以与感光器件13的第一极131通过同一次光刻构图工艺制成，因此，感光器件13的P型半导体层133、本征层134、N型半导体层135与感光器件13的第一极131在第一基底上的正投影范围可以相同。如图5i所示，第一基底上可以设置多个光电检测电路，多个光电检测电路可以呈阵列排布，同一列的光电检测电路可以连接同一条数据读取线DataRead，同一行光电检测电路所连接的扫描线Scan为同一条，同一行光电检测电路所连接的 公共电压线Vcom为同一条，同一行光电检测电路所连接的复位线Reset为同一条。多个光电检测电路中感光器件13的第二极132可以连接为整层结构。因此，对于其中一个感光器件13而言，感光器件13的第二极132在第一基底上的正投影超出第一极131在第一基底上的正投影。其中，第二极132超出第一极131的部分通过贯穿第一绝缘层和第二绝缘层的过孔与公共电压线Vcom连接。例如，在第一基底的边缘区域，可以设置公共电压总线，该公共电压总线与每条公共电压线Vcom连接，第二极132通过贯穿第一绝缘层和第二绝缘层的过孔与公共电压总线连接。
其中，感光器件13的第一极131在第一基底上的正投影至少覆盖第一电容C1在第一基底上的正投影。在一些示例中，如图5h和图5i所示，感光器件13的第一极131在第一基底上的正投影覆盖其所在的光电检测电路中的第一电容C1在第一基底上的正投影，并与其所在的光电检测电路中的数据读取晶体管T3在第一基底上的正投影存在交叠，同时与上一行光电检测电路中的数据读取晶体管T3、第一复位晶体管T1、第二复位晶体管T2在第一基底上的正投影均存在交叠。当然，在另一些实施例中，还可以使感光器件13的第一极131在第一基底上的正投影覆盖其所在的光电检测电路中的第一电容C1、数据读取晶体管T3、第一复位晶体管T1和第二复位晶体管T2在第一基底上的正投影。
本公开实施例还提供一种上述光电检测电路的驱动方法，图6为本公开实施例中提供的光电检测电路的驱动方法流程图，如图6所示，该驱动方法包括：
S1、在复位阶段，向复位线加载有效电平信号、向扫描线加载无效电平信号，以使第一复位子电路对第一节点的电压进行复位、第二复位子电路对扫描线的电压进行复位。
S2、在电荷累积阶段，向复位线和扫描线均加载无效电平信号，以使光电检测器件进行电荷累积。
S3、在读取阶段，向扫描线加载有效电平信号，以使第一节点的电压传输至数据读取线。
S4、在冗余阶段，向扫描线和复位线加载无效电平信号，以使数据读取子电路将第一节点与数据读取线断开。
光电检测电路的具体工作过程已在上文进行描述，这里不再赘述。
本公开实施例还提供一种显示装置，图7a为本公开实施例中提供的一种显示装置的结构示意图，如图7a所示，包括：显示基板2、光电检测基板1。显示基板2包括相对的显示侧和非显示侧。光电检测基板1包括：第一基底17和设置在第一基底17上的多个光电检测电路10，光电检测电路10采用上述任一实施例中光电检测电路10。其中，光电检测基板1位于显示基板2的非显示侧，光电检测电路10的感光器件与至少一个发光器件22正对，以接收发光器件22的光线。
显示基板2包括：第二基底20和设置在所述第二基底20上的多个像素结构，所述像素结构包括发光器件22和像素驱动电路21。其中，本公开实施例中的发光器件22可以是LED(Light Emitting Diode，发光二极管)或OLED(Organic Light Emitting Diode，有机发光二极管)在内的电流驱动的发光器件22，在本公开实施例中是以OLED为例进行的说明。需要说明的是，显示基板2的显示侧为，显示基板2进行显示时观看者所在的一侧；显示基板2的非显示侧为与显示侧相对的一侧。
在一些实施例中，发光器件22所发射的部分光线朝向显示侧射出，另一部分光线被导入显示基板2的非显示侧。图7b为图7a中的光电检测电路检测光线的示意图，图7b中箭头表示光线，如图7b所示，发光器件22设置在像素驱动电路21远离第二基底20的一侧，发光器 件22包括：沿远离第二基底20的方向依次设置的：第一电极221、空穴注入层222、空穴传输层223、发光层224、电子传输层225、电子注入层226、第二电极227。可选地，第一电极221为阳极，第二电极227为阴极。
为了将发光器件22的一部分光线导入第二基底20远离发光器件22的一侧，在本公开实施例中，像素结构还包括位于发光层224与第二基底20之间的通光部，通光部用于通光，以使发光层224发射的光线的一部分射向第二基底20，进而透过第二基底20照射至非显示侧。光电检测电路10包括感光器件13和感光器件驱动结构13t，感光器件驱动结构13t包括上述实施例中的第一复位晶体管T1、第二复位晶体管T2、数据读取晶体管T3、第一电容C1和第二电容C2.。感光器件13设置在感光器件驱动结构13t与第二基底20之间，以接收发光器件22所发射的一部分光线。
在本公开实施例中，像素驱动电路21包括半导体层、第一栅金属层、第二栅金属层、第一源漏金属层、第二源漏金属层等导电膜层，导电膜层之间通过绝缘层(例如，第一栅绝缘层、第二栅绝缘层等)间隔开。每个导电膜层均包括多个不透光的导电图形，例如，第一栅金属层包括栅线、多个晶体管的栅极等，半导体层包括多个晶体管的有源层，具体将在下文进行描述。在一些示例中，通光部可以包括第一通光孔Vt1，该第一通光孔Vt1穿过像素驱动电路21。例如，第一通光孔Vt1穿过绝缘层，且第一通光孔Vt1在第二基底20上的正投影与像素驱动电路21中的导电图形在第二基底20上的正投影无交叠。
在另一些示例中，通光部包括位于像素驱动电路21中的通光狭缝。例如，导电膜层之间的绝缘层采用透明材料制成，通光狭缝即为导电图形之间的间隙。这种情况下，可以不再设置第一通光孔Vt1，发光器件22所发射的光线可以通过导电图形之间的间隙，并直接透过绝缘 层，从而照射至感光器件13。
需要说明的是，本公开实施例中的发光器件22的第一电极221可以采用反射电极，此时，通光部还包括穿过第一电极221的第二通光孔Vt2，第二通光孔Vt2在第二基底20上的正投影与第一通光孔Vt1(或通光狭缝)在第二基底20上的正投影存在交叠。当然，第一电极221也可以采用透明电极，此时，第一电极221上可以设置第二通光孔Vt2，也可以不设置第二通光孔Vt2。
结合图3和图7a所示，在一些实施例中，每个感光器件13可以与一个发光器件22相对，也可以与多个感光器件13相对。当感光器件13与一个发光器件22相对时，感光器件13接收到一个发光器件22的光线；当感光器件与多个发光器件22相对时，可以控制该多个发光器件22在不同的发光阶段发光，以保证感光器件13在不同的发光阶段接收到不同发光器件22所发射的光线。在一些实施例中，每个感光器件13在第二基底20上的正投影位于y个像素结构在第二基底20上的正投影范围内。其中，1≤y≤100，且y为整数，从而可以在保证检测精度的同时，防止制作工艺难度过大。其中，每个感光器件13在第二基底20上的正投影位于y个像素结构在第二基底20上的正投影范围内可以为：每个感光器件13与y个像素结构正对设置，以接收y个发光器件22所发射的光线。其中，每个像素结构在第二基底20上的正投影面积可以为70平方微米，当然，显示基板2也可以适用于更高分辨率的产品，此时，每个像素结构在第二基底20上的正投影面积小于70平方微米。当单个像素结构在第二基底20上的正投影面积变化时，每个感光器件13在第二基底20上的正投影面积也相应变化，但每个感光器件13在第二基底20上的正投影与像素结构在第二基底20上的正投影的比例关系固定即可，例如，每个感光器件13在第二基底20上的正投影位于4*4(即，16)个像素结构在第二基底 20上的正投影范围内，且每个感光器件13与4*4个像素结构正对。
在一些实施例中，显示基板2与光电检测基板之间还设置有光学胶层3，从而利用光学胶层3将显示基板2与光电检测基板1粘结。
图8a为本公开实施例中提供的另一种显示装置的结构示意图，图8b为图8a中的光电检测电路检测光线的示意图，图8b中的箭头表示光线。如图8a所示，显示装置还包括：透镜层，透镜层设置在显示基板2与光电检测基板之间。透镜层包括多个透镜4。透镜层与显示基板2之间、透镜层与光电检测基板之间均设置有光学胶层3。透镜层的多个透镜4排成多行多列，每个透镜4可以与一个或多个发光器件22正对。透镜4可以为凸透镜，用于对光线进行汇聚。和图7b类似地，在图8b中，发光器件22的一部分光线经过通光部照射至感光器件13，与图7b不同的是，在图8b中，光线在照射至感光器件13之前，还经过透镜4，从而进行汇聚。
在本公开实施例中，第二基底20可以采用玻璃基底，例如，玻璃基底的厚度在100μm～500μm之间，也可以采用厚度较薄的柔性基底，例如，柔性基底采用聚酰亚胺(PI)制成，厚度在3μm～20μm之间。当第二基底20采用厚度较大的玻璃基底时，发光器件22照射至非显示侧的光线会发生严重的发散，透镜4的汇聚作用可以减小发散角度，以提高感光器件13生成的电信号的准确性。当第二基底20采用厚度较小的柔性基底时，发光器件22照射至非显示侧的光线的发散程度较小，因此，可以设置透镜层，也可以不设置透镜层。
图9a为本公开实施例中提供的显示装置的工作原理示意图，如图9a所示，显示装置还包括补偿电路4和显示驱动电路5，补偿电路4与上述数据读取线DataRead连接，用于根据所述数据读取线DataRead上的实际电压与理论电压的差异，确定发光器件22的补偿参数。其中，补偿电路4可以包括信号读取子电路和信号处理子电路，信号读取子 电路可以读取数据读取线DataRead上的电压，信号处理子电路用于对信号读取子电路输出的电压信号进行模数转换等信号处理。显示驱动电路5与补偿电路4和像素结构的像素驱动电路21连接，用于根据发光器件22的补偿参数以及发光器件22的目标发光亮度，确定发光器件22的驱动信号，并将驱动信号输出至所述像素结构的像素驱动电路21，从而使发光器件22在像素驱动电路21的驱动下发光时，能够达到所述目标亮度。
其中，实际电压可以为显示基板在显示测试图像时，数据读取线DataRead实际所读取到的电压信号；理论电压为显示基板在显示测试图像且发光器件22发射的光线达到理想亮度时，数据读取线DataRead理论上应该读取到的电压信号。可以理解的是，由于发光器件22的老化以及像素驱动电路21中晶体管的阈值漂移，数据读取线DataRead上的实际电压与理论电压可能会出现差异。显示基板在后续显示目标图像时，显示驱动电路5可以根据待显示的目标图像，确定发光器件22的目标亮度，从而确定目标亮度对应的初始驱动信号，并根据发光器件22的补偿参数对初始驱动信号进行调整，得到补偿后的驱动信号，之后，将该驱动信号提供给像素驱动电路21，以驱动发光器件22发光。
图9b为电荷累积阶段时长一定的情况下感光器件产生的电信号强度与光线亮度的关系曲线，图9c为通过时长调整后的电信号强度与光线亮度的关系曲线。根据图9b可以看出，当光电检测电路10的电荷累积阶段的时长为一定值时，感光器件13检测到的光强越大，则生成的电信号的强度越大；而当电信号的强度低于阈值V0时，可能会导致补偿电路4无法识别出此时的电信号。而当光线亮度一定的情况下，通过改变电荷累积阶段的时长，可以改变感光器件所产生的电信号强度，因此，在本公开实施例中，可以对每个光电检测电路10的电荷累 积阶段的时长进行调整，使得发光器件22的发光亮度较高时，减小光电检测电路10的电荷累积阶段的时长；发光器件22的发光亮度较低时，增大光电检测电路10的电荷累积阶段的时长，从而实现各发光亮度下，感光器件13生成的电信号强度一致，且该电信号的强度高于V0，如图9c所示。
例如，当发光器件22的实际亮度为L1、且光电检测电路10的电荷累积阶段的时长为time1时，数据读取线DataRead应当读取到的电压为Vd；当发光器件22的实际亮度为L2、且光电感测电路的电荷累积时长为time2时，数据读取线DataRead应当读取到的电压为Vd；此时，当显示基板在显示某一帧测试画面，且该测试画面中需要发光器件22达到亮度L1时，则控制光电检测电路10的电荷累积阶段的时长为time1，此时，若数据读取线DataRead读取到的电压Vd'与Vd有所变差，则表示发光器件22并没有达到理想的亮度L1，因此，可以根据Vd'与Vd之间的差值，确定发光器件22的补偿值，从而在显示基板后续显示目标图像时，根据发光器件22的补偿值对提供给发光器件22的驱动电压进行补偿。
在本公开实施例中，发光器件22可以呈阵列排布，相应地，光电检测基板1的多个光电检测电路10也呈阵列排布。图10为本公开实施例中提供的光电检测电路的排布示意图，如图10所示，同一列的光电检测电路10可以连接同一条数据读取线DataRead，同一行光电检测电路10所连接的扫描线Scan为同一条，同一行光电检测电路10所连接的公共电压线Vcom为同一条，同一行光电检测电路10所连接的复位线Reset为同一条。多个感光器件13的第二极可以连接为一体结构，即，多个感光器件13的第二极可以连接为一个整体结构，且可以在第一基底17的边缘区域通过过孔与公共电压线Vcom连接。
图11为本公开实施例中提供的像素驱动电路的电路示意图，如图 11所示，像素驱动电路21可以采用简单的2T1C(即两个晶体管和一个电容)的结构，以简化显示基板2的结构，并有利于提高显示装置的分辨率。具体地，像素驱动电路21包括：驱动晶体管Td、数据写入晶体管T1’、第三电容C3。数据写入晶体管T1’的栅极连接栅线Gate，数据写入晶体管T1’的第一极连接数据线Data，数据写入晶体管T1’的第二极连接驱动晶体管Td的栅极，驱动晶体管Td的第一极连接第一电源线VDD，驱动晶体管Td的第二极连接发光器件22的第一电极，发光器件22的第二电极连接第二电源线VSS。第三电容C3的两端分别连接驱动晶体管Td的栅极和第一极。其中，第一电源线VDD可以为高电平电源线，第二电源线VSS可以为低电平电源线。
在数据写入阶段，栅线Gate加载有效电平信号。此时，数据写入晶体管T1’导通，驱动晶体管Td关断，从而将数据线Data上的数据电压写入第三电容C3中。在发光阶段，栅线Gate加载无效电平信号，此时，由于第三电容C3存储有数据电压，因此，驱动晶体管Td开启，并根据其栅极与第一极之间的电压向发光器件22输出驱动电流。
需要说明的是，像素驱动电路21也可以采用其他结构的电路(例如，7T1C，9T1C等)，在此不做限定。
在本公开实施例中，像素驱动电路21的各晶体管的有源层被布置在半导体层中，各晶体管的栅极被布置在第一栅金属层中，第三电容C3的第二极板被布置在第二栅金属层中，第一电源线VDD被布置在第一源漏金属层中，数据线Data被布置在第二源漏金属层中，下面结合附图对本公开实施例中的像素结构进行介绍。
图12a为本公开实施例中提供的显示基板的半导体层的平面图，图12a中示出了两行三列像素结构的半导体层poly2。如图12a所示，像素结构的半导体层poly2包括各晶体管的有源层。可选地，半导体层poly2的制作材料可以为多晶硅或者金属氧化物，本公开实施例对 此不作具体限定。
可选地，驱动晶体管Td的第一极Td_1和第二极Td_2与有源层Td_p同层设置，数据写入晶体管T1’的第二极T1’_2和有源层T1’_p也同层设置，均位于半导体层poly2中。驱动晶体管Td的第一极Td_1和第二极Td_2、数据写入晶体管T1’的第二极T1’_2可以通过对半导体层poly2进行离子掺杂后形成。
图12b为本公开实施例中提供的显示基板的第一栅金属层的平面图，图12c为本公开实施例中提供的显示基板的半导体层和第一栅金属层的平面图，如图12b和图12c所示，第一栅金属层G1包括数据写入晶体管T1’的栅极T1’_g和驱动晶体管Td的栅极Td_g。其中，第三电容C3的第一极板C3_1为驱动晶体管Td的栅极Td_g的至少一部分，以简化像素驱动电路21的整体结构，并简化制作工艺。
半导体层poly2与第一栅金属层G1之间设置有第一栅绝缘层，第一栅金属层G1位于第一栅绝缘层远离半导体层poly2的一侧。可选地，第一栅绝缘层可以采用氮化硅层、氧化硅层、氮氧化硅层中的单层或多层。
图12d为本公开实施例中提供的显示基板的第二栅金属层的平面图，图12e为本公开实施例中提供的显示基板的半导体层、第一栅金属层和第二栅金属层的平面图，如图12d和图12e所示，第二栅金属层G2位于第一栅金属层G1远离第二基底20的一侧，第二栅金属层G2与第一栅金属层G1之间设置有第二栅绝缘层。每个第三电容C3的第二极板C3_2位于第二栅金属层G2。可选地，第一栅金属层G1和第二栅金属层G2的制作材料可以为银、铝、钼或铜等金属材料，本公开实施例对此不作具体限定。
第二栅金属层G2远离第二基底20的一侧设置有层间介质层。可选地，层间介质层可以采用氮化硅层、氧化硅层、氮氧化硅层中的单 层或多层。
图12f为本公开实施例中提供的层间介质层上的过孔示意图，图12g为沿图12f中C-C'线的剖视图，结合图12f和图12g所示，层间介质层ILD上设置有第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7、第八过孔V8和源极过孔V_s1，源极过孔V_s1用于连接数据写入晶体管T1’的第二极T1’_2与数据线。其中，第四过孔V4贯穿层间介质层ILD，并暴露出第三电容C3的第二极板C3_2的一部分。第五过孔V5同时贯穿层间介质层ILD、第二栅绝缘层GI2和第一栅绝缘层GI1，并暴露出驱动晶体管Td的第一极Td_1的一部分。第六过孔V6同时贯穿层间介质层ILD和第二栅绝缘层GI2，并暴露出驱动晶体管Td的栅极Td_g的一部分，其中，第六过孔V6在第二基底20上的正投影与第三电容C3的第二极板C3_2在第二基底20上的正投影无交叠。第七过孔V7同时贯穿层间介质层ILD、第二栅绝缘层GI2和第一栅绝缘层GI1，并暴露出数据写入晶体管T1’的第二极T1’_2的一部分。第八过孔V8同时贯穿层间介质层ILD、第二栅绝缘层GI2和第一栅绝缘层GI1，并暴露出驱动晶体管Td的第二极Td_2的一部分。
图12h为本公开实施例中提供的第一源漏金属层的平面图，图12i为本公开实施例中提供的显示基板的半导体层、第一栅金属层、第二栅金属层和第一源漏金属层的平面图。结合图12e至图12i所示，第一源漏金属层SD1位于第二栅金属层G2远离第二基底20的一侧，层间介质层ILD设置在第一源漏金属层SD1与第二栅金属层G2之间。第一源漏金属层SD1包括：第一电源线VDD，第一电源线VDD通过第四过孔V4与第三电容C3的第二极板C3_2连接，并通过第五过孔V5与驱动晶体管Td的第一极Td_1连接。
另外，像素结构还包括桥接件BR，桥接件BR与第一电源线VDD同层设置，均位于第一源漏金属层SD1中。桥接件BR的一端通过第 六过孔V6与驱动晶体管Td的栅极Td_g连接，桥接件BR的另一端通过第七过孔V7与数据写入晶体管T1’的第二极T1’_2连接。可选地，第六过孔V6与第七过孔V7连通，以提高桥接件BR与驱动晶体管Td的栅极Td_g和数据写入晶体管T1’的第二极T1’_2连接的稳定性。
另外，像素结构还包括第一转接件CT1和第三转接件CT3，第一转接件CT1和第三转接件CT3与桥接件BR同层设置，均位于第一源漏金属层SD1中。第一转接件CT1通过第八过孔V8与驱动晶体管Td的第二极Td_2连接。第三转接件CT3通过源极过孔V_s1与数据写入晶体管T1’的第一极连接。
第一源漏金属层SD1远离第二基底20的一侧设置有钝化层。可选地，钝化层可以采用氮化硅层、氧化硅层、氮氧化硅层中的单层或多层。图12j为本公开实施例中提供的钝化层上的过孔示意图，如图12j所示，钝化层上设置有第九过孔V9和第十一过孔V11，第九过孔V9暴露出第一转接件CT1的一部分，第十一过孔V11暴露出第三转接件CT3的一部分。
图12k为本公开实施例中提供的显示基板的第二源漏金属层的平面图，图13a为本公开实施例中提供的显示基板的半导体层、第一栅金属层、第二栅金属层、第一源漏金属层和第二源漏金属层的平面图，图13b为沿图13a中D-D'线的剖视图。结合图12j至图13b所示，第二源漏金属层SD2位于第一源漏金属层SD1远离第二基底20的一侧，钝化层PVX设置在第二源漏金属层SD2与第一源漏金属层SD1之间。第二源漏金属层SD2包括数据线Data和第二转接件CT2，第二转接件CT2通过钝化层PVX上的第九过孔V9与第一转接件CT1连接。数据写入晶体管T1’的第一极T1’_1与数据线Data形成为一体，并通过第十一过孔V11与第三转接件CT3连接，从而通过第三转接件CT3与数据写入晶体管T1’的有源层连接。可选地，第一源漏金属层SD1和第 二源漏金属层SD2的制作材料可以为银、铝、钼或铜等金属材料。
可选地，栅线Gate和第一电源线VDD沿第三方向延伸，数据线Data沿第四方向延伸，第三方向与第四方向交叉，例如，第三方向与第四方向垂直。可选地，第三方向与第一方向相同，第四方向与第二方向相同。
例如，显示基板2的多个像素结构排成多行多列，第四方向为列方向。可选地，同一列中的相邻两个像素驱动电路21的数据写入晶体管T1’分别连接两条相邻的所述数据线Data。
在一些实施例中，第i行第j列像素驱动电路21沿列方向移动后得到的虚拟结构与第i+1行第j+2列像素驱动电路21呈镜像对称，其中，1≤i≤m-1，1≤j≤n-2，m为所述像素驱动电路21的总行数，n为所述像素驱动电路21的总列数。其中，第i行第j列像素驱动电路21沿列方向移动后得到的虚拟结构与第i+1行第j+2列像素驱动电路21呈镜像对称。其中，1≤i≤m-1，1≤j≤n-2，m为像素驱动电路21的总行数，n为所述像素驱动电路21的总列数。其中，第i行第j列像素驱动电路21与第i+1行第j+2列像素驱动电路21分别连接两条相邻的数据线Data。
第二源漏金属层SD2远离第二基底20的一侧设置有平坦化层，平坦化层上设置有第十过孔。图13c为本公开实施例中提供的第十过孔与第二源漏金属层的位置关系图，如图13c所示，第十过孔V10暴露出第二转接件CT2的至少一部分。
发光器件22的第一电极221所在层位于第二源漏金属层SD2远离第二基底20的一侧，平坦化层设置在发光器件22的第一电极所在层与第二源漏金属层SD2之间。图13d为本公开实施例中提供的显示基板的第一电极层与第二源漏金属层的平面图，图13e为本公开实施例中提供的显示基板的第一电极层与第二源漏金属层的连接示意图， 如图13d和图13e所示，第一电极层包括多个发光器件22的第一电极221。第一电极221通过贯穿平坦化层PLN的第十过孔V10与第二转接件CT2连接，从而通过第二转接件CT2和第一转接件CT1连接驱动晶体管Td的第二极Td_2。
当然，也可以不设置第二转接件CT2和第一转接件CT1，从而使第一电极221通过同时贯穿平坦化层PLN、钝化层PVX、层间介质层ILD、第二栅绝缘层GI2和第一栅绝缘层GI1的过孔来连接驱动晶体管Td。而通过第二转接件CT2和第一转接件CT1的设置，可以防止直接形成较深的过孔，从而保证第一电极221与驱动晶体管Td的连接可靠性。
可选地，发光器件22的第一电极221在第二基底20上的正投影与数据线Data在第二基底20上的正投影存在交叠，从而在显示基板2分辨率一定的情况下，尽量增大发光器件22的发光面积。
可选地，第一电极221远离第二基底20的一侧还可以设置像素界定层，像素界定层上设置有与第一电极221一一对应的像素开口，发光器件22的空穴注入层、空穴传输层、发光层、电子传输层、电子注入层等膜层均设置在像素开口中。其中，该像素开口在第二基底20上的正投影可以与数据线Data在第二基底20上的正投影存在交叠。
其中，第一电极221被像素开口暴露出的区域可以作为发光器件22的发光区域。为了保证感光器件13充分接收到发光器件22所发射的光线，在一些实施例中，相邻感光器件13的第一极131之间的间隙与相邻发光器件22的发光区域之间的间隙正对。
图14为本公开实施例提供的一种显示装置的制作方法流程图，如图14所示，所述制作方法包括：
S10、在第一基底上形成多个光电检测电路，以形成光电检测基板。其中，光电检测电路采用上述实施例中所述的光电检测电路。
例如，在第一基板上形成多个光电检测电路的感测器件驱动结构，该感测器件驱动结构包括上述实施例中的第一复位晶体管T1、第二复位晶体管T2、数据读取晶体管T3、第一电容C1和第二电容C2；之后，形成多个光电检测电路的感光器件。
S20、在第二基底上形成多个像素结构，以形成显示基板；所述像素结构包括发光器件和像素驱动电路。
例如，在第二基底上形成多个像素结构的像素驱动电路，之后形成多个像素结构的发光器件。像素驱动电路和发光器件的具体结构参见上文描述，在形成多个像素驱动电路时，位于同一层中的结构可以同步制作，例如，多个像素驱动电路中各晶体管的有源层同步制作，多个像素驱动电路中的第三电容的第一极板与栅线同步制作，多个像素驱动电路中的第三电容的第二极板同步制作，等等。
需要说明的是，本公开实施例对步骤S10和步骤S20的先后顺序不作限定，步骤S10可以在步骤S20之前，也可以在步骤S20之后。
S30、将显示基板与光电检测基板固定在一起，其中，光电检测基板位于显示基板的非显示侧，感光器件与至少一个发光器件正对，以接收发光器件的光线。
例如，可以通过光学胶层将显示基板和光电检测基板粘结在一起。
在另一些实施例中，所述显示装置的制作方法还包括：制作透镜层，所述透镜层包括多个透镜，所述透镜用于对光线进行汇聚。这种情况下，步骤S30可以包括：将透镜层固定在显示基板的非显示侧，将光电检测基板固定在所述透镜层远离所述显示基板的一侧。例如，采用光学胶层将透镜层粘结在显示基板的非显示侧，并采用光学胶层将光电检测基板粘结在透镜层远离显示基板的一侧。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普 通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (33)

  1. 一种光电检测电路，包括：第一复位子电路、第二复位子电路、第一存储子电路、数据读取子电路和感光器件，其中，所述数据读取子电路的第一端、所述第一存储子电路的第一端、所述感光器件的第一极、所述第一复位子电路的第一端连接于第一节点；所述感光器件的第二极连接公共电压线；
    其中，所述感光器件配置为，根据感应到的光信号生成感应电信号；
    所述数据读取子电路配置为，响应于扫描线的信号的控制，将所述第一节点的电压传输至数据读取线；
    所述第一复位子电路配置为，响应于复位线的信号的控制，对所述第一节点的电压进行复位；
    所述第一存储子电路配置为，存储所述第一节点与所述公共电压线之间的电压；
    所述第二复位子电路配置为，响应于所述复位线的信号的控制，对所述扫描线上的电压进行复位。
  2. 根据权利要求1所述的光电检测电路，其中，所述光电检测电路还包括第二存储子电路，所述第二存储子电路配置为，存储所述扫描线与所述公共电压线之间的电压。
  3. 根据权利要求1所述的光电检测电路，其中，所述第一复位子电路包括：第一复位晶体管，所述第一复位晶体管的栅极连接所述复位线，所述第一复位晶体管的第一极连接公共电压线，所述第一复位晶体管的第二极形成所述第一复位子电路的第一端；
    所述数据读取子电路包括：数据读取晶体管，所述数据读取晶体 管的栅极连接所述扫描线，所述数据读取晶体管的第一极连接所述数据读取线，所述数据读取晶体管的第二极形成为所述数据读取子电路的第一端。
  4. 根据权利要求3所述的光电检测电路，其中，所述数据读取线和所述扫描线位于绝缘间隔的不同层中，所述扫描线沿第一方向延伸，所述数据读取线沿第二方向延伸，所述第一方向与所述第二方向相交叉，
    所述数据读取晶体管的栅极为所述扫描线的一部分，所述数据读取晶体管的第一极和第二极在第一基底上的正投影分别位于所述扫描线在所述第一基底上的正投影沿所述第二方向的两侧。
  5. 根据权利要求3所述的光电检测电路，其中，所述第一复位晶体管的第一极和第二极、所述数据读取晶体管的第一极和第二极均与所述数据读取线同层设置，
    所述第一复位晶体管的第一极所在层与所述公共电压线所在层之间设置有第一绝缘层，所述第一绝缘层上设置有第一过孔，所述第一过孔暴露出所述公共电压线的一部分，所述第一复位晶体管的第一极通过所述第一过孔连接所述公共电压线。
  6. 根据权利要求5所述的光电检测电路，其中，所述第二复位子电路包括：第二复位晶体管，所述第二复位晶体管的栅极连接所述复位线，所述第二复位晶体管的第一极与所述第一复位晶体管的第一极形成为一体结构，所述第二复位晶体管的第二极连接所述扫描线。
  7. 根据权利要求6所述的光电检测电路，其中，所述第一绝缘层 上还设置有第二过孔，所述第二过孔暴露出所述扫描线的一部分，所述第二复位晶体管的第二极通过所述第二过孔连接所述扫描线。
  8. 根据权利要求3至7中任意一项所述的光电检测电路，其中，所述第一存储子电路包括：第一电容，所述第一电容的第一极板与所述公共电压线形成为一体结构，所述第一电容的第二极板、所述数据读取晶体管的第二极、所述第一复位晶体管的第二极形成为一体结构。
  9. 根据权利要求8所述的光电检测电路，其中，所述感光器件位于所述第一电容的第二极板远离第一极板的一侧，所述感光器件的第一极所在层与所述第一电容的第二极板所在层之间设置有第二绝缘层，所述第二绝缘层上设置有第三过孔，所述第三过孔暴露出所述第一电容的第二极板的一部分，所述感光器件的第一极通过所述第三过孔与所述第一电容的第二极板连接，以形成所述第一节点；多个所述光电检测电路的感光器件的第二极连接为整层结构。
  10. 根据权利要求8所述的光电检测电路，其中，所述感光器件的第一极在第一基底上的正投影至少覆盖所述第一电容在所述第一基底上的正投影。
  11. 根据权利要求3至7中任意一项所述的光电检测电路，其中，所述第二存储子电路包括第二电容，所述第二电容的第一极板为所述扫描线的一部分，所述第二电容的第二极板为所述第一复位晶体管的第一极的一部分。
  12. 一种显示装置，包括：
    显示基板，所述显示基板包括：第二基底和设置在所述第二基底上的多个像素结构，所述像素结构包括发光器件；
    光电检测基板，所述光电检测基板包括：第一基底和设置在所述第一基底上的多个光电检测电路，所述光电检测电路采用权利要求1至11中任意一项所述的光电检测电路；其中，所述显示基板包括相对的显示侧和非显示侧，所述光电检测基板位于所述显示基板的非显示侧，每个所述感光器件在所述第二基底上的正投影位于y个所述像素结构在所述第二基底上的正投影范围内，以接收所述发光器件的光线，1≤y≤100，且y为整数。
  13. 根据权利要求12所述的显示装置，其中，所述第二基底的材料为玻璃或聚酰亚胺。
  14. 根据权利要求12所述的显示装置，其中，所述公共电压线的延伸方向和所述复位线的延伸方向均与所述扫描线的延伸方向相同，且所述公共电压线和所述复位线均与所述扫描线同层设置，
    所述扫描线位于所述公共电极线与所述复位线之间。
  15. 根据权利要求12所述的显示装置，其中，所述像素结构还包括像素驱动电路，所述像素驱动电路包括：驱动晶体管、数据写入晶体管和第三电容，
    所述数据写入晶体管的栅极连接栅线，所述数据写入晶体管的第一极连接数据线，所述数据写入晶体管的第二极连接所述驱动晶体管的栅极，所述驱动晶体管的第一极连接第一电源线，所述驱动晶体管的第二极连接所述发光器件的第一电极，所述第三电容的两端分别连接所述驱动晶体管的栅极和第一极。
  16. 根据权利要求15所述的显示装置，其中，所述第三电容的第一极板为所述驱动晶体管的栅极的至少一部分，所述第三电容的第二极板位于所述第三电极的第一极板远离所述第二基底的一侧。
  17. 根据权利要求16所述的显示装置，其中，所述驱动晶体管的有源层、第一极和第二极同层设置，所述驱动晶体管的栅极所在层与有源层所在层之间设置有第一栅绝缘层，所述驱动晶体管的栅极所在层与所述第三电容的第二极板所在层之间设置有第二栅绝缘层，所述第一电源线位于所述第三电容的第二极板所在层远离所述第二基底的一侧，所述第一电源线所在层与所述第三电容的第二极板所在层之间设置有层间介质层，
    所述第一电源线通过第四过孔与所述第三电容的第二极板连接，并通过第五过孔与所述驱动晶体管的第一极连接，其中，所述第四过孔贯穿所述层间介质层，并暴露出所述第三电容的第二极板的一部分；所述第五过孔同时贯穿所述层间介质层、所述第二栅绝缘层和所述第一栅绝缘层，并暴露出所述驱动晶体管的第一极的一部分。
  18. 根据权利要求17所述的显示装置，其中，所述数据写入晶体管的第二极和有源层均与所述驱动晶体管的有源层同层设置，
    所述像素结构还包括桥接件，所述桥接件与所述第一电源线同层设置，所述桥接件的一端通过第六过孔与所述驱动晶体管的栅极连接，所述桥接件的另一端通过第七过孔与所述数据写入晶体管的第二极连接，
    其中，所述第六过孔同时贯穿所述层间介质层和所述第二栅绝缘层，并暴露出所述驱动晶体管的栅极的一部分；所述第七过孔同时贯 穿所述层间介质层、所述第二栅绝缘层和所述第一栅绝缘层，并暴露出所述数据写入晶体管的第二极的一部分。
  19. 根据权利要求18所述的显示装置，其中，所述数据线位于所述第一电源线所在层远离所述第二基底的一侧，所述数据线所在层与所述第一电源线所在层之间设置有钝化层，所述发光器件的第一电极位于所述数据线所在层远离所述第二基底的一侧，所述发光器件的第一电极所在层与所述数据线所在层之间设置有平坦化层；
    所述像素结构还包括：
    第一转接件，与所述桥接件同层设置，所述第一转接件通过第八过孔与所述驱动晶体管的第二极连接，所述第八过孔同时贯穿所述层间介质层、所述第二栅绝缘层和所述第一栅绝缘层，并暴露出所述驱动晶体管的第二极的一部分；
    第二转接件，所述第二转接件与所述数据线同层设置，所述第二转接件通过所述钝化层上的第九过孔与所述第一转接件连接，所述发光器件的第一电极通过贯穿所述平坦化层的第十过孔与所述第二转接件连接。
  20. 根据权利要求15所述的显示装置，其中，所述发光器件的第一电极在所述第二基底上的正投影与所述数据线在所述第二基底上的正投影存在交叠。
  21. 根据权利要求15所述的显示装置，其中，多个所述像素结构排成多行多列，同一列中的相邻两个所述像素驱动电路分别连接两条相邻的所述数据线；
    同一行所述像素驱动电路连接同一条所述第一电源线。
  22. 根据权利要求21所述的显示装置，其中，第i行第j列所述像素驱动电路沿列方向移动后得到的虚拟结构与第i+1行第j+2列像素驱动电路呈镜像对称，其中，1≤i≤m-1，1≤j≤n-2，m为所述像素驱动电路的总行数，n为所述像素驱动电路的总列数。
  23. 根据权利要求12所述的显示装置，其中，所述发光器件还包括发光层，所述发光层位于所述发光器件的第一电极远离所述第二基底的一侧，所述像素结构还包括位于所述发光层与所述第二基底之间的通光部，所述通光部用于通光，以使所述发光层所发射的光线的一部分射向所述第二基底。
  24. 根据权利要求23所述的显示装置，其中，所述通光部包括第一通光孔，所述第一通光孔穿过所述像素驱动电路；或者，
    所述通光部包括位于所述像素驱动电路中的通光狭缝。
  25. 根据权利要求24所述的显示装置，其中，所述第一电极为反射电极，所述通光部还包括穿过所述第一电极的第二通光孔。
  26. 根据权利要求12所述的显示装置，其中，所述显示装置还包括：
    设置在所述显示基板与所述光电检测基板之间的透镜层，所述透镜层包括多个透镜，所述透镜用于对光线进行汇聚。
  27. 根据权利要求12所述的显示装置，其中，所述显示装置还包括：
    补偿电路，与所述数据读取线连接，用于根据所述数据读取线上的实际电压与理论电压的差异，确定所述发光器件的补偿参数；
    显示驱动电路，与所述补偿电路和所述像素结构连接，用于根据所述发光器件的补偿参数以及所述发光器件的目标发光亮度，确定所述发光器件的驱动信号，并将所述驱动信号输出至所述像素结构。
  28. 一种光电检测电路的驱动方法，所述光电检测电路采用权利要求1至11中任意一项所述的光电检测电路，其中，所述驱动方法包括：
    在复位阶段，向所述复位线加载有效电平信号、向所述扫描线加载无效电平信号，以使所述第一复位子电路对所述第一节点的电压进行复位、所述第二复位子电路对所述扫描线的电压进行复位；
    在电荷累积阶段，向所述复位线和所述扫描线均加载无效电平信号，以使所述光电检测器件进行电荷累积；
    在读取阶段，向所述扫描线加载有效电平信号，以使所述第一节点的电压传输至数据读取线；
    在冗余阶段，向所述扫描线和所述复位线加载无效电平信号，以使所述数据读取子电路将所述第一节点与所述数据读取线断开。
  29. 一种显示装置的制作方法，包括：
    在第一基底上形成多个光电检测电路，以形成光电检测基板；其中，所述光电检测电路采用权利要求1至11中任意一项所述的光电检测电路；
    在第二基底上形成多个像素结构，以形成显示基板；所述显示基板包括相对的显示侧和非显示侧，所述像素结构包括发光器件；
    将所述显示基板与所述光电检测基板固定在一起，其中，所述光 电检测基板位于所述显示基板的非显示侧，每个所述感光器件在所述第二基底上的正投影位于y个所述像素结构在所述第二基底上的正投影范围内，以接收y个所述发光器件的光线，1≤y≤100，且y为整数。
  30. 根据权利要求29所述的制作方法，其中，所述发光器件包括：第一电极、第二电极和位于所述第一电极与所述第二电极之间的发光层，所述发光层位于所述发光器件的第一电极远离所述第二基底的一侧，
    所述像素结构还包括位于所述发光层与所述第二基底之间的通光部，所述通光部用于通光，以使所述发光层所发射的光线的一部分射向所述第二基底。
  31. 根据权利要求30所述的制作方法，其中，所述通光部包括第一通光孔，所述第一通光孔穿过所述像素驱动电路；或者，
    所述通光部包括位于所述像素驱动电路中的通光狭缝。
  32. 根据权利要求31所述的制作方法，其中，所述第一电极为反射电极，所述通光部还包括穿过所述第一电极的第二通光孔。
  33. 根据权利要求29所述的制作方法，其中，所述制作方法还包括：制作透镜层，所述透镜层包括多个透镜，所述透镜用于对光线进行汇聚；
    将所述显示基板与所述光电检测基板固定在一起，包括：
    将所述透镜层固定在所述显示基板的非显示侧，将所述光电检测基板固定在所述透镜层远离所述显示基板的一侧。
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