WO2022052722A1 - 阵列基板和显示装置 - Google Patents

阵列基板和显示装置 Download PDF

Info

Publication number
WO2022052722A1
WO2022052722A1 PCT/CN2021/111923 CN2021111923W WO2022052722A1 WO 2022052722 A1 WO2022052722 A1 WO 2022052722A1 CN 2021111923 W CN2021111923 W CN 2021111923W WO 2022052722 A1 WO2022052722 A1 WO 2022052722A1
Authority
WO
WIPO (PCT)
Prior art keywords
sub
pixel
lead
pixel electrode
array substrate
Prior art date
Application number
PCT/CN2021/111923
Other languages
English (en)
French (fr)
Inventor
万云海
邹志翔
陈川
桂学海
孙培华
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/913,465 priority Critical patent/US20230134406A1/en
Publication of WO2022052722A1 publication Critical patent/WO2022052722A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/16—Materials and properties conductive

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to an array substrate and a display device.
  • the liquid crystal display panel may include an array substrate and a color filter substrate arranged in a cell.
  • the array substrate may include sub-pixels arranged in an array and scan lines 350 and data lines 360 , wherein any sub-pixel includes a pixel electrode 310 and a switch transistor 320 , and the switch transistor has a drain electrode 330 .
  • the pixel electrode 310 is connected to the drain electrode 330 of the switch transistor
  • the data line 360 is connected to the source electrode of the switch transistor
  • the scan line 350 is connected to the gate electrode of the switch transistor 320
  • the connection line between the source electrode and the drain electrode of the switch transistor is parallel to the scan line 350 direction of extension.
  • the drain electrode 330 is provided between the pixel electrode 310 and the scan line 350 connected to the sub-pixel, which results in a large avoidance space A between the pixel electrode 310 and the scan line 350, The size of the pixel electrode 310 in the column direction C is reduced.
  • the avoidance space A not only includes the space occupied by the drain electrode 330 , but also includes part of the space adjacent to the drain electrode 330 in the row direction B, which makes the size of the avoidance space A much larger than the space occupied by the drain electrode 330 size of.
  • the existence of the avoidance space A restricts the area of the pixel electrode 310 , reduces the aperture ratio of the liquid crystal display panel, and is not conducive to improving the light transmittance of the liquid crystal display panel.
  • the purpose of the present disclosure is to provide an array substrate and a display device to improve the light transmittance of the display panel.
  • an array substrate comprising a plurality of scan lines, a plurality of data lines and a plurality of sub-pixels arranged in an array on a base substrate, any one of the sub-pixels includes a pixel electrode and a plurality of sub-pixels.
  • a switch transistor wherein the pixel electrode is connected to the drain electrode of the switch transistor, the gate electrode of the switch transistor is connected to one of the scan lines, and the source electrode of the switch transistor is connected to one of the data lines;
  • the active layer of the switching transistor of the sub-pixel is located between the pixel electrode of the sub-pixel and the data line connected to the sub-pixel.
  • the data line includes a plurality of alternately connected first conductive leads and second conductive leads;
  • the second conductive wires extend in a direction intersecting the scan lines, and the first conductive wires extend away from the sub-pixels connected to the data lines in the extending direction of the adjacent second conductive wires
  • the direction of the pixel electrode is bent into a curve or a broken line
  • the first end of the first conductive lead is connected to the first end of the second conductive lead, and the second end of the first conductive lead is connected to the second end of the second conductive lead in the next row; the An escape area is formed between the first conductive lead and the adjacent and electrically connected pixel electrodes of the sub-pixels, and the extension line of the second end of the second conductive lead and the active layer are both located in the escape area.
  • a channel direction of the active layer and an extension direction of the scan line have a predetermined included angle.
  • a channel direction of the active layer is perpendicular to an extending direction of the scan line.
  • the pixel electrode in the sub-pixel includes a plurality of strip-shaped sub-electrodes, and the included angle between the plurality of strip-shaped sub-electrodes and the scan line is not 90 degrees;
  • the channel direction of the active layer is consistent with the extending direction of the strip-shaped sub-electrodes of the pixel electrode.
  • a channel direction of the active layer is consistent with an extension direction of the scan line.
  • the second conductive lead is a metal lead
  • the first conductive lead is a metal lead or a transparent metal oxide lead.
  • the second conductive lead and the drain electrode of the switching transistor are provided in the same layer and made of the same material;
  • the first conductive lead and one of the pixel electrode, the common electrode of the array substrate, the common electrode line of the array substrate, the drain electrode of the switching transistor, and the scan line are arranged in the same layer and made of material same.
  • the pixel electrode in the sub-pixel includes a plurality of strip-shaped sub-electrodes arranged in parallel;
  • the first conductive lead is a folded line, including a connecting lead segment and a first strip lead segment connected in sequence; the connecting lead segment is connected to the second lead lead and is parallel to the scan line, and the first lead segment is connected to the scan line.
  • the lead segment is consistent with the extending direction of the strip-shaped sub-electrode of the pixel electrode and is electrically connected to the second conductive lead in the next row.
  • the pixel electrode has a protruding portion, and the protruding portion of the pixel electrode is located at an extension of the first strip-shaped lead segment disposed adjacent to the pixel electrode on-line;
  • the extending direction of the first strip-shaped lead segment is parallel to the extending direction of the adjacent strip-shaped sub-electrodes of the pixel electrode; the first conductive lead and the pixel electrode are provided in the same layer and made of the same material.
  • the pixel electrode in the sub-pixel includes a plurality of strip-shaped sub-electrodes
  • the second conductive lead includes a second strip-shaped lead segment, and the extending direction of the second strip-shaped lead segment is parallel to the extending direction of the strip-shaped sub-electrodes of the adjacent pixel electrodes.
  • a display device including the above-mentioned array substrate.
  • the drain electrodes of the sub-pixels are arranged between the pixel electrodes and the data lines, so that the drain electrodes are avoided to be arranged between the pixel electrodes and the scan lines, thereby avoiding the related art.
  • the use of space increases the area of the pixel electrode, which is beneficial to improve the light transmittance of the display panel using the array substrate.
  • FIG. 1 is a schematic top view of an array substrate in the related art.
  • FIG. 2 is a schematic top-view structural diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic top-view structural diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic view of the cross-sectional structure of the array substrate shown in FIG. 3 at the DE position.
  • FIG. 5 is a schematic top-view structural diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic top-view structural diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic view of the cross-sectional structure of the array substrate shown in FIG. 6 at the DE position.
  • FIG. 8 is a schematic top-view structural diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic view of the cross-sectional structure of the array substrate shown in FIG. 8 at the DE position.
  • FIG. 10 is a schematic top-view structural diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic cross-sectional view of the array substrate shown in FIG. 10 at the DE position.
  • FIG. 12 is a schematic top-view structural diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 13 is a schematic view of the cross-sectional structure of the array substrate shown in FIG. 12 at the DE position.
  • FIG. 14 is a schematic top-view structural diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 15 is a schematic top-view structural diagram of an active layer of a switching transistor in an embodiment of the present disclosure.
  • 16 is a schematic cross-sectional structural diagram of a display device in an embodiment of the present disclosure.
  • Array substrate 110, base substrate; 120, semiconductor layer; 130, gate layer; 140, source-drain metal layer; 150, pixel electrode layer; 160, common electrode layer; 161, avoid opening; 170, alignment layer 210, gate insulating layer; 220, interlayer dielectric layer; 230, planarization layer; 240, insulating dielectric layer; 310, pixel electrode; 311, strip-shaped sub-electrode; 312, hollow slit; 314, protruding part; 320, switching transistor; 3201, active layer of switching transistor; 321, source contact region of switching transistor; 322, drain contact region of switching transistor; 323, channel region of switching transistor; 3202 330, drain electrode; 340, common electrode; 350, scan line; 360, data line; 361, first conductive lead; 3611, first strip lead segment; 3612, connecting lead segment; 362 , the second conductive lead; 3621, the second strip lead segment; 363, the via hole; 2, the color filter substrate; 21, the black matrix layer; 3, the liquid crystal layer; A, the
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided in order to give a thorough understanding of the embodiments of the present disclosure.
  • a structure When a structure is “connected” with other structures, it may mean that a structure is integral with other structures, or a structure is “directly” connected to other structures, or a structure is “indirectly” connected to other structures through another structure connect.
  • a structure When a structure is “electrically connected” to another structure, it may mean that a structure is “directly” electrically connected to another structure, or it may mean that a structure is “indirectly” connected to another structure through other structures that can conduct electricity electrical connection.
  • the terms “a” are used to indicate the presence of an element/component/etc; the terms “include” and “have” are used to indicate an open-ended inclusive meaning and mean in addition to the listed elements/components/etc. Additional elements/components/etc may also be present.
  • the terms “first” and “second” etc. are used only as labels and are not intended to limit the number of their objects.
  • the "same layer arrangement" in the present disclosure means that the two structures are formed from the same material layer through a patterning process, so the two are in the same layer in a lamination relationship, but this does not mean that the two structures are in the same layer.
  • the distance from the base substrate must be the same.
  • the present disclosure provides an array substrate, which can be applied to a liquid crystal display panel.
  • the array substrate includes a plurality of scan lines 350 , a plurality of data lines 360 arranged on the base substrate 110 and a plurality of sub-pixels arranged in an array, and any sub-pixel includes a pixel electrode 310 and a switch transistor 320 ;
  • the pixel electrode 310 is connected with the drain electrode 330 of the switching transistor 320
  • the gate electrode 3202 of the switching transistor 320 is connected with a scan line 350
  • the source electrode of the switching transistor 320 is connected with a data line 360
  • the active layer 3201 is located between the pixel electrode 310 of the sub-pixel and the data line 360 connected to the sub-pixel.
  • the active layer 3201 of the switch transistor 320 of the sub-pixel is disposed between the pixel electrode 310 and the data line 360, so as to avoid disposing the switch transistor 320 between the pixel electrode 310 and the scan line 350, and further
  • the use of the avoidance space A in the related art can be realized to increase the area of the pixel electrode 310, which is beneficial to improve the light transmittance of the display panel to which the array substrate is applied.
  • the connected data lines 360 are between orthographic projections on the base substrate 110 .
  • the drain electrode 330 of any sub-pixel is located between the pixel electrode 310 of the sub-pixel and the data line 360 connected to the sub-pixel
  • the pixel electrode 310 of the sub-pixel can cover the avoidance space A in the related art to increase the area of the pixel electrode 310 .
  • the drain electrode 330 and the active layer 3201 occupy part of the space originally used for arranging the data lines 360 , so that the data lines 360 need to be bent to avoid Drain electrode 330 and active layer 3201. Therefore, this causes the pixel electrode 310 to have an avoidance gap 313; since the size of the avoidance space A in the related art is much larger than the size of the drain electrode 330 and the active layer 3201, the pixel electrode 310 of the present disclosure occupies the space in the related art. The area increased by avoiding the space A is larger than the area lost due to the avoidance gap 313 , so that the area of the pixel electrode 310 is increased compared with the related art.
  • the pixel electrode 310 has an avoidance notch 313; in the same sub-pixel, the avoidance notch 313 is located on the side of the pixel electrode 310 away from the drain electrode 330 and the active layer 3201, and is located on the side of the pixel electrode 310 close to the scan line 350 connected to the sub-pixel; the orthographic projection of the first conductive lead 361 of the drain electrode 330 adjacent to the sub-pixel and away from the sub-pixel’s drain electrode 330 on the base substrate 110, at least A part is located in the orthographic projection of the avoidance notch 313 of the sub-pixel on the base substrate 110 .
  • the pixel electrode 310 has a protruding portion 314 , and the protruding portion 314 of the pixel electrode 310 is located on a side of the pixel electrode 310 away from the electrically connected scan line 350 and at a side of the pixel electrode 310 away from the electrically connected data line 360 . side.
  • the array substrate provided by the present disclosure may include a base substrate 110, a driving circuit layer and a pixel electrode layer 150 stacked in sequence, wherein the driving circuit layer includes the switching transistors 320 and the scan lines 350 of the array substrate; the pixel electrode layer 150 includes the pixel electrode 310 . It can be understood that the pixel electrode 310 is a transparent electrode.
  • the switching transistor 320 may be a metal-oxide-semiconductor field effect transistor (metal-oxide-semiconductor FET, MOS-FET for short). Further, the switching transistor 320 is a thin film transistor. On the film layer structure, the switching transistor 320 may be a top-gate switching transistor 320 or a bottom-gate switching transistor 320, which is not limited in the present disclosure. On the material of the semiconductor layer 120 of the switching transistor 320, the switching transistor 320 may be an amorphous silicon switching thin film transistor, a low temperature polysilicon thin film transistor, an oxide thin film transistor or an organic semiconductor thin film transistor, which is not limited in the present disclosure. On the turn-on condition of the switch transistor 320, the switch transistor 320 may be an N-type switch transistor 320 or a P-type switch transistor 320, which is not limited in the present disclosure.
  • metal-oxide-semiconductor field effect transistor metal-oxide-semiconductor FET, MOS-FET for short
  • the driving circuit layer may include a stacked gate layer 130 , a gate insulating layer 210 , a semiconductor layer 120 , an interlayer dielectric layer 220 , and a source-drain metal layer 140 , the planarization layer 230 and other film layers.
  • the positional relationship of each film layer may be determined according to the film layer structure of the switching transistor 320 .
  • the driving circuit layer may include a semiconductor layer 120, a gate insulating layer 210, a gate layer 130, an interlayer dielectric layer 220, and a source-drain metal layer 140, which are sequentially stacked.
  • the switching transistor 320 thus formed is a top-gate thin film transistor.
  • the driving circuit layer may include a gate layer 130 , a gate insulating layer 210 , an active layer, an interlayer dielectric layer 220 and a source-drain metal layer that are stacked in sequence 140, the switching transistor 320 thus formed is a bottom-gate thin film transistor.
  • the drain electrode 330 is located on the source-drain metal layer 140 of the array substrate.
  • the scan lines 350 are located on the gate layer 130 of the array substrate.
  • the switching transistor 320 is a bottom gate metal oxide thin film transistor.
  • the array substrate may further include a common electrode layer 160 , the common electrode layer 160 may include common electrodes 340 of each sub-pixel, and the common electrodes 340 may be interdigitated Electrodes, plate electrodes, slit electrodes or electrodes of other shapes.
  • the common electrode layer 160 may be disposed between the pixel electrode layer 150 and the driving circuit layer, or may be disposed on the side of the pixel electrode layer 150 away from the driving circuit layer.
  • the common electrode layer 160 is provided between the pixel electrode layer 150 and the driving circuit layer, and the source of the common electrode layer 160 and the driving circuit layer
  • a planarization layer 230 is disposed between the drain metal layers 140
  • an insulating medium layer 240 is disposed between the common electrode layer 160 and the pixel electrode layer 150 .
  • the common electrode 340 is a flat electrode, that is, the common electrode 340 is not provided with a hollow structure, for example, is not provided with a narrow sew etc.
  • the common electrode layer 160 further includes common electrode lines, and the adjacent common electrodes 340 may be connected to each other through common electrode lines.
  • both the common electrode 340 and the pixel electrode 310 are transparent electrodes, and the material thereof may be transparent metal oxide.
  • any one of the data lines 360 may include a first conductive lead 361 and a second conductive lead 362 that are alternately arranged and electrically connected in sequence. connect.
  • FIG. 2 is a top view of an array substrate provided by the present disclosure. In FIG. 2 , only the pixel electrode 310 , the switching transistor 320 , the drain electrode 330 , the scan line 350 and the data line 360 are shown. Wherein, in FIG. 2, the data line 360 only shows the position of its orthographic projection on the base substrate 110, and does not reflect its structure on the film layer. That is, in FIG.
  • the data line 360 may include a first conductive lead 361 and a second conductive lead 362 disposed on the same layer, or may include a first conductive lead 361 disposed on two different film layers and connected through vias 363 Lead 361 and second conductive lead 362 .
  • the array substrate includes a plurality of rows of sub-pixels; any data line 360 includes a conductive lead group corresponding to each row of sub-pixels, wherein one conductive lead group includes a first conductive lead 361 and a first conductive lead 361 connected adjacently. Two conductive leads 362 .
  • each sub-pixel is disposed in a one-to-one correspondence with each conductive lead group, and one sub-pixel is disposed adjacent to the corresponding conductive lead group and is directly or indirectly electrically connected.
  • one sub-pixel is disposed adjacent to the corresponding conductive lead group, and is electrically connected to the data line 360 where the corresponding conductive lead group is located.
  • first end of the first conductive lead 361 is electrically connected to the first end of the second conductive lead 362, the second end of the first conductive lead 361 is electrically connected to the second end of the second conductive lead 362 in the next row, the first The second ends of the two conductive leads 362 are electrically connected to the second ends of the first conductive leads 361 .
  • the source electrode of the switching transistor of one sub-pixel is electrically connected to the second conductive lead 362 of the next row of the corresponding conductive lead group.
  • the second conductive leads 362 extend in a direction intersecting the scan lines 350 , and the first conductive leads 361 move away from the data in the direction in which the adjacent second conductive leads 362 extend
  • the direction of the pixel electrode 310 of the sub-pixel connected by the line 360 is bent into a curved line or a broken line; the first end of the first conductive lead 361 is connected to the first end of the second conductive lead 362, and the second end of the first conductive lead 361 Connected with the second end of the second conductive lead 362 in the next row; an escape area D is formed between the first conductive lead 361 and the pixel electrode 310 of the adjacent and electrically connected sub-pixel, and the extension of the second end of the second conductive lead 362 Both the line and the active layer 3201 are located in the escape area D.
  • the second conductive lead 362 is a metal lead; the first conductive lead 361 is a metal lead or a transparent metal oxide lead.
  • the material of the first conductive lead 361 may also be a heavily doped semiconductor material.
  • the second conductive lead 362 and the drain electrode 330 of the switching transistor 320 are provided in the same layer and made of the same material; the first conductive lead 361 is connected to the pixel electrode 310, the common electrode of the array substrate, and the common electrode of the array substrate.
  • One of the line, the drain electrode 330 of the switching transistor 310, and the scan line 350 is disposed in the same layer and has the same material.
  • the second conductive lead 362 is located in the source-drain metal layer 140 , that is, the second conductive lead 362 and the drain electrode 330 are arranged in the same layer and made of the same material. 362 is a metal lead. Further, referring to FIG. 3 , FIG. 5 , FIG. 6 , FIG. 8 , FIG. 10 , FIG. 12 , and FIG. 14 , the orthographic projection of the second conductive lead 362 on the base substrate 110 and the scan line 350 on the base substrate 110 orthographic overlap.
  • the data line 360 may include a plurality of first conductive leads 361 and second conductive leads 362 that are alternately connected in sequence; wherein, the orthographic projection of the first conductive leads 361 on the base substrate 110 is the same as that of the scan lines 350 on the base substrate 110 and the orthographic projections of the second conductive leads 362 on the base substrate 110 overlap with the orthographic projections of the scan lines 350 on the base substrate 110 .
  • the pixel electrode 310 includes a plurality of strip-shaped sub-electrodes 311 arranged in parallel;
  • the two conductive leads 362 include a second strip-shaped lead segment 3621 , and the extending direction of the second strip-shaped lead segment 3621 is parallel to the extending direction of the strip-shaped sub-electrodes 311 of the adjacent pixel electrodes 310 .
  • the shape of the pixel electrode 310 and the direction of the data line 360 can be matched with each other, thereby reducing the area of the pixel electrode 310 lost due to the arrangement of the data line 360 and increasing the area of the pixel electrode 310 .
  • the extension direction of the stripe-shaped sub-electrodes 311 intersects with the extension direction of the scan lines 350 , for example, the included angle between the two may be 75° ⁇ 90°.
  • the extending directions of the strip-shaped sub-electrodes 311 of the sub-pixels in two adjacent rows may be the same or different.
  • the pixel electrode 310 in the sub-pixel includes a plurality of strip-shaped sub-electrodes 311, and the included angle between the plurality of strip-shaped sub-electrodes 311 and the scan line is not 90 degrees.
  • the extending directions of the strip-shaped sub-electrodes 311 of two adjacent rows of sub-pixels are the same, and intersect with the extending direction of the scan lines 350 at an acute angle of 75° ⁇ 85°.
  • the extending direction of the strip-shaped sub-electrodes 311 of each sub-pixel is perpendicular to the extending direction of the scan lines 350 .
  • the extending directions of the strip-shaped sub-electrodes 311 of the sub-pixels in two adjacent rows are symmetrical with respect to the extending direction of the scan lines 350 , and both are the same as the extending directions of the scan lines 350 .
  • the intersection forms an acute angle of 75° to 85°.
  • the first conductive lead 361 is a broken line, including a connecting lead segment 3612 and a first strip lead segment 3611 connected in sequence; the connecting lead segment 3612 is connected to the second lead lead 362 and is parallel to the scan line 350, the first The lead segment 3611 is consistent with the extending direction of the strip-shaped sub-electrode 311 of the pixel electrode and is electrically connected to the second conductive lead 362 in the next row.
  • the first conductive lead 361 and the second conductive lead 362 may be provided on the same layer, or may be provided on different layers.
  • the data lines 360 may be provided only on the driving circuit layer, partially on the driving circuit layer and partially on the pixel electrode layer 150 , or partially on the driving circuit layer and partially on the common electrode layer 160 . In an embodiment of the present disclosure, referring to FIGS.
  • the data line 360 includes a first conductive lead 361 and a second conductive lead 362 that are alternately connected; the first conductive lead 361 and the pixel electrode 310 are provided in the same layer and made of material Similarly, the second conductive lead 362 and the drain electrode 330 of the switching transistor are provided in the same layer and made of the same material; the first conductive lead 361 and the second conductive lead 362 are electrically connected through the via hole 363 .
  • the array substrate includes a source-drain metal layer 140 and a pixel electrode layer 150 sequentially stacked on one side of the base substrate 110 , wherein the source-drain metal layer 140 includes the second conductive lead 362 and the drain electrode 330 , and the pixel electrode layer 150 includes pixels
  • the electrode 310 and the first conductive lead 361 and the first conductive lead 361 and the second conductive lead 362 are electrically connected through the via hole 363 .
  • the pixel electrode 310 includes a plurality of strip-shaped sub-electrodes 311 arranged in parallel; the first conductive lead 361 arranged adjacent to the pixel electrode 310 includes a first strip-shaped sub-electrode 311 .
  • the extending direction of the first strip-shaped lead segment 3611 is parallel to the extending direction of the strip-shaped sub-electrodes 311 of the adjacent pixel electrodes 310 .
  • the first strip-shaped lead segment 3611 can be made equivalent to another common electrode; the pixel electrode 310
  • An electric field may be formed between the adjacent first strip-shaped lead segment 3611, and the intensity and distribution of the electric field are related to the electromotive force of the pixel electrode 310 itself, so that the pixel electrode 310 and the adjacent first strip-shaped lead can be formed.
  • the light transmittance of the region between the segments 3611 is related to the light transmittance of the sub-pixels themselves.
  • the light transmittance of the region between the first strip-shaped lead segment 3611 and the adjacent pixel electrode 310 can be changed correspondingly with the change of the light transmittance of the adjacent sub-pixels, thereby improving the adjacent sub-pixels.
  • the total amount of light transmitted thereby improving the display brightness of the display panel.
  • different first strip-shaped lead segments 3611 located on the same data line 360 can cooperate with their adjacent pixel electrodes 310 to change the electric field distribution around them independently, so that the first strip-shaped lead segments 3611 both It can be used to enhance the light output intensity of the sub-pixels, and can avoid obvious color shift in the picture displayed by the display panel.
  • the pixel electrode 310 includes hollow slits 312 and strip-shaped sub-electrodes 311 arranged alternately; along the extending direction of the scan line 350 , one hollow arranged adjacently
  • the total size of the slit 312 and one strip-shaped sub-electrode 311 is the third dimension d3; along the extension direction of the scan line 350, the first strip-shaped lead segment 3611 is far away from the edge of the adjacent pixel electrode 310 and the pixel electrode 310 is close to the first strip.
  • the dimension between the edges of the strip-shaped lead segment 3611 is the fourth dimension d4.
  • the fourth dimension d4 is equal to 0.5 to 3 times the third dimension d3.
  • the fourth dimension d4 is equal to 0.8-1.2 times the third dimension d3.
  • the third dimension d3 is 6-10 micrometers
  • the fourth dimension d4 is 6-10 micrometers.
  • the distance between the first strip-shaped lead segment 3611 and the adjacent pixel electrode 310 is equal to 0.5-3 times the width of the hollow slit 312 of the pixel electrode 310 .
  • the distance between the first strip-shaped lead segment 3611 and the adjacent pixel electrode 310 is equal to 0.8-1.2 times the width of the hollow slit 312 of the pixel electrode 310 .
  • the sub-pixels further include a common electrode, and between the common electrodes of two adjacent sub-pixels along the row direction B There is an avoidance opening 161 (dotted line in FIG. 5 ); the orthographic projection of the first conductive lead 361 on the base substrate 110 is located within the orthographic projection of the avoidance opening 161 on the base substrate 110 .
  • the coupling effect of the common electrode 340 on the first conductive lead 361 can be weakened, so that when the display panel is in the scanning stage, the light leakage caused by the first conductive lead 361 that is not related to the transmittance of the adjacent sub-pixels is weakened, thereby improving the display.
  • the accuracy of the screen displayed on the panel improves the display quality.
  • the pixel electrode 310 in the sub-pixel includes a plurality of strip-shaped sub-electrodes 311 arranged in parallel;
  • the first conductive lead 361 is a broken line, including the connecting lead segment and the first strip-shaped lead segment 3611 connected in sequence;
  • the connecting lead segment Connected to the second wire lead 362 and parallel to the scan line 350 the first strip-shaped lead segment 3611 is consistent with the extending direction of the strip-shaped sub-electrode 311 of the pixel electrode and is electrically connected to the next row of the second conductive lead 362 .
  • the pixel electrode 310 has a protruding portion 314, and the protruding portion 314 of the pixel electrode 310 is located on the extension line of the first strip-shaped lead segment 3611 arranged adjacent to the pixel electrode 310;
  • the extending directions of the strip-shaped sub-electrodes 311 of the adjacent pixel electrodes 310 are parallel; the first conductive leads 361 and the pixel electrodes 310 are arranged in the same layer and made of the same material.
  • the sub-pixel further includes a common electrode 340;
  • the data line 360 includes alternately connected first conductive leads 361 and second conductive leads 362; the first conductive leads 361
  • the second conductive lead 362 and the drain electrode 330 of the switching transistor are provided in the same layer and of the same material as the common electrode 340 ;
  • the sub-pixel also includes a common electrode 340;
  • the array substrate includes a source-drain metal layer 140 and a common electrode layer 160 sequentially stacked on one side of the base substrate 110, and the source-drain metal layer 140 includes a drain electrode 330 and a second conductive lead 362;
  • the common electrode layer 160 includes a common electrode 340 and a first conductive lead 361 ; the first conductive lead 361 and the second conductive lead 362 are electrically connected through via holes 363 .
  • the data line 360 and the drain electrode 330 of the switching transistor are provided in the same layer and made of the same material.
  • the array substrate includes the source-drain metal layer 140 disposed on one side of the base substrate 110, and the source-drain metal layer 140 includes the drain electrode 330, the first conductive lead 361 and the second conductive lead 362 connected to each other.
  • the data line 360 includes a first conductive lead 361 and a second conductive lead 362 that are alternately connected; the first conductive lead 361 and the scan line 350 are provided in the same layer and The materials are the same, the second conductive lead 362 and the drain electrode 330 of the switching transistor are provided in the same layer and of the same material; the first conductive lead 361 and the second conductive lead 362 are electrically connected through the via 363 .
  • the array substrate includes a gate layer 130 and a source-drain metal layer 140 sequentially stacked on one side of the base substrate 110 , and the gate layer 130 includes a scan line 350 , a gate electrode 3202 of a switching transistor, and a first conductive lead 361 .
  • the metal layer 140 includes the drain electrode 330 and the second conductive lead 362 ; the first conductive lead 361 and the second conductive lead 362 are electrically connected through the via hole 363 .
  • the data line 360 includes a first conductive lead 361 and a second conductive lead 362 that are alternately connected; the first conductive lead 361 and the active layer 3201 of the switching transistor
  • the second conductive lead 362 and the drain electrode 330 of the switching transistor are provided in the same layer and of the same material; the first conductive lead 361 and the second conductive lead 362 are electrically connected through the via 363 .
  • the array substrate includes the semiconductor layer 120 and the source-drain metal layer 140 sequentially stacked on one side of the base substrate 110 , the semiconductor layer 120 includes the active layer 3201 of the switching transistor and the first conductive lead 361 , and the source-drain metal layer 140 includes the leakage current
  • the pole 330 and the second conductive lead 362 ; the first conductive lead 361 and the second conductive lead 362 are electrically connected through the via 363 .
  • the material of the first conductive lead 361 may be a semiconductor material modified by doping, so that the first conductive lead 361 has good conductivity.
  • the active layer 3201 of the switching transistor may include a channel region 323 and a source contact region 321 and a drain contact region 322 on both sides of the channel region 323, wherein the material of the channel region 323 It is a low temperature polysilicon semiconductor material, and the material of the source contact region 321 and the drain contact region 322 is doped low temperature polysilicon.
  • the material of the first conductive lead 361 is doped low temperature polysilicon.
  • the active layer 3201 of the switching transistor includes a source contact region 321 , a channel region 323 and a drain contact region 322 which are sequentially arranged along a straight line.
  • the active layer 3201 of the switching transistor is arranged in a straight line, which can further reduce the area occupied by the switching transistor 320 , thereby increasing the area of the pixel electrode 310 .
  • the channel direction of the active layer 3201 is the extending direction of the channel region 323 of the active layer 3201 , that is, the connection direction of the source contact region 321 and the drain contact region 322 of the active layer 3201 .
  • the channel direction of the active layer 3201 is consistent with the extending direction of the scan line 350 .
  • the channel direction of the active layer 3201 and the extending direction of the scan line 350 have a predetermined angle.
  • the source contact region 321 is located on the side of the channel region 323 close to the scan line 350 connected to the switching transistor 320
  • the drain contact region 322 is located on the channel region 323 away from the switching transistor 320 The connected scan line 350 side.
  • the distance between the orthographic projection of the pixel electrode 310 on the base substrate 110 and the orthographic projection of the connected scan line 350 on the base substrate 110 is the first dimension; the width of the channel region 323 of the switching transistor is the second size; the first size is not larger than the second size.
  • the width of the channel region 323 of the switching transistor means that the channel region 323 of the switching transistor is in a plane parallel to the plane of the base substrate 110 and is perpendicular to the source contact region 321 and the drain of the switching transistor.
  • the pixel electrode 310 of the sub-pixel can be as close as possible to the scan line 350 connected to the sub-pixel, occupying the avoidance space A in the related art as much as possible, thereby increasing the area of the pixel electrode 310 .
  • the orthographic projection of the switching transistor 320 of the sub-pixel on the base substrate 110 It is located between the orthographic projection of the pixel electrode 310 of the sub-pixel on the base substrate 110 and the orthographic projection of the data line 360 electrically connected to the sub-pixel on the base substrate 110 .
  • the switching transistor 320 of the sub-pixel when viewed from the direction perpendicular to the normal line of the base substrate 110 , the switching transistor 320 of the sub-pixel can be prevented from being disposed between the pixel electrode 310 and the scan line 350 of the sub-pixel, thereby avoiding the position between the pixel electrode 310 and the scan line 350 .
  • a space for avoiding the switching transistor 320 is formed between, so that the area of the pixel electrode 310 is further increased.
  • the channel direction of the active layer 3201 , the extension direction of the scan line 350 and the extension direction of the scan line 350 Orientation is vertical.
  • the extension direction of the connection line between the source contact region 321 and the drain contact region 322 of the switching transistor is perpendicular to the extension direction of the scan line 350 .
  • the size of the switching transistor 320 in the extending direction of the scan line 350 can be reduced, and the avoidance gap 313 of the pixel electrode 310 can be reduced, so that the pixel electrode 310 can be more regular as a whole.
  • the gate electrode 3202 of the switching transistor is also beneficial to set the gate electrode 3202 of the switching transistor at a right angle with the scan line 350 , facilitating the preparation of the gate electrode 3202 of the switching transistor, and improving the accuracy of the pattern of the gate electrode 3202 of the switching transistor.
  • the pixel electrode 310 includes a plurality of strip-shaped sub-electrodes 311 arranged in parallel, and the included angle between the plurality of strip-shaped sub-electrodes 311 and the scan line 350 is not 90 degrees; In the same sub-pixel, the channel direction of the active layer 3201 is consistent with the extending direction of the stripe-shaped sub-electrodes 311 of the pixel electrode.
  • the pixel electrode 310 includes a plurality of strip-shaped sub-electrodes 311 arranged in parallel; in the same sub-pixel, the extension direction of the connection line between the source contact region 321 and the drain contact region 322 of the switching transistor is the same as the extension direction of the strip-shaped sub-electrode 311 parallel. In this way, the direction of the switching transistor 320 is substantially consistent with the edge of the pixel electrode 310 , which can more effectively reduce the space occupied by the switching transistor 320 , thereby increasing the area of the pixel electrode 310 .
  • the array substrate may further be provided with an alignment layer 170 on the side of the pixel electrode 310 away from the base substrate 110 .
  • Embodiments of the present disclosure further provide a display device, which includes any of the array substrates described in the foregoing array substrate embodiments.
  • the display device may be a mobile phone screen, a watch screen, a display or other types of display devices. Since the display device has any of the array substrates described in the above-mentioned embodiments of the array substrate, it has the same beneficial effects, and details are not described here in the present disclosure.
  • the display device includes a color filter substrate 2 arranged in a cell and any array substrate 1 described in the above-mentioned array substrate embodiment, and includes a color filter substrate 2 disposed between the color filter substrate 2 and the array substrate 1 .
  • the display device further includes a backlight module located on the side of the array substrate 1 away from the color filter substrate 2 .
  • the color filter substrate 2 includes a black matrix layer 21 , and the orthographic projection of the black matrix layer 21 on the base substrate 110 covers the frontal projections of the switching transistor 320 and the data line 360 on the base substrate 110 projection. In this way, light transmission at the positions of the switch transistor 320 and the data line 360 can be prevented from affecting the display effect.
  • the array substrate 1 includes a source-drain metal layer 140 and a pixel electrode layer 150 sequentially stacked on one side of the base substrate 110 , wherein the source-drain metal layer 140 Including the second conductive lead 362 and the drain electrode 330 , the pixel electrode layer 150 includes the pixel electrode 310 and the first conductive lead 361 , and the first conductive lead 361 and the second conductive lead 362 are electrically connected through the via hole 363 .
  • the pixel electrode 310 includes a plurality of strip-shaped sub-electrodes 311 arranged in parallel; the first conductive lead 361 arranged adjacent to the pixel electrode 310 includes a first strip-shaped lead segment 3611, and the extension direction of the first strip-shaped lead segment 3611 is the same as the adjacent one.
  • the extending directions of the strip-shaped sub-electrodes 311 of the arranged pixel electrodes 310 are parallel.
  • the color filter substrate 2 includes a black matrix layer 21 , and the orthographic projection of the black matrix layer 21 on the base substrate 110 does not overlap with the orthographic projection of the first strip-shaped lead segment 3611 on the base substrate 110 .
  • the black matrix may not block the position of the first strip-shaped lead segment 3611, so that the light transmitted through the first strip-shaped lead segment 3611 can be emitted outside the display panel, thereby improving the display brightness of the display panel.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列基板和显示装置，属于显示技术领域。该阵列基板包括设于衬底基板（110）上的多条扫描线（350）、多条数据线（360）和阵列设置的子像素，任意一个子像素包括像素电极（310）和开关晶体管（320）；其中，像素电极（310）与开关晶体管（320）的漏电极（330）连接，开关晶体管（320）的栅电极（3202）与一条扫描线（350）连接，开关晶体管（320）的源电极与一条数据线（360）连接；子像素的开关晶体管（320）的有源层（3201）位于子像素的像素电极（310）和子像素连接的数据线（360）之间。该阵列基板能够提高显示面板的透光率。

Description

阵列基板和显示装置
交叉引用
本公开要求于2020年9月11日提交的申请号为202010955164.5、名称为“阵列基板和显示装置”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板和显示装置。
背景技术
液晶显示面板可以包括对盒设置的阵列基板和彩膜基板。相关技术中，参见图1，阵列基板可以包括阵列设置的子像素以及扫描线350和数据线360，其中，任意一个子像素包括像素电极310、开关晶体管320，开关晶体管具有漏电极330。像素电极310连接开关晶体管的漏电极330，数据线360与开关晶体管的源电极连接，扫描线350与开关晶体管320的栅电极连接，开关晶体管的源电极和漏电极的连线平行于扫描线350的延伸方向。
参见图1，对于任意一个子像素，漏电极330设于像素电极310和该子像素所连接的扫描线350之间，这导致像素电极310与扫描线350之间存在较大的避让空间A，使得像素电极310在列方向C上的尺寸减小。该避让空间A不仅仅包括漏电极330所占用的空间，而且包括与漏电极330在行方向B上相邻设置的部分空间，这使得该避让空间A的尺寸远大于漏电极330所占用的空间的尺寸。该避让空间A的存在制约了像素电极310的面积，降低了液晶显示面板的开口率，不利于提高液晶显示面板的透光率。
所述背景技术部分公开的上述信息仅用于加强对本公开的背景的理解，因此它可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
本公开的目的在于提供一种阵列基板和显示装置，提高显示面板的透光率。
为实现上述发明目的，本公开采用如下技术方案：
根据本公开的第一个方面，提供一种阵列基板，包括设于衬底基板上的多条扫描线、多条数据线和阵列设置的多个子像素，任意一个所述子像素包括像素电极和开关晶体管；其中，所述像素电极与所述开关晶体管的漏电极连接，所述开关晶体管的栅电极与一条所述扫描线连接，所述开关晶体管的源电极与一条所述数据线连接；
所述子像素的开关晶体管的有源层位于所述子像素的像素电极和所述子像素连接 的数据线之间。
在本公开的一种示例性实施例中，所述数据线包括多个交替连接的第一导电引线和第二导电引线；
所述第二导电引线沿与所述扫描线交叉的方向延伸，所述第一导电引线在相邻的所述第二导电引线延伸的方向上向远离所述数据线所连接的所述子像素的像素电极的方向弯折成曲线或折线；
所述第一导电引线的第一端与所述第二导电引线的第一端连接，所述第一导电引线的第二端与下一行所述第二导电引线的第二端连接；所述第一导电引线与相邻且电连接的所述子像素的像素电极之间形成有避让区域，所述第二导电引线的第二端的延长线和所述有源层均位于所述避让区域。
在本公开的一种示例性实施例中，所述有源层的沟道方向与所述扫描线的延伸方向有设定夹角。
在本公开的一种示例性实施例中，所述有源层的沟道方向与所述扫描线的延伸方向垂直。
在本公开的一种示例性实施例中，所述子像素中的像素电极包括多个条形子电极，所述多个条形子电极与所述扫描线的夹角为非90度；在同一所述子像素中，所述有源层的沟道方向与所述像素电极的条形子电极的延伸方向一致。
在本公开的一种示例性实施例中，所述有源层的沟道方向与所述扫描线的延伸方向一致。
在本公开的一种示例性实施例中，所述第二导电引线为金属引线；
所述第一导电引线为金属引线或透明金属氧化物引线。
在本公开的一种示例性实施例中，所述第二导电引线与所述开关晶体管的漏电极同层设置且材料相同；
所述第一导电引线与所述像素电极、所述阵列基板的公共电极、所述阵列基板的公共电极线、所述开关晶体管的漏电极、所述扫描线中的一者同层设置且材料相同。
在本公开的一种示例性实施例中，所述子像素中的像素电极包括多个平行设置的条形子电极；
所述第一导电引线为折线，包括依次连接的连接引线段和第一条形引线段；所述连接引线段与所述第二导线引线连接且平行于所述扫描线，所述第一条形引线段与所述像素电极的条形子电极的延伸方向一致且电连接到下一行所述第二导电引线。
在本公开的一种示例性实施例中，所述像素电极具有一凸出部分，所述像素电极的凸出部分位于与所述像素电极相邻设置的所述第一条形引线段的延伸线上；
所述第一条形引线段的延伸方向与相邻设置的所述像素电极的条形子电极的延伸方向平行；所述第一导电引线与所述像素电极同层设置且材料相同。
在本公开的一种示例性实施例中，所述子像素中的像素电极包括多个条形子电极；
所述第二导电引线包括第二条形引线段，所述第二条形引线段的延伸方向与相邻设置的所述像素电极的条形子电极的延伸方向平行。
根据本公开的第二个方面，提供一种显示装置，包括上述的阵列基板。
本公开提供的阵列基板和显示装置中，子像素的漏电极设于像素电极和数据线之间，避免了将漏电极设于像素电极和扫描线之间，进而可以实现对相关技术中的避让空间的利用而增大像素电极的面积，有利于提高应用该阵列基板的显示面板的透光率。
附图说明
通过参照附图详细描述其示例实施方式，本公开的上述和其它特征及优点将变得更加明显。
图1是相关技术中阵列基板的俯视结构示意图。
图2是本公开实施方式的阵列基板的俯视结构示意图。
图3是本公开一种实施方式的阵列基板的俯视结构示意图。
图4是图3所示的阵列基板在DE位置的剖切结构示意图。
图5是本公开一种实施方式的阵列基板的俯视结构示意图。
图6是本公开一种实施方式的阵列基板的俯视结构示意图。
图7是图6所示的阵列基板在DE位置的剖切结构示意图。
图8是本公开一种实施方式的阵列基板的俯视结构示意图。
图9是图8所示的阵列基板在DE位置的剖切结构示意图。
图10是本公开一种实施方式的阵列基板的俯视结构示意图。
图11是图10所示的阵列基板在DE位置的剖切结构示意图。
图12是本公开一种实施方式的阵列基板的俯视结构示意图。
图13是图12所示的阵列基板在DE位置的剖切结构示意图。
图14是本公开一种实施方式的阵列基板的俯视结构示意图。
图15是本公开一种实施方式中开关晶体管的有源层的俯视结构示意图。
图16是本公开一种实施方式中显示装置的剖视结构示意图。
图中主要元件附图标记说明如下：
1、阵列基板；110、衬底基板；120、半导体层；130、栅极层；140、源漏金属层；150、像素电极层；160、公共电极层；161、避让开口；170、取向层；210、栅极绝缘层；220、层间电介质层；230、平坦化层；240、绝缘介质层；310、像素电极；311、条形子电极；312、镂空狭缝；313、避让缺口；314、凸出部分；320、开关晶体管；3201、开关晶体管的有源层；321、开关晶体管的源极接触区；322、开关晶体管的漏极接触区；323、开关晶体管的沟道区；3202、开关晶体管的栅电极；330、漏电极；340、公共电极；350、扫描线；360、数据线；361、第一导电引线；3611、第一条形引线段；3612、连接引线段；362、第二导电引线；3621、第二条形引线段；363、过 孔；2、彩膜基板；21、黑矩阵层；3、液晶层；A、避让空间；B、行方向；C、列方向；D、避让区域。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。
在图中，为了清晰，可能夸大了区域和层的厚度。在图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而没有所述特定细节中的一个或更多，或者可以采用其它的方法、组元、材料等。在其它情况下，不详细示出或描述公知结构、材料或者操作以避免模糊本公开的主要技术创意。
当某结构与其它结构“连接”时，有可能是指某结构与其它结构是一体的，或者某结构与其它结构“直接”的连接，或者某结构与其它结构通过另外的结构“间接”的连接。当某结构与另一结构“电连接”时，有可能是指某结构与另一结构“直接的”电性连接，也可能是指某结构与另一结构通过可导电的其他结构“间接”的电性连接。用语“一个”用以表示存在一个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。用语“第一”和“第二”等仅作为标记使用，不是对其对象的数量限制。
本公开中的“同层设置”是指两个结构是由同一个材料层经过构图工艺形成的，故二者在在层叠关系上是处于同一个层之中的，但这并不表示二者与衬底基板间的距离必定相同。
本公开提供一种阵列基板，该阵列基板可以应用于液晶显示面板中。参见图2～图15，该阵列基板包括设于衬底基板110上的多条扫描线350、多条数据线360和阵列设置的多个子像素，任意一个子像素包括像素电极310和开关晶体管320；其中，像素电极310与开关晶体管320的漏电极330连接，开关晶体管320的栅电极3202与一条扫描线350连接，开关晶体管320的源电极与一条数据线360连接；子像素的开关晶体管320的有源层3201位于子像素的像素电极310和子像素连接的数据线360之间。
本公开提供的阵列基板中，子像素的开关晶体管320的有源层3201设于像素电极310和数据线360之间，避免了将开关晶体管320设于像素电极310和扫描线350之间，进而可以实现对相关技术中的避让空间A的利用而增大像素电极310的面积，有 利于提高应用该阵列基板的显示面板的透光率。
下面，结合附图对本公开的阵列基板的结构、原理和效果做进一步的解释和说明。
本公开提供的阵列基板中，子像素的开关晶体管320的有源层3201在衬底基板110上的正投影，位于子像素的像素电极310在衬底基板110上的正投影和与子像素电连接的数据线360在衬底基板110上的正投影之间。
参见图2，本公开提供的阵列基板中，从垂直于衬底基板110的方向上观察，任意一个子像素的漏电极330位于该子像素的像素电极310和该子像素所连接的数据线360之间，而非设置于子像素的像素电极310与该子像素所连接的扫描线350之间，因此子像素的像素电极310与该子像素连接的扫描线350之间不必设置相关技术中的避让空间A，子像素的像素电极310可以覆盖相关技术中的避让空间A而增大像素电极310的面积。
进一步地，参见图2，从垂直于衬底基板110的方向上观察，漏电极330和有源层3201占用了原本用于设置数据线360的部分空间，使得数据线360需要通过弯折以避让漏电极330和有源层3201。因此，这会使得像素电极310具有一避让缺口313；由于相关技术中的避让空间A的尺寸远大于漏电极330和有源层3201的尺寸，因此本公开的像素电极310因占用相关技术中的避让空间A而增加的面积，大于因设置避让缺口313而损失的面积，使得像素电极310的面积相较于相关技术增大。
示例性地，参见图2，本公开提供的阵列基板中，像素电极310具有避让缺口313；在同一子像素中，避让缺口313位于像素电极310远离漏电极330和有源层3201的一侧，且位于像素电极310靠近该子像素所连接的扫描线350的一侧；与子像素相邻设置且远离子像素的漏电极330的第一导电引线361在衬底基板110上的正投影，至少部分位于子像素的避让缺口313在衬底基板110上的正投影内。换言之，像素电极310具有一凸出部分314，像素电极310的凸出部分314位于像素电极310远离所电连接的扫描线350的一侧且位于像素电极310远离所电连接的数据线360的一侧。本公开提供的阵列基板可以包括依次层叠的衬底基板110、驱动电路层和像素电极层150，其中，驱动电路层包括阵列基板的开关晶体管320和扫描线350；像素电极层150包括阵列基板的像素电极310。可以理解的是，像素电极310为透明电极。开关晶体管320可以为金属-氧化物-半导体场效应管(metal-oxide-semiconductor FET，简称MOS-FET)。进一步地，开关晶体管320为一薄膜晶体管。在膜层结构上，开关晶体管320可以为顶栅型开关晶体管320或者底栅型开关晶体管320，本公开对此不做限制。在开关晶体管320的半导体层120的材料上，开关晶体管320可以为非晶硅开关薄膜晶体管、低温多晶硅薄膜晶体管、氧化物薄膜晶体管或者有机半导体薄膜晶体管，本公开对此不做限制。在开关晶体管320的导通条件上，开关晶体管320可以为N型开关晶体管320或者P型开关晶体管320，本公开对此也不做限制。
可选地，参见图4、图9、图11和图13，驱动电路层可以包括层叠的栅极层130、 栅极绝缘层210、半导体层120、层间电介质层220、源漏金属层140、平坦化层230等膜层。其中，各个膜层的位置关系可以根据开关晶体管320的膜层结构确定。举例而言，在本公开的一种实施方式中，驱动电路层可以包括依次层叠设置的半导体层120、栅极绝缘层210、栅极层130、层间电介质层220和源漏金属层140，如此所形成的开关晶体管320为顶栅型薄膜晶体管。再举例而言，在本公开的另一种实施方式中，驱动电路层可以包括依次层叠设置的栅极层130、栅极绝缘层210、有源层、层间电介质层220和源漏金属层140，如此所形成的开关晶体管320为底栅型薄膜晶体管。
在一些实施方式中，漏电极330位于阵列基板的源漏金属层140。
在一些实施方式中，扫描线350位于阵列基板的栅极层130。
在一些实施方式中，开关晶体管320为底栅型金属氧化物薄膜晶体管。
在一些实施方式中，参见图4、图9、图11和图13，阵列基板还可以包括公共电极层160，公共电极层160可以包括各个子像素的公共电极340，公共电极340可以为叉指电极、平板电极、狭缝电极或者其他形状的电极。公共电极层160可以设置于像素电极层150与驱动电路层之间，或者设置于像素电极层150远离驱动电路层的一侧。在本公开的一种实施方式中，参见图4、图9、图11和图13，公共电极层160设于像素电极层150与驱动电路层之间，公共电极层160与驱动电路层的源漏金属层140之间设置有平坦化层230，公共电极层160与像素电极层150之间设置有绝缘介质层240。在本公开的另一种实施方式中，参见图4、图9、图11和图13，公共电极层160中，公共电极340为平板电极，即公共电极340没有设置镂空结构，例如没有设置狭缝等。在本公开的另一种实施方式中，公共电极层160还包括公共电极线，相邻设置的公共电极340之间可以通过公共电极线相互连接。
可选地，公共电极340和像素电极310均为透明电极，其材料可以为透明金属氧化物。
可选地，任意一条数据线360可以包括交替设置且依次电连接的第一导电引线361和第二导电引线362，第一导电引线361与第二导电引线362同层设置或者通过过孔363电连接。图2为本公开提供的阵列基板的俯视图。在图2中，仅示出了像素电极310、开关晶体管320、漏电极330、扫描线350和数据线360。其中，在图2中，数据线360仅仅给出了其在衬底基板110上的正投影的位置，并未体现其在膜层上的结构。即，在图2中，数据线360既可以包括同层设置的第一导电引线361和第二导电引线362，也可以包括设于两个不同的膜层且通过过孔363连接的第一导电引线361和第二导电引线362。
可选地，阵列基板包括多行子像素；任意一条数据线360包括与各行子像素一一对应的导电引线组，其中，一个导电引线组包括相邻连接的一个第一导电引线361和一个第二导电引线362。如此，各个子像素与各个导电引线组一一对应设置，一个子像素与对应的导电引线组相邻设置且直接或者间接地电连接。换言之，一个子像素与 对应的导电引线组相邻设置，且与对应的导电引线组所在的数据线360电连接。进一步地，第一导电引线361的第一端与第二导电引线362的第一端电连接，第一导电引线361的第二端与下一行第二导电引线362的第二端电连接，第二导电引线362的第二端与第一导电引线361的第二端电连接。在本公开的一种实施方式中，一个子像素的开关晶体管的源电极与对应的导电引线组的下一行的第二导电引线362电连接。
在本公开的一种实施方式中，参见图2，第二导电引线362沿与扫描线350交叉的方向延伸，第一导电引线361在相邻的第二导电引线362延伸的方向上向远离数据线360所连接的子像素的像素电极310的方向弯折成曲线或折线；第一导电引线361的第一端与第二导电引线362的第一端连接，第一导电引线361的第二端与下一行第二导电引线362的第二端连接；第一导电引线361与相邻且电连接的子像素的像素电极310之间形成有避让区域D，第二导电引线362的第二端的延长线和有源层3201均位于避让区域D。在一些实施方式中，第二导电引线362为金属引线；第一导电引线361为金属引线或透明金属氧化物引线。当然的，在其他实施方式中，第一导电引线361的材料还可以是重掺杂的半导体材料。进一步地，在一些实施方式中，第二导电引线362与开关晶体管320的漏电极330同层设置且材料相同；第一导电引线361与像素电极310、阵列基板的公共电极、阵列基板的公共电极线、开关晶体管310的漏电极330、扫描线350中的一者同层设置且材料相同。
可选地，参见图4、图9、图11和图13，第二导电引线362位于源漏金属层140，即第二导电引线362与漏电极330同层设置且材料相同，第二导电引线362为金属引线。进一步地，参见图3、图5、图6、图8、图10、图12、图14，第二导电引线362在衬底基板110上的正投影，与扫描线350在衬底基板110上的正投影交叠。换言之，数据线360可以包括多个依次交替连接的第一导电引线361和第二导电引线362；其中，第一导电引线361在衬底基板110上的正投影与扫描线350在衬底基板110上的正投影不交叠；且第二导电引线362在衬底基板110上的正投影，与扫描线350在衬底基板110上的正投影交叠。
可选地，参见图3、图5、图6、图8、图10、图12、图14，像素电极310包括多个平行设置的条形子电极311；与像素电极310相邻设置的第二导电引线362包括第二条形引线段3621，第二条形引线段3621的延伸方向与相邻设置的像素电极310的条形子电极311的延伸方向平行。如此，可以使得像素电极310的形状和数据线360的走向之间相互配合，进而减小因设置数据线360而损失的像素电极310的面积，提高像素电极310的面积。
条形子电极311的延伸方向与扫描线350的延伸方向相交，例如两者之间的夹角可以为75°～90°。相邻两行子像素的条形子电极311的延伸方向可以相同，也可以不相同。举例而言，在本公开的一种实施方式中，子像素中的像素电极310包括多个条形子电极311，多个条形子电极311与扫描线的夹角为非90度。示例性地，相邻两 行子像素的条形子电极311的延伸方向相同，且与扫描线350的延伸方向相交成75°～85°的锐角。再举例而言，在本公开的另一种实施方式中，各个子像素的条形子电极311的延伸方向与扫描线350的延伸方向垂直。再举例而言，在本公开的另一种实施方式中，相邻两行子像素的条形子电极311的延伸方向相对于扫描线350的延伸方向对称，且均与扫描线350的延伸方向相交成75°～85°的锐角。
可选地，第一导电引线361为折线，包括依次连接的连接引线段3612和第一条形引线段3611；连接引线段3612与第二导线引线362连接且平行于扫描线350，第一条形引线段3611与像素电极的条形子电极311的延伸方向一致且电连接到下一行第二导电引线362。
可选地，第一导电引线361和第二导电引线362可以设于同一层，也可以设于不同层。相应的，数据线360可以仅设置于驱动电路层，也可以部分设于驱动电路层且部分设于像素电极层150，还可以部分设于驱动电路层且部分设于公共电极层160。在本公开的一种实施方式中，参见图3和图4，数据线360包括交替连接的第一导电引线361和第二导电引线362；第一导电引线361与像素电极310同层设置且材料相同，第二导电引线362与开关晶体管的漏电极330同层设置且材料相同；第一导电引线361和第二导电引线362通过过孔363电连接。换言之，阵列基板包括依次层叠于衬底基板110一侧的源漏金属层140和像素电极层150，其中，源漏金属层140包括第二导电引线362和漏电极330，像素电极层150包括像素电极310和第一导电引线361，第一导电引线361和第二导电引线362通过过孔363电连接。
可选地，在该实施方式中，参见图3和图4，像素电极310包括多个平行设置的条形子电极311；与像素电极310相邻设置的第一导电引线361包括第一条形引线段3611，第一条形引线段3611的延伸方向与相邻设置的像素电极310的条形子电极311的延伸方向平行。如此，通过调整第一条形引线段3611与相邻的像素电极310之间的距离，在显示面板的显示阶段，可以使得该第一条形引线段3611相当于另一个公共电极；像素电极310与相邻的第一条形引线段3611之间可以形成有电场且该电场的强度和分布与该像素电极310本身的电动势相关，进而可以使得该像素电极310与相邻的第一条形引线段3611之间区域的透光率与子像素本身的透光率相关。因此，该第一条形引线段3611与相邻的像素电极310之间的区域的透光率可以随着相邻的子像素的透光率的改变而相应改变，进而可以提高相邻子像素的总透光量，进而提高显示面板的显示亮度。不仅如此，位于同一数据线360上的不同第一条形引线段3611，可以分别与各自相邻的像素电极310配合而各自独立地改变各自周围的电场分布，使得第一条形引线段3611既可以用于增强子像素的出光强度，又可以避免显示面板所显示的画面出现明显的色偏。
进一步可选地，在该实施方式中，参见图3和图4，像素电极310包括交替设置的镂空狭缝312和条形子电极311；沿扫描线350的延伸方向，相邻设置的一个镂空 狭缝312和一个条形子电极311的总尺寸为第三尺寸d3；沿扫描线350的延伸方向，第一条形引线段3611远离相邻的像素电极310的边缘与该像素电极310靠近第一条形引线段3611的边缘之间的尺寸为第四尺寸d4。第四尺寸d4等于第三尺寸d3的0.5～3倍。优选地，第四尺寸d4等于第三尺寸d3的0.8～1.2倍。
进一步可选地，在该实施方式中，第三尺寸d3为6～10微米，第四尺寸d4为6～10微米。
进一步可选地，在该实施方式中，第一条形引线段3611与相邻的像素电极310之间的距离，等于像素电极310的镂空狭缝312的宽度的0.5～3倍。优选地，第一条形引线段3611与相邻的像素电极310之间的距离，等于像素电极310的镂空狭缝312的宽度的0.8～1.2倍。
可选地，在该实施方式中，参见图4和图5(图5中未示出公共电极340)，子像素还包括公共电极，沿行方向B相邻的两个子像素的公共电极之间具有避让开口161(图5中虚线位置)；第一导电引线361在衬底基板110上的正投影，位于避让开口161在衬底基板110上的正投影内。如此，可以减弱公共电极340对第一导电引线361的耦合作用，使得显示面板在扫描阶段时，第一导电引线361引起的与相邻子像素的透光率不相关的漏光减弱，进而提高显示面板显示的画面的准确性，提高显示品质。
示例性地，子像素中的像素电极310包括多个平行设置的条形子电极311；第一导电引线361为折线，包括依次连接的连接引线段和第一条形引线段3611；连接引线段与第二导线引线362连接且平行于扫描线350，第一条形引线段3611与像素电极的条形子电极311的延伸方向一致且电连接到下一行第二导电引线362。像素电极310具有一凸出部分314，像素电极310的凸出部分314位于与像素电极310相邻设置的第一条形引线段3611的延伸线上；第一条形引线段3611的延伸方向与相邻设置的像素电极310的条形子电极311的延伸方向平行；第一导电引线361与像素电极310同层设置且材料相同。
在本公开的另一种实施方式中，参见图6和图7，子像素还包括公共电极340；数据线360包括交替连接的第一导电引线361和第二导电引线362；第一导电引线361与公共电极340同层设置且材料相同，第二导电引线362与开关晶体管的漏电极330同层设置且材料相同；第一导电引线361和第二导电引线362通过过孔363电连接。换言之，子像素还包括公共电极340；阵列基板包括依次层叠于衬底基板110一侧的源漏金属层140和公共电极层160，源漏金属层140包括漏电极330和第二导电引线362；公共电极层160包括公共电极340和第一导电引线361；第一导电引线361和第二导电引线362通过过孔363电连接。
在本公开的另一种实施方式中，参见图8和图9，数据线360与开关晶体管的漏电极330同层设置且材料相同。换言之，阵列基板包括设于衬底基板110一侧的源漏金属层140，源漏金属层140包括漏电极330、相互连接的第一导电引线361和第二导 电引线362。
在本公开的另一种实施方式中，参见图10和图11，数据线360包括交替连接的第一导电引线361和第二导电引线362；第一导电引线361与扫描线350同层设置且材料相同，第二导电引线362与开关晶体管的漏电极330同层设置且材料相同；第一导电引线361和第二导电引线362通过过孔363电连接。换言之，阵列基板包括依次层叠于衬底基板110一侧的栅极层130和源漏金属层140，栅极层130包括扫描线350、开关晶体管的栅电极3202和第一导电引线361，源漏金属层140包括漏电极330和第二导电引线362；第一导电引线361和第二导电引线362通过过孔363电连接。
在本公开的另一种实施方式中，参见图12和图13，数据线360包括交替连接的第一导电引线361和第二导电引线362；第一导电引线361与开关晶体管的有源层3201同层设置，第二导电引线362与开关晶体管的漏电极330同层设置且材料相同；第一导电引线361和第二导电引线362通过过孔363电连接。换言之，阵列基板包括依次层叠于衬底基板110一侧的半导体层120和源漏金属层140，半导体层120包括开关晶体管的有源层3201和第一导电引线361，源漏金属层140包括漏电极330和第二导电引线362；第一导电引线361和第二导电引线362通过过孔363电连接。
可选地，在该实施方式中，第一导电引线361的材料可以为通过掺杂改性后的半导体材料，使得第一导电引线361具有良好的导电率。示例性地，参见图15，开关晶体管的有源层3201可以包括沟道区323和位于沟道区323两侧的源极接触区321和漏极接触区322，其中，沟道区323的材料为低温多晶硅半导体材料，源极接触区321和漏极接触区322的材料为掺杂的低温多晶硅。第一导电引线361的材料为掺杂的低温多晶硅。
可选地，参见图15，开关晶体管的有源层3201包括沿直线依次排列的源极接触区321、沟道区323和漏极接触区322。如此，该开关晶体管的有源层3201呈一字型直线设置，能够进一步减小开关晶体管320的所占用的面积，进而提高像素电极310的面积。其中，有源层3201的沟道方向为有源层3201的沟道区323延伸方向，亦即有源层3201的源极接触区321和漏极接触区322的连线方向。
在一些实施方式中，有源层3201的沟道方向与扫描线350的延伸方向一致。
在另一些实施方式中，有源层3201的沟道方向与扫描线350的延伸方向有设定夹角。
在本公开的一种实施方式中，源极接触区321位于沟道区323靠近该开关晶体管320所连接的扫描线350一侧，漏极接触区322位于该沟道区323远离该开关晶体管320所连接的扫描线350一侧。
可选地，像素电极310在衬底基板110上的正投影，与相连的扫描线350在衬底基板110上的正投影之间的间距为第一尺寸；开关晶体管的沟道区323的宽度为第二尺寸；第一尺寸不大于第二尺寸。其中，开关晶体管的沟道区323的宽度，指的是开 关晶体管的沟道区323在平行于衬底基板110所在平面的平面内，且在垂直于开关晶体管的源极接触区321和漏极接触区322连线的方向上的尺寸。如此，子像素的像素电极310可以尽量靠近子像素连接的扫描线350，尽量占用相关技术中的避让空间A，进而提高像素电极310的面积。
可选的，参见图3、图5、图6、图8、图10、图12、图14，本公开提供的阵列基板中，子像素的开关晶体管320在衬底基板110上的正投影，位于子像素的像素电极310在衬底基板110上的正投影和与子像素电连接的数据线360在衬底基板110上的正投影之间。如此，从垂直于衬底基板110的法线方向观察，可以避免子像素的开关晶体管320设置于该子像素的像素电极310和扫描线350之间，进而避免在像素电极310与扫描线350之间形成避让开关晶体管320的空间，便于像素电极310的面积进一步增大。
在本公开的一种实施方式中，参见图3、图5、图6、图8、图10、图12，有源层3201的沟道方向与扫描线350的延伸方向与扫描线350的延伸方向垂直。换言之，开关晶体管的源极接触区321和漏极接触区322的连线的延伸方向，与扫描线350的延伸方向垂直。如此，可以使得开关晶体管320在扫描线350延伸方向的尺寸减小，进而可以减小像素电极310的避让缺口313，使得像素电极310在整体上更为规整。不仅如此，这也可以利于开关晶体管的栅电极3202与扫描线350之间呈直角设置，便于开关晶体管的栅电极3202的制备，可以提高开关晶体管的栅电极3202图案的准确性。
在另外本公开的一种实施方式中，参见图14，像素电极310包括多个平行设置的条形子电极311，多个条形子电极311与扫描线350的夹角为非90度；在同一子像素中，有源层3201的沟道方向与像素电极的条形子电极311的延伸方向一致。像素电极310包括多个平行设置的条形子电极311；同一子像素中，开关晶体管的源极接触区321和漏极接触区322的连线的延伸方向，与条形子电极311的延伸方向平行。如此，开关晶体管320的走向与像素电极310的边缘基本一致，能够更有效减小开关晶体管320所占用的空间，进而提高像素电极310的面积。
可选地，参见图4、图9、图11和图13，阵列基板在像素电极310远离衬底基板110的一侧还可以设置有取向层170。
本公开实施方式还提供一种显示装置，该显示装置包括上述阵列基板实施方式所描述的任意一种阵列基板。该显示装置可以为手机屏幕、手表屏幕、显示器或者其他类型的显示装置。由于该显示装置具有上述阵列基板实施方式所描述的任意一种阵列基板，因此具有相同的有益效果，本公开在此不再赘述。
可选的，参见图16，该显示装置包括对盒设置的彩膜基板2和上述阵列基板实施方式所描述的任意一种阵列基板1，以及包括设于彩膜基板2与阵列基板1之间的液晶层3。进一步地，该显示装置还包括位于所述阵列基板1远离彩膜基板2一侧的背光模组。
在本公开的一种实施方式中，彩膜基板2包括黑矩阵层21，黑矩阵层21在衬底基板110上的正投影，覆盖开关晶体管320和数据线360在衬底基板110上的正投影。如此，可以避免开关晶体管320和数据线360位置处透光而影响显示效果。
在本公开的另一种实施方式中，参见图3和图4，阵列基板1包括依次层叠于衬底基板110一侧的源漏金属层140和像素电极层150，其中，源漏金属层140包括第二导电引线362和漏电极330，像素电极层150包括像素电极310和第一导电引线361，第一导电引线361和第二导电引线362通过过孔363电连接。像素电极310包括多个平行设置的条形子电极311；与像素电极310相邻设置的第一导电引线361包括第一条形引线段3611，第一条形引线段3611的延伸方向与相邻设置的像素电极310的条形子电极311的延伸方向平行。
参见图16，彩膜基板2包括黑矩阵层21，黑矩阵层21在衬底基板110上的正投影，与第一条形引线段3611在衬底基板110上的正投影不交叠。如此，黑矩阵可以不遮挡第一条形引线段3611位置，进而可以使得第一条形引线段3611位置透光的光线出射至显示面板以外，进而提高显示面板的显示亮度。
应可理解的是，本公开不将其应用限制到本说明书提出的部件的详细结构和布置方式。本公开能够具有其他实施方式，并且能够以多种方式实现并且执行。前述变形形式和修改形式落在本公开的范围内。应可理解的是，本说明书公开和限定的本公开延伸到文中和/或附图中提到或明显的两个或两个以上单独特征的所有可替代组合。所有这些不同的组合构成本公开的多个可替代方面。本说明书的实施方式说明了已知用于实现本公开的最佳方式，并且将使本领域技术人员能够利用本公开。

Claims (12)

  1. 一种阵列基板，包括设于衬底基板上的多条扫描线、多条数据线和阵列设置的多个子像素，任意一个所述子像素包括像素电极和开关晶体管；其中，所述像素电极与所述开关晶体管的漏电极连接，所述开关晶体管的栅电极与一条所述扫描线连接，所述开关晶体管的源电极与一条所述数据线连接；
    所述子像素的开关晶体管的有源层位于所述子像素的像素电极和所述子像素连接的数据线之间。
  2. 根据权利要求1所述的阵列基板，其中，所述数据线包括多个交替连接的第一导电引线和第二导电引线；
    所述第二导电引线沿与所述扫描线交叉的方向延伸，所述第一导电引线在相邻的所述第二导电引线延伸的方向上向远离所述数据线所连接的所述子像素的像素电极的方向弯折成曲线或折线；
    所述第一导电引线的第一端与所述第二导电引线的第一端连接，所述第一导电引线的第二端与下一行所述第二导电引线的第二端连接；所述第一导电引线与相邻且电连接的所述子像素的像素电极之间形成有避让区域，所述第二导电引线的第二端的延长线和所述有源层均位于所述避让区域。
  3. 根据权利要求1所述的阵列基板，其中，所述有源层的沟道方向与所述扫描线的延伸方向有设定夹角。
  4. 根据权利要求3所述的阵列基板，其中，所述有源层的沟道方向与所述扫描线的延伸方向垂直。
  5. 根据权利要求3所述的阵列基板，其中，所述子像素中的像素电极包括多个条形子电极，所述多个条形子电极与所述扫描线的夹角为非90度；在同一所述子像素中，所述有源层的沟道方向与所述像素电极的条形子电极的延伸方向一致。
  6. 根据权利要求1所述的阵列基板，其中，所述有源层的沟道方向与所述扫描线的延伸方向一致。
  7. 根据权利要求2所述的阵列基板，其中，所述第二导电引线为金属引线；
    所述第一导电引线为金属引线或透明金属氧化物引线。
  8. 根据权利要求2所述的阵列基板，其中，所述第二导电引线与所述开关晶体管的漏电极同层设置且材料相同；
    所述第一导电引线与所述像素电极、所述阵列基板的公共电极、所述阵列基板的公共电极线、所述开关晶体管的漏电极、所述扫描线中的一者同层设置且材料相同。
  9. 根据权利要求2所述的阵列基板，其中，所述子像素中的像素电极包括多个平行设置的条形子电极；
    所述第一导电引线为折线，包括依次连接的连接引线段和第一条形引线段；所述连接引线段与所述第二导线引线连接且平行于所述扫描线，所述第一条形引线段与所 述像素电极的条形子电极的延伸方向一致且电连接到下一行所述第二导电引线。
  10. 根据权利要求9所述的阵列基板，其中，所述像素电极具有一凸出部分，所述像素电极的凸出部分位于与所述像素电极相邻设置的所述第一条形引线段的延伸线上；
    所述第一条形引线段的延伸方向与相邻设置的所述像素电极的条形子电极的延伸方向平行；所述第一导电引线与所述像素电极同层设置且材料相同。
  11. 根据权利要求2所述的阵列基板，其中，所述子像素中的像素电极包括多个条形子电极；
    所述第二导电引线包括第二条形引线段，所述第二条形引线段的延伸方向与相邻设置的所述像素电极的条形子电极的延伸方向平行。
  12. 一种显示装置，包括上述的阵列基板。
PCT/CN2021/111923 2020-09-11 2021-08-11 阵列基板和显示装置 WO2022052722A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/913,465 US20230134406A1 (en) 2020-09-11 2021-08-11 Array substrate and display apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010955164.5 2020-09-11
CN202010955164.5A CN112034656B (zh) 2020-09-11 2020-09-11 阵列基板和显示装置

Publications (1)

Publication Number Publication Date
WO2022052722A1 true WO2022052722A1 (zh) 2022-03-17

Family

ID=73588912

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/111923 WO2022052722A1 (zh) 2020-09-11 2021-08-11 阵列基板和显示装置

Country Status (3)

Country Link
US (1) US20230134406A1 (zh)
CN (1) CN112034656B (zh)
WO (1) WO2022052722A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112034656B (zh) * 2020-09-11 2022-08-26 合肥鑫晟光电科技有限公司 阵列基板和显示装置
CN114815417B (zh) * 2021-01-27 2023-11-03 京东方科技集团股份有限公司 阵列基板和显示面板
CN114815416B (zh) * 2021-01-27 2023-10-03 京东方科技集团股份有限公司 阵列基板和显示面板
CN113555373B (zh) * 2021-07-12 2022-10-04 厦门天马微电子有限公司 一种显示面板及显示装置
CN114005855B (zh) * 2021-09-28 2022-07-22 惠科股份有限公司 阵列基板、显示面板及面板坏点修复方法

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100207846A1 (en) * 2009-02-18 2010-08-19 Byoung-Sun Na Thin-film transistor panel
KR20110076016A (ko) * 2009-12-29 2011-07-06 엘지디스플레이 주식회사 액정 표시 패널 및 그 제조 방법
CN203337963U (zh) * 2013-04-18 2013-12-11 合肥京东方光电科技有限公司 一种阵列基板以及液晶显示装置
CN104637958A (zh) * 2015-03-11 2015-05-20 京东方科技集团股份有限公司 阵列基板及显示装置
CN105093762A (zh) * 2015-09-28 2015-11-25 京东方科技集团股份有限公司 阵列基板、制造方法以及相应的显示面板和电子装置
CN106980422A (zh) * 2015-12-31 2017-07-25 乐金显示有限公司 具有内置触摸屏的显示装置及其制造方法
CN108490705A (zh) * 2018-04-13 2018-09-04 上海中航光电子有限公司 阵列基板、液晶显示面板与显示装置
CN110262146A (zh) * 2019-06-17 2019-09-20 深圳市华星光电技术有限公司 显示面板的十字线修复方法及显示面板
CN110308600A (zh) * 2019-06-29 2019-10-08 上海天马微电子有限公司 阵列基板、显示面板和显示装置
CN112034656A (zh) * 2020-09-11 2020-12-04 合肥鑫晟光电科技有限公司 阵列基板和显示装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4552239B2 (ja) * 1999-05-12 2010-09-29 ソニー株式会社 表示用薄膜半導体素子及び表示装置
KR20070028142A (ko) * 2005-09-07 2007-03-12 삼성전자주식회사 액정 표시 장치
CN101556417B (zh) * 2008-04-11 2010-12-01 北京京东方光电科技有限公司 Ffs型tft-lcd阵列基板结构及其制造方法
CN101995700B (zh) * 2009-08-10 2012-07-18 北京京东方光电科技有限公司 液晶面板及其制造方法
CN104122694A (zh) * 2013-06-06 2014-10-29 深超光电（深圳）有限公司 液晶显示器的阵列基板及其制造方法
US20200089066A1 (en) * 2018-09-17 2020-03-19 Chongqing Hkc Optoelectronics Technology Co., Ltd. Array substrate, display panel, and display device

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100207846A1 (en) * 2009-02-18 2010-08-19 Byoung-Sun Na Thin-film transistor panel
KR20110076016A (ko) * 2009-12-29 2011-07-06 엘지디스플레이 주식회사 액정 표시 패널 및 그 제조 방법
CN203337963U (zh) * 2013-04-18 2013-12-11 合肥京东方光电科技有限公司 一种阵列基板以及液晶显示装置
CN104637958A (zh) * 2015-03-11 2015-05-20 京东方科技集团股份有限公司 阵列基板及显示装置
CN105093762A (zh) * 2015-09-28 2015-11-25 京东方科技集团股份有限公司 阵列基板、制造方法以及相应的显示面板和电子装置
CN106980422A (zh) * 2015-12-31 2017-07-25 乐金显示有限公司 具有内置触摸屏的显示装置及其制造方法
CN108490705A (zh) * 2018-04-13 2018-09-04 上海中航光电子有限公司 阵列基板、液晶显示面板与显示装置
CN110262146A (zh) * 2019-06-17 2019-09-20 深圳市华星光电技术有限公司 显示面板的十字线修复方法及显示面板
CN110308600A (zh) * 2019-06-29 2019-10-08 上海天马微电子有限公司 阵列基板、显示面板和显示装置
CN112034656A (zh) * 2020-09-11 2020-12-04 合肥鑫晟光电科技有限公司 阵列基板和显示装置

Also Published As

Publication number Publication date
CN112034656B (zh) 2022-08-26
US20230134406A1 (en) 2023-05-04
CN112034656A (zh) 2020-12-04

Similar Documents

Publication Publication Date Title
WO2022052722A1 (zh) 阵列基板和显示装置
CN108010947B (zh) 一种有机发光显示面板和有机发光显示装置
US10431605B2 (en) Thin film transistor array panel and manufacturing method thereof
JP6373596B2 (ja) 液晶表示装置
US7932986B2 (en) Liquid crystal display comprising a first signal line including a first portion and second portion, wherein the cross-section of the second portion is thinner than the cross-section of the first portion, and wherein a spacer overlaps the second portion
US6320221B1 (en) TFT-LCD having a vertical thin film transistor
KR102007833B1 (ko) 프린지 필드 스위칭 모드 액정표시장치용 어레이 기판
KR102174136B1 (ko) 어레이 기판 및 이를 갖는 액정표시패널
US7355665B2 (en) Thin film transistor array panel and liquid crystal display including the panel
US10139681B2 (en) Array substrate and liquid crystal display device
KR20180094476A (ko) 디스플레이 장치
CN112859463A (zh) 一种显示面板及显示装置
WO2020098034A1 (zh) 显示面板及显示装置
WO2021073253A1 (zh) 薄膜晶体管及其制作方法、阵列基板和显示装置
CN113113425A (zh) 阵列基板及显示面板
KR20160085705A (ko) 디스플레이 패널
CN102446913A (zh) 阵列基板及其制造方法和液晶显示器
CN113568230B (zh) 阵列基板及制作方法、显示面板
CN113467145B (zh) 阵列基板及制作方法、显示面板
CN111627936B (zh) 一种阵列基板及其制备方法和远程触控液晶显示装置
US9285638B2 (en) Liquid crystal display
CN104122721A (zh) 像素结构
KR20110003723A (ko) 표시장치용 어레이 기판
US5777703A (en) Active matrix type liquid crystal display apparatus with a projection part in the drain line
KR102081604B1 (ko) 액정표시장치

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21865778

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21865778

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 20.11.2023)