WO2022052688A1 - 用于显示装置的保护电路及其显示装置以及使用保护电路保护显示装置方法 - Google Patents
用于显示装置的保护电路及其显示装置以及使用保护电路保护显示装置方法 Download PDFInfo
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- WO2022052688A1 WO2022052688A1 PCT/CN2021/110791 CN2021110791W WO2022052688A1 WO 2022052688 A1 WO2022052688 A1 WO 2022052688A1 CN 2021110791 W CN2021110791 W CN 2021110791W WO 2022052688 A1 WO2022052688 A1 WO 2022052688A1
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- 238000000034 method Methods 0.000 title claims abstract description 18
- 238000006243 chemical reaction Methods 0.000 claims abstract description 10
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0404—Matrix technologies
- G09G2300/0408—Integration of the drivers onto the display substrate
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/04—Display protection
Definitions
- Embodiments of the present disclosure relate to the field of display technology, and more particularly, to a protection circuit for a display device, a display device thereof, and a method for protecting the display device using the protection circuit.
- GOA Gate Driver on Array
- Embodiments of the present disclosure provide a protection circuit for a display device, a display device thereof, and a method of protecting the display device using the protection circuit.
- a protection circuit for a display device has a gate drive circuit, a level conversion circuit, and a power management circuit.
- the level shifting circuit is configured to provide an input signal to a signal input terminal of the gate drive circuit.
- the power management circuit is configured to provide power to the gate drive circuit.
- the protection circuit is configured to provide a power control signal to the power management circuit based on the current at the signal input of the gate drive circuit to cause the power management circuit to stop supplying power to the gate drive circuit.
- the protection circuit includes a control circuit, a current detection circuit, a comparison circuit, a current detection terminal and a control signal output terminal.
- the current detection terminal is configured to receive the current at the signal input terminal of the gate drive circuit.
- the control signal output is configured to provide the power control signal to the power management circuit.
- the control circuit is coupled to the current detection circuit and the comparison circuit and is configured to send a first control signal to the current detection circuit to control operation of the current detection circuit and to the comparison circuit A second control signal to control the operation of the comparison circuit.
- the current detection circuit is coupled to the current detection terminal and the comparison circuit, and is configured to detect the current of the signal input terminal of the gate drive circuit under the control of the control circuit, and to The detected current is sent to the comparison circuit.
- the comparison circuit is coupled to the control signal output and is configured to compare the current to a first threshold under the control of the control circuit, and to generate a result at the control signal output based on the comparison result. the power control signal.
- generating the power supply control signal based on the comparison result includes: generating the power supply control signal at the control signal output terminal when the current is greater than the first threshold.
- control circuit is further configured to receive and store control parameters.
- control parameter includes the first threshold and detection time.
- the detection time is the time interval from the transition edge of the voltage signal of the signal input terminal to be detected from the gate driving circuit to the moment when the current is detected.
- control parameter further includes a second threshold.
- the second threshold is the number of times N of continuous current detection based on the detection time, where N is an integer greater than 1, and the current detected each time is greater than the first threshold.
- generating the power supply control signal based on the comparison result includes: generating the power supply control signal at the control signal output terminal when multiple detections are performed continuously and the number of detections is equal to the second threshold.
- the signal input terminal of the gate driving circuit includes a clock signal input terminal for receiving a clock signal from the level shifting circuit.
- the detection time is in the range of 2-16 ⁇ s.
- the range of the first threshold is 30-200mA.
- the second threshold is 4, 8, 16 or 32.
- the detection time is 6 ⁇ s.
- the first threshold is 50mA. and the second threshold is 8.
- the protection circuit and the level conversion circuit or the power management circuit are integrated into the same integrated circuit.
- the power management circuit is further configured to provide power to the level shifting circuit.
- a display device including the protection circuit as described above.
- the display device further includes a display substrate.
- the display substrate includes a display area for display and a peripheral area surrounding the display area.
- the gate drive circuit is located in the peripheral region.
- the gate driving circuit includes a clock signal line located in the peripheral region.
- the level conversion circuit provides a clock signal to the gate driving circuit through the clock signal line.
- the current detection terminal of the protection circuit is coupled to the clock signal line.
- a method of protecting a display device using the protection circuit as described above includes: the protection circuit generating the power supply control signal in response to the detected current at the signal input of the gate drive circuit; and in response to the power supply control signal, the power management The circuit stops supplying power to the gate drive circuit.
- FIG. 1 shows a planar structure of a display panel.
- FIG. 2 shows a current comparison of a specific location of a clock signal line of a gate drive circuit under normal operation conditions and under short circuit conditions.
- FIG. 3 shows a comparison of the temperature of a specific location of a clock signal line of a gate drive circuit under normal operation conditions and under short circuit conditions.
- FIG. 4 illustrates a planar structure of a display device according to an embodiment of the present disclosure.
- FIG. 5 illustrates waveforms of a clock signal voltage signal and a clock signal current signal for a gate driving circuit according to an embodiment of the present disclosure.
- FIG. 6 illustrates waveforms of a clock signal voltage signal and a clock signal current signal for a gate drive circuit according to an embodiment of the present disclosure.
- FIG. 7 shows the temperature at the short circuit location measured after the short circuit protection mechanism is triggered, according to an embodiment of the present disclosure.
- FIG 8 illustrates a signal transfer circuit between a protection circuit and a power management circuit according to an embodiment of the present disclosure.
- FIG. 9 illustrates a cascade structure of gate driving circuits according to an embodiment of the present disclosure.
- FIG. 10 illustrates a method of protecting a display device using a protection circuit according to an embodiment of the present disclosure.
- FIG. 1 shows a planar structure of a display panel.
- the display panel 100 includes the gate driving circuit 20 located in the peripheral area of the display panel 100 .
- the gate driving circuit 20 includes a GOA unit 210 for providing gate driving signals to the pixel array and signal lines 220 for providing various input signals to the GOA unit 210 .
- a specific signal line eg, a clock signal line
- an instantaneous large current and a local temperature rise will be generated at the short-circuit location, thereby possibly causing device destruction.
- some extreme operating conditions in the external environment eg, high temperature, high humidity, electrostatic discharge (Electro-Static Discharge, ESD), etc.
- ESD Electro-Static Discharge
- FIG. 2 shows a current comparison of a specific location of a clock signal line of a gate drive circuit under normal operation conditions and under short circuit conditions.
- Figure 2(a) shows the current measured under normal operating conditions. As shown, the measured current is 14mA.
- Figure 2(b) shows the current measured under short circuit conditions. As shown, the measured current is 169mA. From this, it can be seen that when a short circuit occurs in the clock signal line, the current at the short circuit position increases significantly, which affects the normal operation of the gate driving circuit.
- FIG. 3 shows a comparison of the temperature of a specific location of a clock signal line of a gate drive circuit under normal operation conditions and under short circuit conditions.
- Figure 3(a) shows the temperature measured under normal operating conditions. As shown, the measured temperature was 27.7°C.
- Figure 3(b) shows the temperature measured under short circuit conditions. As shown, the measured temperature was 140°C. From this, it can be seen that when a short circuit occurs in the clock signal line, the temperature at the short circuit position increases significantly along with a sharp increase in current.
- the present disclosure provides a protection circuit for a display device that can stop supplying power to a gate driving circuit when a signal line in a gate driving circuit in the display device is short-circuited, thereby reducing adverse effects caused by the short-circuit, thereby reducing adverse effects caused by the short-circuit. Effectively protect the display device.
- FIG. 4 illustrates a planar structure of a display device according to an embodiment of the present disclosure.
- the display device 1 may include a display panel 100 , a level conversion circuit 200 , a power management circuit 300 and a protection circuit 400 .
- the display panel 100 may include a display assembly 10 located in a display area for display and a gate driving circuit 20 located in a peripheral area surrounding the display area.
- the gate driving circuit 20 may include a GOA unit 210 and a signal line 220 coupled to the GOA unit 210 .
- the signal line 220 may be configured to carry signals for the GOA unit 210 .
- signal lines 220 may include clock signal lines configured to transmit a clock signal to GOA unit 210. It should be noted that an exemplary embodiment of the gate driving circuit 20 will be described later with reference to FIG. 9 .
- the level shifting circuit 200 may be configured to provide an input signal to the signal input terminal A of the gate driving circuit 20 .
- the signal input terminal A of the gate driving circuit 20 may include a clock signal input terminal for receiving a clock signal from the level shifting circuit 200 .
- the level shifting circuit 200 may be configured to provide the clock signal CLK to the signal input terminal A of the gate driving circuit 20 through the signal output terminal B.
- the level shifting circuit 200 may also be configured to provide the frame start signal STV and the noise reduction signal pair VDDO/VDDE for the GOA unit 210 to the corresponding signal input terminals of the gate driving circuit 20 through other signal output terminals.
- the power management circuit 300 may be configured to provide the power PS1 to the gate driving circuit 20 .
- the power management circuit 300 may also be configured to provide power PS2 to the level shifting circuit 200 .
- the power management circuit 300 may provide power PS1, PS2 to the gate driving circuit 20 and the level shifting circuit 200 through the output terminals C and D, respectively.
- the power management circuit 300 may also be configured to provide the display device 1 with an analog voltage signal AVDD, a digital voltage signal DVDD, a common electrode voltage signal Vcom, and a grayscale reference signal GMA.
- the protection circuit 400 may be configured to provide the power management circuit 300 with a power control signal SC based on the current I of the signal input terminal A of the gate driving circuit 20 to make the power management circuit 300 stop supplying the gate
- the pole drive circuit 20 provides power PS1. Therefore, when a short circuit occurs in the gate driving circuit 20, the protection circuit 400 can trigger circuit protection in time, so as to protect the gate driving circuit 20 and avoid device damage.
- the protection circuit 400 may include a control circuit 410 , a current detection circuit 420 , a comparison circuit 430 , a current detection terminal E, and a control signal output terminal F.
- the current detection terminal E may be configured to receive the current I of the signal input terminal A of the gate driving circuit 20 .
- control signal output F may be configured to provide a power control signal SC to the power management circuit 300 .
- control circuit 410 may be coupled with the current detection circuit 420 and the comparison circuit 430 and may be configured to send the first control signal C1 to the current detection circuit 420 to control the operation of the current detection circuit 420 , and the second control signal C2 is sent to the comparison circuit 430 to control the operation of the comparison circuit 430 .
- the current detection circuit 420 may be coupled with the current detection terminal E and the comparison circuit 430, and may be configured to be under the control of the control circuit 410 (eg, under the control of the first control signal C1) Bottom) Detect the current I of the signal input terminal A of the gate driving circuit 20 , and send the detected current I to the comparison circuit 430 .
- the comparison circuit 430 may be coupled to the control signal output terminal F, and may be configured to convert the current under the control of the control circuit 530 (eg, under the control of the second control signal C2 ) I is compared with the first threshold value I 0 , and a power control signal SC is generated at the control signal output terminal F based on the comparison result.
- the protection circuit 400 may be integrated into the same integrated circuit as the level conversion circuit 200 and the power management circuit 300 .
- both can be formed in the same integrated circuit (IC).
- the protection circuit 400 and the level conversion circuit 200 may be integrated into the same integrated circuit IC1.
- the current detection terminal E in the protection circuit 400 and the signal output terminal B in the level conversion circuit 200 may be the same terminal.
- the protection circuit 400 and the power management circuit 300 may be integrated into the same integrated circuit IC2.
- the level shifting circuit 200 may provide a clock signal to the gate driving circuit through a clock signal line.
- the level shifting circuit 200 may be configured to provide the signal input terminal A of the gate driving circuit 20 with the clock signal CLK through the signal output terminal B. This clock signal CLK is transmitted to the GOA unit via the clock signal line of the signal lines 220 in the gate driving circuit 20 .
- the current detection terminal E of the protection circuit 400 may be coupled to the clock signal line. Specifically, the current detection terminal E of the protection circuit 400 may be coupled to the signal input terminal A of the gate driving circuit 20.
- generating the power control signal SC based on the comparison result may include: generating the power control signal SC at the control signal output terminal F when the current I is greater than the first threshold I 0 .
- control circuit 410 may also be configured to receive and store control parameters.
- control parameters may include a first threshold I 0 and a detection time t 0 .
- the first threshold I 0 may be a current threshold.
- the detection time t 0 may be the time interval from the transition edge of the voltage signal of the signal input terminal A to be detected from the gate driving circuit 20 to the moment when the current I is detected.
- control parameter may also include a second threshold N.
- the second threshold N may be the number N of times N that the current I is continuously detected based on the detection time t 0 , where N is an integer greater than 1, and the current I detected each time is greater than the first threshold I 0 .
- generating the power supply control signal SC based on the comparison result may include: generating a power supply control signal at the control signal output end F when a number of detections are continuously performed and the number of detections is equal to the second threshold N SC.
- the power supply control signal SC can be effectively prevented from being erroneously generated due to the current fluctuation of the gate driving circuit during normal operation.
- the enable signal terminal EN of the power management circuit 300 receives the power control signal SC, and stops supplying the power PS1 to the gate driving circuit 20 . Therefore, when the clock signal line in the signal line 220 in the gate driving circuit 20 is short-circuited, the power PS1 supply to the gate driving circuit 20 is stopped, thereby protecting the gate driving circuit 20 and preventing the device from being damaged.
- the current detection terminal E of the protection circuit 400 may be coupled to only one clock signal line, so that the position where the short circuit occurs can be located.
- the current detection terminal E of the protection circuit 400 may be coupled to a plurality of clock signal lines. In this case, those skilled in the art can roughly locate the location where the short circuit occurs based on known conditions such as clock timing.
- FIG. 5 illustrates waveforms of a clock signal voltage signal and a clock signal current signal for a gate drive circuit according to an embodiment of the present disclosure.
- the current I of the current signal ICLK of the clock signal line is detected after t 0 elapses from each transition edge of the voltage signal CLK of the clock signal line.
- the detection time t 0 may range from 2-16 ⁇ s.
- the range of the first threshold I 0 may be 30-200 mA.
- the second threshold N may be 4, 8, 16 or 32.
- the detection time t 0 may be 6 ⁇ s.
- the first threshold I 0 may be 50 mA.
- the second threshold N may be 8.
- FIG. 6 illustrates waveforms of a clock signal voltage signal and a clock signal current signal for a gate drive circuit according to an embodiment of the present disclosure.
- the detection time t 0 is 6 ⁇ s.
- the first threshold I 0 is 50 mA.
- the second threshold N is 8. Specifically, when the current I of the current signal ICLK of the clock signal line is detected 8 times in a row when each transition edge of the voltage signal CLK of the clock signal line starts to elapse 6 ⁇ s, and the detected current I is greater than 50 mA each time , the protection circuit 400 generates the power control signal SC at the control signal output end F.
- the power control signal SC may comprise a voltage signal.
- the voltage signal may be a low voltage signal.
- the low voltage may range from 0-0.6V.
- FIG. 7 shows the temperature at the short circuit location measured after the short circuit protection mechanism is triggered, according to an embodiment of the present disclosure.
- the power management circuit 300 responds to the power supply from the protection circuit 400
- the measured temperature at the short-circuit position was 29.8°C. This temperature is close to the room temperature during measurement, which can effectively avoid device damage.
- the control signal output end F of the protection circuit 400 and the enabling of the power management circuit 300 A signal transmission circuit may be provided between the signal terminals EN.
- the signal transfer circuit 60 may be coupled with the protection circuit 400 and the power management circuit 300.
- the signal transmission circuit 60 may be coupled to the control signal output terminal F of the protection circuit 400 and coupled to the enable signal terminal EN of the power management circuit 300 .
- the signal transmission circuit 60 may be configured to perform noise reduction and filtering for the power control signal SC output from the control signal output terminal F.
- FIG. The signal transfer circuit 60 may include a resistor R and a capacitor C.
- the resistance R may be a zero ohm resistance.
- FIG. 8 only shows one capacitor C, which is only a schematic example, and those skilled in the art can set multiple capacitors C according to actual needs and designs.
- a plurality of capacitors C may be arranged in parallel to more effectively denoise and filter the signal.
- FIG. 9 illustrates a cascade structure of gate driving circuits according to an embodiment of the present disclosure.
- the GOA unit 210 of the gate drive circuit 20 includes a plurality of cascaded shift register units, eg, SR1, SR2, SR3.
- the first stage shift register unit SR1 receives the frame start signal STV as the input signal received by its input signal terminal IN. Except for the first stage shift register unit SR1, each stage shift register unit (eg, SR2 and SR3) receives the output signal from the output signal terminal OUT of the previous stage shift register unit as the current stage shift register input signal of the unit.
- the first clock signal terminal CLK1 of each stage of the shift register unit is connected to one of the first clock signal line CLK and the second clock signal line CLKB
- the second clock signal terminal of each stage of the shift register unit CLK2 is connected to the other of the first clock signal line CLK and the second clock signal line CLKB.
- the first clock signal terminals in adjacent two-stage shift register units are connected to different clock signal lines.
- the first clock signal terminals CLK1 of SR1 and SR2 shown in FIG. 9 are connected to CLK and CLKB, respectively.
- Embodiments of the present disclosure also provide a display device including the protection circuit as described above.
- the display device may further include a display substrate.
- the display substrate may include a display area for display and a peripheral area surrounding the display area.
- the gate drive circuit is located in the peripheral area.
- the display device may further include a clock signal line in the peripheral area.
- the level shifting circuit may provide a clock signal to the gate driving circuit through the clock signal line.
- a current detection terminal of the protection circuit may be coupled to the clock signal line.
- Embodiments of the present disclosure also provide a method of protecting a display device using the protection circuit as described above.
- the protection mechanism is triggered to stop supplying power to the gate driving circuit, thereby protecting the gate driving circuit and preventing the device from being damaged.
- FIG. 10 illustrates a method of protecting a display device using a protection circuit according to an embodiment of the present disclosure.
- the method may include steps S100 and S200.
- the protection circuit generates a power control signal in response to the detected current at the signal input terminal of the gate driving circuit.
- the power management circuit stops supplying power to the gate driving circuit.
- step S100 may further include: S101 , in response to the first control signal C1 from the control circuit 210 in the protection circuit 400 , the current detection circuit 420 in the protection circuit 400 receives the gate driving circuit 20 The current I of the signal input terminal A, and the detected current I is sent to the comparison circuit 430 in the protection circuit 400; S102 In response to the second control signal C2 from the control circuit 210, the comparison circuit 430 receives the current I from the current detection circuit 420.
- the output terminal F of the control signal generates Power control signal SC.
- the second threshold value N may be the number N of times N that the current I is continuously detected based on the detection time t 0 , where N is an integer greater than 1, and the current I detected each time is greater than the first threshold value I 0 .
- the detection time t 0 may be the time interval from the transition edge of the voltage signal of the signal input terminal A to be detected from the gate driving circuit 20 to the moment when the current I is detected.
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Abstract
Description
Claims (15)
- 一种用于显示装置的保护电路,所述显示装置具有栅极驱动电路、电平转换电路和电源管理电路,所述电平转换电路被配置为向所述栅极驱动电路的信号输入端提供输入信号,所述电源管理电路被配置为向所述栅极驱动电路提供电力,其中,所述保护电路被配置为基于所述栅极驱动电路的所述信号输入端的电流向所述电源管理电路提供电源控制信号以使所述电源管理电路停止向所述栅极驱动电路提供电力。
- 根据权利要求1所述的保护电路,其中,所述保护电路包括控制电路、电流检测电路、比较电路、电流检测端和控制信号输出端,所述电流检测端被配置为接收所述栅极驱动电路的所述信号输入端的所述电流,所述控制信号输出端被配置为向所述电源管理电路提供所述电源控制信号,所述控制电路与所述电流检测电路和所述比较电路耦接,并被配置为向所述电流检测电路发送第一控制信号以控制所述电流检测电路的操作,以及向所述比较电路发送第二控制信号以控制所述比较电路的操作,所述电流检测电路与所述电流检测端和所述比较电路耦接,并被配置为在所述控制电路的控制下检测所述栅极驱动电路的所述信号输入端的所述电流,并将检测的所述电流发送给所述比较电路,以及所述比较电路与所述控制信号输出端耦接,并被配置为在所述控制电路的控制下将所述电流与第一阈值进行比较,并基于比较结果在所述控制信号输出端产生所述电源控制信号。
- 根据权利要求2所述的保护电路,其中,基于比较结果产生所述电源控制信号包括:在所述电流大于所述第一阈值时在所述控制信号输出端产生所述电源控制信号。
- 根据权利要求3所述的保护电路,其中,所述控制电路还被配置为接收并存储控制参数。
- 根据权利要求4所述的保护电路,其中,所述控制参数包括所述第一阈值和检测时间,其中,所述检测时间为来自所述栅极驱动电路的待检测的所述信号输入端的电压信号的跳变沿至检测所述电流的时刻之间的时间间隔。
- 根据权利要求5所述的保护电路,其中,所述控制参数还包括第二阈值,其中,所述第二阈值为基于所述检测时间连续进行所述电流的检测的次数N,其中,N为大于1的整数,每次检测的电流都大于所述第一阈值。
- 根据权利要求6所述的保护电路,其中,基于比较结果产生所述电源控制信号包括:在连续进行多次检测且检测次数等于所述第二阈值时,在所述控制信号输出端产生所述电源控制信号。
- 根据权利要求7所述的保护电路,其中,所述栅极驱动电路的所述信号输入端包括用于接收来自所述电平转换电路的时钟信号的时钟信号输入端。
- 根据权利要求8所述的保护电路,其中,所述检测时间的范围为2-16μs,所述第一阈值的范围为30-200mA,以及所述第二阈值为4、8、16或32。
- 根据权利要求9所述的保护电路,其中,所述检测时间为6μs,所述第一阈值为50mA,以及所述第二阈值为8。
- 根据权利要求1所述的保护电路,其中,所述保护电路与所述电平转换电路或所述电源管理电路集成为同一集成电路。
- 根据权利要求1所述的保护电路,其中,所述电源管理电路还被配置为向所述电平转换电路提供电力。
- 一种包括根据权利要求1-12中任一项所述的保护电路的显示装置,还包括显示基板,所述显示基板包括用于显示的显示区域和围绕所述显示区域的周边区域,其中,所述栅极驱动电路位于所述周边区域中。
- 根据权利要求13所述的显示装置,其中,所述栅极驱动电路包括位于所述周边区域中的时钟信号线,其中,所述电平转换电路通过所述时钟信号线向所述栅极驱动电路提供时钟信号,所述保护电路的所述电流检测端被耦接到所述时钟信号线。
- 一种使用根据权利要求1-11中任一项所述的保护电路来保护显示装置的方法,包括:响应于检测到的所述栅极驱动电路的所述信号输入端的所述电流,所述保护电路产生所述电源控制信号;以及响应于所述电源控制信号,所述电源管理电路停止向所述栅极驱动电路提供电力。
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105304050A (zh) * | 2015-11-20 | 2016-02-03 | 深圳市华星光电技术有限公司 | 一种过流保护电路和过流保护方法 |
CN105448260A (zh) * | 2015-12-29 | 2016-03-30 | 深圳市华星光电技术有限公司 | 一种过流保护电路及液晶显示器 |
CN107068092A (zh) * | 2017-05-04 | 2017-08-18 | 京东方科技集团股份有限公司 | 一种静电防护方法、装置及液晶显示器 |
CN107508252A (zh) * | 2017-09-20 | 2017-12-22 | 深圳市华星光电技术有限公司 | 一种过流保护电路及显示面板 |
CN109617008A (zh) * | 2018-12-12 | 2019-04-12 | 惠科股份有限公司 | 过流保护方法、显示面板及显示装置 |
CN111986611A (zh) * | 2020-09-14 | 2020-11-24 | 合肥京东方显示技术有限公司 | 用于显示装置的保护电路及其显示装置以及使用保护电路保护显示装置方法 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103703507B (zh) * | 2011-08-10 | 2016-04-27 | 夏普株式会社 | 液晶显示装置及其驱动方法 |
CN105162077A (zh) * | 2015-10-13 | 2015-12-16 | 深圳市华星光电技术有限公司 | 线路保护电路以及液晶显示器 |
KR102487588B1 (ko) * | 2016-04-27 | 2023-01-13 | 삼성디스플레이 주식회사 | 표시 장치 및 그것의 구동 방법 |
CN107395006B (zh) * | 2017-09-13 | 2020-07-03 | 深圳市华星光电技术有限公司 | 过流保护电路及液晶显示器 |
CN107742493B (zh) * | 2017-11-13 | 2020-03-17 | 深圳市华星光电技术有限公司 | 一种驱动电路及驱动方法 |
KR102524598B1 (ko) * | 2018-07-11 | 2023-04-24 | 삼성디스플레이 주식회사 | 게이트 구동 장치 및 이를 포함하는 표시 장치 |
CN112673416A (zh) * | 2018-07-13 | 2021-04-16 | 堺显示器制品株式会社 | 控制装置及液晶显示装置 |
US11091468B2 (en) * | 2018-07-23 | 2021-08-17 | Research Foundation Of The City University Of New York | Carbohydrate-binding small molecules with antiviral activity |
CN109616061B (zh) * | 2018-12-24 | 2024-04-26 | 惠科股份有限公司 | 源极驱动芯片保护电路、显示面板驱动电路和显示装置 |
CN109637412B (zh) * | 2018-12-25 | 2020-10-30 | 惠科股份有限公司 | 显示面板的过流保护方法及显示装置 |
CN109448658A (zh) * | 2018-12-27 | 2019-03-08 | 惠科股份有限公司 | 过流保护电路及显示装置 |
JP7181825B2 (ja) * | 2019-03-26 | 2022-12-01 | 株式会社ジャパンディスプレイ | 表示装置 |
CN110060644B (zh) * | 2019-04-10 | 2021-01-01 | 深圳市华星光电技术有限公司 | 液晶显示装置及其过流保护方法 |
CN111627376B (zh) * | 2020-06-17 | 2021-11-30 | 合肥鑫晟光电科技有限公司 | 过流保护电路、显示装置及其驱动电路、过流保护方法 |
KR20220026752A (ko) * | 2020-08-26 | 2022-03-07 | 엘지디스플레이 주식회사 | 전원 공급부 및 이를 포함하는 표시장치 |
-
2020
- 2020-09-14 CN CN202010961074.7A patent/CN111986611B/zh active Active
-
2021
- 2021-08-05 US US17/788,540 patent/US11900856B2/en active Active
- 2021-08-05 WO PCT/CN2021/110791 patent/WO2022052688A1/zh active Application Filing
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105304050A (zh) * | 2015-11-20 | 2016-02-03 | 深圳市华星光电技术有限公司 | 一种过流保护电路和过流保护方法 |
CN105448260A (zh) * | 2015-12-29 | 2016-03-30 | 深圳市华星光电技术有限公司 | 一种过流保护电路及液晶显示器 |
CN107068092A (zh) * | 2017-05-04 | 2017-08-18 | 京东方科技集团股份有限公司 | 一种静电防护方法、装置及液晶显示器 |
CN107508252A (zh) * | 2017-09-20 | 2017-12-22 | 深圳市华星光电技术有限公司 | 一种过流保护电路及显示面板 |
CN109617008A (zh) * | 2018-12-12 | 2019-04-12 | 惠科股份有限公司 | 过流保护方法、显示面板及显示装置 |
CN111986611A (zh) * | 2020-09-14 | 2020-11-24 | 合肥京东方显示技术有限公司 | 用于显示装置的保护电路及其显示装置以及使用保护电路保护显示装置方法 |
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