WO2022052688A1 - 用于显示装置的保护电路及其显示装置以及使用保护电路保护显示装置方法 - Google Patents

用于显示装置的保护电路及其显示装置以及使用保护电路保护显示装置方法 Download PDF

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Publication number
WO2022052688A1
WO2022052688A1 PCT/CN2021/110791 CN2021110791W WO2022052688A1 WO 2022052688 A1 WO2022052688 A1 WO 2022052688A1 CN 2021110791 W CN2021110791 W CN 2021110791W WO 2022052688 A1 WO2022052688 A1 WO 2022052688A1
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WIPO (PCT)
Prior art keywords
circuit
current
control signal
protection circuit
power
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PCT/CN2021/110791
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English (en)
French (fr)
Inventor
唐继托
杨昆
孙志华
曲峰
邓鸣
李瑞莲
修天洵
林准
Original Assignee
京东方科技集团股份有限公司
合肥京东方显示技术有限公司
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Priority to US17/788,540 priority Critical patent/US11900856B2/en
Publication of WO2022052688A1 publication Critical patent/WO2022052688A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection

Definitions

  • Embodiments of the present disclosure relate to the field of display technology, and more particularly, to a protection circuit for a display device, a display device thereof, and a method for protecting the display device using the protection circuit.
  • GOA Gate Driver on Array
  • Embodiments of the present disclosure provide a protection circuit for a display device, a display device thereof, and a method of protecting the display device using the protection circuit.
  • a protection circuit for a display device has a gate drive circuit, a level conversion circuit, and a power management circuit.
  • the level shifting circuit is configured to provide an input signal to a signal input terminal of the gate drive circuit.
  • the power management circuit is configured to provide power to the gate drive circuit.
  • the protection circuit is configured to provide a power control signal to the power management circuit based on the current at the signal input of the gate drive circuit to cause the power management circuit to stop supplying power to the gate drive circuit.
  • the protection circuit includes a control circuit, a current detection circuit, a comparison circuit, a current detection terminal and a control signal output terminal.
  • the current detection terminal is configured to receive the current at the signal input terminal of the gate drive circuit.
  • the control signal output is configured to provide the power control signal to the power management circuit.
  • the control circuit is coupled to the current detection circuit and the comparison circuit and is configured to send a first control signal to the current detection circuit to control operation of the current detection circuit and to the comparison circuit A second control signal to control the operation of the comparison circuit.
  • the current detection circuit is coupled to the current detection terminal and the comparison circuit, and is configured to detect the current of the signal input terminal of the gate drive circuit under the control of the control circuit, and to The detected current is sent to the comparison circuit.
  • the comparison circuit is coupled to the control signal output and is configured to compare the current to a first threshold under the control of the control circuit, and to generate a result at the control signal output based on the comparison result. the power control signal.
  • generating the power supply control signal based on the comparison result includes: generating the power supply control signal at the control signal output terminal when the current is greater than the first threshold.
  • control circuit is further configured to receive and store control parameters.
  • control parameter includes the first threshold and detection time.
  • the detection time is the time interval from the transition edge of the voltage signal of the signal input terminal to be detected from the gate driving circuit to the moment when the current is detected.
  • control parameter further includes a second threshold.
  • the second threshold is the number of times N of continuous current detection based on the detection time, where N is an integer greater than 1, and the current detected each time is greater than the first threshold.
  • generating the power supply control signal based on the comparison result includes: generating the power supply control signal at the control signal output terminal when multiple detections are performed continuously and the number of detections is equal to the second threshold.
  • the signal input terminal of the gate driving circuit includes a clock signal input terminal for receiving a clock signal from the level shifting circuit.
  • the detection time is in the range of 2-16 ⁇ s.
  • the range of the first threshold is 30-200mA.
  • the second threshold is 4, 8, 16 or 32.
  • the detection time is 6 ⁇ s.
  • the first threshold is 50mA. and the second threshold is 8.
  • the protection circuit and the level conversion circuit or the power management circuit are integrated into the same integrated circuit.
  • the power management circuit is further configured to provide power to the level shifting circuit.
  • a display device including the protection circuit as described above.
  • the display device further includes a display substrate.
  • the display substrate includes a display area for display and a peripheral area surrounding the display area.
  • the gate drive circuit is located in the peripheral region.
  • the gate driving circuit includes a clock signal line located in the peripheral region.
  • the level conversion circuit provides a clock signal to the gate driving circuit through the clock signal line.
  • the current detection terminal of the protection circuit is coupled to the clock signal line.
  • a method of protecting a display device using the protection circuit as described above includes: the protection circuit generating the power supply control signal in response to the detected current at the signal input of the gate drive circuit; and in response to the power supply control signal, the power management The circuit stops supplying power to the gate drive circuit.
  • FIG. 1 shows a planar structure of a display panel.
  • FIG. 2 shows a current comparison of a specific location of a clock signal line of a gate drive circuit under normal operation conditions and under short circuit conditions.
  • FIG. 3 shows a comparison of the temperature of a specific location of a clock signal line of a gate drive circuit under normal operation conditions and under short circuit conditions.
  • FIG. 4 illustrates a planar structure of a display device according to an embodiment of the present disclosure.
  • FIG. 5 illustrates waveforms of a clock signal voltage signal and a clock signal current signal for a gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 6 illustrates waveforms of a clock signal voltage signal and a clock signal current signal for a gate drive circuit according to an embodiment of the present disclosure.
  • FIG. 7 shows the temperature at the short circuit location measured after the short circuit protection mechanism is triggered, according to an embodiment of the present disclosure.
  • FIG 8 illustrates a signal transfer circuit between a protection circuit and a power management circuit according to an embodiment of the present disclosure.
  • FIG. 9 illustrates a cascade structure of gate driving circuits according to an embodiment of the present disclosure.
  • FIG. 10 illustrates a method of protecting a display device using a protection circuit according to an embodiment of the present disclosure.
  • FIG. 1 shows a planar structure of a display panel.
  • the display panel 100 includes the gate driving circuit 20 located in the peripheral area of the display panel 100 .
  • the gate driving circuit 20 includes a GOA unit 210 for providing gate driving signals to the pixel array and signal lines 220 for providing various input signals to the GOA unit 210 .
  • a specific signal line eg, a clock signal line
  • an instantaneous large current and a local temperature rise will be generated at the short-circuit location, thereby possibly causing device destruction.
  • some extreme operating conditions in the external environment eg, high temperature, high humidity, electrostatic discharge (Electro-Static Discharge, ESD), etc.
  • ESD Electro-Static Discharge
  • FIG. 2 shows a current comparison of a specific location of a clock signal line of a gate drive circuit under normal operation conditions and under short circuit conditions.
  • Figure 2(a) shows the current measured under normal operating conditions. As shown, the measured current is 14mA.
  • Figure 2(b) shows the current measured under short circuit conditions. As shown, the measured current is 169mA. From this, it can be seen that when a short circuit occurs in the clock signal line, the current at the short circuit position increases significantly, which affects the normal operation of the gate driving circuit.
  • FIG. 3 shows a comparison of the temperature of a specific location of a clock signal line of a gate drive circuit under normal operation conditions and under short circuit conditions.
  • Figure 3(a) shows the temperature measured under normal operating conditions. As shown, the measured temperature was 27.7°C.
  • Figure 3(b) shows the temperature measured under short circuit conditions. As shown, the measured temperature was 140°C. From this, it can be seen that when a short circuit occurs in the clock signal line, the temperature at the short circuit position increases significantly along with a sharp increase in current.
  • the present disclosure provides a protection circuit for a display device that can stop supplying power to a gate driving circuit when a signal line in a gate driving circuit in the display device is short-circuited, thereby reducing adverse effects caused by the short-circuit, thereby reducing adverse effects caused by the short-circuit. Effectively protect the display device.
  • FIG. 4 illustrates a planar structure of a display device according to an embodiment of the present disclosure.
  • the display device 1 may include a display panel 100 , a level conversion circuit 200 , a power management circuit 300 and a protection circuit 400 .
  • the display panel 100 may include a display assembly 10 located in a display area for display and a gate driving circuit 20 located in a peripheral area surrounding the display area.
  • the gate driving circuit 20 may include a GOA unit 210 and a signal line 220 coupled to the GOA unit 210 .
  • the signal line 220 may be configured to carry signals for the GOA unit 210 .
  • signal lines 220 may include clock signal lines configured to transmit a clock signal to GOA unit 210. It should be noted that an exemplary embodiment of the gate driving circuit 20 will be described later with reference to FIG. 9 .
  • the level shifting circuit 200 may be configured to provide an input signal to the signal input terminal A of the gate driving circuit 20 .
  • the signal input terminal A of the gate driving circuit 20 may include a clock signal input terminal for receiving a clock signal from the level shifting circuit 200 .
  • the level shifting circuit 200 may be configured to provide the clock signal CLK to the signal input terminal A of the gate driving circuit 20 through the signal output terminal B.
  • the level shifting circuit 200 may also be configured to provide the frame start signal STV and the noise reduction signal pair VDDO/VDDE for the GOA unit 210 to the corresponding signal input terminals of the gate driving circuit 20 through other signal output terminals.
  • the power management circuit 300 may be configured to provide the power PS1 to the gate driving circuit 20 .
  • the power management circuit 300 may also be configured to provide power PS2 to the level shifting circuit 200 .
  • the power management circuit 300 may provide power PS1, PS2 to the gate driving circuit 20 and the level shifting circuit 200 through the output terminals C and D, respectively.
  • the power management circuit 300 may also be configured to provide the display device 1 with an analog voltage signal AVDD, a digital voltage signal DVDD, a common electrode voltage signal Vcom, and a grayscale reference signal GMA.
  • the protection circuit 400 may be configured to provide the power management circuit 300 with a power control signal SC based on the current I of the signal input terminal A of the gate driving circuit 20 to make the power management circuit 300 stop supplying the gate
  • the pole drive circuit 20 provides power PS1. Therefore, when a short circuit occurs in the gate driving circuit 20, the protection circuit 400 can trigger circuit protection in time, so as to protect the gate driving circuit 20 and avoid device damage.
  • the protection circuit 400 may include a control circuit 410 , a current detection circuit 420 , a comparison circuit 430 , a current detection terminal E, and a control signal output terminal F.
  • the current detection terminal E may be configured to receive the current I of the signal input terminal A of the gate driving circuit 20 .
  • control signal output F may be configured to provide a power control signal SC to the power management circuit 300 .
  • control circuit 410 may be coupled with the current detection circuit 420 and the comparison circuit 430 and may be configured to send the first control signal C1 to the current detection circuit 420 to control the operation of the current detection circuit 420 , and the second control signal C2 is sent to the comparison circuit 430 to control the operation of the comparison circuit 430 .
  • the current detection circuit 420 may be coupled with the current detection terminal E and the comparison circuit 430, and may be configured to be under the control of the control circuit 410 (eg, under the control of the first control signal C1) Bottom) Detect the current I of the signal input terminal A of the gate driving circuit 20 , and send the detected current I to the comparison circuit 430 .
  • the comparison circuit 430 may be coupled to the control signal output terminal F, and may be configured to convert the current under the control of the control circuit 530 (eg, under the control of the second control signal C2 ) I is compared with the first threshold value I 0 , and a power control signal SC is generated at the control signal output terminal F based on the comparison result.
  • the protection circuit 400 may be integrated into the same integrated circuit as the level conversion circuit 200 and the power management circuit 300 .
  • both can be formed in the same integrated circuit (IC).
  • the protection circuit 400 and the level conversion circuit 200 may be integrated into the same integrated circuit IC1.
  • the current detection terminal E in the protection circuit 400 and the signal output terminal B in the level conversion circuit 200 may be the same terminal.
  • the protection circuit 400 and the power management circuit 300 may be integrated into the same integrated circuit IC2.
  • the level shifting circuit 200 may provide a clock signal to the gate driving circuit through a clock signal line.
  • the level shifting circuit 200 may be configured to provide the signal input terminal A of the gate driving circuit 20 with the clock signal CLK through the signal output terminal B. This clock signal CLK is transmitted to the GOA unit via the clock signal line of the signal lines 220 in the gate driving circuit 20 .
  • the current detection terminal E of the protection circuit 400 may be coupled to the clock signal line. Specifically, the current detection terminal E of the protection circuit 400 may be coupled to the signal input terminal A of the gate driving circuit 20.
  • generating the power control signal SC based on the comparison result may include: generating the power control signal SC at the control signal output terminal F when the current I is greater than the first threshold I 0 .
  • control circuit 410 may also be configured to receive and store control parameters.
  • control parameters may include a first threshold I 0 and a detection time t 0 .
  • the first threshold I 0 may be a current threshold.
  • the detection time t 0 may be the time interval from the transition edge of the voltage signal of the signal input terminal A to be detected from the gate driving circuit 20 to the moment when the current I is detected.
  • control parameter may also include a second threshold N.
  • the second threshold N may be the number N of times N that the current I is continuously detected based on the detection time t 0 , where N is an integer greater than 1, and the current I detected each time is greater than the first threshold I 0 .
  • generating the power supply control signal SC based on the comparison result may include: generating a power supply control signal at the control signal output end F when a number of detections are continuously performed and the number of detections is equal to the second threshold N SC.
  • the power supply control signal SC can be effectively prevented from being erroneously generated due to the current fluctuation of the gate driving circuit during normal operation.
  • the enable signal terminal EN of the power management circuit 300 receives the power control signal SC, and stops supplying the power PS1 to the gate driving circuit 20 . Therefore, when the clock signal line in the signal line 220 in the gate driving circuit 20 is short-circuited, the power PS1 supply to the gate driving circuit 20 is stopped, thereby protecting the gate driving circuit 20 and preventing the device from being damaged.
  • the current detection terminal E of the protection circuit 400 may be coupled to only one clock signal line, so that the position where the short circuit occurs can be located.
  • the current detection terminal E of the protection circuit 400 may be coupled to a plurality of clock signal lines. In this case, those skilled in the art can roughly locate the location where the short circuit occurs based on known conditions such as clock timing.
  • FIG. 5 illustrates waveforms of a clock signal voltage signal and a clock signal current signal for a gate drive circuit according to an embodiment of the present disclosure.
  • the current I of the current signal ICLK of the clock signal line is detected after t 0 elapses from each transition edge of the voltage signal CLK of the clock signal line.
  • the detection time t 0 may range from 2-16 ⁇ s.
  • the range of the first threshold I 0 may be 30-200 mA.
  • the second threshold N may be 4, 8, 16 or 32.
  • the detection time t 0 may be 6 ⁇ s.
  • the first threshold I 0 may be 50 mA.
  • the second threshold N may be 8.
  • FIG. 6 illustrates waveforms of a clock signal voltage signal and a clock signal current signal for a gate drive circuit according to an embodiment of the present disclosure.
  • the detection time t 0 is 6 ⁇ s.
  • the first threshold I 0 is 50 mA.
  • the second threshold N is 8. Specifically, when the current I of the current signal ICLK of the clock signal line is detected 8 times in a row when each transition edge of the voltage signal CLK of the clock signal line starts to elapse 6 ⁇ s, and the detected current I is greater than 50 mA each time , the protection circuit 400 generates the power control signal SC at the control signal output end F.
  • the power control signal SC may comprise a voltage signal.
  • the voltage signal may be a low voltage signal.
  • the low voltage may range from 0-0.6V.
  • FIG. 7 shows the temperature at the short circuit location measured after the short circuit protection mechanism is triggered, according to an embodiment of the present disclosure.
  • the power management circuit 300 responds to the power supply from the protection circuit 400
  • the measured temperature at the short-circuit position was 29.8°C. This temperature is close to the room temperature during measurement, which can effectively avoid device damage.
  • the control signal output end F of the protection circuit 400 and the enabling of the power management circuit 300 A signal transmission circuit may be provided between the signal terminals EN.
  • the signal transfer circuit 60 may be coupled with the protection circuit 400 and the power management circuit 300.
  • the signal transmission circuit 60 may be coupled to the control signal output terminal F of the protection circuit 400 and coupled to the enable signal terminal EN of the power management circuit 300 .
  • the signal transmission circuit 60 may be configured to perform noise reduction and filtering for the power control signal SC output from the control signal output terminal F.
  • FIG. The signal transfer circuit 60 may include a resistor R and a capacitor C.
  • the resistance R may be a zero ohm resistance.
  • FIG. 8 only shows one capacitor C, which is only a schematic example, and those skilled in the art can set multiple capacitors C according to actual needs and designs.
  • a plurality of capacitors C may be arranged in parallel to more effectively denoise and filter the signal.
  • FIG. 9 illustrates a cascade structure of gate driving circuits according to an embodiment of the present disclosure.
  • the GOA unit 210 of the gate drive circuit 20 includes a plurality of cascaded shift register units, eg, SR1, SR2, SR3.
  • the first stage shift register unit SR1 receives the frame start signal STV as the input signal received by its input signal terminal IN. Except for the first stage shift register unit SR1, each stage shift register unit (eg, SR2 and SR3) receives the output signal from the output signal terminal OUT of the previous stage shift register unit as the current stage shift register input signal of the unit.
  • the first clock signal terminal CLK1 of each stage of the shift register unit is connected to one of the first clock signal line CLK and the second clock signal line CLKB
  • the second clock signal terminal of each stage of the shift register unit CLK2 is connected to the other of the first clock signal line CLK and the second clock signal line CLKB.
  • the first clock signal terminals in adjacent two-stage shift register units are connected to different clock signal lines.
  • the first clock signal terminals CLK1 of SR1 and SR2 shown in FIG. 9 are connected to CLK and CLKB, respectively.
  • Embodiments of the present disclosure also provide a display device including the protection circuit as described above.
  • the display device may further include a display substrate.
  • the display substrate may include a display area for display and a peripheral area surrounding the display area.
  • the gate drive circuit is located in the peripheral area.
  • the display device may further include a clock signal line in the peripheral area.
  • the level shifting circuit may provide a clock signal to the gate driving circuit through the clock signal line.
  • a current detection terminal of the protection circuit may be coupled to the clock signal line.
  • Embodiments of the present disclosure also provide a method of protecting a display device using the protection circuit as described above.
  • the protection mechanism is triggered to stop supplying power to the gate driving circuit, thereby protecting the gate driving circuit and preventing the device from being damaged.
  • FIG. 10 illustrates a method of protecting a display device using a protection circuit according to an embodiment of the present disclosure.
  • the method may include steps S100 and S200.
  • the protection circuit generates a power control signal in response to the detected current at the signal input terminal of the gate driving circuit.
  • the power management circuit stops supplying power to the gate driving circuit.
  • step S100 may further include: S101 , in response to the first control signal C1 from the control circuit 210 in the protection circuit 400 , the current detection circuit 420 in the protection circuit 400 receives the gate driving circuit 20 The current I of the signal input terminal A, and the detected current I is sent to the comparison circuit 430 in the protection circuit 400; S102 In response to the second control signal C2 from the control circuit 210, the comparison circuit 430 receives the current I from the current detection circuit 420.
  • the output terminal F of the control signal generates Power control signal SC.
  • the second threshold value N may be the number N of times N that the current I is continuously detected based on the detection time t 0 , where N is an integer greater than 1, and the current I detected each time is greater than the first threshold value I 0 .
  • the detection time t 0 may be the time interval from the transition edge of the voltage signal of the signal input terminal A to be detected from the gate driving circuit 20 to the moment when the current I is detected.

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Abstract

本公开涉及一种用于显示装置的保护电路及其显示装置以及使用保护电路保护显示装置的方法。所述显示装置具有栅极驱动电路、电平转换电路、电源管理电路。所述电平转换电路被配置为向所述栅极驱动电路的信号输入端提供输入信号。所述电源管理电路被配置为向所述栅极驱动电路提供电力。所述保护电路被配置为基于所述栅极驱动电路的所述信号输入端的电流向所述电源管理电路提供电源控制信号以使所述电源管理电路停止向所述栅极驱动电路提供电力。

Description

用于显示装置的保护电路及其显示装置以及使用保护电路保护显示装置方法
相关申请的交叉引用
本申请要求于2020年9月14日递交的中国专利申请第202010961074.7号优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及显示技术领域，更具体地，涉及一种用于显示装置的保护电路及其显示装置以及使用保护电路保护显示装置方法。
背景技术
随着显示技术的发展，显示面板越来越向着高集成度和低成本的方向发展。目前，中大尺寸显示面板基本采用阵列上栅极驱动(Gate Driver on Array，GOA)架构。也就是，采用与TFT相同的制造工艺将行扫描驱动电路集成在显示面板内部。
发明内容
本公开的实施例提供了一种用于显示装置的保护电路及其显示装置以及使用保护电路保护显示装置方法。
在本公开的一方面，提供了一种用于显示装置的保护电路。所述显示装置具有栅极驱动电路、电平转换电路、电源管理电路。所述电平转换电路被配置为向所述栅极驱动电路的信号输入端提供输入信号。所述电源管理电路被配置为向所述栅极驱动电路提供电力。所述保护电路被配置为基于所述栅极驱动电路的所述信号输入端的电流向所述电源管理电路提供电源控制信号以使所述电源管理电路停止向所述栅极驱动电路提供电力。
在本公开的实施例中，所述保护电路包括控制电路、电流检测电路、 比较电路、电流检测端和控制信号输出端。所述电流检测端被配置为接收所述栅极驱动电路的所述信号输入端的所述电流。所述控制信号输出端被配置为向所述电源管理电路提供所述电源控制信号。所述控制电路与所述电流检测电路和所述比较电路耦接，并被配置为向所述电流检测电路发送第一控制信号以控制所述电流检测电路的操作，以及向所述比较电路发送第二控制信号以控制所述比较电路的操作。所述电流检测电路与所述电流检测端和所述比较电路耦接，并被配置为在所述控制电路的控制下检测所述栅极驱动电路的所述信号输入端的所述电流，并将检测的所述电流发送给所述比较电路。所述比较电路与所述控制信号输出端耦接，并被配置为在所述控制电路的控制下将所述电流与第一阈值进行比较，并基于比较结果在所述控制信号输出端产生所述电源控制信号。
在本公开的实施例中，基于比较结果产生所述电源控制信号包括：在所述电流大于所述第一阈值时在所述控制信号输出端产生所述电源控制信号。
在本公开的实施例中，所述控制电路还被配置为接收并存储控制参数。
在本公开的实施例中，所述控制参数包括所述第一阈值和检测时间。所述检测时间为来自所述栅极驱动电路的待检测的所述信号输入端的电压信号的跳变沿至检测所述电流的时刻之间的时间间隔。
在本公开的实施例中，所述控制参数还包括第二阈值。所述第二阈值为基于所述检测时间连续进行所述电流的检测的次数N，其中，N为大于1的整数，每次检测的电流都大于所述第一阈值。
在本公开的实施例中，基于比较结果产生所述电源控制信号包括：在连续进行多次检测且检测次数等于所述第二阈值时，在所述控制信号输出端产生所述电源控制信号。
在本公开的实施例中，所述栅极驱动电路的所述信号输入端包括用于接收来自所述电平转换电路的时钟信号的时钟信号输入端。
在本公开的实施例中，所述检测时间的范围为2-16μs。所述第一阈值 的范围为30-200mA。所述第二阈值为4、8、16或32。
在本公开的实施例中，所述检测时间为6μs。所述第一阈值为50mA。以及所述第二阈值为8。
在本公开的实施例中，所述保护电路与所述电平转换电路或所述电源管理电路集成为同一集成电路。
在本公开的实施例中，所述电源管理电路还被配置为向所述电平转换电路提供电力。
在本公开的另一方面，提供了一种包括如上所述的保护电路的显示装置。所述显示装置还包括显示基板。所述显示基板包括用于显示的显示区域和围绕所述显示区域的周边区域。所述栅极驱动电路位于所述周边区域中。
在本公开的实施例中，所述栅极驱动电路包括位于所述周边区域中的时钟信号线。所述电平转换电路通过所述时钟信号线向所述栅极驱动电路提供时钟信号。所述保护电路的所述电流检测端被耦接到所述时钟信号线。
在本公开的又一方面，提供了一种使用根据如上所述的保护电路来保护显示装置的方法。所述方法包括：响应于检测到的所述栅极驱动电路的所述信号输入端的所述电流，所述保护电路产生所述电源控制信号；以及响应于所述电源控制信号，所述电源管理电路停止向所述栅极驱动电路提供电力。
适应性的进一步的方面和范围从本文中提供的描述变得明显。应当理解，本申请的各个方面可以单独或者与一个或多个其他方面组合实施。还应当理解，本文中的描述和特定实施例旨在仅说明的目的并不旨在限制本申请的范围。
附图说明
本文中描述的附图用于仅对所选择的实施例的说明的目的，并不是所有可能的实施方式，并且不旨在限制本公开的范围，其中：
图1示出了一种显示面板的平面结构。
图2示出了栅极驱动电路的时钟信号线在正常操作情况下和短路情况下的特定位置的电流比较。
图3示出了栅极驱动电路的时钟信号线在正常操作情况下和短路情况下的特定位置的温度比较。
图4示出了根据本公开的实施例的显示装置的平面结构。
图5示出了根据本公开的实施例的用于栅极驱动电路的时钟信号电压信号和时钟信号电流信号的波形。
图6示出了根据本公开的实施例的用于栅极驱动电路的时钟信号电压信号和时钟信号电流信号的波形。
图7示出了根据本公开的实施例的在触发短路保护机制后所测量的短路位置处的温度。
图8示出了根据本公开的实施例的保护电路与电源管理电路之间的信号传递电路。
图9示出了根据本公开的实施例的栅极驱动电路的级联结构。
图10示出了根据本公开的实施例的使用保护电路来保护显示装置的方法。
贯穿这些附图的各个视图，相应的参考编号指示相应的部件或特征。
具体实施方式
首先，需要说明的是，除非上下文中另外明确地指出，否则在本文和所附权利要求中所使用的词语的单数形式包括复数，反之亦然。因而，当提及单数时，通常包括相应术语的复数。相似地，措辞“包含”和“包括”将解释为包含在内而不是独占性地。同样地，术语“包括”和“或”应当解释为包括在内的，除非本文中另有说明。在本文中使用术语“实例”之处，特别是当其位于一组术语之后时，所述“实例”仅仅是示例性的和阐述性的，且不应当被认为是独占性的或广泛性的。
另外，还需要说明的是，当介绍本申请的元素及其实施例时，冠词“一”、“一个”、“该”和“所述”旨在表示存在一个或者多个要素；除非另有说明，“多个”的含义是两个或两个以上；用语“包含”、“包括”、“含有”和“具有”旨在包括性的并且表示可以存在除所列要素之外的另外的要素；术语“第一”、“第二”、“第三”等仅用于描述的目的，而不能理解为指示或暗示相对重要性及形成顺序。
其次，在附图中，为了清楚起见夸大了各层的厚度及区域。应当理解的是，当提到层、区域、或组件在别的部分“上”时，指其直接位于别的部分上，或者也可能有别的组件介于其间。相反，当某个组件被提到“直接”位于别的组件上时，指并无别的组件介于其间。
本公开中描绘的流程图仅仅是一个例子。在不脱离本公开精神的情况下，可以存在该流程图或其中描述的步骤的很多变型。例如，所述步骤可以以不同的顺序进行，或者可以添加、删除或者修改步骤。这些变型都被认为是所要求保护的方面的一部分。
现将参照附图更全面地描述示例性的实施例。
由于在制造显示装置的过程中，设备、工艺环境、原材料等因素都存在一定波动性，当这种波动超出工艺规格时，就会产生工艺不良。具体而言，在制造器件时，工艺不良可能造成布线短接，从而导致短路；或者布线之间存在较多的灰尘颗粒，这造成相邻布线之间的搭接，从而导致短路。
图1示出了一种显示面板的平面结构。显示面板100包括位于显示面板100的周边区域内的栅极驱动电路20。该栅极驱动电路20包括用于向像素阵列提供栅极驱动信号的GOA单元210和用于向GOA单元210提供各种输入信号的信号线220。当信号线220中的特定信号线(例如，时钟信号线)短路时，将在短路位置处产生瞬时大电流和局部温度升高，由此可能导致器件毁坏。另外，外界环境中的一些极端操作条件(例如，高温度、高湿度、静电释放(Electro-Static Discharge，ESD)等)潜在地增加了器件毁坏的可能性。此外，当在信号线220中在位置a和b出现两处短 路时，由于位置a比位置b更靠近信号输入端IN且具有更小的IR降(IR-drop)，因此位置a处的短路电流大于位置b处的短路电流。
图2示出了栅极驱动电路的时钟信号线在正常操作情况下和短路情况下的特定位置的电流比较。图2(a)示出了在正常操作情况下所测量的电流。如图所示，所测得的电流为14mA。图2(b)示出了在短路情况下所测量的电流。如图所示，所测得的电流为169mA。由此可知，当在时钟信号线中发生短路时，短路位置处的电流显著升高，这会影响栅极驱动电路的正常操作。
图3示出了栅极驱动电路的时钟信号线在正常操作情况下和短路情况下的特定位置的温度比较。图3(a)示出了在正常操作情况下所测量的温度。如图所示，所测得的温度为27.7℃。图3(b)示出了在短路情况下所测量的温度。如图所示，所测得的温度为140℃。由此可知，当在时钟信号线中发生短路时，伴随着电流的急剧升高，短路位置处的温度显著升高。
如上所述，当在信号线中发生短路时，短路位置处的电流和温度都显著升高，由此不利地影响栅极驱动电路操作，并且如果在短路情况下继续使栅极驱动电路维持操作状态，则可能导致不可逆的器件毁坏。特别地，对于具有GOA配置的栅极驱动电路，如果缺乏短路保护机制，将导致具有栅极驱动电路的整个显示基板报废。
本公开提供了一种用于显示装置的保护电路，能够在显示装置中的栅极驱动电路中的信号线发生短路时停止对栅极驱动电路提供电力，由此降低短路导致的不利影响，从而有效地保护显示装置。
图4示出了根据本公开的实施例的显示装置的平面结构。如图4所示，显示装置1可以包括显示面板100、电平转换电路200、电源管理电路300和保护电路400。该显示面板100可以包括位于用于显示的显示区域内的显示组件10和位于围绕显示区域的周边区域内的栅极驱动电路20。栅极驱动电路20可以包括GOA单元210和与该GOA单元210耦接的信号线220。该信号线220可以被配置为传输用于GOA单元210的信号。作为示 例，信号线220可以包括被配置为向GOA单元210传输时钟信号的时钟信号线。需要说明的是，关于栅极驱动电路20的示例性实施例将稍后在下文中参考图9进行描述。
在本公开的示例性实施例中，电平转换电路200可以被配置为向栅极驱动电路20的信号输入端A提供输入信号。作为示例，栅极驱动电路20的信号输入端A可以包括用于接收来自电平转换电路200的时钟信号的时钟信号输入端。例如，电平转换电路200可以被配置为通过信号输出端B向栅极驱动电路20的信号输入端A提供时钟信号CLK。此外，电平转换电路200还可以被配置为通过其他信号输出端向栅极驱动电路20的对应信号输入端提供帧起始信号STV和用于GOA单元210的降噪信号对VDDO/VDDE。
在本公开的示例性实施例中，电源管理电路300可以被配置为向栅极驱动电路20提供电力PS1。此外，电源管理电路300还可以被配置为向电平转换电路200提供电力PS2。例如，电源管理电路300可以分别通过输出端C和D向栅极驱动电路20和电平转换电路200提供电力PS1、PS2。另外，电源管理电路300还可以被配置为向显示装置1提供模拟电压信号AVDD、数字电压信号DVDD、公共电极电压信号Vcom和灰阶参考信号GMA。
在本公开的示例性实施例中，保护电路400可以被配置为基于栅极驱动电路20的信号输入端A的电流I向电源管理电路300提供电源控制信号SC以使电源管理电路300停止向栅极驱动电路20提供电力PS1。由此，当栅极驱动电路20中出现短路问题时，该保护电路400能够及时触发电路保护，以便保护栅极驱动电路20，避免器件毁坏。
在本公开的示例性实施例中，保护电路400可以包括控制电路410、电流检测电路420、比较电路430、电流检测端E和控制信号输出端F。
在本公开的示例性实施例中，电流检测端E可以被配置为接收栅极驱动电路20的信号输入端A的电流I。
在本公开的示例性实施例中，控制信号输出端F可以被配置为向电源管理电路300提供电源控制信号SC。
在本公开的示例性实施例中，控制电路410可以与电流检测电路420和比较电路430耦接，并且可以被配置为向电流检测电路420发送第一控制信号C1以控制电流检测电路420的操作，以及向比较电路430发送第二控制信号C2以控制比较电路430的操作。
在本公开的示例性实施例中，电流检测电路420可以与电流检测端E和比较电路430耦接，并且可以被配置为在控制电路410的控制下(例如，在第一控制信号C1的控制下)检测栅极驱动电路20的信号输入端A的电流I，并将检测的电流I发送给比较电路430。
在本公开的示例性实施例中，比较电路430可以与控制信号输出端F耦接，并且可以被配置为在控制电路530的控制下(例如，在第二控制信号C2的控制下)将电流I与第一阈值I 0进行比较，并基于比较结果在控制信号输出端F产生电源控制信号SC。
在本公开的示例性实施例中，保护电路400与电平转换电路200和电源管理电路300可以集成为同一集成电路。例如，两者可形成在同一集成电路(Integrated Circuit，IC)中。作为示例，参考图4，保护电路400与电平转换电路200可以集成为同一集成电路IC1。在这种情况下，作为示例，保护电路400中的电流检测端E与电平转换电路200中的信号输出端B可以为同一端。作为另一示例，保护电路400与电源管理电路300可以集成为同一集成电路IC2。
进一步地，在本公开的示例性实施例中，电平转换电路200可以通过时钟信号线向栅极驱动电路提供时钟信号。具体地，如上所述，参考图4，电平转换电路200可以被配置为通过信号输出端B向栅极驱动电路20的信号输入端A提供时钟信号CLK。该时钟信号CLK经由栅极驱动电路20中的信号线220中的时钟信号线被传输到GOA单元。此外，作为示例，保护电路400的电流检测端E可以被耦接到时钟信号线。具体地，保护电 路400的电流检测端E可以与栅极驱动电路20的信号输入端A耦接。
在本公开的示例性实施例中，基于比较结果产生电源控制信号SC可以包括：在电流I大于第一阈值I 0时在控制信号输出端F产生电源控制信号SC。
在本公开的示例性实施例中，控制电路410还可以被配置为接收并存储控制参数。
作为示例，控制参数可以包括第一阈值I 0和检测时间t 0。具体地，第一阈值I 0可以为电流阈值。检测时间t 0可以为来自栅极驱动电路20的待检测的信号输入端A的电压信号的跳变沿至检测电流I的时刻之间的时间间隔。
进一步地，控制参数还可以包括第二阈值N。具体地，第二阈值N可以为基于检测时间t 0连续进行电流I的检测的次数N，其中，N为大于1的整数，并且每次检测的电流I都大于第一阈值I 0。
在本公开的示例性实施例中，进一步地，基于比较结果产生电源控制信号SC可以包括：在连续进行多次检测且检测次数等于第二阈值N时，在控制信号输出端F产生电源控制信号SC。通过设定第二阈值，可以有效避免因栅极驱动电路在正常操作时的电流波动而错误地产生电源控制信号SC。
在本公开的示例性实施例中，电源管理电路300的使能信号端EN接收该电源控制信号SC，并停止向栅极驱动电路20提供电力PS1。由此，在栅极驱动电路20中的信号线220中的时钟信号线发生短路时，停止对栅极驱动电路20的电力PS1供应，从而保护栅极驱动电路20，避免器件毁坏。
作为示例，保护电路400的电流检测端E可以仅与一条时钟信号线耦接，由此能够定位发生短路的位置。作为另一示例，保护电路400的电流检测端E可以与多条时钟信号线耦接。在这种情况下，本领域技术人员可以基于时钟时序等已知条件来大致定位发生短路的位置。
图5示出了根据本公开的实施例的用于栅极驱动电路的时钟信号电压信号和时钟信号电流信号的波形。如图5所示，在从时钟信号线的电压信号CLK的每次跳变沿开始经过t 0后检测时钟信号线的电流信号ICLK的电流I。
作为示例，检测时间t 0的范围可以为2-16μs。第一阈值I 0的范围可以为30-200mA。第二阈值N可以为4、8、16或32。
进一步地，作为示例，检测时间t 0可以为6μs。第一阈值I 0可以为50mA。第二阈值N可以为8。
图6示出了根据本公开的实施例的用于栅极驱动电路的时钟信号电压信号和时钟信号电流信号的波形。在图6所示的情况下，检测时间t 0为6μs。第一阈值I 0为50mA。第二阈值N为8。具体地，当连续8次在时钟信号线的电压信号CLK的每次跳变沿开始经过6μs处对时钟信号线的电流信号ICLK的电流I进行检测并且每次检测到的电流I都大于50mA时，保护电路400在控制信号输出端F产生电源控制信号SC。
作为示例，该电源控制信号SC可以包括电压信号。例如，该电压信号可以为低电压信号。例如，该低电压的范围可以为0-0.6V。
图7示出了根据本公开的实施例的在触发短路保护机制后所测量的短路位置处的温度。如图7所示，在触发短路保护机制之后，也就是，在栅极驱动电路20的信号线220中的时钟信号线发生短路的情况下，在电源管理电路300响应于来自保护电路400的电源控制信号SC而停止向栅极驱动电路20提供电力PS1时，测量的短路位置处的温度为29.8℃。该温度接近测量时的室温，可以有效避免器件毁坏。
在本公开的示例性实施例中，可选地，在保护电路400未与电源管理电路300集成为同一集成电路的情况下，保护电路400的控制信号输出端F与电源管理电路300的使能信号端EN之间可以设置有信号传递电路。
图8示出了根据本公开的实施例的保护电路与电源管理电路之间的信号传递电路。如图8所示，信号传递电路60可以与保护电路400和电源管 理电路300耦接。具体地，信号传递电路60可以耦接到保护电路400的控制信号输出端F，并且耦接到电源管理电路300的使能信号端EN。
在本公开的示例性实施例中，信号传递电路60可以被配置为控制信号输出端F输出的电源控制信号SC进行降噪和滤波。该信号传递电路60可以包括电阻R和电容C。作为示例，该电阻R可以为零欧姆电阻。需要注意，图8仅示出一个电容C，该图仅为示意性示例，本领域的技术人员可以根据实际需要和设计设置多个电容C。例如，作为另一示例，可以并联设置多个电容C，从而更有效地对信号进行降噪和滤波。
图9示出了根据本公开的实施例的栅极驱动电路的级联结构。栅极驱动电路20的GOA单元210包括多个级联的移位寄存器单元，例如，SR1、SR2、SR3。第一级移位寄存器单元SR1接收帧起始信号STV，作为其输入信号端IN接收的输入信号。除第一级移位寄存器单元SR1之外，每一级移位寄存器单元(例如，SR2和SR3)接收来自上一级移位寄存器单元的输出信号端OUT的输出信号，作为本级移位寄存器单元的输入信号。
如图9所示，每级移位寄存器单元的第一时钟信号端CLK1连接到第一时钟信号线CLK和第二时钟信号线CLKB中的一个，每级移位寄存器单元的第二时钟信号端CLK2连接到第一时钟信号线CLK和第二时钟信号线CLKB中的另一个。
在本公开的示例性实施例中，相邻的两级移位寄存器单元中的第一时钟信号端连接到不同的时钟信号线。例如，如图9所示的SR1和SR2的第一时钟信号端CLK1分别连接到CLK和CLKB。
本公开的实施例还提供了一种包括如上所述的保护电路的显示装置。显示装置还可以包括显示基板。显示基板可以包括用于显示的显示区域和围绕显示区域的周边区域。栅极驱动电路位于周边区域中。
在本公开的示例性实施例中，显示装置还可以包括位于周边区域中的时钟信号线。电平转换电路可以通过时钟信号线向栅极驱动电路提供时钟信号。保护电路的电流检测端可以被耦接到所述时钟信号线。
本公开的实施例还提供了一种使用如上所述的保护电路来保护显示装置的方法。由此，当显示装置中的栅极驱动电路中的信号线中发生短路时，触发保护机制以停止向栅极驱动电路提供电力，从而保护栅极驱动电路，避免器件毁坏。
图10示出了根据本公开的实施例的使用保护电路来保护显示装置的方法。如图10所示，该方法可以包括步骤S100和S200。在步骤S100处，响应于检测到的栅极驱动电路的信号输入端的电流，保护电路产生电源控制信号。在步骤S200处，响应于电源控制信号，电源管理电路停止向栅极驱动电路提供电力。
下面参考图4详细地描述该保护方法。应当理解，关于图4中的电路、信号端等与上文中对图4的描述类似，下文中不再对相应的术语进行赘述。
在本公开的示例性实施例中，步骤S100可以进一步包括：S101响应于来自保护电路400中的控制电路210的第一控制信号C1，保护电路400中的电流检测电路420接收栅极驱动电路20信号输入端A的电流I，并将检测到的电流I发送给保护电路400中的比较电路430；S102响应于来自控制电路210的第二控制信号C2，比较电路430接收来自电流检测电路420的检测电流I，并且将电流I与第一阈值I 0进行比较，在电流I大于第一阈值I 0且在连续进行多次检测且检测次数等于第二阈值N时，在控制信号输出端F产生电源控制信号SC。
这里，第二阈值N可以为基于检测时间t 0连续进行电流I的检测的次数N，其中，N为大于1的整数，并且每次检测的电流I都大于第一阈值I 0。检测时间t 0可以为来自栅极驱动电路20的待检测的信号输入端A的电压信号的跳变沿至检测电流I的时刻之间的时间间隔。
关于保护电路的其他描述可参考关于图2-9的详细描述，在此不再赘述。
以上为了说明和描述的目的提供了实施例的前述描述。其并不旨在是穷举的或者限制本申请。特定实施例的各个元件或特征通常不限于特定的 实施例，但是，在合适的情况下，这些元件和特征是可互换的并且可用在所选择的实施例中，即使没有具体示出或描述。同样也可以以许多方式来改变。这种改变不能被认为脱离了本申请，并且所有这些修改都包含在本申请的范围内。

Claims (15)

  1. 一种用于显示装置的保护电路，所述显示装置具有栅极驱动电路、电平转换电路和电源管理电路，所述电平转换电路被配置为向所述栅极驱动电路的信号输入端提供输入信号，所述电源管理电路被配置为向所述栅极驱动电路提供电力，
    其中，所述保护电路被配置为基于所述栅极驱动电路的所述信号输入端的电流向所述电源管理电路提供电源控制信号以使所述电源管理电路停止向所述栅极驱动电路提供电力。
  2. 根据权利要求1所述的保护电路，其中，所述保护电路包括控制电路、电流检测电路、比较电路、电流检测端和控制信号输出端，
    所述电流检测端被配置为接收所述栅极驱动电路的所述信号输入端的所述电流，
    所述控制信号输出端被配置为向所述电源管理电路提供所述电源控制信号，
    所述控制电路与所述电流检测电路和所述比较电路耦接，并被配置为向所述电流检测电路发送第一控制信号以控制所述电流检测电路的操作，以及向所述比较电路发送第二控制信号以控制所述比较电路的操作，
    所述电流检测电路与所述电流检测端和所述比较电路耦接，并被配置为在所述控制电路的控制下检测所述栅极驱动电路的所述信号输入端的所述电流，并将检测的所述电流发送给所述比较电路，以及
    所述比较电路与所述控制信号输出端耦接，并被配置为在所述控制电路的控制下将所述电流与第一阈值进行比较，并基于比较结果在所述控制信号输出端产生所述电源控制信号。
  3. 根据权利要求2所述的保护电路，其中，基于比较结果产生所述电源控制信号包括：在所述电流大于所述第一阈值时在所述控制信号输出端产生所述电源控制信号。
  4. 根据权利要求3所述的保护电路，其中，所述控制电路还被配置为接收并存储控制参数。
  5. 根据权利要求4所述的保护电路，其中，所述控制参数包括所述第一阈值和检测时间，
    其中，所述检测时间为来自所述栅极驱动电路的待检测的所述信号输入端的电压信号的跳变沿至检测所述电流的时刻之间的时间间隔。
  6. 根据权利要求5所述的保护电路，其中，所述控制参数还包括第二阈值，
    其中，所述第二阈值为基于所述检测时间连续进行所述电流的检测的次数N，其中，N为大于1的整数，每次检测的电流都大于所述第一阈值。
  7. 根据权利要求6所述的保护电路，其中，基于比较结果产生所述电源控制信号包括：在连续进行多次检测且检测次数等于所述第二阈值时，在所述控制信号输出端产生所述电源控制信号。
  8. 根据权利要求7所述的保护电路，其中，所述栅极驱动电路的所述信号输入端包括用于接收来自所述电平转换电路的时钟信号的时钟信号输入端。
  9. 根据权利要求8所述的保护电路，其中，所述检测时间的范围为2-16μs，
    所述第一阈值的范围为30-200mA，以及
    所述第二阈值为4、8、16或32。
  10. 根据权利要求9所述的保护电路，其中，所述检测时间为6μs，所述第一阈值为50mA，以及所述第二阈值为8。
  11. 根据权利要求1所述的保护电路，其中，所述保护电路与所述电平转换电路或所述电源管理电路集成为同一集成电路。
  12. 根据权利要求1所述的保护电路，其中，所述电源管理电路还被配置为向所述电平转换电路提供电力。
  13. 一种包括根据权利要求1-12中任一项所述的保护电路的显示装置，还包括显示基板，所述显示基板包括用于显示的显示区域和围绕所述显示区域的周边区域，
    其中，所述栅极驱动电路位于所述周边区域中。
  14. 根据权利要求13所述的显示装置，其中，所述栅极驱动电路包括位于所述周边区域中的时钟信号线，
    其中，所述电平转换电路通过所述时钟信号线向所述栅极驱动电路提供时钟信号，
    所述保护电路的所述电流检测端被耦接到所述时钟信号线。
  15. 一种使用根据权利要求1-11中任一项所述的保护电路来保护显示装置的方法，包括：响应于检测到的所述栅极驱动电路的所述信号输入端的所述电流，所述保护电路产生所述电源控制信号；以及
    响应于所述电源控制信号，所述电源管理电路停止向所述栅极驱动电路提供电力。
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