WO2022052249A1 - Oled 显示面板及其制备方法 - Google Patents

Oled 显示面板及其制备方法 Download PDF

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Publication number
WO2022052249A1
WO2022052249A1 PCT/CN2020/125035 CN2020125035W WO2022052249A1 WO 2022052249 A1 WO2022052249 A1 WO 2022052249A1 CN 2020125035 W CN2020125035 W CN 2020125035W WO 2022052249 A1 WO2022052249 A1 WO 2022052249A1
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Prior art keywords
layer
display panel
oled display
array substrate
light
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PCT/CN2020/125035
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English (en)
French (fr)
Inventor
唐甲
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US16/972,977 priority Critical patent/US11665935B2/en
Publication of WO2022052249A1 publication Critical patent/WO2022052249A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0241—Manufacture or treatment of multiple TFTs using liquid deposition, e.g. printing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0251—Manufacture or treatment of multiple TFTs characterised by increasing the uniformity of device parameters
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H10K71/12—Deposition of organic active material using liquid deposition, e.g. spin coating
    • H10K71/13—Deposition of organic active material using liquid deposition, e.g. spin coating using printing techniques, e.g. ink-jet printing or screen printing
    • H10K71/135—Deposition of organic active material using liquid deposition, e.g. spin coating using printing techniques, e.g. ink-jet printing or screen printing using ink-jet printing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/20—Changing the shape of the active layer in the devices, e.g. patterning
    • H10K71/231—Changing the shape of the active layer in the devices, e.g. patterning by etching of existing layers
    • H10K71/233—Changing the shape of the active layer in the devices, e.g. patterning by etching of existing layers by photolithographic etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present application relates to the field of display technology, and in particular, to an OLED display panel and a preparation method thereof.
  • OLEDs Organic light emitting diodes
  • AMOLED Active-matrix In terms of organic light emitting diode, active organic light emitting diode
  • the evaporation material reaches the pixel area with good film thickness uniformity, and the requirements for the flatness of the pixel area substrate are relatively loose
  • IJP Ink Jet
  • IJP Ink Jet Printing, inkjet printing
  • AMOLED ink (ink) printing to the pixel area is flowing, one of the main influencing factors of ink spreadability is the flatness of the pixel area substrate, the smaller the maximum step difference of the entire pixel area, the better. If the spreadability of ink exceeds this specification, the film thickness after drying will be uneven, which will ultimately affect the luminous effect. Therefore, the flatness of the IJP-AMOLED's Planarization Layer (PLN) has more stringent requirements.
  • PPN Planarization Layer
  • PLN is an organic photosensitive material.
  • the current solution is to thicken the PLN film layer.
  • the one-time flattening ability of PLN is limited, that is, when When the base level difference reaches a certain level, the PLN has been increased to a very thick (above 4um) and the flatness still cannot meet the requirements; 2.
  • PLN has an opening design, and the opening is too deep, which will affect the subsequent film deposition, such as climbing and breaking lines, etc. bad.
  • an OLED display panel includes a TFT array substrate, a passivation layer, a planarization layer, a planarization compensation layer, an anode metal layer, a pixel defining layer, and an organic light-emitting layer;
  • the TFT array substrate has a plurality of pixel regions, the pixel regions include a light-emitting region and a defined region surrounding the light-emitting region, and the surface of the TFT array substrate also has at least one raised portion, and the raised portion corresponds to the light emitting region;
  • the passivation layer is prepared on the surface of the TFT array substrate and completely covers the raised part;
  • the planarization layer has a first flat part and a second flat part, and the first flat part has The uneven surface corresponds to the light-emitting area, the second flat portion is in contact with both ends of the edge of the first flat portion and corresponds to the limited area and part of the light-emitting area, and the first flat portion is The thickness is smaller than the thickness of the second flat part;
  • the height of the surface of the flattening compensation layer from the surface of the TFT array substrate is the same as the height of the surface of the second flat part from the surface of the TFT array substrate;
  • the anode metal layer is prepared on the second flat part
  • the planarization compensation layer is prepared from organic ink through an inkjet printing process.
  • the material of the planarization layer is a hydrophobic organic material.
  • the anode metal layer is a three-layer ITO/Ag/ITO conductive layer or a single-layer ITO transmissive conductive layer.
  • the TFT array substrate is any one of a low temperature polysilicon thin film transistor, an oxidized thin film transistor, and a solid-phase crystalline polysilicon thin film transistor.
  • the material of the passivation layer is silicon nitride or silicon oxide.
  • the material of the planarization compensation layer is an organic insulating material.
  • embodiments of the present application further provide an OLED display panel, the OLED display panel includes a TFT array substrate, a passivation layer, a planarization layer, a planarization compensation layer, an anode metal layer, a pixel defining layer, and an organic light-emitting layer ;
  • the TFT array substrate has a plurality of pixel regions, the pixel regions include a light-emitting region and a defined region surrounding the light-emitting region, and the surface of the TFT array substrate also has at least one raised portion, and the raised portion corresponds to the light emitting region;
  • the passivation layer is prepared on the surface of the TFT array substrate and completely covers the raised part;
  • the planarization layer has a first flat part and a second flat part, and the first flat part has The uneven surface corresponds to the light-emitting area, the second flat portion is in contact with both ends of the edge of the first flat portion and corresponds to the limited area and part of the light-emitting area, and the first flat portion is The thickness is smaller than the thickness of the second flat part;
  • the height of the surface of the flattening compensation layer from the surface of the TFT array substrate is the same as the height of the surface of the second flat part from the surface of the TFT array substrate;
  • the anode metal layer is prepared on the second flat part
  • the material of the planarization layer is a hydrophobic organic material.
  • the anode metal layer is a three-layer ITO/Ag/ITO conductive layer or a single-layer ITO transmissive conductive layer.
  • the TFT array substrate is any one of a low temperature polysilicon thin film transistor, an oxidized thin film transistor, and a solid-phase crystalline polysilicon thin film transistor.
  • the material of the passivation layer is silicon nitride or silicon oxide.
  • the material of the planarization compensation layer is an organic insulating material.
  • an embodiment of the present application further provides a method for preparing an OLED display panel, the method comprising:
  • a TFT array substrate has a plurality of pixel regions, the pixel regions include a light-emitting region and a defined region surrounding the light-emitting region, and the surface of the TFT array substrate further has at least one protrusion, so the raised portion corresponds to the light-emitting region;
  • a passivation layer and a planarization layer are sequentially prepared on the surface of the TFT array substrate, the passivation layer completely covers the raised portion, and the planarization layer corresponding to a portion of the light-emitting region has an uneven surface ;
  • the TFT array substrate is any one of a low temperature polysilicon thin film transistor, an oxidized thin film transistor and a solid-phase crystalline polysilicon thin film transistor.
  • the material of the planarization layer is a hydrophobic organic material.
  • the material of the passivation layer is silicon nitride or silicon oxide.
  • the first flat portion has an uneven surface and corresponds to the light-emitting region
  • the second flat portion is connected to the first flat portion. Both ends of the edge of the portion are in contact with each other and correspond to the limited area and part of the light-emitting area, and the thickness of the first flat portion is smaller than the thickness of the second flat portion.
  • the S30 further includes: S301 , opening a first through hole in a portion of the planarization layer corresponding to the limited area, the first through hole passing through the The planarization layer and the passivation layer are exposed and the TFT array substrate is exposed.
  • the material of the planarization compensation layer is an organic insulating material.
  • the anode metal layer is a three-layer ITO/Ag/ITO conductive layer or a single-layer ITO transmissive conductive layer, and the pixel definition layer has a
  • the material is an inorganic insulating layer material.
  • the part of the planarization layer with the uneven surface located in the light-emitting area is thinned, and the planarization compensation layer is filled, and the planarization compensation layer is filled in the light-emitting area.
  • the organic film layer with high flatness can be obtained in the middle of the process, which solves the problem that the flattening layer is difficult to achieve the flatness required for the preparation in the IJP-AMOLED process of the prior art, the maximum step difference of the entire pixel area is large, and the spreadability of organic inkjet Uneven, the thickness of the light emitting layer after drying is uneven, which in turn affects the display effect of the OLED display panel.
  • FIG. 1 is a schematic structural diagram of an OLED display panel provided by an embodiment of the present application.
  • FIG. 2 is a schematic flowchart of a method for fabricating an OLED display panel according to an embodiment of the present application.
  • 3A-3F are schematic structural diagrams of a method for fabricating an OLED display panel according to an embodiment of the present application.
  • the embodiments of the present application are aimed at the IJP-AMOLED of the prior art.
  • the planarization layer is difficult to achieve the required flatness, the maximum step difference in the entire pixel area is large, the spreadability of the spraying material (ink) is uneven, and the drying
  • the non-uniform thickness of the light-emitting layer affects the technical problem of the display effect of the OLED display panel. This embodiment can solve the problem.
  • an embodiment of the present application provides an OLED display panel.
  • the OLED display panel includes a TFT array substrate 101 , a passivation layer 103 , a planarization layer 104 , a planarization compensation layer 105 , an anode metal layer 106 , and pixels The defining layer 107 and the organic light-emitting layer 108 ; wherein, the TFT array substrate 101 has a plurality of pixel regions 110 , and the pixel regions 110 include a light-emitting region 1101 and a defining region 1102 surrounding the light-emitting region 1101 .
  • a scan line and a data line are prepared at the same time, the scan line is correspondingly connected to the gate of the TFT device, and the data line is correspondingly connected to the source electrode of the TFT device.
  • the scan line and the data line are arranged so that the area corresponding to the scan line and the data line is higher than other areas, and at least one raised portion is formed, and the raised portion includes the first raised portion 1021 and The second raised portion 1022 .
  • the TFT array substrate 101 is any one of a low temperature polysilicon thin film transistor, an oxidized thin film transistor and a solid-phase crystalline polysilicon thin film transistor.
  • the passivation layer 103 is made of silicon nitride or silicon oxide, and the passivation layer 103 completely covers the first protrusions 1021 and the second protrusions 1022 .
  • the material of the planarization layer 104 is a hydrophobic organic material, preferably a polyimide material or a polymethyl methacrylate.
  • the planarization layer 104 has a first flat portion 1041 and a second flat portion 1052.
  • the first flat portion 1041 has an uneven surface and corresponds to the light emitting region 1101.
  • the second flat portion 1042 is connected to the first flat portion 1041. Both ends of the edge of a flat portion 1041 are in contact with each other and correspond to the defining area 1102 and part of the light emitting area 1101 .
  • the thickness of the first flat portion 1041 is smaller than the thickness of the second flat portion 1042 .
  • the planarization compensation layer 105 is printed on the first flat portion 1041 by an inkjet printing process with the second flat portion 1042 as a barrier. Since the organic ink itself has fluidity, after the organic ink is dried According to the terrain, the uneven surface of the first flat part 1041 is filled up automatically; finally, the height of the surface of the flattening compensation layer 105 from the surface of the TFT array substrate 101 is equal to the height of the second flat part The height of the surface of the part from the surface of the TFT array substrate is equal to H, and both are H.
  • the material of the planarization compensation layer 105 is an organic insulating material.
  • the anode metal layer 106 is prepared on the planarization compensation layer 105 and the second flat portion 1042 , and the anode metal layer 106 is connected to the TFT array substrate 101 through the first through hole 10421
  • the material of the anode metal layer 106 is preferably a three-layer ITO/Ag/ITO conductive layer or a single-layer ITO transmissive conductive layer, that is, the OLED display panel can be top-emitting or bottom-emitting, and the corresponding anode electrode is ITO/Ag /ITO and other reflective anodes and ITO transmission anodes.
  • the pixel definition layer 107 is prepared on the second flat portion 1042 , the pixel definition layer 107 covers both edges of the anode metal layer 106 , and the material of the pixel definition layer 107 is an inorganic insulating layer material, the pixel defining layer 107 defines the light emitting area 1101 and the defining area 1102 .
  • the organic light-emitting layer 108 is prepared in the light-emitting region 1101 through an inkjet printing process.
  • the OLED display panel provided by the embodiment of the present application uses a hydrophobic organic material as the planarization layer, and uses a halftone mask to weakly expose the pixel section.
  • Device lifetime or efficiency issues are examples of the organic ink for printing the flat compensation layer, and uses a halftone mask to weakly expose the pixel section.
  • an embodiment of the present application further provides a method for preparing the OLED display panel, the method includes the following steps:
  • the TFT array substrate 101 has a plurality of pixel regions 110, the pixel regions include a light-emitting region 1101 and a defined region 1102 surrounding the light-emitting region 1101, and the surface of the TFT array substrate 101 also has At least one protruding portion, the protruding portion corresponds to the light-emitting area 1101 .
  • the S10 further includes:
  • a substrate is provided; in step S102 , a TFT (thin film transistor) device is prepared on the surface of the substrate to form a TFT array substrate 101 .
  • a scan line and a data line are prepared at the same time, the scan line is correspondingly connected to the gate electrode of the TFT device, and the data line is correspondingly connected to the source electrode of the TFT device.
  • the scan line and the data line are arranged so that the area corresponding to the scan line and the data line is higher than other areas, and at least one raised portion is formed, and the raised portion includes the first raised portion 1021 and The second raised portion 1022 .
  • the TFT array substrate 101 has a plurality of pixel regions 110 , and the pixel regions 110 include a light-emitting region 1101 , a defined region 1102 surrounding the light-emitting region 1101 , the first raised portion 1021 and the second The raised portions 1022 all correspond to the light-emitting regions 1101 .
  • the TFT array substrate 101 is any one of a low temperature polysilicon thin film transistor, an oxidized thin film transistor and a solid-phase crystalline polysilicon thin film transistor, as shown in FIG. 3A .
  • a passivation layer 103 and a planarization layer 104 are sequentially prepared on the surface of the TFT array substrate 101 , the passivation layer 103 completely covers the raised portion, and the planarization layer 104 corresponds to a part of the light emitting area 1101 The area has a bumpy surface.
  • the S20 further includes:
  • a passivation layer 103 is deposited on the surface of the TFT array substrate 101.
  • the passivation layer 103 is made of silicon nitride or silicon oxide, and the passivation layer 103 completely covers the first protrusions. part 1021 and the second raised part 1022; after that, a planarization layer 104 is deposited on the passivation layer 103, and the material of the planarization layer 104 is a hydrophobic organic material, preferably a polyimide Amine material or polymethyl methacrylate. Due to the existence of the protrusions, a region of the planarization layer 104 corresponding to the light emitting region 1101 has an uneven surface, as shown in FIG. 3B .
  • the S30 further includes:
  • a half tone mask 20 is provided, and the half tone mask 20 has a half-exposed part 201 , a completely unexposed part 202 and a fully exposed part 203 .
  • the planarization layer 104 is subjected to an exposure thinning process using the halftone mask 20 .
  • the planarization layer 104 forms a first planar portion 1041 at a portion corresponding to the half-exposed portion 201
  • the planarization layer 104 forms a second planar portion 1042 at a portion corresponding to the completely unexposed portion 202 .
  • the planarization layer 104 forms a first through hole 10421 in a portion corresponding to the fully exposed portion 203 .
  • the first flat portion 1041 has an uneven surface and corresponds to the light emitting area 1101
  • the second flat portion 1102 is in contact with both edges of the first flat portion 1101 and corresponds to the limiting area 1102 and In part of the light-emitting area 1101 , the second flat portion 1102 has a flat surface; the thickness of the first flat portion 1041 is smaller than the thickness of the second flat portion 1042 .
  • the first through hole 10421 corresponds to the defined region 1102 , the first through hole 10421 penetrates through the planarization layer 104 and the passivation layer 103 and exposes the TFT array substrate 101 , as shown in FIG. 3C shown.
  • the height of the surface of the planarization compensation layer 105 from the surface of the TFT array substrate 101 is the same as the height of the surface of the TFT array substrate 101.
  • the surface of the second flat portion is flush with the height of the surface of the TFT array substrate.
  • the S40 further includes:
  • the planarization compensation layer 105 is printed on the first flat portion 1041 by an inkjet printing process with the second flat portion 1042 as a barrier. Since the organic ink itself has fluidity, the organic ink will be automatically filled according to the terrain after drying. , the uneven surface of the first flat portion 1041 is filled up; finally, the height of the surface of the flattening compensation layer 105 from the surface of the TFT array substrate 101 is equal to the distance between the surface of the second flat portion The heights of the surfaces of the TFT array substrates are equal to each other, and both are H.
  • the material of the planarization compensation layer 105 is an organic insulating material, as shown in FIG. 3D .
  • an anode metal layer 106 is formed on the planarization compensation layer 105 and the second flat portion 1042 , and then a pixel definition layer 107 is formed on the second flat portion 1042 , and the pixel definition layer 107 covers part of the The anode metal layer 106 is described.
  • the S50 further includes:
  • An anode metal layer 106 is prepared on the planarization compensation layer 105 and the second flat portion 1042.
  • the anode metal layer 106 is connected to the TFT array substrate 101 through the first through holes 10421;
  • the material of the layer 106 is preferably a three-layer ITO/Ag/ITO conductive layer or a single-layer ITO transmissive conductive layer, that is, the OLED display panel can be top-emitting or bottom-emitting, and the corresponding anode electrode is a reflective type such as ITO/Ag/ITO.
  • Anode and ITO transmissive anode is prepared on the planarization compensation layer 105 and the second flat portion 1042.
  • the anode metal layer 106 is connected to the TFT array substrate 101 through the first through holes 10421;
  • the material of the layer 106 is preferably a three-layer ITO/Ag/ITO conductive layer or a single-layer ITO transmissive conductive layer, that is, the OLED
  • a pixel definition layer 107 is prepared on the second flat portion 1042, the pixel definition layer 107 covers both edges of the anode metal layer 106, and the material of the pixel definition layer 107 is an inorganic insulating layer material, so The pixel definition layer 107 defines the light emitting area 1101 and the defining area 1102, as shown in FIG. 3E.
  • the S60 further includes:
  • an organic light-emitting layer 108 is printed on the portion of the anode metal layer 106 corresponding to the light-emitting region 1102 by an inkjet printing process, and the organic light-emitting layer 108 is used to make the OLED display panel. glow, as shown in Figure 3F.
  • the preparation method of the OLED display panel provided by the embodiment of the present application can improve the flatness of the IJP-AMOLED substrate without adding a photomask, make the spreading thickness of the printed organic ink uniform, and prevent uneven lighting and light emission of the backplane, which affects the OLED. Device lifetime or efficiency.
  • the part of the planarization layer with the uneven surface located in the light emitting area is thinned, and the planarization compensation layer is filled, and the planarization compensation layer can be filled in the light emitting area.
  • the organic film layer with higher flatness is obtained, which solves the problem that the flattening layer is difficult to achieve the required flatness in the IJP-AMOLED process of the prior art, the maximum step difference in the entire pixel area is large, and the spreadability of organic inkjet is uneven. , the thickness of the light emitting layer after drying is not uniform, thereby affecting the display effect of the OLED display panel.

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  • Manufacturing & Machinery (AREA)
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  • Optics & Photonics (AREA)
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Abstract

一种OLED显示面板及其制备方法，所述OLED显示面板至少包括TFT阵列基板、钝化层、平坦化层以及平坦化补偿层；所述平坦化层具有对应发光区的第一平坦部以及对应限定区和部分所述发光区的第二平坦部；所述平坦化补偿层的表面距离所述TFT阵列基板表面的高度与所述第二平坦部的表面距离所述TFT阵列基板表面的高度平齐。

Description

OLED显示面板及其制备方法 技术领域
本申请涉及显示技术领域，尤其涉及一种OLED显示面板及其制备方法。
 背景技术
有机发光二极管(organic light emitting diode，OLED)具有自发光性、应答速度快、广视角等特点，应用前景广阔。对于蒸镀AMOLED(Active-matrix organic light emitting diode，主动式有机发光二极体)来讲，蒸镀材料到达像素区膜厚均匀性好，对像素区基底平坦度的要求相对较松，而IJP(Ink Jet Printing，喷墨印刷)工艺的AMOLED的ink(油墨)打印到像素区是流动的，ink铺展性的主要影响因素之一是像素区基底的平坦度，要求整个像素区最大段差越小越好，超过该规格时ink的铺展性不均，则烘干后膜厚不均，最终影响发光效果，因此IJP- AMOLED的平坦化层（Planarization Layer，PLN）的平坦能力有了更苛刻的要求。
PLN是有机感光材料，目前的应对方案是PLN膜层的加厚，段差越大需要越厚的 PLN，所以存在的问题及可能的风险：1、PLN的一次平坦化能力是有限的，即当基底段差达到一定程度，PLN已经增加至很厚(4um以上)平坦度依然不能达到要求；2、PLN都有开孔设计，开孔过深对后续的薄膜沉积有影响，比如爬坡断线等不良。
综上所述，现有技术的IJP-AMOLED在制程中，平坦化层难以达到制备需求的平整度，整个像素区最大段差较大，ink的铺展性不均匀，烘干后的发光层膜厚不均匀，进而影响 OLED显示面板的显示效果。
 技术问题
现有技术的IJP-AMOLED在制程中，平坦化层难以达到制备需求的平整度，整个像素区最大段差较大，ink的铺展性不均匀，烘干后的发光层膜厚不均匀，进而影响 OLED显示面板的显示效果。
 技术解决方案
第一方面，提供一种OLED显示面板，所述OLED显示面板包括TFT阵列基板、钝化层、平坦化层、平坦化补偿层、阳极金属层、像素限定层以及有机发光层；
其中，所述TFT阵列基板具有多个像素区，所述像素区包括发光区以及围绕所述发光区的限定区，所述TFT阵列基板表面还具有至少一个凸起部，所述凸起部对应所述发光区；所述钝化层制备于所述TFT阵列基板表面并完全覆盖所述凸起部；所述平坦化层具有第一平坦部以及第二平坦部，所述第一平坦部具有凹凸不平的表面且对应所述发光区，所述第二平坦部与所述第一平坦部的边缘两端相接触且对应所述限定区以及部分所述发光区，所述第一平坦部的厚度小于所述第二平坦部的厚度；所述平坦化补偿层的表面距离所述TFT阵列基板表面的高度与所述第二平坦部的表面距离所述TFT阵列基板表面的高度平齐；所述阳极金属层制备于所述第二平坦部以及所述平坦化补偿层上；所述像素限定层制备于所述第二平坦部上并覆盖部分所述阳极金属层；所述有机发光层制备于所述阳极金属层上且对应所述发光区。
其中，所述平坦化补偿层由有机墨水经喷墨打印工艺制备而成。在本申请实施例提供的OLED显示面板中，所述平坦化层的材料为疏水性的有机材料。
在本申请实施例提供的OLED显示面板中，所述阳极金属层为三层ITO/Ag/ITO导电层或者单层ITO透射型导电层。
在本申请实施例提供的OLED显示面板中，所述TFT阵列基板为低温多晶硅薄膜晶体管、氧化型薄膜晶体管以及固相结晶多晶硅薄膜晶体管中的任意一种。
在本申请实施例提供的OLED显示面板中，所述钝化层的材料为硅氮化物或者硅氧化物。
在本申请实施例提供的OLED显示面板中，所述平坦化补偿层的材料为有机绝缘材料。
第二方面，本申请实施例还提供一种OLED显示面板，所述OLED显示面板包括TFT阵列基板、钝化层、平坦化层、平坦化补偿层、阳极金属层、像素限定层以及有机发光层；
其中，所述TFT阵列基板具有多个像素区，所述像素区包括发光区以及围绕所述发光区的限定区，所述TFT阵列基板表面还具有至少一个凸起部，所述凸起部对应所述发光区；所述钝化层制备于所述TFT阵列基板表面并完全覆盖所述凸起部；所述平坦化层具有第一平坦部以及第二平坦部，所述第一平坦部具有凹凸不平的表面且对应所述发光区，所述第二平坦部与所述第一平坦部的边缘两端相接触且对应所述限定区以及部分所述发光区，所述第一平坦部的厚度小于所述第二平坦部的厚度；所述平坦化补偿层的表面距离所述TFT阵列基板表面的高度与所述第二平坦部的表面距离所述TFT阵列基板表面的高度平齐；所述阳极金属层制备于所述第二平坦部以及所述平坦化补偿层上；所述像素限定层制备于所述第二平坦部上并覆盖部分所述阳极金属层；所述有机发光层制备于所述阳极金属层上且对应所述发光区。
在本申请实施例提供的OLED显示面板中，所述平坦化层的材料为疏水性的有机材料。
在本申请实施例提供的OLED显示面板中，所述阳极金属层为三层ITO/Ag/ITO导电层或者单层ITO透射型导电层。
在本申请实施例提供的OLED显示面板中，所述TFT阵列基板为低温多晶硅薄膜晶体管、氧化型薄膜晶体管以及固相结晶多晶硅薄膜晶体管中的任意一种。
在本申请实施例提供的OLED显示面板中，所述钝化层的材料为硅氮化物或者硅氧化物。
在本申请实施例提供的OLED显示面板中，所述平坦化补偿层的材料为有机绝缘材料。
第三方面，本申请实施例又提供一种OLED显示面板的制备方法，所述方法包括：
S10，提供TFT阵列基板，所述TFT阵列基板具有多个像素区，所述像素区包括发光区以及围绕所述发光区的限定区，所述TFT阵列基板表面还具有至少一个凸起部，所述凸起部对应所述发光区；
S20，在所述TFT阵列基板表面依次制备钝化层以及平坦化层，所述钝化层完全覆盖所述凸起部，所述平坦化层对应部分所述发光区的区域具有凹凸不平的表面；
S30，使用半色调掩膜版对位于所述发光区的部分所述平坦化层进行减薄处理，形成第一平坦部以及第二平坦部；
S40，以所述第二平坦部为阻挡在所述第一平坦部上打印平坦化补偿层，所述平坦化补偿层的表面距离所述TFT阵列基板表面的高度与所述第二平坦部的表面距离所述TFT阵列基板表面的高度平齐；
S50，在所述平坦化补偿层以及所述第二平坦部上制备阳极金属层，之后在所述第二平坦部上制备像素定义层，所述像素定义层覆盖部分所述阳极金属层；
S60，以所述像素定义层为阻挡在所述阳极金属层对应所述发光区的部分打印有机发光层。
在本申请实施例提供的OLED显示面板的制备方法中，所述S10中，所述TFT阵列基板为低温多晶硅薄膜晶体管、氧化型薄膜晶体管以及固相结晶多晶硅薄膜晶体管中的任意一种。
在本申请实施例提供的OLED显示面板的制备方法中，所述S20中，所述平坦化层的材料为疏水性的有机材料。
在本申请实施例提供的OLED显示面板的制备方法中，所述S20中，所述钝化层的材料为硅氮化物或者硅氧化物。
在本申请实施例提供的OLED显示面板的制备方法中，所述S30中，所述第一平坦部具有凹凸不平的表面且对应所述发光区，所述第二平坦部与所述第一平坦部的边缘两端相接触且对应所述限定区以及部分所述发光区，所述第一平坦部的厚度小于所述第二平坦部的厚度。
在本申请实施例提供的OLED显示面板的制备方法中，所述S30还包括：S301，在所述平坦化层对应所述限定区的部分开设第一通孔，所述第一通孔贯穿所述平坦化层以及所述钝化层并暴露出所述TFT阵列基板。
在本申请实施例提供的OLED显示面板的制备方法中，所述S40中，所述平坦化补偿层的材料为有机绝缘材料。
在本申请实施例提供的OLED显示面板的制备方法中，所述S50中，所述阳极金属层为三层ITO/Ag/ITO导电层或者单层ITO透射型导电层，所述像素定义层的材料为无机绝缘层材料。
 有益效果
相较于现有技术，本申请实施例所提供的OLED 显示面板及其制备方法，将位于发光区中的具有凹凸不平表面的部分平坦化层减薄，并填充平坦化补偿层，在发光区中可得到较高平坦度的有机膜层，解决了现有技术的IJP-AMOLED在制程中，平坦化层难以达到制备需求的平整度，整个像素区最大段差较大，有机喷墨的铺展性不均匀，烘干后的发光层膜厚不均匀，进而影响OLED显示面板的显示效果。
 附图说明
图1为本申请实施例提供的OLED显示面板的结构示意图。
图2为本申请实施例提供的OLED显示面板的制备方法流程示意图。
图3A-图3F为本申请实施例提供的OLED显示面板的制备方法结构示意图。
 本发明的实施方式
本申请实施例针对现有技术的IJP-AMOLED在制程中，平坦化层难以达到制备需求的平整度，整个像素区最大段差较大，喷涂材料(ink)的铺展性不均匀，烘干后的发光层膜厚不均匀，进而影响OLED显示面板的显示效果的技术问题，本实施例能够解决该缺陷。
如图1所示，本申请实施例提供一种OLED显示面板，所述OLED显示面板包括TFT阵列基板101、钝化层103、平坦化层104、平坦化补偿层105、阳极金属层106、像素限定层107以及有机发光层108；其中，所述TFT阵列基板101具有多个像素区110，所述像素区110包括发光区1101以及围绕所述发光区1101的限定区1102。
具体地，在制备所述TFT器件时，同时制备扫描线和数据线，所述扫描线对应连接所述TFT器件的栅极，所述数据线对应连接所述TFT器件的源极。所述扫描线与所述数据线的设置，使得所述扫描线与所述数据线对应的区域高于其他区域，形成至少一个凸起部，所述凸起部包括第一凸起部1021以及第二凸起部1022。所述TFT阵列基板101为低温多晶硅薄膜晶体管、氧化型薄膜晶体管以及固相结晶多晶硅薄膜晶体管中的任意一种。
优选地，所述钝化层103的材料为硅氮化物或者硅氧化物，所述钝化层103完全覆盖所述第一凸起部1021以及所述第二凸起部1022。
优选地，所述平坦化层104的材料为疏水性的有机材料，优选为聚酰亚胺材料或者聚甲基丙烯酸甲酯。所述平坦化层104具有第一平坦部1041以及第二平坦部1052，所述第一平坦部1041具有凹凸不平的表面且对应所述发光区1101，所述第二平坦部1042与所述第一平坦部1041的边缘两端相接触且对应所述限定区1102以及部分所述发光区1101，所述第一平坦部1041的厚度小于所述第二平坦部1042的厚度。
具体地，以所述第二平坦部1042为阻挡通过喷墨打印工艺在所述第一平坦部1041上打印所述平坦化补偿层105，由于有机墨水本身具有流动性，所述有机墨水干燥后会根据地势自动填充，将所述第一平坦部1041的凹凸不平的表面填平；最终，使得所述平坦化补偿层105的表面距离所述TFT阵列基板101表面的高度与所述第二平坦部的表面距离所述TFT阵列基板表面的高度平齐，均为H。优选的，所述平坦化补偿层105的材料为有机绝缘材料。
具体地，在所述平坦化补偿层105以及所述第二平坦部1042上制备所述阳极金属层106，所述阳极金属层106经由所述第一通孔10421与所述TFT阵列基板101相连；所述阳极金属层106的材料优选为三层ITO/Ag/ITO导电层或者单层ITO透射型导电层，即所述OLED显示面板可以是顶发光或底发光，对应阳极电极为ITO/Ag/ITO等反射型阳极和ITO透射型阳极。
具体地，在所述第二平坦部1042上制备所述像素定义层107，所述像素定义层107覆盖所述阳极金属层106的两端边缘，所述像素定义层107的材料为无机绝缘层材料，所述像素定义层107定义出所述发光区1101以及所述限定区1102。
具体地，所述有机发光层108经由喷墨打印工艺制备于所述发光区1101中。
本申请实施例所提供的OLED显示面板采用具有疏水性的有机材料作为平坦化层，并利用半色调掩膜版将像素区段差弱曝，显影后该区域的平坦化层随地势均匀降低一定的膜厚，以像素区周围的平坦化层（未曝光部分）为阻挡堤坝（Barrier Bank），打印平坦补偿层的有机墨水，由于有机墨水本身具有流动性，会根据地势自动填充，最终将整个像素区填平，改善了制备有机发光层的有机墨水干燥后厚度不均匀，影响OLED器件寿命或效率的问题。
如图2所示，本申请实施例还提供一种所述OLED显示面板的制备方法，所述方法包括如下步骤：
S10，提供TFT阵列基板101，所述TFT阵列基板101具有多个像素区110，所述像素区包括发光区1101以及围绕所述发光区1101的限定区1102，所述TFT阵列基板101表面还具有至少一个凸起部，所述凸起部对应所述发光区1101。
具体地，所述S10还包括：
步骤S101，提供一基板；步骤S102，在所述基板表面制备TFT（薄膜晶体管）器件，形成TFT阵列基板101。在制备所述TFT器件时，同时制备扫描线和数据线，所述扫描线对应连接所述TFT器件的栅极，所述数据线对应连接所述TFT器件的源极。所述扫描线与所述数据线的设置，使得所述扫描线与所述数据线对应的区域高于其他区域，形成至少一个凸起部，所述凸起部包括第一凸起部1021以及第二凸起部1022。
具体地，所述TFT阵列基板101具有多个像素区110，所述像素区110包括发光区1101以及围绕所述发光区1101的限定区1102，所述第一凸起部1021以及所述第二凸起部1022均对应所述发光区1101。优选地，所述TFT阵列基板101为低温多晶硅薄膜晶体管、氧化型薄膜晶体管以及固相结晶多晶硅薄膜晶体管中的任意一种，如图3A所示。
S20，在所述TFT阵列基板101表面依次制备钝化层103以及平坦化层104，所述钝化层103完全覆盖所述凸起部，所述平坦化层104对应部分所述发光区1101的区域具有凹凸不平的表面。
具体地，所述S20还包括：
首先，在所述TFT阵列基板101表面沉积制备一层钝化层103，所述钝化层103的材料为硅氮化物或者硅氧化物，所述钝化层103完全覆盖所述第一凸起部1021以及所述第二凸起部1022；之后，在所述钝化层103上沉积一层平坦化层104，所述平坦化层104的材料为疏水性的有机材料，优选为聚酰亚胺材料或者聚甲基丙烯酸甲酯。由于所述凸起部的存在，所述平坦化层104对应部分所述发光区1101的区域具有凹凸不平的表面，如图3B所示。
S30，使用半色调掩膜版20对位于所述发光区1101的部分所述平坦化层104进行减薄处理，形成第一平坦部1041以及第二平坦部1042。
具体地，所述S30还包括：
首先提供一半色调掩膜版20（Half tone mask），所述半色调掩膜版20具有半曝光部201、完全不曝光部202以及完全曝光部203。之后，使用所述半色调掩膜版20对所述平坦化层104进行曝光减薄处理。所述平坦化层104在对应于所述半曝光部201的部分形成第一平坦部1041，所述平坦化层104在对应于所述完全不曝光部202的部分形成第二平坦部1042，所述平坦化层104在对应于所述完全曝光部203的部分形成第一通孔10421。其中，由于所述半曝光部201的曝光能量相同，则所述平坦化层104减薄的厚度ΔH相同。因此所述第一平坦部1041具有凹凸不平的表面且对应所述发光区1101，所述第二平坦部1102与所述第一平坦部1101的边缘两端相接触且对应所述限定区1102以及部分所述发光区1101，所述第二平坦部1102具有平坦的表面；所述第一平坦部1041的厚度小于所述第二平坦部1042的厚度。具体地，所述第一通孔10421对应所述限定区1102，所述第一通孔10421贯穿所述平坦化层104以及所述钝化层103并暴露出所述TFT阵列基板101，如图3C所示。
S40，以所述第二平坦部1042为阻挡在所述第一平坦部1041上打印平坦化补偿层105，所述平坦化补偿层105的表面距离所述TFT阵列基板101表面的高度与所述第二平坦部的表面距离所述TFT阵列基板表面的高度平齐。
具体地，所述S40还包括：
以所述第二平坦部1042为阻挡通过喷墨打印工艺在所述第一平坦部1041上打印平坦化补偿层105，由于有机墨水本身具有流动性，所述有机墨水干燥后会根据地势自动填充，将所述第一平坦部1041的凹凸不平的表面填平；最终，使得所述平坦化补偿层105的表面距离所述TFT阵列基板101表面的高度与所述第二平坦部的表面距离所述TFT阵列基板表面的高度平齐，均为H。优选的，所述平坦化补偿层105的材料为有机绝缘材料，如图3D所示。
S50，在所述平坦化补偿层105以及所述第二平坦部1042上制备阳极金属层106，之后在所述第二平坦部1042上制备像素定义层107，所述像素定义层107覆盖部分所述阳极金属层106。
具体地，所述S50还包括：
在所述平坦化补偿层105以及所述第二平坦部1042上制备阳极金属层106，所述阳极金属层106经由所述第一通孔10421与所述TFT阵列基板101相连；所述阳极金属层106的材料优选为三层ITO/Ag/ITO导电层或者单层ITO透射型导电层，即所述OLED显示面板可以是顶发光或底发光，对应阳极电极为ITO/Ag/ITO等反射型阳极和ITO透射型阳极。之后，在所述第二平坦部1042上制备像素定义层107，所述像素定义层107覆盖所述阳极金属层106的两端边缘，所述像素定义层107的材料为无机绝缘层材料，所述像素定义层107定义出所述发光区1101以及所述限定区1102，如图3E所示。
S60，以所述像素定义层107为阻挡在所述阳极金属层106对应所述发光区1102的部分打印有机发光层108。
具体地，所述S60还包括：
以所述像素定义层107为阻挡，通过喷墨打印工艺在所述阳极金属层106对应所述发光区1102的部分打印有机发光层108，所述有机发光层108用于使所述OLED显示面板发光，如图3F所示。
本申请实施例提供的OLED 显示面板的制备方法，能够在不增加光罩情况下，提高IJP-AMOLED基底平坦程度，使打印有机墨水的铺展厚度均匀，防止背板点亮发光不均，影响OLED器件寿命或效率。
以上各个操作的具体实施可参见前面的实施例，在此不再赘述。
综上所述，本申请实施例所提供的OLED 显示面板及其制备方法，将位于发光区中的具有凹凸不平表面的部分平坦化层减薄，并填充平坦化补偿层，在发光区中可得到较高平坦度的有机膜层，解决了现有技术的IJP-AMOLED在制程中，平坦化层难以达到制备需求的平整度，整个像素区最大段差较大，有机喷墨的铺展性不均匀，烘干后的发光层膜厚不均匀，进而影响OLED显示面板的显示效果。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种OLED显示面板，其中，所述OLED显示面板包括：
    TFT阵列基板，所述TFT阵列基板具有多个像素区，所述像素区包括发光区以及围绕所述发光区的限定区，所述TFT阵列基板表面还具有至少一个凸起部，所述凸起部对应所述发光区；
    钝化层，制备于所述TFT阵列基板表面并完全覆盖所述凸起部；
    平坦化层，制备于所述钝化层上，所述平坦化层具有第一平坦部以及第二平坦部，所述第一平坦部具有凹凸不平的表面且对应所述发光区，所述第二平坦部与所述第一平坦部的边缘两端相接触且对应所述限定区以及部分所述发光区，所述第一平坦部的厚度小于所述第二平坦部的厚度；
    平坦化补偿层，制备于所述第一平坦部上，所述平坦化补偿层的表面距离所述TFT阵列基板表面的高度与所述第二平坦部的表面距离所述TFT阵列基板表面的高度平齐；
    阳极金属层，制备于所述第二平坦部以及所述平坦化补偿层上；
    像素限定层，制备于所述第二平坦部上并覆盖部分所述阳极金属层；
    有机发光层，制备于所述阳极金属层上且对应所述发光区；
    其中，所述平坦化补偿层由有机墨水经喷墨打印工艺制备而成。
  2. 根据权利要求1所述的OLED显示面板，其中，所述平坦化层的材料为疏水性的有机材料。
  3. 根据权利要求1所述的OLED显示面板，其中，所述阳极金属层为三层ITO/Ag/ITO导电层或者单层ITO透射型导电层。
  4. 根据权利要求1所述的OLED显示面板，其中，所述TFT阵列基板为低温多晶硅薄膜晶体管、氧化型薄膜晶体管以及固相结晶多晶硅薄膜晶体管中的任意一种。
  5. 根据权利要求1所述的OLED显示面板，其中，所述钝化层的材料为硅氮化物或者硅氧化物。
  6. 根据权利要求1所述的OLED显示面板，其中，所述平坦化补偿层的材料为有机绝缘材料。
  7. 一种OLED显示面板，其中，所述OLED显示面板包括：
    TFT阵列基板，所述TFT阵列基板具有多个像素区，所述像素区包括发光区以及围绕所述发光区的限定区，所述TFT阵列基板表面还具有至少一个凸起部，所述凸起部对应所述发光区；
    钝化层，制备于所述TFT阵列基板表面并完全覆盖所述凸起部；
    平坦化层，制备于所述钝化层上，所述平坦化层具有第一平坦部以及第二平坦部，所述第一平坦部具有凹凸不平的表面且对应所述发光区，所述第二平坦部与所述第一平坦部的边缘两端相接触且对应所述限定区以及部分所述发光区，所述第一平坦部的厚度小于所述第二平坦部的厚度；
    平坦化补偿层，制备于所述第一平坦部上，所述平坦化补偿层的表面距离所述TFT阵列基板表面的高度与所述第二平坦部的表面距离所述TFT阵列基板表面的高度平齐；
    阳极金属层，制备于所述第二平坦部以及所述平坦化补偿层上；
    像素限定层，制备于所述第二平坦部上并覆盖部分所述阳极金属层；
    有机发光层，制备于所述阳极金属层上且对应所述发光区。
  8. 根据权利要求7所述的OLED显示面板，其中，所述平坦化层的材料为疏水性的有机材料。
  9. 根据权利要求7所述的OLED显示面板，其中，所述阳极金属层为三层ITO/Ag/ITO导电层或者单层ITO透射型导电层。
  10. 根据权利要求7所述的OLED显示面板，其中，所述TFT阵列基板为低温多晶硅薄膜晶体管、氧化型薄膜晶体管以及固相结晶多晶硅薄膜晶体管中的任意一种。
  11. 根据权利要求7所述的OLED显示面板，其中，所述钝化层的材料为硅氮化物或者硅氧化物。
  12. 根据权利要求7所述的OLED显示面板，其中，所述平坦化补偿层的材料为有机绝缘材料。
  13. 一种OLED显示面板的制备方法，其中，所述方法包括：
    S10，提供TFT阵列基板，所述TFT阵列基板具有多个像素区，所述像素区包括发光区以及围绕所述发光区的限定区，所述TFT阵列基板表面还具有至少一个凸起部，所述凸起部对应所述发光区；
    S20，在所述TFT阵列基板表面依次制备钝化层以及平坦化层，所述钝化层完全覆盖所述凸起部，所述平坦化层对应部分所述发光区的区域具有凹凸不平的表面；
    S30，使用半色调掩膜版对位于所述发光区的部分所述平坦化层进行减薄处理，形成第一平坦部以及第二平坦部；
    S40，以所述第二平坦部为阻挡在所述第一平坦部上打印平坦化补偿层，所述平坦化补偿层的表面距离所述TFT阵列基板表面的高度与所述第二平坦部的表面距离所述TFT阵列基板表面的高度平齐；
    S50，在所述平坦化补偿层以及所述第二平坦部上制备阳极金属层，之后在所述第二平坦部上制备像素定义层，所述像素定义层覆盖部分所述阳极金属层；
    S60，以所述像素定义层为阻挡在所述阳极金属层对应所述发光区的部分打印有机发光层。
  14. 根据权利要求13所述的OLED显示面板的制备方法，其中，所述S10中，所述TFT阵列基板为低温多晶硅薄膜晶体管、氧化型薄膜晶体管以及固相结晶多晶硅薄膜晶体管中的任意一种。
  15. 根据权利要求13所述的OLED显示面板的制备方法，其中，所述S20中，所述平坦化层的材料为疏水性的有机材料。
  16. 根据权利要求13所述的OLED显示面板的制备方法，其中，所述S20中，所述钝化层的材料为硅氮化物或者硅氧化物。
  17. 根据权利要求13所述的OLED显示面板的制备方法，其中，所述S30中，所述第一平坦部具有凹凸不平的表面且对应所述发光区，所述第二平坦部与所述第一平坦部的边缘两端相接触且对应所述限定区以及部分所述发光区，所述第一平坦部的厚度小于所述第二平坦部的厚度。
  18. 根据权利要求13所述的OLED显示面板的制备方法，其中，所述S30还包括：
    S301，在所述平坦化层对应所述限定区的部分开设第一通孔，所述第一通孔贯穿所述平坦化层以及所述钝化层并暴露出所述TFT阵列基板。
  19. 根据权利要求13所述的OLED显示面板的制备方法，其中，所述S40中，所述平坦化补偿层的材料为有机绝缘材料。
  20. 根据权利要求13所述的OLED显示面板的制备方法，其中，所述S50中，所述阳极金属层为三层ITO/Ag/ITO导电层或者单层ITO透射型导电层，所述像素定义层的材料为无机绝缘层材料。
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