WO2022050134A1 - Dispositif d'imagerie à semi-conducteurs et appareil électronique - Google Patents

Dispositif d'imagerie à semi-conducteurs et appareil électronique Download PDF

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Publication number
WO2022050134A1
WO2022050134A1 PCT/JP2021/031016 JP2021031016W WO2022050134A1 WO 2022050134 A1 WO2022050134 A1 WO 2022050134A1 JP 2021031016 W JP2021031016 W JP 2021031016W WO 2022050134 A1 WO2022050134 A1 WO 2022050134A1
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Prior art keywords
light receiving
receiving element
circuit
signal
analog
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PCT/JP2021/031016
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English (en)
Japanese (ja)
Inventor
潔志 牧川
洋介 植野
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ソニーセミコンダクタソリューションズ株式会社
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Publication of WO2022050134A1 publication Critical patent/WO2022050134A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith

Definitions

  • This disclosure relates to a solid-state image sensor and an electronic device.
  • a sensor equipped with a pixel array in which pixels such as a conventional CMOS (Complementary Metal-Oxide Semiconductor) element are formed in an array has a problem that the frame rate is low because signals are acquired in order from a predetermined element.
  • CMOS Complementary Metal-Oxide Semiconductor
  • Various technologies have been developed to increase the frame rate. In these techniques, while increasing the frame rate, the shape of the focal plane distortion may not be preferable.
  • connection lead wire to another semiconductor layer laminated under the pixel for example, in a back-illuminated sensor, on the front surface side of the pixel is required, and the connection with another circuit is required. It has low affinity and tends to be complicated. As a result, there is one aspect that is unsuitable for miniaturization of pixel size and increase in the number of pixels.
  • the present disclosure provides a solid-state image pickup device and an electronic device in which an array of light receiving elements is provided with a plurality of regions and the occurrence of distortion is suppressed.
  • the solid-state imaging device has a plurality of light receiving elements that photoelectrically convert light and output an analog signal along a row along a first direction and a second direction intersecting the first direction.
  • a first substrate having a light receiving element array arranged in a two-dimensional array as a row, and a second substrate laminated on the first substrate, which intersects the first direction and the second direction.
  • the analog circuit is divided into a first region and a second region, each of which has a continuous light receiving element, by a pixel dividing portion along the direction, and the analog circuit is a region that does not overlap with the light receiving element array in the third direction.
  • a first analog circuit connected to the light receiving element belonging to the first region via a first connecting portion arranged in the third direction, and a second arranged in a region not overlapping with the light receiving element array in the third direction.
  • a second analog circuit which is connected to the light receiving element belonging to the second region via a connecting portion, is provided.
  • the light receiving element array among the rows including the light receiving elements continuous in the second direction, one or a plurality of the rows in the first direction are selected, and a plurality of rows are arranged along the first direction.
  • the rows including the first signal line and the light receiving element continuous in the first direction one or more of the rows in the second direction are selected, and a plurality of the rows are arranged along the second direction.
  • a second signal line may be provided, and the analog signal output by the light receiving element selected by the first signal line is transmitted via the second signal line and processed by the analog circuit.
  • the second signal line may be electrically cut off at the pixel dividing portion.
  • the pixel dividing portion may be arranged near the center of the light receiving element array in the first direction.
  • the first connection portion may be connected to the second signal line belonging to the first region, and the light receiving element belonging to the first region and the first analog circuit may be connected to the second signal line.
  • the connection unit may be connected to the second signal line belonging to the second region, and may be connected to the light receiving element belonging to the second region and the second analog circuit.
  • the first connection portion and the second connection portion may be provided at least as many as the number of the rows along the second direction, respectively.
  • the second substrate may further include a control circuit that controls the order in which signals are output from the light receiving element.
  • the control circuit controls the reading order from the row provided on the outside in the light receiving element array toward the pixel dividing unit, and the first read mode and the pixel dividing unit in the light receiving element array. From the row at one end of the first direction to the other end in the light receiving element array, the second read mode, which controls the read order from to the outer row towards the row. A third read mode, which controls the order of reading toward the line, may be selected and controlled.
  • the first analog circuit and the second analog circuit may be driven exclusively.
  • the second board performs AE / AF processing for calculating a signal processing circuit that executes signal processing of the signal output by the analog circuit and parameters for adjusting exposure and focus based on the output of the signal processing circuit.
  • a circuit may be further provided, and the control circuit may control the exposure and focus of the light receiving element based on the output of the AE / AF processing circuit.
  • the control circuit may switch between the first read mode, the second read mode, and the third read mode based on the output of the AE / AF processing circuit.
  • the control circuit may select and control the first read mode or the second read mode until the exposure control and the focus control are completed based on the output of the AE / AF processing circuit. After the exposure control and the focus control are completed, the third read mode may be selected and controlled.
  • the second board further includes a signal processing circuit that executes signal processing of the signal output by the analog circuit, and a recognition processing circuit that executes object recognition processing based on the output of the signal processing circuit.
  • the control circuit may switch between the first read mode, the second read mode, and the third read mode based on the output of the recognition processing circuit.
  • the control circuit may select and control the first read mode or the second read mode until the object is detected based on the output of the recognition processing circuit, and the object is detected. Later, the third read mode may be selected and controlled.
  • the first analog circuit and the second analog circuit may process the analog signals of the different pixels belonging to the one or a plurality of the rows along the second direction at the same timing.
  • the first analog circuit and the second analog circuit may convert the analog signal into a digital signal
  • the second board is a logic circuit for processing the digital signal and is the first analog circuit.
  • a logic circuit which is arranged between the second analog circuits.
  • the logic circuit may include a memory so as to overlap the pixel dividing portion in the third direction.
  • a plurality of the pixel dividing portions, a region of the light receiving element array divided into a plurality of regions, and an analog circuit corresponding to each region may be provided.
  • the second board is output from a signal processing circuit that executes signal processing of the digital signal, an image processing circuit that executes image processing of the digital signal that is image information, the digital signal, and the signal processing circuit.
  • the data is stored in the memory, the data output by the signal processing circuit, the data output by the image processing circuit, and the storage unit for storing arbitrary data among the data output by the image processing circuit. It may be provided with an interface that outputs at least one arbitrary data or an arbitrary signal to the outside, or accepts an input of the data or a signal from the outside.
  • the electronic device includes the solid-state image sensor according to any one of the above.
  • the electronic device may be a smartphone, a tablet terminal, a digital camera, or a digital video camera.
  • the block diagram of the solid-state image pickup apparatus which concerns on one Embodiment The figure which shows typically the arrangement of each element of the solid-state image sensor which concerns on one Embodiment.
  • the figure which shows the reading order of the light receiving element which concerns on one Embodiment The figure which shows the reading order of the light receiving element which concerns on one Embodiment.
  • FIG. 1 is a block diagram showing the functions of the solid-state image sensor 1 according to the embodiment.
  • the solid-state image sensor 1 includes, for example, a first substrate 10 and a second substrate 20.
  • the first substrate 10 includes an optical system 12 and a light receiving element 14.
  • the second substrate 20 includes a signal processing circuit 22, a control circuit 24, and an AE / AF processing circuit 26.
  • the second substrate 20 may include, for example, an interface for inputting / outputting data between the above circuit and an external circuit or the like.
  • the optical system 12 is a system that corrects optical paths, aberrations, etc. for sensing light in the light receiving element 14.
  • the optical system 12 includes, for example, a lens (including a virtual lens or the like), and is grounded so that light is appropriately received by the light receiving element 14.
  • the light receiving element 14 includes an element that photoelectrically converts the received light and outputs an analog signal.
  • the light receiving element 14 includes, for example, a back-illuminated photodiode.
  • the light receiving element 14 is not limited to this configuration, and may be configured as a surface-illuminated type, or may be configured to include an element different from the photodiode.
  • the electric charge accumulated by the light receiving element 14 by photoelectric conversion is transmitted to the second substrate via the connection portion 30.
  • Each light receiving element 14 may be provided with a color filter.
  • the color filter may be arranged by, for example, a Bayer arrangement or another arrangement. When a color filter is used, processing using the color matrix may be executed by a signal processing circuit 22 or the like described later. Further, in order to reproduce colors, an organic photoelectric conversion film may be used as the light receiving element 14 instead of the configuration provided with a filter.
  • the signal processing circuit 22 is a circuit that processes the signal output by the light receiving element 14.
  • the signal processing circuit 22 includes, for example, an ADC (Analog to Digital Converter), and converts an analog signal output by the light receiving element 14 into a digital signal.
  • ADC Analog to Digital Converter
  • DAC Digital to Analog Converter
  • An amplifier which amplifies the output from the counter, may be provided.
  • the signal processing circuit 22 further includes a circuit that executes appropriate signal processing and image processing on this digital signal.
  • the signal processing circuit may include, for example, a circuit that generates image data such as interpolation processing and color adjustment processing of the signal output by the light receiving element 14.
  • the image processing circuit may include a circuit that executes various filter processing, deformation processing, and the like on the image data generated by the signal processing circuit. These circuits may be configured by, for example, a digital circuit.
  • the signal processing circuit 22 may output a signal appropriately processed via the interface to the outside.
  • the signal processing circuit 22 outputs an appropriately processed signal to the control circuit and the AE / AF processing circuit 26. Further, the signal processing circuit 22 may be one in which parameters and the like related to signal processing are controlled based on a request from the control circuit 24.
  • the control circuit 24 has an optical system 12, a light receiving element 14, a signal processing circuit 22, and an AE / AF processing circuit 26 based on at least one of the output from the signal processing circuit 22 and the output from the AE / AF processing circuit 26. Generates and outputs a signal that controls at least one of these configurations.
  • the control circuit 24 controls, for example, the exposure timing, the exposure time, the pixel reading order, and the like. The detailed operation of the control circuit 24 will be described later.
  • the AE / AF processing circuit 26 outputs a signal for processing between AE (Auto Exposure) and AF (Auto Focus) based on the image data output by the signal processing circuit 22.
  • AE Auto Exposure
  • AF Automatic Focus
  • the connection unit 30 connects the first board 10 and the second board 20.
  • the connection unit 30 connects, for example, the light receiving element 14 and the signal processing circuit 22, and transmits the analog signal output by the light receiving element 14 to the signal processing circuit 22.
  • the connection unit 30 directly connects, for example, a metal electrode that is an output unit of the light receiving element 14 on the first substrate 10 and a metal electrode that is an input unit to the signal processing circuit 22 on the second substrate 20. This metal electrode is, for example, a Cu electrode.
  • the connection unit 30 may have a path for connecting the control circuit 24, the optical system 12, and the light receiving element 14.
  • the above describes the configuration regarding the path for the propagation of the analog signal and the digital signal according to the present embodiment. Therefore, other configurations required for control are omitted.
  • the first substrate 10 is appropriately provided with wiring and the like, for example, from which light receiving element 14 the output is received. Further, the second substrate 20 is appropriately provided with a circuit or the like that controls each configuration of the solid-state image sensor 1.
  • the components, wiring, etc. for the solid-state image sensor 1 to operate properly are appropriately provided, including those not shown.
  • FIG. 2 is a diagram showing an example of arrangement of an analog circuit and a logic circuit showing a light receiving element 14, a signal processing circuit 22, a control circuit 24, an AE / AF processing circuit 26, etc. according to the present embodiment.
  • the light receiving elements 14 are arranged in a two-dimensional array.
  • the light receiving element 14 is arranged in an array along the first direction and the second direction, for example, to form the light receiving element array 140.
  • Each light receiving element 14 includes, for example, a photodiode (PD: Photo Diode) or the like as an optical system 12 that receives light through a lens and outputs an analog signal based on the intensity of the received light.
  • PD Photo Diode
  • pixels that are continuous in the second direction may be called rows, and pixels that are continuous in the first direction may be called columns. That is, the light receiving element array 140 is formed by providing a plurality of rows, which are a group of light receiving elements 14 continuous in the second direction, in the first direction. In other words, the light receiving element array 140 is formed by providing a plurality of rows, which are a group of light receiving elements 14 continuous in the first direction, in the second direction.
  • the light receiving element array 140 includes a first region 141 and a second region 142.
  • the first region 141 and the second region 142 are divided by the pixel dividing unit 143.
  • the pixel dividing unit 143 is provided near the center in the first direction so as to cross the light receiving element array 140 along the second direction, for example.
  • near the center means, for example, in the light receiving element array 140, when n light receiving elements 14 are provided along the first direction, the pixel corresponding to the [n / 2] th pixel and [n / 2] + It is provided between the first pixel and the corresponding pixel.
  • [ ⁇ ] is a floor function.
  • the present invention is not limited to this, and may be not exactly in the center and may be significantly or not significantly biased to either the upper or lower side of the light receiving element array 140 in FIG. 2, but in the present specification, it may be biased. These states are collectively described as near the center in a broad sense.
  • connection portion 30 is connected to the first substrate 10 so as to be adjacent to the light receiving element array 140.
  • the first substrate 10 and the second substrate 20 are connected to each other via the connection portion 30.
  • the connection between the connection portion 30, the respective light receiving element 14, and each circuit on the second substrate 20 is not shown, but wiring by a conductor such as metal is appropriately arranged.
  • the connection portion 30 may not be provided under the light receiving element 14 between the first substrate 10 and the second substrate 20.
  • connection portion 30 is provided for each row in the light receiving element 14 belonging to each region (first region 141, second region 142), for example. Further, in order to propagate the control signal or the like from the circuit on the second substrate 20 onto the first substrate 10, it may be provided for each row. As shown in FIG. 2, the connection portion 30 connecting the second substrate 20 to the first substrate 10 does not need to be provided for each row, and the processing for the optical system 12 and the light receiving element 14 can be appropriately realized. If so, a larger number may be provided, or a smaller number may be provided.
  • the second board 20 includes an analog circuit 200 constituting the above-mentioned signal processing circuit 22, a control circuit 24, and an AE / AF processing circuit 26, and a logic circuit 210.
  • the broken line is a region to be projected onto the second substrate 20 in a state where the range provided with the light receiving element array 140 is laminated on the first substrate 10.
  • the analog circuit 200 is provided at both ends of the region where the light receiving element array 140 exists on the corresponding first substrate 10 in the laminated state, for example.
  • the analog circuit 200 is thus provided near both ends of the range in which the light receiving element array 140 is provided.
  • the analog circuit 200 includes a first analog circuit 201 and a second analog circuit 202.
  • the first analog circuit 201 and the second analog circuit 202 are provided so as to be adjacent to the connection portion 30, so that the analog signal output from the light receiving element 14 via the connection portion 30 can be easily received. Is placed in.
  • the first analog circuit 201 and the second analog circuit 202 each operate as an analog circuit.
  • the first analog circuit 201 acquires an analog signal from the light receiving element 14 belonging to the first region 141 via the connection portion 30, and outputs a digital signal based on the light receiving intensity of each light receiving element 14 belonging to the first region 141. Generate.
  • the second analog circuit 202 acquires an analog signal from the light receiving element 14 belonging to the second region 142 via the connection portion 30, and is based on the light receiving intensity of each light receiving element 14 belonging to the second region 142. Generate a digital signal.
  • the analog circuit 200 converts, for example, the analog signal output by the light receiving element 14 into a digital signal for each pixel and outputs the analog signal.
  • the first analog circuit 201 and the second analog circuit 202 operate exclusively, for example.
  • the digital signal converted by the first analog circuit 201 and the second analog circuit 202 is output to the logic circuit 210.
  • the logic circuit 210 executes appropriate signal processing and image processing on image data composed of digital signals for each pixel, for example. That is, the signal processing circuit 22 in FIG. 1 may be, for example, a set of various circuits configured over the analog circuit 200 and the logic circuit 210.
  • the logic circuit 210 further includes a control circuit 24 that generates a control signal based on the image processed image data, and an AE / AF processing circuit 26 that executes AE / AF processing based on the image data and the control signal. It is configured with and.
  • control signal output from the control circuit 24 provided in the logic circuit 210 is propagated to the first board 10 via the connection portion 30 arranged adjacent to the logic circuit 210.
  • the second substrate 20 may be provided with appropriate wiring and an interface (not shown).
  • the logic circuit 210 can be configured as one area so as to be sandwiched between the analog circuits 200, as opposed to the analog circuit 200 which is divided into two and arranged.
  • the logic circuit 210 By arranging the logic circuit 210 between the analog circuits 200, it becomes easy to control the timing of processing the signal output from the light receiving element 14 belonging to each region of the first substrate 10.
  • the configuration can be easily synchronized. It also has the effect of improving the layout efficiency of the semiconductor substrate.
  • a memory such as SRAM (Static Random Access Memory) may be provided in the logic circuit 210 so as to sandwich the dotted line portion. That is, it is also possible to have a configuration in which SRAM is collectively provided in one area.
  • SRAM Static Random Access Memory
  • FIG. 3 is a diagram schematically showing the positions of the light receiving element array 140, the analog circuit 200, and the logic circuit 210 in a state where the first board 10 and the second board 20 are stacked. As shown in FIG. 3, the light receiving element array 140 and the analog circuit 200 are laminated so as to overlap each other near both ends of the light receiving element array 140 in the first direction.
  • connection portion 30 is arranged so as to connect the light receiving element 14 and the analog circuit 200 along the third direction in the peripheral portion of the light receiving element array 140.
  • the logic circuit 210 and the light receiving element 14 are arranged so as to be connected along the third direction. It is arranged so as to connect the periphery of the pixel dividing portion 143 and the periphery of the circuit dividing portion 223.
  • the first analog circuit 201 and the second analog circuit 202 receive the analog signal from the light receiving element 14 connected by the connection unit 30, and execute appropriate processing.
  • a logic circuit 210 (digital circuit) is provided so as to be sandwiched between the first analog circuit 201 and the second analog circuit 202 in the first direction.
  • FIG. 4 is a diagram showing an example of wiring in the light receiving element array 140 according to the present embodiment.
  • the analog signal output by the light receiving element 14 provided on the first substrate 10 is transmitted to the analog circuit 200 provided on the second substrate 20.
  • the spacing is drawn wider than the other pixels above and below the pixel dividing portion 143, but this is for the sake of explanation, and in reality, the spacing is equivalent to that between the other pixels. May have.
  • the light receiving element array 140 is provided with a plurality of first signal lines 16 and a plurality of second signal lines 181, 182.
  • the second signal lines 181, 182 related to the same row are electrically cut off around the pixel dividing portion 143. That is, the second signal line 181 connected to the light receiving element 14 belonging to the first region 141 and the second signal line 182 connected to the light receiving element 14 belonging to the second region 142 are electrically connected to the first substrate 10. Not connected to.
  • first connecting parts 301 and a second connecting part 302 are provided as connecting parts 30, and the light receiving element 14 is a second signal.
  • the lines 181, 182 are connected to the analog circuit 200 of the second substrate 20 via these connections. More specifically, the light receiving element 14 belonging to the first region 141 is connected to the first analog circuit 201 via the second signal line 181 and the first connecting portion 301, and the light receiving element 14 belonging to the second region 142 is connected. Is connected to the second analog circuit 202 via the second signal line 182 and the second connection portion 302.
  • the first signal line 16 is a wiring for selecting which line of the light receiving element array 140 to process the analog signal output from the light receiving element 14.
  • the first signal line 16 is connected to a row selection circuit outside the region connected to the light receiving element 14, for example, and a line for outputting an analog signal to the analog circuit 200 is selected by the signal from the row selection circuit. Therefore, the first signal line 16 along the second direction is arranged by at least the number of lines in the second direction.
  • the line-based light receiving element 14 selected by the first signal line 16 is transmitted to the first connection portion 301 or the second connection portion 302 via the corresponding second signal lines 181, 182.
  • the second signal lines 181, 182 along the first direction are arranged at least one for each row, that is, at least as many as the number of rows in the first direction.
  • the first connection portion 301 and the second connection portion 302 are provided along the second direction for at least the number of columns, respectively.
  • the first connection unit 301 and the second connection unit 302 output the analog signal output from the light receiving element 14 to the first analog circuit 201 and the second analog circuit 202, respectively, and the analog signal processing is executed. ..
  • the processing of the analog signal output from the light receiving element 14, that is, the reading order of the light receiving element 14, is executed by switching, for example, three reading modes.
  • the three reading orders will be described below.
  • FIG. 5 is a diagram showing the first read mode.
  • reading is executed line by line so as to sequentially move from both ends of the light receiving element 14 in the first direction toward the pixel dividing portion 143. These reads from above and below are executed in parallel.
  • processing is executed for the light receiving element 14 belonging to the bottom row and the top row.
  • the processes are executed for the light receiving element 14 belonging to the second line from the bottom and the second line from the top, respectively. This process is repeated until the pixel division unit 143 is reached.
  • the first analog circuit 201 and the second analog circuit 202 parallel the analog signals of the light receiving element 14 belonging to the first region 141 and the light receiving element 14 belonging to the second region 142, respectively. May be converted into a digital signal. That is, the first analog circuit 201 and the second analog circuit 202 convert the analog signal output from the light receiving element 14 belonging to the corresponding region at the same timing into a digital signal.
  • FIG. 6 is a diagram showing the second read mode.
  • the second read mode in the light receiving element array 140, reading is executed row by row in the direction from the pixel adjacent to the pixel dividing portion 143 in the first direction of the light receiving element 14 toward the respective end portions. These readings from the center periphery to the top and bottom are performed in parallel.
  • processing is executed for the light receiving element 14 belonging to the row below the first direction of the pixel dividing unit 143 and the row in the first direction information.
  • the processes for the light receiving element 14 belonging to the second line from the pixel dividing unit 143 are executed. This process is repeated until the light receiving element 14 at the first-direction end of the light receiving element array 140 is reached.
  • the first analog circuit 201 and the second analog circuit 202 relate to the light receiving element 14 belonging to the first region 141 and the light receiving element 14 belonging to the second region 142, respectively.
  • Analog signals may be converted into digital signals in parallel. That is, the first analog circuit 201 and the second analog circuit 202 convert the analog signal output from the light receiving element 14 belonging to the corresponding region at the same timing into a digital signal.
  • FIG. 7 is a diagram showing a third read mode.
  • the third read mode in the light receiving element array 140, reading is sequentially executed from the light receiving element 14 belonging to the row at one end of the light receiving element 14 to the light receiving element 14 belonging to the other row.
  • the process is executed for the light receiving element 14 belonging to the bottom row in FIG. 7.
  • the analog signals output from the respective light receiving elements 14 are subjected to signal processing in parallel in the first analog circuit 201.
  • the processing is executed in the same manner for the line above, that is, the second line from the bottom. This process is executed, for example, by selecting rows in order from the bottom from the row selection circuit by a synchronization signal in the row direction.
  • the light receiving element 14 belonging to the first region 141 belongs to the second region 142 while the signal is transmitted to the first analog circuit 201 via the second signal line 181 and the first connection portion 301.
  • the light receiving element 14 transmits a signal to the second analog circuit 202 via the second signal line 182 and the second connection portion 302. After this, the scan is sequentially executed from the lower side to the upper side of the second region 142 based on the synchronization signal in the row direction.
  • the first analog circuit 201 and the second analog circuit 202 sequentially transmit analog signals about the light receiving element 14 belonging to the first region 141 and the light receiving element 14 belonging to the second region 142, respectively. Convert to a digital signal. That is, in this case, the first analog circuit 201 and the second analog circuit 202 can be configured to exclusively execute signal conversion except for the moment of processing a row straddling the pixel dividing unit 143.
  • the first analog circuit 201 and the second analog circuit 202 may exclusively stop the power supply except for the timing of straddling the pixel division unit 143.
  • the power supply may be stopped. By stopping the power supply in this way, it is possible to reduce power consumption.
  • the timing of reading the signals from the light receiving elements 14 above and below the pixel dividing unit 143 is substantially the same. Therefore, it is possible to generate image data with less discomfort without significantly changing the state of distortion in the central portion of the image or video.
  • the above reading method may be constantly read by the reading method, the user may switch the mode, or the reading method may be automatically switched.
  • the row selection is executed, for example, by applying a selection signal to the first signal line 16 corresponding to the row selected by the row selection circuit based on the synchronization signal.
  • a selection signal By controlling the signal output unit of the light receiving element 14 belonging to the selected line and the energized state of the second signal lines 181, 182 by this selection signal, an analog signal is output to an appropriate analog circuit 200.
  • a MOSFET Metal
  • the gate is connected to the first signal line 16 and the drain and source (or source and drain) are connected to the light receiving element 14 and the second signal lines 181, 182, respectively.
  • -Oxide-Semiconductor Field-Effect-Transistor The present invention is not limited to this, and an energized state may be formed by a switch or the like driven by a signal via the first signal line 16 by another method.
  • the region of the light receiving element array 140 provided in the first substrate 10 is divided near the center, and the analog circuits 200 are arranged at both ends in the first direction so as to overlap each other in the stacked second substrate 20. This makes it possible to shorten the transmission path of the signal output from the light receiving element 14 in the second signal lines 181, 182.
  • the connection portion 30 according to the present embodiment, it is possible to easily mount the circuit on the chip without significantly changing the arrangement of the conventional connection portion 30.
  • the logic circuit 210 can be collectively arranged in one area of the second board 20, it is possible to make the power supply quality uniform by centralized power supply and ground wiring. Similarly, since the logic circuit 210 can be formed in one area, it is possible to realize a centralized arrangement of control signal generation, and accordingly, it is possible to realize equal length and shortest control signal wiring. This applies not only to the wiring related to the control signal but also to the wiring of the read signal.
  • the first reading order or the second reading order which has a higher frame rate, is used, and when shooting, etc., where it is necessary to acquire a highly accurate image, and still.
  • the reading is performed in the third reading order in which the focal plane distortion is further suppressed while maintaining a high frame rate.
  • FIG. 8 is a diagram schematically showing the focal plane distortion in each mode described above.
  • the left figure shows the first read mode
  • the middle figure shows the second read mode
  • the right figure shows the focal plane distortion corresponding to the third read mode.
  • FIG. 8 shows, for example, an image of a rectangular object covering the entire region of the light receiving element 14 in the first direction moving to the right.
  • the dotted line is a line segment indicating the pixel division portion 143 in the acquired image.
  • the rectangular object in the first read mode, the rectangular object is imaged with a delay in timing as it approaches the pixel dividing portion 143 near the center. Therefore, the object is distorted to the right as it approaches the pixel dividing portion 143.
  • the rectangular object is imaged with a delay in timing as it approaches the end in the first direction. Therefore, the object is distorted to the right as it approaches the end (upper and lower) from the pixel dividing portion 143.
  • the image is distorted so that a monotonous shift occurs.
  • the imaging time is twice that of the first read mode and the second read mode, that is, the frame rate is 1/2, but on the other hand, the direction of image distortion in the pixel dividing unit 143 is It does not change. Therefore, for humans, the image captured by the third read mode gives a natural impression as compared with other read modes.
  • FIG. 9 is a flowchart showing a process of taking a picture by the solid-state image sensor 1 in such a method.
  • the control circuit 24 sets the first read mode or the second read mode as the read mode (S100).
  • the signals from the light receiving element 14 for the two regions divided by the pixel dividing unit 143 are processed at the same timing, so that the frame rate is about twice as high as that in the third read mode. Can be done.
  • focal plane distortion such as folding back at the pixel dividing portion 143 is generated. Therefore, in the initial stage of processing AE / AF at high speed, the first read mode or the second read mode, which enables reading at a higher speed than the third read mode, is set.
  • control circuit 24 controls the shooting conditions (S102). This control may be set using a shooting parameter or the like set as an initial value. If information from an illuminometer or the like is available, parameters such as exposure and focus may be set based on the information.
  • control circuit 24 shoots based on the set shooting conditions, and the signal processing circuit 22 executes signal processing (S104).
  • the signal processing circuit 22 executes signal processing and image processing of an analog signal received and output by the light receiving element 14 under controlled shooting conditions.
  • a display unit such as a display is provided in the solid-state image sensor 1, the processed image may be displayed on the display or the like.
  • the AE / AF processing circuit 26 executes AE / AF processing based on the image data output by the signal processing circuit 22 (S106). AF / AE processing is executed based on the acquired image data.
  • the AE / AF processing circuit 26 may set the AE by, for example, calculating the statistics of the luminance information in the image.
  • the AE / AF processing circuit 26 may, for example, reduce the exposure when it is determined that there are many whiteout pixels, and conversely, increase the exposure when it is determined that there are many blackout pixels. You may.
  • the AE / AF processing circuit 26 may detect the contrast in the image, for example, and set the AF so that the contrast becomes high. Further, as another example, the AE / AF processing circuit 26 may set AF so that the high frequency component of the spatial frequency becomes high.
  • Each of the AE and AF processes may be executed, for example, based on the statistical information of the pixel values in the predetermined area.
  • the predetermined region may be, for example, the entire image or a region near the center of the image. Further, the user may set the area.
  • These processes may be automatically performed at predetermined intervals at the timing before shooting, or may be executed based on the AE / AF lock request via the user interface.
  • the lock request may be accepted by half-pressing the shutter button in an electronic device such as a digital camera provided with the solid-state image sensor 1.
  • the AE / AF processing circuit 26 outputs the parameters related to AE and AF calculated in this way to the control circuit 24. If the exposure and focus are appropriate, that fact is output to the control circuit 24.
  • the AE / AF processing circuit 26 determines, for example, whether or not appropriate AE and AF parameters are set based on the above-mentioned statistics on exposure and focus, and outputs the result to the control circuit 24. Further, the AE / AF processing circuit 26 may simply transmit the parameters, and in this case, the control circuit 24 may determine whether or not the parameters are appropriately set.
  • control circuit 24 determines whether or not appropriate parameters such as AE / AF are set based on the output from the AE / AF processing circuit 26 (S108).
  • the process from S102 is repeated.
  • the AE / AF processing circuit 26 sets the parameters based on the output, and the optical system 12, the light receiving element 14, the signal processing circuit 22, and the AE / AF processing circuit 26. To control.
  • the control circuit 24 transmits, for example, a control signal for adjusting the exposure time and focus to the optical system 12 and the light receiving element 14. Further, the control circuit 24 processes the signal output by the light receiving element 14 by transmitting the parameters used until the next control timing to the signal processing circuit 22 and the AE / AF processing circuit 26. Control the parameters of.
  • the control circuit 24 sets the read mode to the third read mode (S110).
  • the third read mode as described above, the frame rate is lower than that of the first read mode and the second read mode, but the focal plane distortion becomes more natural for humans than the other modes. It shifts to the mode to acquire the image.
  • shooting and signal processing are executed based on the request from the control circuit 24 (S112).
  • the optical system 12 and the light receiving element 14 take an image in the third read mode according to appropriately set parameters related to exposure, focus, and the like.
  • the signal processing circuit 22 executes various processes such as signal processing and image processing based on the parameters acquired from the control circuit 24.
  • the signal processing circuit 22 outputs image data to an appropriate location (S114).
  • the signal processing circuit 22 stores image data in a memory inside or outside the solid-state image sensor 1. Further, at the same timing, if there is a display unit such as a display, the image data may be displayed.
  • control circuit 24 determines whether or not the imaging process is complete (S116). This determination may be made based on instructions from the user. If the process is not completed, for example, if the user continues shooting (S116: NO), the process from S100 is repeated again. In this case, the processes of S100 to S106 may be executed using the parameters set in S112 and S114 as initial values.
  • FIG. 10 is a block diagram showing the configuration of the solid-state image sensor 1 according to the second embodiment.
  • the solid-state image sensor 1 includes a recognition processing circuit 28 instead of the AE / AF processing circuit 26 of the solid-state image pickup device 1 in the first embodiment. It should be noted that this figure is shown as an example, and may be configured to further include an AE / AF processing circuit 26 and also execute the above-mentioned AE / AF processing.
  • the recognition processing circuit 28 is provided, for example, as a part of the logic circuit 210 in FIG.
  • the recognition processing circuit 28 executes various recognition processing using, for example, a trained machine learning model.
  • the recognition processing circuit 28 recognizes a human face and extracts the area of the face. Not limited to the human face, the recognition processing circuit 28 may detect and recognize a predetermined object. As a configuration further including the AE / AF processing circuit 26, even if a person's face is detected and parameters for controlling AE and AF are calculated in a region of a predetermined size and shape including the detected face. good. In this case, the facial area may be detected and tracked frame by frame.
  • the facial expression may be read at the timing of recognizing the face of the person. Then, the control circuit 24 may execute control to perform imaging at the timing when the read facial expression is a smile. Further, in the above, the face of a person is used as the subject, but the subject is not limited to this, and any object can be set as the subject.
  • FIG. 11 is a flowchart showing the processing of the solid-state image sensor 1 according to the present embodiment. Since the processes with the same reference numerals are the same as those in the above-described embodiment, detailed description thereof will be omitted.
  • the recognition processing circuit 28 executes the recognition processing on the image data output by the signal processing circuit 22 (S118).
  • the recognition process is executed, for example, by inputting image data into a trained neural network model. Note that the recognition process may be executed by a rule-based process or the like without using the neural network model.
  • the recognition processing circuit 28 determines whether or not a predetermined object has been recognized and detected (S120). If it is not detected (S120: NO), the process from S104 is repeated. As shown by the dotted arrow, the recognition process may be repeatedly executed a predetermined number of times or for a predetermined time. After that, if the recognition cannot be further performed, the process from S104 may be repeated.
  • the control circuit 24 shifts the processing mode of the solid-state image sensor 1 to the third read mode (S110).
  • control circuit 24 executes ROI (Region of Interest) control based on the detection result of the recognition processing circuit 28 (S122). By controlling this ROI, the area where the subject is shown may be tracked. Further, AE and AF processing may be executed based on the statistical information in the ROI.
  • ROI Region of Interest
  • the image is acquired and output, and the process is terminated.
  • the solid-state image sensor 1 may choose not to execute the recognition process even when the recognition process circuit 28 is provided. Even if the solid-state image sensor 1 cannot detect an object, it can perform imaging, signal processing, etc. based on the parameters set at that timing according to the user's request based on the set AE and AF. The process may be executed.
  • the recognition process may be executed in the logic circuit 210 provided in the second board 20.
  • the solid-state image sensor 1 performs reading in a mode with a high frame rate in order to detect the subject at high speed while executing the recognition process, and has high accuracy so that the focal plane distortion does not become unnatural after the recognition is completed. It is possible to switch to the mode to acquire the image of.
  • the recognition processing circuit 28 is supposed to detect a predetermined object, but the present invention is not limited to this.
  • an event-driven operation that detects movement may be realized.
  • control circuit 24 may execute various controls, for example, switching of the read mode, based on the result recognized by the recognition processing circuit 28.
  • the recognition processing circuit 28 was supposed to be recognized using a trained model, but it is not limited to this.
  • the recognition processing circuit 28 may execute machine learning to improve the accuracy of the recognition result based on the recognition result or the instruction from the user. This machine learning may be executed, for example, at a timing when the solid-state image sensor 1 is not taking a picture.
  • the configuration is provided with one pixel dividing unit 143, but the present invention is not limited to this. That is, the light receiving element array 140 may be divided into more regions. Along with this, the analog circuit 200 may also be mounted in more areas.
  • FIG. 12 is a diagram showing a laminated state of the light receiving element array 140 and the analog circuit 200 according to the present embodiment.
  • the light receiving element array 140 is provided with three pixel dividing units 143A, 143B, and 143C.
  • the light receiving element array 140 is roughly divided into two regions by the pixel dividing unit 143C. These regions are divided into a first region 141A and a second region 142A by the pixel dividing unit 143A, and a first region 141B and a second region 142B by the pixel dividing unit 143B. In this way, the light receiving element array 140 is divided into, for example, four regions.
  • one first signal line is arranged for the light receiving element 14 continuous in the second direction, that is, the pixels belonging to the same row.
  • the second signal line connected to the light receiving element 14 continuous in the first direction belonging to each region of 141A, 142A, 141B, 142B is cut in each region in the same manner as in the above-described embodiment. It is output to the analog circuit 200 via each connection. That is, in the example of FIG. 12, four second signal lines are provided in each row.
  • FIG. 13 is a diagram showing an outline of the light receiving element array 140 according to the present embodiment.
  • the light receiving element array 140 is divided into regions 141A, 142A, 141B, and 142B by the pixel dividing portions 143A, 143B, and 143C.
  • Each of the divided regions is provided with a first signal line 16 for selecting whether or not to output from the light receiving element 14 belonging to the same line for the number of lines in which the light receiving element 14 exists. Similar to FIG. 4, the interval between pixels is wide at the portion straddling the pixel division portion, but for the sake of explanation, even if the interval is actually the same as the interval between other pixels. good.
  • the second signal line is provided so that the output is connected from the light receiving element 14 belonging to the same row for each region and is cut off in different regions.
  • the plurality of second signal lines 181A arranged in the region 141A connect the light receiving elements 14 belonging to the respective rows.
  • it is provided so as not to be electrically connected to the second signal lines 182A, 181B, 182B of the other regions 142A, 141B, 142B.
  • Each signal line is connected to the second board 20 by a connecting part.
  • each second signal line 181A in the first region 141A is connected to the first analog circuit 201 via the first connection portion 301A.
  • the second signal line 182A in the second region 142A is connected to the second analog circuit 202 via the second connection portion 302A.
  • the upper side of the figure is the same as the lower side, and the second signal line 181B of the first region 141B is connected to the third analog circuit 203 via the first connection portion 301B, and the second signal line of the second region 142B is connected.
  • the 182B is connected to the fourth analog circuit 204 via the second connection portion 302B.
  • the light receiving element array 140 may be divided into a plurality of regions by the plurality of pixel dividing units 143 in this way. As shown in FIG. 13, a second signal line and a connection portion are independently provided in each region, and each is connected to the analog circuit 200 of the second substrate 20.
  • the second board 20 will be explained.
  • analog circuits are provided respectively.
  • the second board 20 includes a first analog circuit 201, a second analog circuit 202, a third analog circuit 203, and a fourth analog circuit 204.
  • each analog circuit 200 is provided with the first analog circuit 201 and the fourth analog circuit 204 at the end in the first direction of the light receiving element array 140 in the third direction in a stacked state. Further, the second analog circuit 202 and the third analog circuit 203 are arranged so as to overlap the pixel dividing portion 143. Since the configuration of each circuit is the same as that shown in FIG. 5, details are omitted. It should be noted that the second analog circuit 202 and the third analog circuit 203 do not need to be clearly distinguished, and if the signal output from the light receiving element 14 belonging to each region can be appropriately processed, they are integrated. It may be formed as.
  • the power of the unnecessary analog circuit may be turned off in accordance with the light receiving element 14 that outputs an analog signal.
  • the logic circuits 210A and 210B may be arranged, for example, between the first analog circuit 201 and the second analog circuit 202, and between the third analog circuit 203 and the fourth analog circuit 204 in the figure.
  • connection portion 30 must be provided below the light receiving element 14, while the load on the second signal line can be further reduced, resulting in further speedup and lower power consumption. Can be realized.
  • one second signal line is provided in one row, but the present invention is not limited to this.
  • the light receiving element 14 belonging to one row may be provided with a plurality of second signal lines.
  • the plurality of second signal lines may be provided with a connection portion for each.
  • FIG. 14 is a diagram schematically showing an outline of a pixel array, a second signal line, and a connection portion according to the present embodiment.
  • the pixels, wiring, connection parts, etc. are all drawn on a plane, but the present invention is not limited to this.
  • the pixel may be on the upper surface, wiring may be provided below the third direction, and the wiring and the connecting portion may be connected in the first substrate 10.
  • the light receiving element array 140 is provided with a plurality of light receiving elements 14.
  • the plurality of second signal lines 181, 182 are provided so that the outputs of the light receiving elements 14 belonging to the same row are connected to each other. Unlike the above-described embodiment, a plurality of second signal lines 181, 182 are provided between the rows.
  • the first signal line is provided in the same manner as in FIG. 4, although it is not shown.
  • twelve second signal lines 181, 182 may be provided between the rows of the light receiving elements 14 and the rows, respectively.
  • analog signals output from 12 or less light receiving elements 14 along the first direction may be output to the analog circuit 200 of the second substrate 20 in parallel. That is, analog signal processing can be executed in parallel for the light receiving elements 14 belonging to 12 rows or less at the same timing. In other words, it is possible to output the signals of the light receiving element 14 belonging to a plurality of lines to the analog circuit 200 at the same timing.
  • the wiring connected from the light receiving element 14 and the portion where the second signal line is indicated by a black dot are electrically connected, and the portion without a black dot is not electrically connected. It is a place.
  • a switch is provided at a point where the wiring from the light receiving element 14 and the second signal line intersect, and the first signal line appropriately switches the state of these switches to process the analog signal.
  • the light receiving element 14 can be selected.
  • the solid-state image sensor 1 is a laminated body in which the first substrate 10 and the second substrate 20 are laminated.
  • the first substrate 10 and the second substrate 20 are sometimes called dies.
  • the first substrate 10 and the second substrate 20 have a rectangular shape, but the specific shape and size are arbitrary. Further, the first substrate 10 and the second substrate 20 may have the same size or may be different sizes from each other.
  • the light receiving element array 140 shown in FIG. 4 and the like is arranged on the first substrate 10. Further, at least a part of the optical system 12 may be mounted on the first substrate 10 on-chip.
  • the second board 20 is provided with at least an analog circuit 200 and a logic circuit 210, and is also provided with other necessary circuits such as an interface circuit.
  • a clock generation circuit or the like that outputs a clock signal for timing the row selection signal, synchronization signal, or the like described above may be provided.
  • a control circuit for comprehensively or partially controlling each circuit may be provided.
  • the first substrate 10 and the second substrate 20 are cut out from a wafer, separated into individual pieces, and then laminated one above the other, so-called.
  • a CoC (Chip on Chip) method may be adopted.
  • one of the first substrate 10 and the second substrate 20 (for example, the first substrate 10) is cut out from the wafer and individualized, and then the individualized first substrate 10 is separated into the second substrate 20 before individualization.
  • the so-called CoW (Chip on Wafer) method may be adopted.
  • a so-called WoW (Wafer on Wafer) method in which the first substrate 10 and the second substrate 20 are bonded together in the state of a wafer, may be adopted.
  • first substrate 10 and the second substrate 20 may be joined using Various joining methods.
  • plasma junction or the like can be used.
  • the joining portion as shown in the following figure may be used for the connection portion for electrically connecting the first substrate 10 and the second substrate 20. .. It should be noted that it is not shown in the state of a detailed circuit, but only the connection of the connection part is shown. Therefore, in the figure, drawing of various circuit elements and the like is omitted. Further, the second signal line 181 will be described, but the same applies to the second signal line 182, ..., Etc.
  • FIG. 15 is a diagram showing an example of a connection portion.
  • the analog circuit 200 and the second signal line 181 are connected in the region where the second signal line 181 exists.
  • the light receiving element 14 that photoelectrically converts the light collected by the optical system 12 is connected by a second signal line 181.
  • the second signal line 181 is connected to, for example, a connection portion 30 formed with microbumps and is connected to an analog circuit 200.
  • micropads are formed on both the light receiving element 14 side and the analog circuit 200 side, and these micropads are connected to each other by microbumps.
  • FIG. 16 is a diagram showing another example of the connection portion.
  • the connection portion 30 may be connected by a micro pad, for example, as shown in the figure.
  • the micro pads may be directly connected.
  • FIG. 17 is a diagram showing another example of the connection portion.
  • the connecting portion 30 may form a via hole, for example, and connect the light receiving element 14 and the analog circuit 200 by making contact between the via hole, the second signal line 181 and the analog circuit 200.
  • first substrate 10 and the second substrate 20 are connected via the connection portion 30 with respect to the light receiving element 14, but even if a connection line for transmitting and receiving other signals is further provided as needed. good.
  • FIG. 18 is a diagram showing an example of a case where the solid-state image sensor 1 is formed of two layers.
  • the second substrate 20 includes an optical system 12 and a light receiving element array 140 having the light receiving elements 14 in a two-dimensional array. Further, it is provided with wiring and the like necessary for extracting pixel information such as the first signal line and the second signal line.
  • the second board 20 includes an analog circuit 200, a logic circuit 210, a memory 220, and an input / output I / F 230. In addition, a circuit necessary for controlling the solid-state image sensor 1 is provided.
  • FIG. 19 is a diagram showing an example of a case where the solid-state image sensor 1 is formed of three layers.
  • the elements of the first substrate 10 and the second substrate 20 are almost the same as those in FIG.
  • the second board 20 is not provided with the memory
  • the third board 40 is provided with the memory.
  • the third substrate 40 is below the second substrate 20, but is not limited to this. That is, the third substrate 40 may be provided between the first substrate 10 and the second substrate 20.
  • the connection between the layers is the same as that of the above-described embodiment.
  • the layers are connected by the connection method as shown in FIGS. 15 to 17.
  • CMOS sensors All embodiments have described examples of CMOS sensors, but are not limited to this. It can also be applied to organic film sensors and other types of light receiving devices.
  • the solid-state image sensor 1 switches a plurality of modes based on the application, environment, and the like to perform imaging.
  • the solid-state imaging device 1 can be mounted on various electronic devices such as feature phones, smartphones, tablet terminals, digital cameras, digital video cameras, and surveillance cameras.
  • the circuit that executes each of the above operations is appropriately mounted by an analog circuit or a digital circuit.
  • this circuit may be configured by a circuit such as an ASIC (Application Specific Integrated Circuitry), or at least a part of the operation may be implemented by software in a circuit such as a general-purpose CPU (Central Processing Unit). It may be what is done.
  • an executable file, a program, or the like related to the software or the like may be stored in a storage unit.
  • at least a part of these circuits may be implemented as a programmable circuit such as an FPGA (Field Programmable Gate Array).
  • a plurality of light receiving elements that photoelectrically convert light and output an analog signal are arranged in a two-dimensional array as columns along the first direction and rows along the second direction intersecting the first direction.
  • a second board with an analog circuit, which processes the signal, and Equipped with The light receiving element array is By the pixel dividing portion along the second direction, it is divided into a first region and a second region, each of which has a continuous light receiving element.
  • the analog circuit is A first analog circuit connected to the light receiving element belonging to the first region via a first connecting portion arranged in a region not overlapping with the light receiving element array in the third direction.
  • a second analog circuit connected to the light receiving element belonging to the second region via a second connecting portion arranged in a region not overlapping with the light receiving element array in the third direction.
  • a first signal line which selects one or more of the rows in the first direction and is arranged along the first direction
  • a first signal line which selects one or more of the rows in the first direction and is arranged along the first direction
  • a second signal line which is arranged along the second direction, selects one or more of the rows having the light receiving element continuous in the first direction. Equipped with The analog signal output by the light receiving element selected by the first signal line is transmitted via the second signal line and processed by the analog circuit. The second signal line is electrically cut off at the pixel dividing portion.
  • the pixel dividing portion is arranged near the center of the light receiving element array in the first direction.
  • the first connection portion is connected to the second signal line belonging to the first region, and the light receiving element belonging to the first region and the first analog circuit are connected to each other.
  • the second connection portion is connected to the second signal line belonging to the second region, and is connected to the light receiving element belonging to the second region and the second analog circuit.
  • the first connection and the second connection are each provided in at least the number of rows along the second direction.
  • the second substrate is a control circuit that controls the order in which signals are output from the light receiving element.
  • the control circuit is In the light receiving element array, a first read mode for controlling the order of reading from the row provided on the outside toward the pixel dividing portion. In the light receiving element array, a second read mode for controlling the reading order from the pixel dividing portion toward the row provided on the outside, In the light receiving element array, a third read mode for controlling the reading order from the row at one end in the first direction to the row at the other end.
  • a first read mode for controlling the order of reading from the row provided on the outside toward the pixel dividing portion.
  • a second read mode for controlling the reading order from the pixel dividing portion toward the row provided on the outside
  • a third read mode for controlling the reading order from the row at one end in the first direction to the row at the other end.
  • the second substrate is A signal processing circuit that executes signal processing of the signal output by the analog circuit, and An AE / AF processing circuit that calculates parameters for adjusting exposure and focus based on the output of the signal processing circuit. Further prepare The control circuit controls the exposure and focus of the light receiving element based on the output of the AE / AF processing circuit.
  • the solid-state image sensor according to (7) or (8).
  • the control circuit is The first read mode, the second read mode, and the third read mode are switched based on the output of the AE / AF processing circuit.
  • the control circuit is Based on the output of the AE / AF processing circuit, the first read mode or the second read mode is selected and controlled until the exposure control and the focus control are completed. After the exposure control and focus control are completed, the third read mode is selected and controlled.
  • the second substrate is A signal processing circuit that executes signal processing of the signal output by the analog circuit, and A recognition processing circuit that executes object recognition processing based on the output of the signal processing circuit. Further prepare The control circuit switches between the first read mode, the second read mode, and the third read mode based on the output of the recognition processing circuit.
  • the solid-state image sensor according to (7) or (8).
  • the control circuit is Based on the output of the recognition processing circuit, the first read mode or the second read mode is selected and controlled until the object is detected. After the object is detected, the third read mode is selected and controlled.
  • the solid-state image sensor according to (12).
  • the first analog circuit and the second analog circuit process the analog signals of one or a plurality of different pixels belonging to the row along the second direction at the same timing.
  • the solid-state image sensor according to any one of (1) to (13).
  • the first analog circuit and the second analog circuit convert the analog signal into a digital signal.
  • the second board is a logic circuit that processes the digital signal, and includes a logic circuit that is sandwiched between the first analog circuit and the second analog circuit.
  • the solid-state image sensor according to (1) is a logic circuit that processes the digital signal, and includes a logic circuit that is sandwiched between the first analog circuit and the second analog circuit.
  • the logic circuit includes a memory so as to overlap the pixel dividing portion in the third direction.
  • the second substrate is A signal processing circuit that executes signal processing of the digital signal, and An image processing circuit that executes image processing of the digital signal, which is image information, and A memory for storing arbitrary data among the digital signal, the data output by the signal processing circuit, and the data output by the image processing circuit.
  • the data output by the image processing circuit, and the data stored in the storage unit at least one arbitrary data or any signal is output to the outside, or An interface that accepts data or signal input from the outside, The solid-state image sensor according to (1).
  • the aspect of the present disclosure is not limited to the above-mentioned embodiment, but also includes various possible modifications, and the effect of the present disclosure is not limited to the above-mentioned contents.
  • the components in each embodiment may be applied in appropriate combinations. That is, various additions, changes and partial deletions are possible without departing from the conceptual idea and purpose of the present disclosure derived from the contents specified in the claims and their equivalents.
  • 1 Solid-state image sensor, 10: 1st board, 12: Optical system, 14: Light receiving element, 140: Light receiving element array, 141: 1st area, 142: 2nd area, 143: Pixel dividing part, 16: 1st signal line, 181, 182: 2nd signal line, 20: 2nd board, 22: Signal processing circuit, 24: Control circuit, 26: AE / AF processing circuit, 28: Recognition processing circuit, 200: Analog circuit, 201: 1st analog circuit, 202: 2nd analog circuit, 203: 3rd analog circuit, 204: 4th analog circuit, 210: Logic circuit, 220: Memory, 230: I / O I / F 30: Connection, 301: 1st connection, 302: 2nd connection

Abstract

Pour prévenir la survenue d'une distorsion, le dispositif d'imagerie à semi-conducteurs selon l'invention comprend : un premier substrat comportant un réseau d'éléments de réception de lumière dans lequel une pluralité d'éléments de réception de lumière sont agencés pour former un réseau bidimensionnel doté de colonnes le long d'une première direction, et de rangées le long d'une deuxième direction ; et un second substrat, qui est stratifié sur le premier substrat et comporte un circuit analogique installé de façon à chevaucher le réseau d'éléments de réception de lumière dans une troisième direction, et qui traite des signaux analogiques produits par les éléments de réception de lumière. Le réseau d'éléments de réception de lumière est divisé par une pièce de division de pixels le long de la deuxième direction, en une première région et une seconde région comprenant respectivement les éléments de réception de lumière. Le circuit analogique comprend : un premier circuit analogique connecté aux éléments de réception de lumière appartenant à la première région par l'intermédiaire d'une première pièce de connexion, qui se situe dans une région ne chevauchant pas le réseau d'éléments de réception de lumière dans la troisième direction ; et un second circuit analogique, connecté aux éléments de réception de lumière appartenant à la seconde région par l'intermédiaire d'une seconde pièce de connexion qui se situe dans une région ne chevauchant pas le réseau d'éléments de réception de lumière dans la troisième direction.
PCT/JP2021/031016 2020-09-07 2021-08-24 Dispositif d'imagerie à semi-conducteurs et appareil électronique WO2022050134A1 (fr)

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WO2020153123A1 (fr) * 2019-01-25 2020-07-30 ソニーセミコンダクタソリューションズ株式会社 Dispositif d'imagerie et appareil électronique

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