WO2022050134A1 - Solid-state imaging device and electronic apparatus - Google Patents

Solid-state imaging device and electronic apparatus Download PDF

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Publication number
WO2022050134A1
WO2022050134A1 PCT/JP2021/031016 JP2021031016W WO2022050134A1 WO 2022050134 A1 WO2022050134 A1 WO 2022050134A1 JP 2021031016 W JP2021031016 W JP 2021031016W WO 2022050134 A1 WO2022050134 A1 WO 2022050134A1
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Prior art keywords
light receiving
receiving element
circuit
signal
analog
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PCT/JP2021/031016
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French (fr)
Japanese (ja)
Inventor
潔志 牧川
洋介 植野
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ソニーセミコンダクタソリューションズ株式会社
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Publication of WO2022050134A1 publication Critical patent/WO2022050134A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith

Definitions

  • This disclosure relates to a solid-state image sensor and an electronic device.
  • a sensor equipped with a pixel array in which pixels such as a conventional CMOS (Complementary Metal-Oxide Semiconductor) element are formed in an array has a problem that the frame rate is low because signals are acquired in order from a predetermined element.
  • CMOS Complementary Metal-Oxide Semiconductor
  • Various technologies have been developed to increase the frame rate. In these techniques, while increasing the frame rate, the shape of the focal plane distortion may not be preferable.
  • connection lead wire to another semiconductor layer laminated under the pixel for example, in a back-illuminated sensor, on the front surface side of the pixel is required, and the connection with another circuit is required. It has low affinity and tends to be complicated. As a result, there is one aspect that is unsuitable for miniaturization of pixel size and increase in the number of pixels.
  • the present disclosure provides a solid-state image pickup device and an electronic device in which an array of light receiving elements is provided with a plurality of regions and the occurrence of distortion is suppressed.
  • the solid-state imaging device has a plurality of light receiving elements that photoelectrically convert light and output an analog signal along a row along a first direction and a second direction intersecting the first direction.
  • a first substrate having a light receiving element array arranged in a two-dimensional array as a row, and a second substrate laminated on the first substrate, which intersects the first direction and the second direction.
  • the analog circuit is divided into a first region and a second region, each of which has a continuous light receiving element, by a pixel dividing portion along the direction, and the analog circuit is a region that does not overlap with the light receiving element array in the third direction.
  • a first analog circuit connected to the light receiving element belonging to the first region via a first connecting portion arranged in the third direction, and a second arranged in a region not overlapping with the light receiving element array in the third direction.
  • a second analog circuit which is connected to the light receiving element belonging to the second region via a connecting portion, is provided.
  • the light receiving element array among the rows including the light receiving elements continuous in the second direction, one or a plurality of the rows in the first direction are selected, and a plurality of rows are arranged along the first direction.
  • the rows including the first signal line and the light receiving element continuous in the first direction one or more of the rows in the second direction are selected, and a plurality of the rows are arranged along the second direction.
  • a second signal line may be provided, and the analog signal output by the light receiving element selected by the first signal line is transmitted via the second signal line and processed by the analog circuit.
  • the second signal line may be electrically cut off at the pixel dividing portion.
  • the pixel dividing portion may be arranged near the center of the light receiving element array in the first direction.
  • the first connection portion may be connected to the second signal line belonging to the first region, and the light receiving element belonging to the first region and the first analog circuit may be connected to the second signal line.
  • the connection unit may be connected to the second signal line belonging to the second region, and may be connected to the light receiving element belonging to the second region and the second analog circuit.
  • the first connection portion and the second connection portion may be provided at least as many as the number of the rows along the second direction, respectively.
  • the second substrate may further include a control circuit that controls the order in which signals are output from the light receiving element.
  • the control circuit controls the reading order from the row provided on the outside in the light receiving element array toward the pixel dividing unit, and the first read mode and the pixel dividing unit in the light receiving element array. From the row at one end of the first direction to the other end in the light receiving element array, the second read mode, which controls the read order from to the outer row towards the row. A third read mode, which controls the order of reading toward the line, may be selected and controlled.
  • the first analog circuit and the second analog circuit may be driven exclusively.
  • the second board performs AE / AF processing for calculating a signal processing circuit that executes signal processing of the signal output by the analog circuit and parameters for adjusting exposure and focus based on the output of the signal processing circuit.
  • a circuit may be further provided, and the control circuit may control the exposure and focus of the light receiving element based on the output of the AE / AF processing circuit.
  • the control circuit may switch between the first read mode, the second read mode, and the third read mode based on the output of the AE / AF processing circuit.
  • the control circuit may select and control the first read mode or the second read mode until the exposure control and the focus control are completed based on the output of the AE / AF processing circuit. After the exposure control and the focus control are completed, the third read mode may be selected and controlled.
  • the second board further includes a signal processing circuit that executes signal processing of the signal output by the analog circuit, and a recognition processing circuit that executes object recognition processing based on the output of the signal processing circuit.
  • the control circuit may switch between the first read mode, the second read mode, and the third read mode based on the output of the recognition processing circuit.
  • the control circuit may select and control the first read mode or the second read mode until the object is detected based on the output of the recognition processing circuit, and the object is detected. Later, the third read mode may be selected and controlled.
  • the first analog circuit and the second analog circuit may process the analog signals of the different pixels belonging to the one or a plurality of the rows along the second direction at the same timing.
  • the first analog circuit and the second analog circuit may convert the analog signal into a digital signal
  • the second board is a logic circuit for processing the digital signal and is the first analog circuit.
  • a logic circuit which is arranged between the second analog circuits.
  • the logic circuit may include a memory so as to overlap the pixel dividing portion in the third direction.
  • a plurality of the pixel dividing portions, a region of the light receiving element array divided into a plurality of regions, and an analog circuit corresponding to each region may be provided.
  • the second board is output from a signal processing circuit that executes signal processing of the digital signal, an image processing circuit that executes image processing of the digital signal that is image information, the digital signal, and the signal processing circuit.
  • the data is stored in the memory, the data output by the signal processing circuit, the data output by the image processing circuit, and the storage unit for storing arbitrary data among the data output by the image processing circuit. It may be provided with an interface that outputs at least one arbitrary data or an arbitrary signal to the outside, or accepts an input of the data or a signal from the outside.
  • the electronic device includes the solid-state image sensor according to any one of the above.
  • the electronic device may be a smartphone, a tablet terminal, a digital camera, or a digital video camera.
  • the block diagram of the solid-state image pickup apparatus which concerns on one Embodiment The figure which shows typically the arrangement of each element of the solid-state image sensor which concerns on one Embodiment.
  • the figure which shows the reading order of the light receiving element which concerns on one Embodiment The figure which shows the reading order of the light receiving element which concerns on one Embodiment.
  • FIG. 1 is a block diagram showing the functions of the solid-state image sensor 1 according to the embodiment.
  • the solid-state image sensor 1 includes, for example, a first substrate 10 and a second substrate 20.
  • the first substrate 10 includes an optical system 12 and a light receiving element 14.
  • the second substrate 20 includes a signal processing circuit 22, a control circuit 24, and an AE / AF processing circuit 26.
  • the second substrate 20 may include, for example, an interface for inputting / outputting data between the above circuit and an external circuit or the like.
  • the optical system 12 is a system that corrects optical paths, aberrations, etc. for sensing light in the light receiving element 14.
  • the optical system 12 includes, for example, a lens (including a virtual lens or the like), and is grounded so that light is appropriately received by the light receiving element 14.
  • the light receiving element 14 includes an element that photoelectrically converts the received light and outputs an analog signal.
  • the light receiving element 14 includes, for example, a back-illuminated photodiode.
  • the light receiving element 14 is not limited to this configuration, and may be configured as a surface-illuminated type, or may be configured to include an element different from the photodiode.
  • the electric charge accumulated by the light receiving element 14 by photoelectric conversion is transmitted to the second substrate via the connection portion 30.
  • Each light receiving element 14 may be provided with a color filter.
  • the color filter may be arranged by, for example, a Bayer arrangement or another arrangement. When a color filter is used, processing using the color matrix may be executed by a signal processing circuit 22 or the like described later. Further, in order to reproduce colors, an organic photoelectric conversion film may be used as the light receiving element 14 instead of the configuration provided with a filter.
  • the signal processing circuit 22 is a circuit that processes the signal output by the light receiving element 14.
  • the signal processing circuit 22 includes, for example, an ADC (Analog to Digital Converter), and converts an analog signal output by the light receiving element 14 into a digital signal.
  • ADC Analog to Digital Converter
  • DAC Digital to Analog Converter
  • An amplifier which amplifies the output from the counter, may be provided.
  • the signal processing circuit 22 further includes a circuit that executes appropriate signal processing and image processing on this digital signal.
  • the signal processing circuit may include, for example, a circuit that generates image data such as interpolation processing and color adjustment processing of the signal output by the light receiving element 14.
  • the image processing circuit may include a circuit that executes various filter processing, deformation processing, and the like on the image data generated by the signal processing circuit. These circuits may be configured by, for example, a digital circuit.
  • the signal processing circuit 22 may output a signal appropriately processed via the interface to the outside.
  • the signal processing circuit 22 outputs an appropriately processed signal to the control circuit and the AE / AF processing circuit 26. Further, the signal processing circuit 22 may be one in which parameters and the like related to signal processing are controlled based on a request from the control circuit 24.
  • the control circuit 24 has an optical system 12, a light receiving element 14, a signal processing circuit 22, and an AE / AF processing circuit 26 based on at least one of the output from the signal processing circuit 22 and the output from the AE / AF processing circuit 26. Generates and outputs a signal that controls at least one of these configurations.
  • the control circuit 24 controls, for example, the exposure timing, the exposure time, the pixel reading order, and the like. The detailed operation of the control circuit 24 will be described later.
  • the AE / AF processing circuit 26 outputs a signal for processing between AE (Auto Exposure) and AF (Auto Focus) based on the image data output by the signal processing circuit 22.
  • AE Auto Exposure
  • AF Automatic Focus
  • the connection unit 30 connects the first board 10 and the second board 20.
  • the connection unit 30 connects, for example, the light receiving element 14 and the signal processing circuit 22, and transmits the analog signal output by the light receiving element 14 to the signal processing circuit 22.
  • the connection unit 30 directly connects, for example, a metal electrode that is an output unit of the light receiving element 14 on the first substrate 10 and a metal electrode that is an input unit to the signal processing circuit 22 on the second substrate 20. This metal electrode is, for example, a Cu electrode.
  • the connection unit 30 may have a path for connecting the control circuit 24, the optical system 12, and the light receiving element 14.
  • the above describes the configuration regarding the path for the propagation of the analog signal and the digital signal according to the present embodiment. Therefore, other configurations required for control are omitted.
  • the first substrate 10 is appropriately provided with wiring and the like, for example, from which light receiving element 14 the output is received. Further, the second substrate 20 is appropriately provided with a circuit or the like that controls each configuration of the solid-state image sensor 1.
  • the components, wiring, etc. for the solid-state image sensor 1 to operate properly are appropriately provided, including those not shown.
  • FIG. 2 is a diagram showing an example of arrangement of an analog circuit and a logic circuit showing a light receiving element 14, a signal processing circuit 22, a control circuit 24, an AE / AF processing circuit 26, etc. according to the present embodiment.
  • the light receiving elements 14 are arranged in a two-dimensional array.
  • the light receiving element 14 is arranged in an array along the first direction and the second direction, for example, to form the light receiving element array 140.
  • Each light receiving element 14 includes, for example, a photodiode (PD: Photo Diode) or the like as an optical system 12 that receives light through a lens and outputs an analog signal based on the intensity of the received light.
  • PD Photo Diode
  • pixels that are continuous in the second direction may be called rows, and pixels that are continuous in the first direction may be called columns. That is, the light receiving element array 140 is formed by providing a plurality of rows, which are a group of light receiving elements 14 continuous in the second direction, in the first direction. In other words, the light receiving element array 140 is formed by providing a plurality of rows, which are a group of light receiving elements 14 continuous in the first direction, in the second direction.
  • the light receiving element array 140 includes a first region 141 and a second region 142.
  • the first region 141 and the second region 142 are divided by the pixel dividing unit 143.
  • the pixel dividing unit 143 is provided near the center in the first direction so as to cross the light receiving element array 140 along the second direction, for example.
  • near the center means, for example, in the light receiving element array 140, when n light receiving elements 14 are provided along the first direction, the pixel corresponding to the [n / 2] th pixel and [n / 2] + It is provided between the first pixel and the corresponding pixel.
  • [ ⁇ ] is a floor function.
  • the present invention is not limited to this, and may be not exactly in the center and may be significantly or not significantly biased to either the upper or lower side of the light receiving element array 140 in FIG. 2, but in the present specification, it may be biased. These states are collectively described as near the center in a broad sense.
  • connection portion 30 is connected to the first substrate 10 so as to be adjacent to the light receiving element array 140.
  • the first substrate 10 and the second substrate 20 are connected to each other via the connection portion 30.
  • the connection between the connection portion 30, the respective light receiving element 14, and each circuit on the second substrate 20 is not shown, but wiring by a conductor such as metal is appropriately arranged.
  • the connection portion 30 may not be provided under the light receiving element 14 between the first substrate 10 and the second substrate 20.
  • connection portion 30 is provided for each row in the light receiving element 14 belonging to each region (first region 141, second region 142), for example. Further, in order to propagate the control signal or the like from the circuit on the second substrate 20 onto the first substrate 10, it may be provided for each row. As shown in FIG. 2, the connection portion 30 connecting the second substrate 20 to the first substrate 10 does not need to be provided for each row, and the processing for the optical system 12 and the light receiving element 14 can be appropriately realized. If so, a larger number may be provided, or a smaller number may be provided.
  • the second board 20 includes an analog circuit 200 constituting the above-mentioned signal processing circuit 22, a control circuit 24, and an AE / AF processing circuit 26, and a logic circuit 210.
  • the broken line is a region to be projected onto the second substrate 20 in a state where the range provided with the light receiving element array 140 is laminated on the first substrate 10.
  • the analog circuit 200 is provided at both ends of the region where the light receiving element array 140 exists on the corresponding first substrate 10 in the laminated state, for example.
  • the analog circuit 200 is thus provided near both ends of the range in which the light receiving element array 140 is provided.
  • the analog circuit 200 includes a first analog circuit 201 and a second analog circuit 202.
  • the first analog circuit 201 and the second analog circuit 202 are provided so as to be adjacent to the connection portion 30, so that the analog signal output from the light receiving element 14 via the connection portion 30 can be easily received. Is placed in.
  • the first analog circuit 201 and the second analog circuit 202 each operate as an analog circuit.
  • the first analog circuit 201 acquires an analog signal from the light receiving element 14 belonging to the first region 141 via the connection portion 30, and outputs a digital signal based on the light receiving intensity of each light receiving element 14 belonging to the first region 141. Generate.
  • the second analog circuit 202 acquires an analog signal from the light receiving element 14 belonging to the second region 142 via the connection portion 30, and is based on the light receiving intensity of each light receiving element 14 belonging to the second region 142. Generate a digital signal.
  • the analog circuit 200 converts, for example, the analog signal output by the light receiving element 14 into a digital signal for each pixel and outputs the analog signal.
  • the first analog circuit 201 and the second analog circuit 202 operate exclusively, for example.
  • the digital signal converted by the first analog circuit 201 and the second analog circuit 202 is output to the logic circuit 210.
  • the logic circuit 210 executes appropriate signal processing and image processing on image data composed of digital signals for each pixel, for example. That is, the signal processing circuit 22 in FIG. 1 may be, for example, a set of various circuits configured over the analog circuit 200 and the logic circuit 210.
  • the logic circuit 210 further includes a control circuit 24 that generates a control signal based on the image processed image data, and an AE / AF processing circuit 26 that executes AE / AF processing based on the image data and the control signal. It is configured with and.
  • control signal output from the control circuit 24 provided in the logic circuit 210 is propagated to the first board 10 via the connection portion 30 arranged adjacent to the logic circuit 210.
  • the second substrate 20 may be provided with appropriate wiring and an interface (not shown).
  • the logic circuit 210 can be configured as one area so as to be sandwiched between the analog circuits 200, as opposed to the analog circuit 200 which is divided into two and arranged.
  • the logic circuit 210 By arranging the logic circuit 210 between the analog circuits 200, it becomes easy to control the timing of processing the signal output from the light receiving element 14 belonging to each region of the first substrate 10.
  • the configuration can be easily synchronized. It also has the effect of improving the layout efficiency of the semiconductor substrate.
  • a memory such as SRAM (Static Random Access Memory) may be provided in the logic circuit 210 so as to sandwich the dotted line portion. That is, it is also possible to have a configuration in which SRAM is collectively provided in one area.
  • SRAM Static Random Access Memory
  • FIG. 3 is a diagram schematically showing the positions of the light receiving element array 140, the analog circuit 200, and the logic circuit 210 in a state where the first board 10 and the second board 20 are stacked. As shown in FIG. 3, the light receiving element array 140 and the analog circuit 200 are laminated so as to overlap each other near both ends of the light receiving element array 140 in the first direction.
  • connection portion 30 is arranged so as to connect the light receiving element 14 and the analog circuit 200 along the third direction in the peripheral portion of the light receiving element array 140.
  • the logic circuit 210 and the light receiving element 14 are arranged so as to be connected along the third direction. It is arranged so as to connect the periphery of the pixel dividing portion 143 and the periphery of the circuit dividing portion 223.
  • the first analog circuit 201 and the second analog circuit 202 receive the analog signal from the light receiving element 14 connected by the connection unit 30, and execute appropriate processing.
  • a logic circuit 210 (digital circuit) is provided so as to be sandwiched between the first analog circuit 201 and the second analog circuit 202 in the first direction.
  • FIG. 4 is a diagram showing an example of wiring in the light receiving element array 140 according to the present embodiment.
  • the analog signal output by the light receiving element 14 provided on the first substrate 10 is transmitted to the analog circuit 200 provided on the second substrate 20.
  • the spacing is drawn wider than the other pixels above and below the pixel dividing portion 143, but this is for the sake of explanation, and in reality, the spacing is equivalent to that between the other pixels. May have.
  • the light receiving element array 140 is provided with a plurality of first signal lines 16 and a plurality of second signal lines 181, 182.
  • the second signal lines 181, 182 related to the same row are electrically cut off around the pixel dividing portion 143. That is, the second signal line 181 connected to the light receiving element 14 belonging to the first region 141 and the second signal line 182 connected to the light receiving element 14 belonging to the second region 142 are electrically connected to the first substrate 10. Not connected to.
  • first connecting parts 301 and a second connecting part 302 are provided as connecting parts 30, and the light receiving element 14 is a second signal.
  • the lines 181, 182 are connected to the analog circuit 200 of the second substrate 20 via these connections. More specifically, the light receiving element 14 belonging to the first region 141 is connected to the first analog circuit 201 via the second signal line 181 and the first connecting portion 301, and the light receiving element 14 belonging to the second region 142 is connected. Is connected to the second analog circuit 202 via the second signal line 182 and the second connection portion 302.
  • the first signal line 16 is a wiring for selecting which line of the light receiving element array 140 to process the analog signal output from the light receiving element 14.
  • the first signal line 16 is connected to a row selection circuit outside the region connected to the light receiving element 14, for example, and a line for outputting an analog signal to the analog circuit 200 is selected by the signal from the row selection circuit. Therefore, the first signal line 16 along the second direction is arranged by at least the number of lines in the second direction.
  • the line-based light receiving element 14 selected by the first signal line 16 is transmitted to the first connection portion 301 or the second connection portion 302 via the corresponding second signal lines 181, 182.
  • the second signal lines 181, 182 along the first direction are arranged at least one for each row, that is, at least as many as the number of rows in the first direction.
  • the first connection portion 301 and the second connection portion 302 are provided along the second direction for at least the number of columns, respectively.
  • the first connection unit 301 and the second connection unit 302 output the analog signal output from the light receiving element 14 to the first analog circuit 201 and the second analog circuit 202, respectively, and the analog signal processing is executed. ..
  • the processing of the analog signal output from the light receiving element 14, that is, the reading order of the light receiving element 14, is executed by switching, for example, three reading modes.
  • the three reading orders will be described below.
  • FIG. 5 is a diagram showing the first read mode.
  • reading is executed line by line so as to sequentially move from both ends of the light receiving element 14 in the first direction toward the pixel dividing portion 143. These reads from above and below are executed in parallel.
  • processing is executed for the light receiving element 14 belonging to the bottom row and the top row.
  • the processes are executed for the light receiving element 14 belonging to the second line from the bottom and the second line from the top, respectively. This process is repeated until the pixel division unit 143 is reached.
  • the first analog circuit 201 and the second analog circuit 202 parallel the analog signals of the light receiving element 14 belonging to the first region 141 and the light receiving element 14 belonging to the second region 142, respectively. May be converted into a digital signal. That is, the first analog circuit 201 and the second analog circuit 202 convert the analog signal output from the light receiving element 14 belonging to the corresponding region at the same timing into a digital signal.
  • FIG. 6 is a diagram showing the second read mode.
  • the second read mode in the light receiving element array 140, reading is executed row by row in the direction from the pixel adjacent to the pixel dividing portion 143 in the first direction of the light receiving element 14 toward the respective end portions. These readings from the center periphery to the top and bottom are performed in parallel.
  • processing is executed for the light receiving element 14 belonging to the row below the first direction of the pixel dividing unit 143 and the row in the first direction information.
  • the processes for the light receiving element 14 belonging to the second line from the pixel dividing unit 143 are executed. This process is repeated until the light receiving element 14 at the first-direction end of the light receiving element array 140 is reached.
  • the first analog circuit 201 and the second analog circuit 202 relate to the light receiving element 14 belonging to the first region 141 and the light receiving element 14 belonging to the second region 142, respectively.
  • Analog signals may be converted into digital signals in parallel. That is, the first analog circuit 201 and the second analog circuit 202 convert the analog signal output from the light receiving element 14 belonging to the corresponding region at the same timing into a digital signal.
  • FIG. 7 is a diagram showing a third read mode.
  • the third read mode in the light receiving element array 140, reading is sequentially executed from the light receiving element 14 belonging to the row at one end of the light receiving element 14 to the light receiving element 14 belonging to the other row.
  • the process is executed for the light receiving element 14 belonging to the bottom row in FIG. 7.
  • the analog signals output from the respective light receiving elements 14 are subjected to signal processing in parallel in the first analog circuit 201.
  • the processing is executed in the same manner for the line above, that is, the second line from the bottom. This process is executed, for example, by selecting rows in order from the bottom from the row selection circuit by a synchronization signal in the row direction.
  • the light receiving element 14 belonging to the first region 141 belongs to the second region 142 while the signal is transmitted to the first analog circuit 201 via the second signal line 181 and the first connection portion 301.
  • the light receiving element 14 transmits a signal to the second analog circuit 202 via the second signal line 182 and the second connection portion 302. After this, the scan is sequentially executed from the lower side to the upper side of the second region 142 based on the synchronization signal in the row direction.
  • the first analog circuit 201 and the second analog circuit 202 sequentially transmit analog signals about the light receiving element 14 belonging to the first region 141 and the light receiving element 14 belonging to the second region 142, respectively. Convert to a digital signal. That is, in this case, the first analog circuit 201 and the second analog circuit 202 can be configured to exclusively execute signal conversion except for the moment of processing a row straddling the pixel dividing unit 143.
  • the first analog circuit 201 and the second analog circuit 202 may exclusively stop the power supply except for the timing of straddling the pixel division unit 143.
  • the power supply may be stopped. By stopping the power supply in this way, it is possible to reduce power consumption.
  • the timing of reading the signals from the light receiving elements 14 above and below the pixel dividing unit 143 is substantially the same. Therefore, it is possible to generate image data with less discomfort without significantly changing the state of distortion in the central portion of the image or video.
  • the above reading method may be constantly read by the reading method, the user may switch the mode, or the reading method may be automatically switched.
  • the row selection is executed, for example, by applying a selection signal to the first signal line 16 corresponding to the row selected by the row selection circuit based on the synchronization signal.
  • a selection signal By controlling the signal output unit of the light receiving element 14 belonging to the selected line and the energized state of the second signal lines 181, 182 by this selection signal, an analog signal is output to an appropriate analog circuit 200.
  • a MOSFET Metal
  • the gate is connected to the first signal line 16 and the drain and source (or source and drain) are connected to the light receiving element 14 and the second signal lines 181, 182, respectively.
  • -Oxide-Semiconductor Field-Effect-Transistor The present invention is not limited to this, and an energized state may be formed by a switch or the like driven by a signal via the first signal line 16 by another method.
  • the region of the light receiving element array 140 provided in the first substrate 10 is divided near the center, and the analog circuits 200 are arranged at both ends in the first direction so as to overlap each other in the stacked second substrate 20. This makes it possible to shorten the transmission path of the signal output from the light receiving element 14 in the second signal lines 181, 182.
  • the connection portion 30 according to the present embodiment, it is possible to easily mount the circuit on the chip without significantly changing the arrangement of the conventional connection portion 30.
  • the logic circuit 210 can be collectively arranged in one area of the second board 20, it is possible to make the power supply quality uniform by centralized power supply and ground wiring. Similarly, since the logic circuit 210 can be formed in one area, it is possible to realize a centralized arrangement of control signal generation, and accordingly, it is possible to realize equal length and shortest control signal wiring. This applies not only to the wiring related to the control signal but also to the wiring of the read signal.
  • the first reading order or the second reading order which has a higher frame rate, is used, and when shooting, etc., where it is necessary to acquire a highly accurate image, and still.
  • the reading is performed in the third reading order in which the focal plane distortion is further suppressed while maintaining a high frame rate.
  • FIG. 8 is a diagram schematically showing the focal plane distortion in each mode described above.
  • the left figure shows the first read mode
  • the middle figure shows the second read mode
  • the right figure shows the focal plane distortion corresponding to the third read mode.
  • FIG. 8 shows, for example, an image of a rectangular object covering the entire region of the light receiving element 14 in the first direction moving to the right.
  • the dotted line is a line segment indicating the pixel division portion 143 in the acquired image.
  • the rectangular object in the first read mode, the rectangular object is imaged with a delay in timing as it approaches the pixel dividing portion 143 near the center. Therefore, the object is distorted to the right as it approaches the pixel dividing portion 143.
  • the rectangular object is imaged with a delay in timing as it approaches the end in the first direction. Therefore, the object is distorted to the right as it approaches the end (upper and lower) from the pixel dividing portion 143.
  • the image is distorted so that a monotonous shift occurs.
  • the imaging time is twice that of the first read mode and the second read mode, that is, the frame rate is 1/2, but on the other hand, the direction of image distortion in the pixel dividing unit 143 is It does not change. Therefore, for humans, the image captured by the third read mode gives a natural impression as compared with other read modes.
  • FIG. 9 is a flowchart showing a process of taking a picture by the solid-state image sensor 1 in such a method.
  • the control circuit 24 sets the first read mode or the second read mode as the read mode (S100).
  • the signals from the light receiving element 14 for the two regions divided by the pixel dividing unit 143 are processed at the same timing, so that the frame rate is about twice as high as that in the third read mode. Can be done.
  • focal plane distortion such as folding back at the pixel dividing portion 143 is generated. Therefore, in the initial stage of processing AE / AF at high speed, the first read mode or the second read mode, which enables reading at a higher speed than the third read mode, is set.
  • control circuit 24 controls the shooting conditions (S102). This control may be set using a shooting parameter or the like set as an initial value. If information from an illuminometer or the like is available, parameters such as exposure and focus may be set based on the information.
  • control circuit 24 shoots based on the set shooting conditions, and the signal processing circuit 22 executes signal processing (S104).
  • the signal processing circuit 22 executes signal processing and image processing of an analog signal received and output by the light receiving element 14 under controlled shooting conditions.
  • a display unit such as a display is provided in the solid-state image sensor 1, the processed image may be displayed on the display or the like.
  • the AE / AF processing circuit 26 executes AE / AF processing based on the image data output by the signal processing circuit 22 (S106). AF / AE processing is executed based on the acquired image data.
  • the AE / AF processing circuit 26 may set the AE by, for example, calculating the statistics of the luminance information in the image.
  • the AE / AF processing circuit 26 may, for example, reduce the exposure when it is determined that there are many whiteout pixels, and conversely, increase the exposure when it is determined that there are many blackout pixels. You may.
  • the AE / AF processing circuit 26 may detect the contrast in the image, for example, and set the AF so that the contrast becomes high. Further, as another example, the AE / AF processing circuit 26 may set AF so that the high frequency component of the spatial frequency becomes high.
  • Each of the AE and AF processes may be executed, for example, based on the statistical information of the pixel values in the predetermined area.
  • the predetermined region may be, for example, the entire image or a region near the center of the image. Further, the user may set the area.
  • These processes may be automatically performed at predetermined intervals at the timing before shooting, or may be executed based on the AE / AF lock request via the user interface.
  • the lock request may be accepted by half-pressing the shutter button in an electronic device such as a digital camera provided with the solid-state image sensor 1.
  • the AE / AF processing circuit 26 outputs the parameters related to AE and AF calculated in this way to the control circuit 24. If the exposure and focus are appropriate, that fact is output to the control circuit 24.
  • the AE / AF processing circuit 26 determines, for example, whether or not appropriate AE and AF parameters are set based on the above-mentioned statistics on exposure and focus, and outputs the result to the control circuit 24. Further, the AE / AF processing circuit 26 may simply transmit the parameters, and in this case, the control circuit 24 may determine whether or not the parameters are appropriately set.
  • control circuit 24 determines whether or not appropriate parameters such as AE / AF are set based on the output from the AE / AF processing circuit 26 (S108).
  • the process from S102 is repeated.
  • the AE / AF processing circuit 26 sets the parameters based on the output, and the optical system 12, the light receiving element 14, the signal processing circuit 22, and the AE / AF processing circuit 26. To control.
  • the control circuit 24 transmits, for example, a control signal for adjusting the exposure time and focus to the optical system 12 and the light receiving element 14. Further, the control circuit 24 processes the signal output by the light receiving element 14 by transmitting the parameters used until the next control timing to the signal processing circuit 22 and the AE / AF processing circuit 26. Control the parameters of.
  • the control circuit 24 sets the read mode to the third read mode (S110).
  • the third read mode as described above, the frame rate is lower than that of the first read mode and the second read mode, but the focal plane distortion becomes more natural for humans than the other modes. It shifts to the mode to acquire the image.
  • shooting and signal processing are executed based on the request from the control circuit 24 (S112).
  • the optical system 12 and the light receiving element 14 take an image in the third read mode according to appropriately set parameters related to exposure, focus, and the like.
  • the signal processing circuit 22 executes various processes such as signal processing and image processing based on the parameters acquired from the control circuit 24.
  • the signal processing circuit 22 outputs image data to an appropriate location (S114).
  • the signal processing circuit 22 stores image data in a memory inside or outside the solid-state image sensor 1. Further, at the same timing, if there is a display unit such as a display, the image data may be displayed.
  • control circuit 24 determines whether or not the imaging process is complete (S116). This determination may be made based on instructions from the user. If the process is not completed, for example, if the user continues shooting (S116: NO), the process from S100 is repeated again. In this case, the processes of S100 to S106 may be executed using the parameters set in S112 and S114 as initial values.
  • FIG. 10 is a block diagram showing the configuration of the solid-state image sensor 1 according to the second embodiment.
  • the solid-state image sensor 1 includes a recognition processing circuit 28 instead of the AE / AF processing circuit 26 of the solid-state image pickup device 1 in the first embodiment. It should be noted that this figure is shown as an example, and may be configured to further include an AE / AF processing circuit 26 and also execute the above-mentioned AE / AF processing.
  • the recognition processing circuit 28 is provided, for example, as a part of the logic circuit 210 in FIG.
  • the recognition processing circuit 28 executes various recognition processing using, for example, a trained machine learning model.
  • the recognition processing circuit 28 recognizes a human face and extracts the area of the face. Not limited to the human face, the recognition processing circuit 28 may detect and recognize a predetermined object. As a configuration further including the AE / AF processing circuit 26, even if a person's face is detected and parameters for controlling AE and AF are calculated in a region of a predetermined size and shape including the detected face. good. In this case, the facial area may be detected and tracked frame by frame.
  • the facial expression may be read at the timing of recognizing the face of the person. Then, the control circuit 24 may execute control to perform imaging at the timing when the read facial expression is a smile. Further, in the above, the face of a person is used as the subject, but the subject is not limited to this, and any object can be set as the subject.
  • FIG. 11 is a flowchart showing the processing of the solid-state image sensor 1 according to the present embodiment. Since the processes with the same reference numerals are the same as those in the above-described embodiment, detailed description thereof will be omitted.
  • the recognition processing circuit 28 executes the recognition processing on the image data output by the signal processing circuit 22 (S118).
  • the recognition process is executed, for example, by inputting image data into a trained neural network model. Note that the recognition process may be executed by a rule-based process or the like without using the neural network model.
  • the recognition processing circuit 28 determines whether or not a predetermined object has been recognized and detected (S120). If it is not detected (S120: NO), the process from S104 is repeated. As shown by the dotted arrow, the recognition process may be repeatedly executed a predetermined number of times or for a predetermined time. After that, if the recognition cannot be further performed, the process from S104 may be repeated.
  • the control circuit 24 shifts the processing mode of the solid-state image sensor 1 to the third read mode (S110).
  • control circuit 24 executes ROI (Region of Interest) control based on the detection result of the recognition processing circuit 28 (S122). By controlling this ROI, the area where the subject is shown may be tracked. Further, AE and AF processing may be executed based on the statistical information in the ROI.
  • ROI Region of Interest
  • the image is acquired and output, and the process is terminated.
  • the solid-state image sensor 1 may choose not to execute the recognition process even when the recognition process circuit 28 is provided. Even if the solid-state image sensor 1 cannot detect an object, it can perform imaging, signal processing, etc. based on the parameters set at that timing according to the user's request based on the set AE and AF. The process may be executed.
  • the recognition process may be executed in the logic circuit 210 provided in the second board 20.
  • the solid-state image sensor 1 performs reading in a mode with a high frame rate in order to detect the subject at high speed while executing the recognition process, and has high accuracy so that the focal plane distortion does not become unnatural after the recognition is completed. It is possible to switch to the mode to acquire the image of.
  • the recognition processing circuit 28 is supposed to detect a predetermined object, but the present invention is not limited to this.
  • an event-driven operation that detects movement may be realized.
  • control circuit 24 may execute various controls, for example, switching of the read mode, based on the result recognized by the recognition processing circuit 28.
  • the recognition processing circuit 28 was supposed to be recognized using a trained model, but it is not limited to this.
  • the recognition processing circuit 28 may execute machine learning to improve the accuracy of the recognition result based on the recognition result or the instruction from the user. This machine learning may be executed, for example, at a timing when the solid-state image sensor 1 is not taking a picture.
  • the configuration is provided with one pixel dividing unit 143, but the present invention is not limited to this. That is, the light receiving element array 140 may be divided into more regions. Along with this, the analog circuit 200 may also be mounted in more areas.
  • FIG. 12 is a diagram showing a laminated state of the light receiving element array 140 and the analog circuit 200 according to the present embodiment.
  • the light receiving element array 140 is provided with three pixel dividing units 143A, 143B, and 143C.
  • the light receiving element array 140 is roughly divided into two regions by the pixel dividing unit 143C. These regions are divided into a first region 141A and a second region 142A by the pixel dividing unit 143A, and a first region 141B and a second region 142B by the pixel dividing unit 143B. In this way, the light receiving element array 140 is divided into, for example, four regions.
  • one first signal line is arranged for the light receiving element 14 continuous in the second direction, that is, the pixels belonging to the same row.
  • the second signal line connected to the light receiving element 14 continuous in the first direction belonging to each region of 141A, 142A, 141B, 142B is cut in each region in the same manner as in the above-described embodiment. It is output to the analog circuit 200 via each connection. That is, in the example of FIG. 12, four second signal lines are provided in each row.
  • FIG. 13 is a diagram showing an outline of the light receiving element array 140 according to the present embodiment.
  • the light receiving element array 140 is divided into regions 141A, 142A, 141B, and 142B by the pixel dividing portions 143A, 143B, and 143C.
  • Each of the divided regions is provided with a first signal line 16 for selecting whether or not to output from the light receiving element 14 belonging to the same line for the number of lines in which the light receiving element 14 exists. Similar to FIG. 4, the interval between pixels is wide at the portion straddling the pixel division portion, but for the sake of explanation, even if the interval is actually the same as the interval between other pixels. good.
  • the second signal line is provided so that the output is connected from the light receiving element 14 belonging to the same row for each region and is cut off in different regions.
  • the plurality of second signal lines 181A arranged in the region 141A connect the light receiving elements 14 belonging to the respective rows.
  • it is provided so as not to be electrically connected to the second signal lines 182A, 181B, 182B of the other regions 142A, 141B, 142B.
  • Each signal line is connected to the second board 20 by a connecting part.
  • each second signal line 181A in the first region 141A is connected to the first analog circuit 201 via the first connection portion 301A.
  • the second signal line 182A in the second region 142A is connected to the second analog circuit 202 via the second connection portion 302A.
  • the upper side of the figure is the same as the lower side, and the second signal line 181B of the first region 141B is connected to the third analog circuit 203 via the first connection portion 301B, and the second signal line of the second region 142B is connected.
  • the 182B is connected to the fourth analog circuit 204 via the second connection portion 302B.
  • the light receiving element array 140 may be divided into a plurality of regions by the plurality of pixel dividing units 143 in this way. As shown in FIG. 13, a second signal line and a connection portion are independently provided in each region, and each is connected to the analog circuit 200 of the second substrate 20.
  • the second board 20 will be explained.
  • analog circuits are provided respectively.
  • the second board 20 includes a first analog circuit 201, a second analog circuit 202, a third analog circuit 203, and a fourth analog circuit 204.
  • each analog circuit 200 is provided with the first analog circuit 201 and the fourth analog circuit 204 at the end in the first direction of the light receiving element array 140 in the third direction in a stacked state. Further, the second analog circuit 202 and the third analog circuit 203 are arranged so as to overlap the pixel dividing portion 143. Since the configuration of each circuit is the same as that shown in FIG. 5, details are omitted. It should be noted that the second analog circuit 202 and the third analog circuit 203 do not need to be clearly distinguished, and if the signal output from the light receiving element 14 belonging to each region can be appropriately processed, they are integrated. It may be formed as.
  • the power of the unnecessary analog circuit may be turned off in accordance with the light receiving element 14 that outputs an analog signal.
  • the logic circuits 210A and 210B may be arranged, for example, between the first analog circuit 201 and the second analog circuit 202, and between the third analog circuit 203 and the fourth analog circuit 204 in the figure.
  • connection portion 30 must be provided below the light receiving element 14, while the load on the second signal line can be further reduced, resulting in further speedup and lower power consumption. Can be realized.
  • one second signal line is provided in one row, but the present invention is not limited to this.
  • the light receiving element 14 belonging to one row may be provided with a plurality of second signal lines.
  • the plurality of second signal lines may be provided with a connection portion for each.
  • FIG. 14 is a diagram schematically showing an outline of a pixel array, a second signal line, and a connection portion according to the present embodiment.
  • the pixels, wiring, connection parts, etc. are all drawn on a plane, but the present invention is not limited to this.
  • the pixel may be on the upper surface, wiring may be provided below the third direction, and the wiring and the connecting portion may be connected in the first substrate 10.
  • the light receiving element array 140 is provided with a plurality of light receiving elements 14.
  • the plurality of second signal lines 181, 182 are provided so that the outputs of the light receiving elements 14 belonging to the same row are connected to each other. Unlike the above-described embodiment, a plurality of second signal lines 181, 182 are provided between the rows.
  • the first signal line is provided in the same manner as in FIG. 4, although it is not shown.
  • twelve second signal lines 181, 182 may be provided between the rows of the light receiving elements 14 and the rows, respectively.
  • analog signals output from 12 or less light receiving elements 14 along the first direction may be output to the analog circuit 200 of the second substrate 20 in parallel. That is, analog signal processing can be executed in parallel for the light receiving elements 14 belonging to 12 rows or less at the same timing. In other words, it is possible to output the signals of the light receiving element 14 belonging to a plurality of lines to the analog circuit 200 at the same timing.
  • the wiring connected from the light receiving element 14 and the portion where the second signal line is indicated by a black dot are electrically connected, and the portion without a black dot is not electrically connected. It is a place.
  • a switch is provided at a point where the wiring from the light receiving element 14 and the second signal line intersect, and the first signal line appropriately switches the state of these switches to process the analog signal.
  • the light receiving element 14 can be selected.
  • the solid-state image sensor 1 is a laminated body in which the first substrate 10 and the second substrate 20 are laminated.
  • the first substrate 10 and the second substrate 20 are sometimes called dies.
  • the first substrate 10 and the second substrate 20 have a rectangular shape, but the specific shape and size are arbitrary. Further, the first substrate 10 and the second substrate 20 may have the same size or may be different sizes from each other.
  • the light receiving element array 140 shown in FIG. 4 and the like is arranged on the first substrate 10. Further, at least a part of the optical system 12 may be mounted on the first substrate 10 on-chip.
  • the second board 20 is provided with at least an analog circuit 200 and a logic circuit 210, and is also provided with other necessary circuits such as an interface circuit.
  • a clock generation circuit or the like that outputs a clock signal for timing the row selection signal, synchronization signal, or the like described above may be provided.
  • a control circuit for comprehensively or partially controlling each circuit may be provided.
  • the first substrate 10 and the second substrate 20 are cut out from a wafer, separated into individual pieces, and then laminated one above the other, so-called.
  • a CoC (Chip on Chip) method may be adopted.
  • one of the first substrate 10 and the second substrate 20 (for example, the first substrate 10) is cut out from the wafer and individualized, and then the individualized first substrate 10 is separated into the second substrate 20 before individualization.
  • the so-called CoW (Chip on Wafer) method may be adopted.
  • a so-called WoW (Wafer on Wafer) method in which the first substrate 10 and the second substrate 20 are bonded together in the state of a wafer, may be adopted.
  • first substrate 10 and the second substrate 20 may be joined using Various joining methods.
  • plasma junction or the like can be used.
  • the joining portion as shown in the following figure may be used for the connection portion for electrically connecting the first substrate 10 and the second substrate 20. .. It should be noted that it is not shown in the state of a detailed circuit, but only the connection of the connection part is shown. Therefore, in the figure, drawing of various circuit elements and the like is omitted. Further, the second signal line 181 will be described, but the same applies to the second signal line 182, ..., Etc.
  • FIG. 15 is a diagram showing an example of a connection portion.
  • the analog circuit 200 and the second signal line 181 are connected in the region where the second signal line 181 exists.
  • the light receiving element 14 that photoelectrically converts the light collected by the optical system 12 is connected by a second signal line 181.
  • the second signal line 181 is connected to, for example, a connection portion 30 formed with microbumps and is connected to an analog circuit 200.
  • micropads are formed on both the light receiving element 14 side and the analog circuit 200 side, and these micropads are connected to each other by microbumps.
  • FIG. 16 is a diagram showing another example of the connection portion.
  • the connection portion 30 may be connected by a micro pad, for example, as shown in the figure.
  • the micro pads may be directly connected.
  • FIG. 17 is a diagram showing another example of the connection portion.
  • the connecting portion 30 may form a via hole, for example, and connect the light receiving element 14 and the analog circuit 200 by making contact between the via hole, the second signal line 181 and the analog circuit 200.
  • first substrate 10 and the second substrate 20 are connected via the connection portion 30 with respect to the light receiving element 14, but even if a connection line for transmitting and receiving other signals is further provided as needed. good.
  • FIG. 18 is a diagram showing an example of a case where the solid-state image sensor 1 is formed of two layers.
  • the second substrate 20 includes an optical system 12 and a light receiving element array 140 having the light receiving elements 14 in a two-dimensional array. Further, it is provided with wiring and the like necessary for extracting pixel information such as the first signal line and the second signal line.
  • the second board 20 includes an analog circuit 200, a logic circuit 210, a memory 220, and an input / output I / F 230. In addition, a circuit necessary for controlling the solid-state image sensor 1 is provided.
  • FIG. 19 is a diagram showing an example of a case where the solid-state image sensor 1 is formed of three layers.
  • the elements of the first substrate 10 and the second substrate 20 are almost the same as those in FIG.
  • the second board 20 is not provided with the memory
  • the third board 40 is provided with the memory.
  • the third substrate 40 is below the second substrate 20, but is not limited to this. That is, the third substrate 40 may be provided between the first substrate 10 and the second substrate 20.
  • the connection between the layers is the same as that of the above-described embodiment.
  • the layers are connected by the connection method as shown in FIGS. 15 to 17.
  • CMOS sensors All embodiments have described examples of CMOS sensors, but are not limited to this. It can also be applied to organic film sensors and other types of light receiving devices.
  • the solid-state image sensor 1 switches a plurality of modes based on the application, environment, and the like to perform imaging.
  • the solid-state imaging device 1 can be mounted on various electronic devices such as feature phones, smartphones, tablet terminals, digital cameras, digital video cameras, and surveillance cameras.
  • the circuit that executes each of the above operations is appropriately mounted by an analog circuit or a digital circuit.
  • this circuit may be configured by a circuit such as an ASIC (Application Specific Integrated Circuitry), or at least a part of the operation may be implemented by software in a circuit such as a general-purpose CPU (Central Processing Unit). It may be what is done.
  • an executable file, a program, or the like related to the software or the like may be stored in a storage unit.
  • at least a part of these circuits may be implemented as a programmable circuit such as an FPGA (Field Programmable Gate Array).
  • a plurality of light receiving elements that photoelectrically convert light and output an analog signal are arranged in a two-dimensional array as columns along the first direction and rows along the second direction intersecting the first direction.
  • a second board with an analog circuit, which processes the signal, and Equipped with The light receiving element array is By the pixel dividing portion along the second direction, it is divided into a first region and a second region, each of which has a continuous light receiving element.
  • the analog circuit is A first analog circuit connected to the light receiving element belonging to the first region via a first connecting portion arranged in a region not overlapping with the light receiving element array in the third direction.
  • a second analog circuit connected to the light receiving element belonging to the second region via a second connecting portion arranged in a region not overlapping with the light receiving element array in the third direction.
  • a first signal line which selects one or more of the rows in the first direction and is arranged along the first direction
  • a first signal line which selects one or more of the rows in the first direction and is arranged along the first direction
  • a second signal line which is arranged along the second direction, selects one or more of the rows having the light receiving element continuous in the first direction. Equipped with The analog signal output by the light receiving element selected by the first signal line is transmitted via the second signal line and processed by the analog circuit. The second signal line is electrically cut off at the pixel dividing portion.
  • the pixel dividing portion is arranged near the center of the light receiving element array in the first direction.
  • the first connection portion is connected to the second signal line belonging to the first region, and the light receiving element belonging to the first region and the first analog circuit are connected to each other.
  • the second connection portion is connected to the second signal line belonging to the second region, and is connected to the light receiving element belonging to the second region and the second analog circuit.
  • the first connection and the second connection are each provided in at least the number of rows along the second direction.
  • the second substrate is a control circuit that controls the order in which signals are output from the light receiving element.
  • the control circuit is In the light receiving element array, a first read mode for controlling the order of reading from the row provided on the outside toward the pixel dividing portion. In the light receiving element array, a second read mode for controlling the reading order from the pixel dividing portion toward the row provided on the outside, In the light receiving element array, a third read mode for controlling the reading order from the row at one end in the first direction to the row at the other end.
  • a first read mode for controlling the order of reading from the row provided on the outside toward the pixel dividing portion.
  • a second read mode for controlling the reading order from the pixel dividing portion toward the row provided on the outside
  • a third read mode for controlling the reading order from the row at one end in the first direction to the row at the other end.
  • the second substrate is A signal processing circuit that executes signal processing of the signal output by the analog circuit, and An AE / AF processing circuit that calculates parameters for adjusting exposure and focus based on the output of the signal processing circuit. Further prepare The control circuit controls the exposure and focus of the light receiving element based on the output of the AE / AF processing circuit.
  • the solid-state image sensor according to (7) or (8).
  • the control circuit is The first read mode, the second read mode, and the third read mode are switched based on the output of the AE / AF processing circuit.
  • the control circuit is Based on the output of the AE / AF processing circuit, the first read mode or the second read mode is selected and controlled until the exposure control and the focus control are completed. After the exposure control and focus control are completed, the third read mode is selected and controlled.
  • the second substrate is A signal processing circuit that executes signal processing of the signal output by the analog circuit, and A recognition processing circuit that executes object recognition processing based on the output of the signal processing circuit. Further prepare The control circuit switches between the first read mode, the second read mode, and the third read mode based on the output of the recognition processing circuit.
  • the solid-state image sensor according to (7) or (8).
  • the control circuit is Based on the output of the recognition processing circuit, the first read mode or the second read mode is selected and controlled until the object is detected. After the object is detected, the third read mode is selected and controlled.
  • the solid-state image sensor according to (12).
  • the first analog circuit and the second analog circuit process the analog signals of one or a plurality of different pixels belonging to the row along the second direction at the same timing.
  • the solid-state image sensor according to any one of (1) to (13).
  • the first analog circuit and the second analog circuit convert the analog signal into a digital signal.
  • the second board is a logic circuit that processes the digital signal, and includes a logic circuit that is sandwiched between the first analog circuit and the second analog circuit.
  • the solid-state image sensor according to (1) is a logic circuit that processes the digital signal, and includes a logic circuit that is sandwiched between the first analog circuit and the second analog circuit.
  • the logic circuit includes a memory so as to overlap the pixel dividing portion in the third direction.
  • the second substrate is A signal processing circuit that executes signal processing of the digital signal, and An image processing circuit that executes image processing of the digital signal, which is image information, and A memory for storing arbitrary data among the digital signal, the data output by the signal processing circuit, and the data output by the image processing circuit.
  • the data output by the image processing circuit, and the data stored in the storage unit at least one arbitrary data or any signal is output to the outside, or An interface that accepts data or signal input from the outside, The solid-state image sensor according to (1).
  • the aspect of the present disclosure is not limited to the above-mentioned embodiment, but also includes various possible modifications, and the effect of the present disclosure is not limited to the above-mentioned contents.
  • the components in each embodiment may be applied in appropriate combinations. That is, various additions, changes and partial deletions are possible without departing from the conceptual idea and purpose of the present disclosure derived from the contents specified in the claims and their equivalents.
  • 1 Solid-state image sensor, 10: 1st board, 12: Optical system, 14: Light receiving element, 140: Light receiving element array, 141: 1st area, 142: 2nd area, 143: Pixel dividing part, 16: 1st signal line, 181, 182: 2nd signal line, 20: 2nd board, 22: Signal processing circuit, 24: Control circuit, 26: AE / AF processing circuit, 28: Recognition processing circuit, 200: Analog circuit, 201: 1st analog circuit, 202: 2nd analog circuit, 203: 3rd analog circuit, 204: 4th analog circuit, 210: Logic circuit, 220: Memory, 230: I / O I / F 30: Connection, 301: 1st connection, 302: 2nd connection

Abstract

[Problem] To inhibit the occurrence of distortion. [Solution] A solid-state imaging device comprises: a first substrate having a light-receiving element array in which a plurality of light-receiving elements are arranged in a two-dimensional array with columns along a first direction and rows along a second direction; and a second substrate that is layered on the first substrate, and that has an analog circuit which is disposed overlapping the light-receiving element array in a third direction and which processes analog signals output from the light-receiving elements. The light-receiving element array is divided, by a pixel division part along the second direction, into a first region and a second region comprising the light-receiving elements. The analog circuit comprises: a first analog circuit connected to the light-receiving elements belonging to the first region via a first connection part that is disposed in a region which does not overlap the light-receiving element array in the third direction; and a second analog circuit connected to the light-receiving elements belonging to the second region via a second connection part that is disposed in a region which does not overlap the light-receiving element array in the third direction.

Description

固体撮像装置及び電子機器Solid-state image sensor and electronic equipment
　本開示は、固体撮像装置及び電子機器に関する。 This disclosure relates to a solid-state image sensor and an electronic device.
　従来のCMOS（Complementary Metal-Oxide Semiconductor）素子等の画素をアレイ状に形成した画素アレイを備えるセンサは、所定の素子から順番に信号を取得するため、フレームレートが低いという問題がある。フレームレートを高めるために様々な技術が開発されている。これらの技術においては、フレームレートを高める一方で、フォーカルプレーン歪みの形状が好ましくない場合がある。 A sensor equipped with a pixel array in which pixels such as a conventional CMOS (Complementary Metal-Oxide Semiconductor) element are formed in an array has a problem that the frame rate is low because signals are acquired in order from a predetermined element. Various technologies have been developed to increase the frame rate. In these techniques, while increasing the frame rate, the shape of the focal plane distortion may not be preferable.
　これを回避するために、画素アレイを単純な領域に分割することが考えられる。単純に分割すると、画素アレイにおいては隣接するが異なるアナログ回路により処理される複数の画素、すなわち、領域の境界をまたぐように隣接する画素同士は、信号処理のタイミングが異なる信号線により伝播される。信号処理のタイミングが異なることにより、境界をまたぐように隣接する画素同士は、受光するタイミングが他の隣接画素同士と比較して大きく異なることがある。この結果、領域の境界におけるローリングシャッター歪みの原因となりうる。 In order to avoid this, it is conceivable to divide the pixel array into simple areas. When simply divided, in a pixel array, a plurality of pixels that are adjacent to each other but are processed by different analog circuits, that is, pixels that are adjacent to each other so as to straddle the boundary of a region, are propagated by signal lines having different signal processing timings. .. Due to the difference in the timing of signal processing, the timing of receiving light may be significantly different between the pixels adjacent to each other so as to cross the boundary as compared with the other adjacent pixels. As a result, it can cause rolling shutter distortion at the boundaries of the region.
　しかしながら、画素と論理回路を積層させる撮像素子においては、画素の下、例えば、裏面照射型センサにおいては画素の表面側に積層する他の半導体層への接続導線が必要となり、他の回路との親和性が低く、複雑になりがちである。これらの結果、画素サイズの微細化や多画素化には、不向きな一面がある。 However, in an image sensor in which a pixel and a logic circuit are laminated, a connection lead wire to another semiconductor layer laminated under the pixel, for example, in a back-illuminated sensor, on the front surface side of the pixel is required, and the connection with another circuit is required. It has low affinity and tends to be complicated. As a result, there is one aspect that is unsuitable for miniaturization of pixel size and increase in the number of pixels.
特開2013-243781号公報Japanese Unexamined Patent Publication No. 2013-243781
　本開示は、受光素子のアレイに複数の領域を備え、歪みの発生が抑制された固体撮像装置及び電子機器を提供する。 The present disclosure provides a solid-state image pickup device and an electronic device in which an array of light receiving elements is provided with a plurality of regions and the occurrence of distortion is suppressed.
　一実施形態によれば、固体撮像装置は、光を光電変換してアナログ信号を出力する複数の受光素子が、第1方向に沿った列及び前記第1方向と交差する第2方向に沿った行として2次元のアレイ状に配置される、受光素子アレイを有する、第1基板と、前記第1基板に積層する第2基板であって、前記第1方向及び前記第2方向に交差する第3方向において、前記受光素子アレイと重なって配置され、前記受光素子から出力された前記アナログ信号を処理する、アナログ回路、を有する第2基板と、を備え、前記受光素子アレイは、前記第2方向に沿った画素分割部により、それぞれが連続する前記受光素子を備える第1領域と、第2領域と、に分割され、前記アナログ回路は、前記第3方向において前記受光素子アレイと重ならない領域に配置される第1接続部を介して前記第1領域に属する前記受光素子と接続される、第1アナログ回路と、前記第3方向において前記受光素子アレイと重ならない領域に配置される第2接続部を介して前記第2領域に属する前記受光素子と接続される、第2アナログ回路と、を備える。 According to one embodiment, the solid-state imaging device has a plurality of light receiving elements that photoelectrically convert light and output an analog signal along a row along a first direction and a second direction intersecting the first direction. A first substrate having a light receiving element array arranged in a two-dimensional array as a row, and a second substrate laminated on the first substrate, which intersects the first direction and the second direction. A second substrate having an analog circuit, which is arranged so as to overlap the light receiving element array in three directions and processes the analog signal output from the light receiving element, is provided, and the light receiving element array is provided with the second light receiving element array. The analog circuit is divided into a first region and a second region, each of which has a continuous light receiving element, by a pixel dividing portion along the direction, and the analog circuit is a region that does not overlap with the light receiving element array in the third direction. A first analog circuit connected to the light receiving element belonging to the first region via a first connecting portion arranged in the third direction, and a second arranged in a region not overlapping with the light receiving element array in the third direction. A second analog circuit, which is connected to the light receiving element belonging to the second region via a connecting portion, is provided.
　前記受光素子アレイにおいて、前記第2方向に連続する前記受光素子を備える前記行のうち、前記第1方向における1又は複数の前記行を選択する、前記第1方向に沿って複数配置される、第1信号線と、前記第1方向に連続する前記受光素子を備える前記列のうち、前記第2方向における1又は複数の前記列を選択する、前記第2方向に沿って複数配置される、第2信号線と、を備えてもよく、前記第1信号線により選択された前記受光素子が出力する前記アナログ信号を、前記第2信号線を介して伝送して前記アナログ回路により処理し、前記第2信号線は、前記画素分割部において、電気的に切断されてもよい。 In the light receiving element array, among the rows including the light receiving elements continuous in the second direction, one or a plurality of the rows in the first direction are selected, and a plurality of rows are arranged along the first direction. Among the rows including the first signal line and the light receiving element continuous in the first direction, one or more of the rows in the second direction are selected, and a plurality of the rows are arranged along the second direction. A second signal line may be provided, and the analog signal output by the light receiving element selected by the first signal line is transmitted via the second signal line and processed by the analog circuit. The second signal line may be electrically cut off at the pixel dividing portion.
　前記画素分割部は、前記第１方向において、前記受光素子アレイの中央付近に配置されてもよい。 The pixel dividing portion may be arranged near the center of the light receiving element array in the first direction.
　前記第1接続部は、前記第1領域に属する前記第2信号線と接続し、前記第1領域に属する前記受光素子と、前記第1アナログ回路と、を接続してもよく、前記第2接続部は、前記第2領域に属する前記第2信号線と接続し、前記第2領域に属する前記受光素子と、前記第2アナログ回路と、を接続してもよい。 The first connection portion may be connected to the second signal line belonging to the first region, and the light receiving element belonging to the first region and the first analog circuit may be connected to the second signal line. The connection unit may be connected to the second signal line belonging to the second region, and may be connected to the light receiving element belonging to the second region and the second analog circuit.
　前記第1接続部及び前記第2接続部は、それぞれ、前記第2方向に沿って少なくとも前記列の数だけ備えられてもよい。 The first connection portion and the second connection portion may be provided at least as many as the number of the rows along the second direction, respectively.
　前記第2基板は、前記受光素子から信号を出力する順番を制御する、制御回路、をさらに備えてもよい。 The second substrate may further include a control circuit that controls the order in which signals are output from the light receiving element.
　前記制御回路は、前記受光素子アレイにおいて、外側に備えられる前記行から、前記画素分割部へと向かって読み出しの順番を制御する、第1読出モードと、前記受光素子アレイにおいて、前記画素分割部から、外側に備えられる前記行へと向かって読み出しの順番を制御する、第2読出モードと、前記受光素子アレイにおいて、第1方向の一方の端部にある前記行から、他方の端部にある前記行へと向かって読み出しの順番を制御する、第3読出モードと、を選択して制御してもよい。 The control circuit controls the reading order from the row provided on the outside in the light receiving element array toward the pixel dividing unit, and the first read mode and the pixel dividing unit in the light receiving element array. From the row at one end of the first direction to the other end in the light receiving element array, the second read mode, which controls the read order from to the outer row towards the row. A third read mode, which controls the order of reading toward the line, may be selected and controlled.
　前記第3読出モードの場合、前記第1アナログ回路と、前記第2アナログ回路は、排他的に駆動してもよい。 In the case of the third read mode, the first analog circuit and the second analog circuit may be driven exclusively.
　前記第2基板は、前記アナログ回路が出力した信号の信号処理を実行する、信号処理回路と、前記信号処理回路の出力に基づいて、露出及びフォーカスを調整するパラメータを算出する、AE/AF処理回路と、をさらに備えてもよく、前記制御回路は、前記AE/AF処理回路の出力に基づいて、前記受光素子の露出及びフォーカスを制御してもよい。 The second board performs AE / AF processing for calculating a signal processing circuit that executes signal processing of the signal output by the analog circuit and parameters for adjusting exposure and focus based on the output of the signal processing circuit. A circuit may be further provided, and the control circuit may control the exposure and focus of the light receiving element based on the output of the AE / AF processing circuit.
　前記制御回路は、前記AE/AF処理回路の出力に基づいて、前記第1読出モード、前記第2読出モード及び前記第3読出モードを切り替えてもよい。 The control circuit may switch between the first read mode, the second read mode, and the third read mode based on the output of the AE / AF processing circuit.
　前記制御回路は、前記AE/AF処理回路の出力に基づいて、露出の制御及びフォーカスの制御が完了するまでは、前記第1読出モード又は前記第2読出モードを選択して制御してもよく、露出の制御及びフォーカスの制御が完了した後に、前記第3読出モードを選択して制御してもよい。 The control circuit may select and control the first read mode or the second read mode until the exposure control and the focus control are completed based on the output of the AE / AF processing circuit. After the exposure control and the focus control are completed, the third read mode may be selected and controlled.
　前記第2基板は、前記アナログ回路が出力した信号の信号処理を実行する、信号処理回路と、前記信号処理回路の出力に基づいて、物体認識処理を実行する、認識処理回路、をさらに備えてもよく、前記制御回路は、前記認識処理回路の出力に基づいて、前記第1読出モード、前記第2読出モード及び前記第3読出モードを切り替えてもよい。 The second board further includes a signal processing circuit that executes signal processing of the signal output by the analog circuit, and a recognition processing circuit that executes object recognition processing based on the output of the signal processing circuit. The control circuit may switch between the first read mode, the second read mode, and the third read mode based on the output of the recognition processing circuit.
　前記制御回路は、前記認識処理回路の出力に基づいて、前記物体が検知されるまでは前記第1読出モード又は前記第2読出モードを選択して制御してもよく、前記物体が検知された後に、前記第3読出モードを選択して制御してもよい。 The control circuit may select and control the first read mode or the second read mode until the object is detected based on the output of the recognition processing circuit, and the object is detected. Later, the third read mode may be selected and controlled.
　前記第1アナログ回路及び前記第2アナログ回路は、前記第2方向に沿った1又は複数の前記行に属する異なる前記画素の前記アナログ信号を、同じタイミングで処理してもよい。 The first analog circuit and the second analog circuit may process the analog signals of the different pixels belonging to the one or a plurality of the rows along the second direction at the same timing.
　前記第1アナログ回路及び前記第2アナログ回路は、前記アナログ信号をデジタル信号へと変換してもよく、前記第2基板は、前記デジタル信号を処理するロジック回路であって、前記第1アナログ回路及び前記第2アナログ回路に挟まれて配置される、ロジック回路、を備えてもよい。 The first analog circuit and the second analog circuit may convert the analog signal into a digital signal, and the second board is a logic circuit for processing the digital signal and is the first analog circuit. And a logic circuit, which is arranged between the second analog circuits.
　前記論理回路は、前記画素分割部と前記第3方向において重なるようにメモリを備えてもよい。 The logic circuit may include a memory so as to overlap the pixel dividing portion in the third direction.
　複数の前記画素分割部と、複数の領域に分割された前記受光素子アレイの領域及びそれぞれに対応する前記アナログ回路と、を備えてもよい。 A plurality of the pixel dividing portions, a region of the light receiving element array divided into a plurality of regions, and an analog circuit corresponding to each region may be provided.
　前記第2基板は、前記デジタル信号の信号処理を実行する、信号処理回路と、画像情報である前記デジタル信号の画像処理を実行する、画像処理回路と、前記デジタル信号、前記信号処理回路が出力したデータ、前記画像処理回路が出力したデータ、のうち任意のデータを格納する、メモリと、前記信号処理回路が出力したデータ、前記画像処理回路が出力したデータ、及び、前記記憶部に格納されているデータのうち、少なくとも１つの任意のデータ若しくは任意の信号を外部へと出力し、又は、外部からデータ若しくは信号の入力を受け付ける、インタフェースと、を備えてもよい。 The second board is output from a signal processing circuit that executes signal processing of the digital signal, an image processing circuit that executes image processing of the digital signal that is image information, the digital signal, and the signal processing circuit. The data is stored in the memory, the data output by the signal processing circuit, the data output by the image processing circuit, and the storage unit for storing arbitrary data among the data output by the image processing circuit. It may be provided with an interface that outputs at least one arbitrary data or an arbitrary signal to the outside, or accepts an input of the data or a signal from the outside.
　一実施形態によれば、電子機器は、上記のいずれかに記載の固体撮像装置を備える。 According to one embodiment, the electronic device includes the solid-state image sensor according to any one of the above.
　電子機器は、スマートフォン、タブレット型端末、デジタルカメラ、又は、デジタルビデオカメラであってもよい。 The electronic device may be a smartphone, a tablet terminal, a digital camera, or a digital video camera.
一実施形態に係る固体撮像装置のブロック図。The block diagram of the solid-state image pickup apparatus which concerns on one Embodiment. 一実施形態に係る固体撮像装置の各要素の配置を模式的に示す図。The figure which shows typically the arrangement of each element of the solid-state image sensor which concerns on one Embodiment. 一実施形態に係る固体撮像装置の基板の積層を模式的に示す図。The figure which shows typically the stacking of the substrate of the solid-state image sensor which concerns on one Embodiment. 一実施形態に係る受光素子の接続を模式的に示す図。The figure which shows typically the connection of the light receiving element which concerns on one Embodiment. 一実施形態に係る受光素子の読み出し順番を示す図。The figure which shows the reading order of the light receiving element which concerns on one Embodiment. 一実施形態に係る受光素子の読み出し順番を示す図。The figure which shows the reading order of the light receiving element which concerns on one Embodiment. 一実施形態に係る受光素子の読み出し順番を示す図。The figure which shows the reading order of the light receiving element which concerns on one Embodiment. 一実施形態に係る受光素子の各読出モードにおけるフォーカルプレーン歪みを模式的に示す図。The figure which shows typically the focal plane distortion in each read mode of the light receiving element which concerns on one Embodiment. 一実施懈怠に係る固体撮像装置の処理を示すフローチャート。(1) A flowchart showing the processing of the solid-state image sensor according to the implementation failure. 一実施形態に係る固体撮像装置のブロック図。The block diagram of the solid-state image pickup apparatus which concerns on one Embodiment. 一実施懈怠に係る固体撮像装置の処理を示すフローチャート。(1) A flowchart showing the processing of the solid-state image sensor according to the implementation failure. 一実施形態に係る固体撮像装置の基板の積層を模式的に示す図。The figure which shows typically the stacking of the substrate of the solid-state image sensor which concerns on one Embodiment. 一実施形態に係る受光素子の接続を模式的に示す図。The figure which shows typically the connection of the light receiving element which concerns on one Embodiment. 一実施形態に係る受光素子の接続を模式的に示す図。The figure which shows typically the connection of the light receiving element which concerns on one Embodiment. 一実施形態に係る積層の様子を模式的に示す図。The figure which shows the state of the stacking which concerns on one Embodiment schematically. 一実施形態に係る積層の様子を模式的に示す図。The figure which shows the state of the stacking which concerns on one Embodiment schematically. 一実施形態に係る積層の様子を模式的に示す図。The figure which shows the state of the stacking which concerns on one Embodiment schematically. 一実施形態に係る積層の様子を模式的に示す図。The figure which shows the state of the stacking which concerns on one Embodiment schematically. 一実施形態に係る積層の様子を模式的に示す図。The figure which shows the state of the stacking which concerns on one Embodiment schematically.
　以下、図面を参照して、いくつかの実施形態に係る固定撮像装置について説明する。なお、図面は、説明のためにわかりやすく示すものであり、図面に示される大きさの比率、大小関係、形状等は、現実の実装とは異なることがあるが、図面に限定されるものではない。 Hereinafter, the fixed imaging apparatus according to some embodiments will be described with reference to the drawings. The drawings are shown in an easy-to-understand manner for the sake of explanation, and the size ratio, size relationship, shape, etc. shown in the drawings may differ from the actual implementation, but are not limited to the drawings. do not have.
　(第1実施形態)
　図1は、一実施形態に係る固体撮像装置1の機能を示すブロック図である。固体撮像装置1は、例えば、第1基板10と、第2基板20と、を備えて構成される。第1基板10は、光学系12と、受光素子14と、を備える。第2基板20は、信号処理回路22と、制御回路24と、AE/AF処理回路26と、を備える。この他、第2基板20は、例えば、上記の回路と外部に備えられる回路等との間でデータを入出力するためのインタフェースを備えていてもよい。 (First Embodiment)
FIG. 1 is a block diagram showing the functions of the solid-state image sensor 1 according to the embodiment. The solid-state image sensor 1 includes, for example, a first substrate 10 and a second substrate 20. The first substrate 10 includes an optical system 12 and a light receiving element 14. The second substrate 20 includes a signal processing circuit 22, a control circuit 24, and an AE / AF processing circuit 26. In addition, the second substrate 20 may include, for example, an interface for inputting / outputting data between the above circuit and an external circuit or the like.
　光学系12は、受光素子14に光を感知するための光路、収差等を補正する系である。光学系12は、例えば、レンズ(仮想的なレンズ等を含む)を備え、適切に受光素子14において光が受光されるように接地される。 The optical system 12 is a system that corrects optical paths, aberrations, etc. for sensing light in the light receiving element 14. The optical system 12 includes, for example, a lens (including a virtual lens or the like), and is grounded so that light is appropriately received by the light receiving element 14.
　受光素子14は、受光した光を光電変換し、アナログ信号を出力する素子を備える。この受光素子14は、例えば、裏面照射型のフォトダイオードを備える。この構成には限られず、受光素子14は、表面照射型の構成であってもよいし、また、フォトダイオードとは異なる素子を備えて構成されてもよい。受光素子14が光電変換により蓄積した電荷は、接続部30を介して第2基板へと送信される。 The light receiving element 14 includes an element that photoelectrically converts the received light and outputs an analog signal. The light receiving element 14 includes, for example, a back-illuminated photodiode. The light receiving element 14 is not limited to this configuration, and may be configured as a surface-illuminated type, or may be configured to include an element different from the photodiode. The electric charge accumulated by the light receiving element 14 by photoelectric conversion is transmitted to the second substrate via the connection portion 30.
　それぞれの受光素子14には、カラーフィルタが備えられてもよい。カラーフィルタは、例えば、ベイヤ配列等により配置されてもよいし、他の配置であってもよい。カラーフィルタを用いる場合には、後述する信号処理回路22等により、カラーマトリクスを用いた処理を実行してもよい。また、色再現をするためには、フィルタを備える構成ではなく、受光素子14として有機光電変換膜を用いてもよい。 Each light receiving element 14 may be provided with a color filter. The color filter may be arranged by, for example, a Bayer arrangement or another arrangement. When a color filter is used, processing using the color matrix may be executed by a signal processing circuit 22 or the like described later. Further, in order to reproduce colors, an organic photoelectric conversion film may be used as the light receiving element 14 instead of the configuration provided with a filter.
　信号処理回路22は、受光素子14が出力する信号を処理する回路である。信号処理回路22は、例えば、ADC(Analog to Digital Converter)を備え、受光素子14が出力するアナログ信号をデジタル信号に変換する。また、ADCの処理に必要となるデジタル信号を生成するDAC(Digital to Analog Converter)、DACから出力された電圧とアナログ信号の電圧とを比較する比較器、比較器からの出力を計数する計数器、計数器からの出力を増幅する増幅器、を備えていてもよい。 The signal processing circuit 22 is a circuit that processes the signal output by the light receiving element 14. The signal processing circuit 22 includes, for example, an ADC (Analog to Digital Converter), and converts an analog signal output by the light receiving element 14 into a digital signal. In addition, a DAC (Digital to Analog Converter) that generates the digital signal required for ADC processing, a comparator that compares the voltage output from the DAC with the voltage of the analog signal, and a counter that counts the output from the comparator. , An amplifier, which amplifies the output from the counter, may be provided.
　信号処理回路22はさらに、このデジタル信号に適切な信号処理、画像処理を実行する回路を備える。信号処理回路は、例えば、受光素子14の出力する信号の補間処理、色調整処理等の画像データを生成する回路を備えていてもよい。画像処理回路は、信号処理回路により生成された画像データについて、種々のフィルタ処理、変形処理等を実行する回路を備えていてもよい。これらの回路は、例えば、デジタル回路により構成されてもよい。 The signal processing circuit 22 further includes a circuit that executes appropriate signal processing and image processing on this digital signal. The signal processing circuit may include, for example, a circuit that generates image data such as interpolation processing and color adjustment processing of the signal output by the light receiving element 14. The image processing circuit may include a circuit that executes various filter processing, deformation processing, and the like on the image data generated by the signal processing circuit. These circuits may be configured by, for example, a digital circuit.
　信号処理回路22は、インタフェースを介して適切に処理された信号を外部へと出力してもよい。信号処理回路22は、制御回路、AE/AF処理回路26へと適切に処理された信号を出力する。また、信号処理回路22は、制御回路24からの要求に基づいて、信号処理に関するパラメータ等が制御されるものであってもよい。 The signal processing circuit 22 may output a signal appropriately processed via the interface to the outside. The signal processing circuit 22 outputs an appropriately processed signal to the control circuit and the AE / AF processing circuit 26. Further, the signal processing circuit 22 may be one in which parameters and the like related to signal processing are controlled based on a request from the control circuit 24.
　制御回路24は、信号処理回路22からの出力及びAE/AF処理回路26からの出力のうち、少なくとも一方に基づいて、光学系12、受光素子14、信号処理回路22及びAE/AF処理回路26のうち少なくとも1つの構成を制御する信号を生成し、出力する。制御回路24は、例えば、露出タイミング、露出時間、画素の読出順番等の制御をする。制御回路24の詳細な動作については、後述する。 The control circuit 24 has an optical system 12, a light receiving element 14, a signal processing circuit 22, and an AE / AF processing circuit 26 based on at least one of the output from the signal processing circuit 22 and the output from the AE / AF processing circuit 26. Generates and outputs a signal that controls at least one of these configurations. The control circuit 24 controls, for example, the exposure timing, the exposure time, the pixel reading order, and the like. The detailed operation of the control circuit 24 will be described later.
　AE/AF処理回路26は、信号処理回路22が出力した画像データに基づいて、AE(Auto Exposure)と、AF(Auto Focus)との処理をする信号を出力する。このAE/AF処理回路26の詳細な処理についても、制御回路24の処理とともに後述する。 The AE / AF processing circuit 26 outputs a signal for processing between AE (Auto Exposure) and AF (Auto Focus) based on the image data output by the signal processing circuit 22. The detailed processing of the AE / AF processing circuit 26 will be described later together with the processing of the control circuit 24.
　接続部30は、第1基板10と、第2基板20とを接続する。この接続部30は、例えば、受光素子14と、信号処理回路22と、を接続し、受光素子14が出力するアナログ信号を信号処理回路22へと伝達する。接続部30は、例えば、第1基板10における受光素子14の出力部であるメタル電極と、第2基板20における信号処理回路22への入力部であるメタル電極と、を直接接続する。このメタル電極は、例えばCu電極である。また、接続部30は、制御回路24と、光学系12、受光素子14とを接続する経路を有していてもよい。 The connection unit 30 connects the first board 10 and the second board 20. The connection unit 30 connects, for example, the light receiving element 14 and the signal processing circuit 22, and transmits the analog signal output by the light receiving element 14 to the signal processing circuit 22. The connection unit 30 directly connects, for example, a metal electrode that is an output unit of the light receiving element 14 on the first substrate 10 and a metal electrode that is an input unit to the signal processing circuit 22 on the second substrate 20. This metal electrode is, for example, a Cu electrode. Further, the connection unit 30 may have a path for connecting the control circuit 24, the optical system 12, and the light receiving element 14.
　以上は、本実施形態に係るアナログ信号及びデジタル信号の伝播についての経路に関する構成を記載したものである。このため、その他の制御に必要な構成は、省略している。第1基板10には、例えば、どの受光素子14からの出力を受け付けるかといった配線等が適切に備えられる。また、第2基板20には、固体撮像装置1の各構成の制御を担う回路等が適切に備えられる。 The above describes the configuration regarding the path for the propagation of the analog signal and the digital signal according to the present embodiment. Therefore, other configurations required for control are omitted. The first substrate 10 is appropriately provided with wiring and the like, for example, from which light receiving element 14 the output is received. Further, the second substrate 20 is appropriately provided with a circuit or the like that controls each configuration of the solid-state image sensor 1.
　このように、固体撮像装置1が適切に動作するための構成要素、配線等は、図示しないものを含めて適切に備えられている。 As described above, the components, wiring, etc. for the solid-state image sensor 1 to operate properly are appropriately provided, including those not shown.
　図2は、本実施形態に係る受光素子14及び信号処理回路22、制御回路24、AE/AF処理回路26等を示すアナログ回路と論理回路の配置の一例を示す図である。 FIG. 2 is a diagram showing an example of arrangement of an analog circuit and a logic circuit showing a light receiving element 14, a signal processing circuit 22, a control circuit 24, an AE / AF processing circuit 26, etc. according to the present embodiment.
　第1基板10において、受光素子14は、2次元にアレイ状に配置される。受光素子14は、例えば、第1方向及び第2方向に沿ってアレイ状に配置され、受光素子アレイ140を形成する。それぞれの受光素子14は、例えば、光学系12としてレンズを介して受光し、受光した光の強度等に基づいてアナログ信号を出力するフォトダイオード（PD：Photo Diode）等を備える。 In the first substrate 10, the light receiving elements 14 are arranged in a two-dimensional array. The light receiving element 14 is arranged in an array along the first direction and the second direction, for example, to form the light receiving element array 140. Each light receiving element 14 includes, for example, a photodiode (PD: Photo Diode) or the like as an optical system 12 that receives light through a lens and outputs an analog signal based on the intensity of the received light.
　説明において、第2方向に連続した画素を行と呼び、第1方向に連続した画素を列と呼ぶことがある。すなわち、第2方向に連続した受光素子14の群である行が第1方向に複数備えられることにより受光素子アレイ140を形成する。換言すると、第1方向に連続した受光素子14の群である列が第2方向に複数備えられることにより受光素子アレイ140を形成する。 In the description, pixels that are continuous in the second direction may be called rows, and pixels that are continuous in the first direction may be called columns. That is, the light receiving element array 140 is formed by providing a plurality of rows, which are a group of light receiving elements 14 continuous in the second direction, in the first direction. In other words, the light receiving element array 140 is formed by providing a plurality of rows, which are a group of light receiving elements 14 continuous in the first direction, in the second direction.
　受光素子アレイ140は、第1領域141と、第2領域142と、を備える。第1領域141と、第2領域142と、は、画素分割部143により分割される。画素分割部143は、例えば、受光素子アレイ140を第2方向に沿って横切るように第1方向において中央付近に備えられる。 The light receiving element array 140 includes a first region 141 and a second region 142. The first region 141 and the second region 142 are divided by the pixel dividing unit 143. The pixel dividing unit 143 is provided near the center in the first direction so as to cross the light receiving element array 140 along the second direction, for example.
　中央付近とは、例えば、受光素子アレイ140において、第1方向に沿ってn個の受光素子14が備えられる場合に、[n / 2]個目に該当する画素と、[n / 2] + 1個目に該当する画素と、の間に備えられる。ここで、[・]は、床関数である。 The term "near the center" means, for example, in the light receiving element array 140, when n light receiving elements 14 are provided along the first direction, the pixel corresponding to the [n / 2] th pixel and [n / 2] + It is provided between the first pixel and the corresponding pixel. Here, [・] is a floor function.
　なお、これには限られず、正確に中央では無く、図2において受光素子アレイ140の上下いずれかの辺に有意に、又は、有意にではなく偏っていてもよいが、本明細書においては、これらの状態をまとめて、広義の意味で中央付近と記載する。 It should be noted that the present invention is not limited to this, and may be not exactly in the center and may be significantly or not significantly biased to either the upper or lower side of the light receiving element array 140 in FIG. 2, but in the present specification, it may be biased. These states are collectively described as near the center in a broad sense.
　受光素子アレイ140に隣接するように、第1基板10には接続部30が接続される。この接続部30を介して、第1基板10と、第2基板20と、が相互に接続される。図2においては、接続部30と、それぞれの受光素子14、及び、第2基板20における各回路との接続は示されていないが、適切に金属といった伝導体による配線が配置される。このように、本実施形態においては、第1基板10と第2基板20との間において、受光素子14の下に接続部30が備えられない構成とすることができる。 The connection portion 30 is connected to the first substrate 10 so as to be adjacent to the light receiving element array 140. The first substrate 10 and the second substrate 20 are connected to each other via the connection portion 30. In FIG. 2, the connection between the connection portion 30, the respective light receiving element 14, and each circuit on the second substrate 20 is not shown, but wiring by a conductor such as metal is appropriately arranged. As described above, in the present embodiment, the connection portion 30 may not be provided under the light receiving element 14 between the first substrate 10 and the second substrate 20.
　接続部30は、図2に示すように、例えば、それぞれの領域(第1領域141、第2領域142)に属する受光素子14において、列ごとに備えられる。また、第2基板20上の回路からの制御信号等を第1基板10上へと伝播するために、行ごとに備えられてもよい。この第2基板20から第1基板10へと接続する接続部30は、図2に示すように、行ごとに備えられる必要はなく、光学系12及び受光素子14に対する処理を適切に実現できるのであれば、さらに多くの個数が備えられてもよいし、より少ない個数が備えられてもよい。 As shown in FIG. 2, the connection portion 30 is provided for each row in the light receiving element 14 belonging to each region (first region 141, second region 142), for example. Further, in order to propagate the control signal or the like from the circuit on the second substrate 20 onto the first substrate 10, it may be provided for each row. As shown in FIG. 2, the connection portion 30 connecting the second substrate 20 to the first substrate 10 does not need to be provided for each row, and the processing for the optical system 12 and the light receiving element 14 can be appropriately realized. If so, a larger number may be provided, or a smaller number may be provided.
　第2基板20は、上述の信号処理回路22、制御回路24、AE/AF処理回路26を構成するアナログ回路200と、ロジック回路210を備える。破線は、第1基板10に受光素子アレイ140が備えられる範囲を積層された状態において第2基板20に投影する領域である。 The second board 20 includes an analog circuit 200 constituting the above-mentioned signal processing circuit 22, a control circuit 24, and an AE / AF processing circuit 26, and a logic circuit 210. The broken line is a region to be projected onto the second substrate 20 in a state where the range provided with the light receiving element array 140 is laminated on the first substrate 10.
　第2基板20において、アナログ回路200は、例えば、受光素子アレイ140が積層状態において対応する第1基板10上に存在する領域の両端に備えられる。アナログ回路200は、このように、受光素子アレイ140が備えられる範囲の両端付近に備えられる。 In the second substrate 20, the analog circuit 200 is provided at both ends of the region where the light receiving element array 140 exists on the corresponding first substrate 10 in the laminated state, for example. The analog circuit 200 is thus provided near both ends of the range in which the light receiving element array 140 is provided.
　アナログ回路200は、第1アナログ回路201と、第2アナログ回路202と、を備える。この第1アナログ回路201と、第2アナログ回路202と、は、それぞれが接続部30と隣接するように備えられ、接続部30を介して受光素子14から出力されたアナログ信号を受信しやすいように配置される。 The analog circuit 200 includes a first analog circuit 201 and a second analog circuit 202. The first analog circuit 201 and the second analog circuit 202 are provided so as to be adjacent to the connection portion 30, so that the analog signal output from the light receiving element 14 via the connection portion 30 can be easily received. Is placed in.
　第1アナログ回路201と、第2アナログ回路202は、それぞれがアナログ回路として動作する。第1アナログ回路201は、接続部30を介して第1領域141に属する受光素子14からのアナログ信号を取得し、第1領域141に属するそれぞれの受光素子14の受光強度に基づいたデジタル信号を生成する。 The first analog circuit 201 and the second analog circuit 202 each operate as an analog circuit. The first analog circuit 201 acquires an analog signal from the light receiving element 14 belonging to the first region 141 via the connection portion 30, and outputs a digital signal based on the light receiving intensity of each light receiving element 14 belonging to the first region 141. Generate.
　同様に、第2アナログ回路202は、接続部30を介して第2領域142に属する受光素子14からのアナログ信号を取得し、第2領域142に属するそれぞれの受光素子14の受光強度に基づいたデジタル信号を生成する。このように、アナログ回路200は、例えば、受光素子14が出力するアナログ信号を画素ごとのデジタル信号へと変換して出力する。 Similarly, the second analog circuit 202 acquires an analog signal from the light receiving element 14 belonging to the second region 142 via the connection portion 30, and is based on the light receiving intensity of each light receiving element 14 belonging to the second region 142. Generate a digital signal. In this way, the analog circuit 200 converts, for example, the analog signal output by the light receiving element 14 into a digital signal for each pixel and outputs the analog signal.
　第1アナログ回路201と、第2アナログ回路202とは、例えば、排他的に動作する。第1アナログ回路201と、第2アナログ回路202とが変換したデジタル信号は、ロジック回路210へと出力される。 The first analog circuit 201 and the second analog circuit 202 operate exclusively, for example. The digital signal converted by the first analog circuit 201 and the second analog circuit 202 is output to the logic circuit 210.
　ロジック回路210は、例えば、画素ごとのデジタル信号により構成される画像データに対して、適切な信号処理及び画像処理を実行する。すなわち、図1における信号処理回路22は、例えば、このアナログ回路200とロジック回路210とに亘り構成される種々の回路の集合のことであってもよい。 The logic circuit 210 executes appropriate signal processing and image processing on image data composed of digital signals for each pixel, for example. That is, the signal processing circuit 22 in FIG. 1 may be, for example, a set of various circuits configured over the analog circuit 200 and the logic circuit 210.
　ロジック回路210は、さらに、画像処理された画像データに基づいて制御信号を生成する制御回路24、及び、画像データと制御信号とに基づいてAE/AF処理を実行する、AE/AF処理回路26とを備えて構成される。 The logic circuit 210 further includes a control circuit 24 that generates a control signal based on the image processed image data, and an AE / AF processing circuit 26 that executes AE / AF processing based on the image data and the control signal. It is configured with and.
　ロジック回路210に備えられる制御回路24から出力された制御信号は、ロジック回路210に隣接して配置される接続部30を介して第1基板10へと伝播される。また、上述したように、図示しない適切な配線、インタフェースが第2基板20に備えられてもよい。 The control signal output from the control circuit 24 provided in the logic circuit 210 is propagated to the first board 10 via the connection portion 30 arranged adjacent to the logic circuit 210. Further, as described above, the second substrate 20 may be provided with appropriate wiring and an interface (not shown).
　このように、2つに分割して配置されるアナログ回路200に対し、ロジック回路210は、アナログ回路200に挟まれるように、1つの領域として構成することができる。ロジック回路210をアナログ回路200の間に配置することにより、第1基板10のそれぞれの領域に属する受光素子14から出力された信号を処理するタイミングの制御が容易になる。特に、第1領域141と第2領域142に属する受光素子14の出力を同じタイミングで処理する場合に、同期をとりやすい構成とすることができる。また、半導体基板におけるレイアウトの効率を向上させるという効果もある。 In this way, the logic circuit 210 can be configured as one area so as to be sandwiched between the analog circuits 200, as opposed to the analog circuit 200 which is divided into two and arranged. By arranging the logic circuit 210 between the analog circuits 200, it becomes easy to control the timing of processing the signal output from the light receiving element 14 belonging to each region of the first substrate 10. In particular, when the outputs of the light receiving elements 14 belonging to the first region 141 and the second region 142 are processed at the same timing, the configuration can be easily synchronized. It also has the effect of improving the layout efficiency of the semiconductor substrate.
　ロジック回路210内には、例えば、点線部を挟むようにSRAM(Static Random Access Memory)等のメモリが備えられてもよい。すなわち、SRAMを1領域にまとめて備える構成とすることも可能である。 For example, a memory such as SRAM (Static Random Access Memory) may be provided in the logic circuit 210 so as to sandwich the dotted line portion. That is, it is also possible to have a configuration in which SRAM is collectively provided in one area.
　SRAM等のメモリを1領域にまとめることにより、メモリへの書込、又は、メモリからの読出の処理タイミング等の制御を、この領域が2以上に分割されている場合よりも容易に実行することができる。 By consolidating the memory such as SRAM into one area, it is easier to control the processing timing of writing to the memory or reading from the memory than when this area is divided into two or more. Can be done.
　図3は、第1基板10と第2基板20とが積層された状態において、受光素子アレイ140とアナログ回路200、ロジック回路210との位置を模式的に示す図である。この図3に示すように、受光素子アレイ140と、アナログ回路200と、は、受光素子アレイ140の第1方向の両端付近において重なるように積層される。 FIG. 3 is a diagram schematically showing the positions of the light receiving element array 140, the analog circuit 200, and the logic circuit 210 in a state where the first board 10 and the second board 20 are stacked. As shown in FIG. 3, the light receiving element array 140 and the analog circuit 200 are laminated so as to overlap each other near both ends of the light receiving element array 140 in the first direction.
　接続部30は、この受光素子アレイ140の周辺部において、受光素子14と、アナログ回路200と、を第3方向に沿って接続するように配置される。また、同様に、受光素子アレイ140の周辺部において、ロジック回路210と、受光素子14と、を第3方向に沿って接続するように配置される。画素分割部１４３の周辺と、回路分割部２２３の周辺とを接続するように配置される。 The connection portion 30 is arranged so as to connect the light receiving element 14 and the analog circuit 200 along the third direction in the peripheral portion of the light receiving element array 140. Similarly, in the peripheral portion of the light receiving element array 140, the logic circuit 210 and the light receiving element 14 are arranged so as to be connected along the third direction. It is arranged so as to connect the periphery of the pixel dividing portion 143 and the periphery of the circuit dividing portion 223.
　第1アナログ回路201と第2アナログ回路202は、接続部30により接続された受光素子14からのアナログ信号を受信し、適切な処理を実行する。後述するように、例えば、第1アナログ回路201と第2アナログ回路202の第１方向において挟まれるように、ロジック回路210(デジタル回路)が備えられる。 The first analog circuit 201 and the second analog circuit 202 receive the analog signal from the light receiving element 14 connected by the connection unit 30, and execute appropriate processing. As will be described later, for example, a logic circuit 210 (digital circuit) is provided so as to be sandwiched between the first analog circuit 201 and the second analog circuit 202 in the first direction.
　次に、受光素子14と、アナログ回路200との接続について詳しく説明する。 Next, the connection between the light receiving element 14 and the analog circuit 200 will be described in detail.
　図4は、本実施形態に係る受光素子アレイ140における配線の一例を示す図である。この図4における配線を介して、第1基板10に備えられる受光素子14が出力するアナログ信号が第2基板20に備えられるアナログ回路200へと伝達される。なお、この図４においては、画素分割部143の上下において他の画素よりも間隔が広く描かれているが、これは、説明のためであり、実際には、他の画素間と同等の間隔を有していていてもよい。 FIG. 4 is a diagram showing an example of wiring in the light receiving element array 140 according to the present embodiment. Through the wiring in FIG. 4, the analog signal output by the light receiving element 14 provided on the first substrate 10 is transmitted to the analog circuit 200 provided on the second substrate 20. In FIG. 4, the spacing is drawn wider than the other pixels above and below the pixel dividing portion 143, but this is for the sake of explanation, and in reality, the spacing is equivalent to that between the other pixels. May have.
　第1基板10において、受光素子アレイ140には、複数の第1信号線16と、複数の第2信号線181、182と、が備えられる。同じ列に係る第2信号線181、182は、画素分割部143の周辺において、電気的に切断される。すなわち、第1領域141に属する受光素子14と接続される第2信号線181と、第2領域142に属する受光素子14に接続される第2信号線182は、第1基板10においては電気的に接続されない。 In the first substrate 10, the light receiving element array 140 is provided with a plurality of first signal lines 16 and a plurality of second signal lines 181, 182. The second signal lines 181, 182 related to the same row are electrically cut off around the pixel dividing portion 143. That is, the second signal line 181 connected to the light receiving element 14 belonging to the first region 141 and the second signal line 182 connected to the light receiving element 14 belonging to the second region 142 are electrically connected to the first substrate 10. Not connected to.
　また、受光素子アレイ140の第1方向における端部の周辺において、接続部30として、複数の第1接続部301と、第2接続部302と、が備えられ、受光素子14は、第2信号線181、182と、これらの接続部を介して第2基板20のアナログ回路200と接続される。より具体的には、第1領域141に属する受光素子14は、第2信号線181と第1接続部301を介して第1アナログ回路201へと接続され、第2領域142に属する受光素子14は、第2信号線182と第2接続部302を介して第2アナログ回路202へと接続される。 Further, around the end portion in the first direction of the light receiving element array 140, a plurality of first connecting parts 301 and a second connecting part 302 are provided as connecting parts 30, and the light receiving element 14 is a second signal. The lines 181, 182 are connected to the analog circuit 200 of the second substrate 20 via these connections. More specifically, the light receiving element 14 belonging to the first region 141 is connected to the first analog circuit 201 via the second signal line 181 and the first connecting portion 301, and the light receiving element 14 belonging to the second region 142 is connected. Is connected to the second analog circuit 202 via the second signal line 182 and the second connection portion 302.
　第1信号線16は、受光素子アレイ140のうちいずれの行における受光素子14から出力されたアナログ信号を処理するかを選択する配線である。第1信号線16は、例えば、受光素子14と接続される領域外において行選択回路と接続され、この行選択回路からの信号により、アナログ回路200へとアナログ信号を出力する行を選択する。このため、第2方向に沿った第1信号線16は、第2方向において少なくとも行数分だけ配置される。 The first signal line 16 is a wiring for selecting which line of the light receiving element array 140 to process the analog signal output from the light receiving element 14. The first signal line 16 is connected to a row selection circuit outside the region connected to the light receiving element 14, for example, and a line for outputting an analog signal to the analog circuit 200 is selected by the signal from the row selection circuit. Therefore, the first signal line 16 along the second direction is arranged by at least the number of lines in the second direction.
　第1信号線16により選択された行単位の受光素子14は、それぞれに対応する第2信号線181、182を介して第1接続部301又は第2接続部302へと伝達される。第1方向に沿った第2信号線181、182は、それぞれの列に対して少なくとも1つずつ、すなわち、第1方向において少なくとも列数分配置される。同様に、第1接続部301及び第2接続部302は、それぞれ、第2方向に沿って、少なくとも列数分備えられる。そして、第1接続部301、第2接続部302は、受光素子14から出力されたアナログ信号を第1アナログ回路201、第2アナログ回路202へとそれぞれ出力し、アナログ信号の処理が実行される。 The line-based light receiving element 14 selected by the first signal line 16 is transmitted to the first connection portion 301 or the second connection portion 302 via the corresponding second signal lines 181, 182. The second signal lines 181, 182 along the first direction are arranged at least one for each row, that is, at least as many as the number of rows in the first direction. Similarly, the first connection portion 301 and the second connection portion 302 are provided along the second direction for at least the number of columns, respectively. Then, the first connection unit 301 and the second connection unit 302 output the analog signal output from the light receiving element 14 to the first analog circuit 201 and the second analog circuit 202, respectively, and the analog signal processing is executed. ..
　受光素子アレイ140において、受光素子14から出力されたアナログ信号の処理、すなわち、受光素子14の読出順番は、例えば、3通りの読出モードを切り替えて実行される。以下、3通りの読出順番について説明する。 In the light receiving element array 140, the processing of the analog signal output from the light receiving element 14, that is, the reading order of the light receiving element 14, is executed by switching, for example, three reading modes. The three reading orders will be described below.
　[第1読出モード]
　図5は、第1読出モードについて示す図である。第1読出モードは、受光素子アレイ140において、受光素子14の第1方向の双方の端部から順番に画素分割部143方向へと向かうように行ごとに読み出しが実行される。これらの上下からの読み出しは、それぞれ並行して実行される。 [1st read mode]
FIG. 5 is a diagram showing the first read mode. In the first read mode, in the light receiving element array 140, reading is executed line by line so as to sequentially move from both ends of the light receiving element 14 in the first direction toward the pixel dividing portion 143. These reads from above and below are executed in parallel.
　まず、一番下の行及び一番上の行に属する受光素子14について処理が実行される。これらの処理が終了すると、それぞれ、下から2行目及び上から2行目に属する受光素子14について処理が実行される。この処理は、画素分割部143に到達するまで繰り返される。 First, processing is executed for the light receiving element 14 belonging to the bottom row and the top row. When these processes are completed, the processes are executed for the light receiving element 14 belonging to the second line from the bottom and the second line from the top, respectively. This process is repeated until the pixel division unit 143 is reached.
　この場合、第2基板20において、第1アナログ回路201と、第2アナログ回路202は、それぞれ第1領域141に属する受光素子14、第2領域142に属する受光素子14についてのアナログ信号を並行してデジタル信号へと変換してもよい。すなわち、第1アナログ回路201と第2アナログ回路202は、同じタイミングでそれぞれに対応する領域に属する受光素子14から出力されたアナログ信号をデジタル信号へと変換する。 In this case, in the second substrate 20, the first analog circuit 201 and the second analog circuit 202 parallel the analog signals of the light receiving element 14 belonging to the first region 141 and the light receiving element 14 belonging to the second region 142, respectively. May be converted into a digital signal. That is, the first analog circuit 201 and the second analog circuit 202 convert the analog signal output from the light receiving element 14 belonging to the corresponding region at the same timing into a digital signal.
　[第2読出モード]
　図6は、第2読出モードについて示す図である。第2読出モードは、受光素子アレイ140において、受光素子14の第1方向において画素分割部143に隣接する画素からそれぞれの端部へと向かう方向に行ごとに読み出しが実行される。これらの中央周辺から上下への読出は、それぞれ並行して実行される。 [Second read mode]
FIG. 6 is a diagram showing the second read mode. In the second read mode, in the light receiving element array 140, reading is executed row by row in the direction from the pixel adjacent to the pixel dividing portion 143 in the first direction of the light receiving element 14 toward the respective end portions. These readings from the center periphery to the top and bottom are performed in parallel.
　まず、画素分割部143の第1方向下方にある行及び第1方向情報にある行に属する受光素子14について処理が実行される。これらの処理が終了すると、それぞれ画素分割部143から2行目に属する受光素子14についての処理が実行される。この処理は、受光素子アレイ140の第1方向端部にある受光素子14に到達するまで繰り返される。 First, processing is executed for the light receiving element 14 belonging to the row below the first direction of the pixel dividing unit 143 and the row in the first direction information. When these processes are completed, the processes for the light receiving element 14 belonging to the second line from the pixel dividing unit 143 are executed. This process is repeated until the light receiving element 14 at the first-direction end of the light receiving element array 140 is reached.
　この場合、上記と同様に、第2基板20において、第1アナログ回路201と、第2アナログ回路202は、それぞれ第1領域141に属する受光素子14、第2領域142に属する受光素子14についてのアナログ信号を並行してデジタル信号へと変換してもよい。すなわち、第1アナログ回路201と第2アナログ回路202は、同じタイミングでそれぞれに対応する領域に属する受光素子14から出力されたアナログ信号をデジタル信号へと変換する。 In this case, similarly to the above, in the second substrate 20, the first analog circuit 201 and the second analog circuit 202 relate to the light receiving element 14 belonging to the first region 141 and the light receiving element 14 belonging to the second region 142, respectively. Analog signals may be converted into digital signals in parallel. That is, the first analog circuit 201 and the second analog circuit 202 convert the analog signal output from the light receiving element 14 belonging to the corresponding region at the same timing into a digital signal.
　[第3読出モード]
　図7は、第3読出モードについて示す図である。第3読出モードは、受光素子アレイ140において、受光素子14の第1方向における一方の端部の行に属する受光素子14から他方の行に属する受光素子14へと順番に読み出しが実行される。 [Third read mode]
FIG. 7 is a diagram showing a third read mode. In the third read mode, in the light receiving element array 140, reading is sequentially executed from the light receiving element 14 belonging to the row at one end of the light receiving element 14 to the light receiving element 14 belonging to the other row.
　例えば、最初に、図7における一番下1行に属する受光素子14について処理が実行される。それぞれの受光素子14から出力されたアナログ信号は、第1アナログ回路201において、並列して信号処理が実行される。次に、1つ上の行、すなわち、下から2行目について、同様に処理が実行される。この処理は、例えば、行方向の同期信号により、行選択回路から下から順番に行が選択されることにより実行される。 For example, first, the process is executed for the light receiving element 14 belonging to the bottom row in FIG. 7. The analog signals output from the respective light receiving elements 14 are subjected to signal processing in parallel in the first analog circuit 201. Next, the processing is executed in the same manner for the line above, that is, the second line from the bottom. This process is executed, for example, by selecting rows in order from the bottom from the row selection circuit by a synchronization signal in the row direction.
　画素分割部143をまたぐ2行についても同様であり、図7において画素分割部143のすぐ下にある行の処理が終了すると、画素分割部143のすぐ上にある行の処理が実行される。この場合、第1領域141に属する受光素子14は、第2信号線181及び第1接続部301を介して第1アナログ回路201へと信号が伝達されるのに対し、第2領域142に属する受光素子14は、第2信号線182及び第2接続部302を介して第2アナログ回路202へと信号が伝達される。この後も、行方向の同期信号に基づいて、第2領域142の下側から上側へと走査が逐次的に実行される。 The same applies to the two lines that straddle the pixel dividing unit 143, and when the processing of the line immediately below the pixel dividing unit 143 is completed in FIG. 7, the processing of the line immediately above the pixel dividing unit 143 is executed. In this case, the light receiving element 14 belonging to the first region 141 belongs to the second region 142 while the signal is transmitted to the first analog circuit 201 via the second signal line 181 and the first connection portion 301. The light receiving element 14 transmits a signal to the second analog circuit 202 via the second signal line 182 and the second connection portion 302. After this, the scan is sequentially executed from the lower side to the upper side of the second region 142 based on the synchronization signal in the row direction.
　この場合、第2基板20において、第1アナログ回路201と、第2アナログ回路202は、それぞれ第1領域141に属する受光素子14、第2領域142に属する受光素子14についてのアナログ信号をシーケンシャルにデジタル信号へと変換する。すなわち、この場合、第1アナログ回路201と、第2アナログ回路202とは、画素分割部143をまたぐ行の処理の瞬間を除き、排他的に信号の変換を実行する構成とすることができる。 In this case, in the second substrate 20, the first analog circuit 201 and the second analog circuit 202 sequentially transmit analog signals about the light receiving element 14 belonging to the first region 141 and the light receiving element 14 belonging to the second region 142, respectively. Convert to a digital signal. That is, in this case, the first analog circuit 201 and the second analog circuit 202 can be configured to exclusively execute signal conversion except for the moment of processing a row straddling the pixel dividing unit 143.
　このため、第1アナログ回路201と、第2アナログ回路202は、画素分割部143をまたぐタイミングを除き、排他的に電源供給を停止してもよい。ロジック回路210についても同様であり、第1アナログ回路201からの信号と、第2アナログ回路202からの信号を処理している回路が異なる回路である場合には、使用しない回路については、排他的に電源供給を停止してもよい。このように電源供給を停止することにより、電力消費の削減を実現できる。 Therefore, the first analog circuit 201 and the second analog circuit 202 may exclusively stop the power supply except for the timing of straddling the pixel division unit 143. The same applies to the logic circuit 210, and if the circuit processing the signal from the first analog circuit 201 and the signal from the second analog circuit 202 are different circuits, the circuits not used are exclusive. The power supply may be stopped. By stopping the power supply in this way, it is possible to reduce power consumption.
　上記のいずれの読み出し方法も、画素分割部143の上下の受光素子14からの信号を読み出しのタイミングが略一致する。このため、画像、映像の中央部で歪みの状態が大きく変化することなく、違和感の少ない画像データを生成することが可能となる。また、以上の読み出し方法は、当該読み出し方法により常時読み出してもよいし、ユーザがモードを切り替えてもよいし、又は、自動的に読み出し方法を切り替えてもよい。 In any of the above reading methods, the timing of reading the signals from the light receiving elements 14 above and below the pixel dividing unit 143 is substantially the same. Therefore, it is possible to generate image data with less discomfort without significantly changing the state of distortion in the central portion of the image or video. Further, the above reading method may be constantly read by the reading method, the user may switch the mode, or the reading method may be automatically switched.
　行選択は、例えば、行選択回路が選択する行に対応する第1信号線16に同期信号に基づいて選択信号を印加することにより実行される。この選択信号により、選択された行に属する受光素子14の信号出力部と、第2信号線181、182の通電状態を制御することにより、アナログ信号を適切なアナログ回路200へと出力する。通電状態の制御は、例えば、ゲートが第1信号線16に接続され、ドレイン、ソース(或いは、ソース、ドレイン)がそれぞれ受光素子14と第2信号線181、182とに接続されるMOSFET(Metal-Oxide-Semiconductor Field-Effect-Transistor)により実行される。これには限られず、他の手法により、第1信号線16を介した信号により駆動されるスイッチ等により通電状態が形成されてもよい。 The row selection is executed, for example, by applying a selection signal to the first signal line 16 corresponding to the row selected by the row selection circuit based on the synchronization signal. By controlling the signal output unit of the light receiving element 14 belonging to the selected line and the energized state of the second signal lines 181, 182 by this selection signal, an analog signal is output to an appropriate analog circuit 200. To control the energized state, for example, a MOSFET (Metal) in which the gate is connected to the first signal line 16 and the drain and source (or source and drain) are connected to the light receiving element 14 and the second signal lines 181, 182, respectively. -Oxide-Semiconductor Field-Effect-Transistor). The present invention is not limited to this, and an energized state may be formed by a switch or the like driven by a signal via the first signal line 16 by another method.
　以上のように、第1基板10に備えられる受光素子アレイ140の領域を中央付近で分割し、積層される第2基板20において重なるように第1方向の両端部にアナログ回路200を配置することにより、第2信号線181、182における受光素子14から出力された信号の伝達経路を短くすることが可能となる。本実施形態による接続部30の配置によれば、従来の接続部30の配置を大きく変えることなく回路をチップ上に容易に実装することが可能である。 As described above, the region of the light receiving element array 140 provided in the first substrate 10 is divided near the center, and the analog circuits 200 are arranged at both ends in the first direction so as to overlap each other in the stacked second substrate 20. This makes it possible to shorten the transmission path of the signal output from the light receiving element 14 in the second signal lines 181, 182. According to the arrangement of the connection portion 30 according to the present embodiment, it is possible to easily mount the circuit on the chip without significantly changing the arrangement of the conventional connection portion 30.
　伝達経路を短くすることから、第2信号線181、182の負荷容量を下げることが可能となる。この結果、固体撮像装置1として、アナログ信号処理の低電力化及び高フレームレート化を実現することができる。この高速化及び受光素子アレイ140全体にわたって連続的に行を処理することにより、フィールドプレート歪みもまた、抑制することが可能となる。 By shortening the transmission path, it is possible to reduce the load capacity of the second signal lines 181, 182. As a result, as the solid-state image sensor 1, it is possible to realize low power consumption and high frame rate of analog signal processing. By processing the rows continuously over this speedup and the light receiving element array 140, field plate distortion can also be suppressed.
　また、ロジック回路210を第2基板20の一領域にまとめて配置することが可能であるので、集中的な電源、接地配線による電源品質の均一化を図ることができる。同様に、ロジック回路210を一領域に形成できるため、制御信号生成の集中配置を実現でき、これに伴い、制御信号配線の等長化、及び、最短化をも実現できる。これは、制御信号に係る配線だけではなく、読み出し信号の配線についても同様である。 Further, since the logic circuit 210 can be collectively arranged in one area of the second board 20, it is possible to make the power supply quality uniform by centralized power supply and ground wiring. Similarly, since the logic circuit 210 can be formed in one area, it is possible to realize a centralized arrangement of control signal generation, and accordingly, it is possible to realize equal length and shortest control signal wiring. This applies not only to the wiring related to the control signal but also to the wiring of the read signal.
　上記に挙げた3つの読み出し方法を自動的に切り替える例について、以下説明する。例えば、デジタルカメラ等においては、撮影する前に撮影対象に関する撮像信号に基づいて露出調整をしたり、オートフォーカスをしたり、また、ディスプレイに表示させて確認することが可能である。このような撮影前の状態においては、フレームレートを高めることが、歪みの発生を高精度に補正することよりも望まれる。 An example of automatically switching between the above three reading methods will be described below. For example, in a digital camera or the like, it is possible to adjust the exposure based on an image pickup signal related to a shooting target, perform autofocus, or display the image on a display for confirmation before shooting. In such a state before shooting, it is more desirable to increase the frame rate than to correct the occurrence of distortion with high accuracy.
　そこで、このような撮影前のAE、AF制御においては、より高フレームレートである第1読出順番又は第2読出順番を用い、高精度な画像の取得が必要となる撮影時等、また、静止物を撮影する場合等には、フレームレートを高く維持しつつもフォーカルプレーン歪みをより抑制する第3読出順番により読み出しを実行する。 Therefore, in such AE and AF control before shooting, the first reading order or the second reading order, which has a higher frame rate, is used, and when shooting, etc., where it is necessary to acquire a highly accurate image, and still. When shooting an object, the reading is performed in the third reading order in which the focal plane distortion is further suppressed while maintaining a high frame rate.
　図8は、上記に説明したそれぞれのモードにおけるフォーカルプレーン歪みを模式的に示す図である。左図は、第1読出モード、真ん中の図は、第2読出モード、右図は、第3読出モードにそれぞれ対応するフォーカルプレーン歪みを示す。この図8では、例えば、右側に移動している第1方向において受光素子14の全ての領域をカバーする矩形状の物体を撮像した様子を示す。点線は、取得された画像における画素分割部143を示す線分である。 FIG. 8 is a diagram schematically showing the focal plane distortion in each mode described above. The left figure shows the first read mode, the middle figure shows the second read mode, and the right figure shows the focal plane distortion corresponding to the third read mode. FIG. 8 shows, for example, an image of a rectangular object covering the entire region of the light receiving element 14 in the first direction moving to the right. The dotted line is a line segment indicating the pixel division portion 143 in the acquired image.
　図に示すように、第1読出モードにおいては、矩形の物体は、中央付近である画素分割部143に近づくにしたがって、タイミングが遅れて撮像される。このため、画素分割部143に近づくにつれて物体が右に歪む。 As shown in the figure, in the first read mode, the rectangular object is imaged with a delay in timing as it approaches the pixel dividing portion 143 near the center. Therefore, the object is distorted to the right as it approaches the pixel dividing portion 143.
　第2読出モードにおいては、第1読出モードとは逆に、矩形の物体は、第1方向の端部に近づくにしたがって、タイミングが遅れて撮像される。このため、画素分割部143から端部(上下)へと近づくにつれて物体が右に歪む。 In the second read mode, contrary to the first read mode, the rectangular object is imaged with a delay in timing as it approaches the end in the first direction. Therefore, the object is distorted to the right as it approaches the end (upper and lower) from the pixel dividing portion 143.
　第3読出モードにおいては、第1読出モード、第2読出モードとは異なり、単調にずれが発生するように画像が歪む。第3読出モードは、第1読出モード及び第2読出モードに比べて撮像時間が2倍、すなわち、フレームレートが1 / 2となるが、一方で、画素分割部143における画像の歪みの方向が変化しない。このため、人間にとって、第3読出モードにより撮像された画像は、他の読出モードと比較して自然な印象を与える。 In the third read mode, unlike the first read mode and the second read mode, the image is distorted so that a monotonous shift occurs. In the third read mode, the imaging time is twice that of the first read mode and the second read mode, that is, the frame rate is 1/2, but on the other hand, the direction of image distortion in the pixel dividing unit 143 is It does not change. Therefore, for humans, the image captured by the third read mode gives a natural impression as compared with other read modes.
　図9は、固体撮像装置1がこのような方法で撮影する処理を示すフローチャートである。 FIG. 9 is a flowchart showing a process of taking a picture by the solid-state image sensor 1 in such a method.
　まず、制御回路24は、読出モードとして、第1読出モード又は第2読出モードを設定する(S100)。この2つのモードは、画素分割部143により分割される2つの領域についての受光素子14からの信号を同じタイミングにおいてそれぞれ処理するので、第3読出モードよりもフレームレートを2倍程度に向上することができる。一方で、図8に示すように画素分割部143で折り返すようなフォーカルプレーン歪みを生じさせる。このため、高速でAE/AFを処理する初期の段階においては、第3読出モードよりも高速に読出が可能である第1読出モード又は第2読出モードを設定する。 First, the control circuit 24 sets the first read mode or the second read mode as the read mode (S100). In these two modes, the signals from the light receiving element 14 for the two regions divided by the pixel dividing unit 143 are processed at the same timing, so that the frame rate is about twice as high as that in the third read mode. Can be done. On the other hand, as shown in FIG. 8, focal plane distortion such as folding back at the pixel dividing portion 143 is generated. Therefore, in the initial stage of processing AE / AF at high speed, the first read mode or the second read mode, which enables reading at a higher speed than the third read mode, is set.
　次に、制御回路24は、撮影条件を制御する(S102)。この制御は、初期値として設定されている撮影パラメータ等を用いて設定されてもよい。また、照度計等の情報が利用できる場合には、当該情報に基づいて露出、フォーカス等のパラメータを設定してもよい。 Next, the control circuit 24 controls the shooting conditions (S102). This control may be set using a shooting parameter or the like set as an initial value. If information from an illuminometer or the like is available, parameters such as exposure and focus may be set based on the information.
　次に、制御回路24は、設定された撮影条件に基づいて、撮影し、信号処理回路22により、信号処理を実行する(S104)。信号処理回路22は、制御された撮影条件により受光素子14が受光して出力したアナログ信号の信号処理、画像処理を実行する。ディスプレイ等の表示部が固体撮像装置1に備えられる場合には、当該ディスプレイ等に処理された画像を表示させてもよい。 Next, the control circuit 24 shoots based on the set shooting conditions, and the signal processing circuit 22 executes signal processing (S104). The signal processing circuit 22 executes signal processing and image processing of an analog signal received and output by the light receiving element 14 under controlled shooting conditions. When a display unit such as a display is provided in the solid-state image sensor 1, the processed image may be displayed on the display or the like.
　次に、AE/AF処理回路26は、信号処理回路22が出力した画像データに基づいて、AE/AF処理を実行する(S106)。AF/AE処理は、取得された画像データに基づいて実行される。 Next, the AE / AF processing circuit 26 executes AE / AF processing based on the image data output by the signal processing circuit 22 (S106). AF / AE processing is executed based on the acquired image data.
　AE/AF処理回路26は、例えば、画像中の輝度情報の統計を算出することにより、AEの設定をしてもよい。AE/AF処理回路26は、例えば、白抜け画素が多いと判断した場合には、露出を減少させてもよいし、逆に、黒つぶれ画素が多いと判断した場合には、露出を増加させてもよい。 The AE / AF processing circuit 26 may set the AE by, for example, calculating the statistics of the luminance information in the image. The AE / AF processing circuit 26 may, for example, reduce the exposure when it is determined that there are many whiteout pixels, and conversely, increase the exposure when it is determined that there are many blackout pixels. You may.
　AE/AF処理回路26は、例えば、画像中のコントラストの検出をし、このコントラストが高くなるようにAFの設定をしてもよい。また、別の例として、AE/AF処理回路26は、空間周波数の高周波成分が高くなるようにAFの設定をしてもよい。 The AE / AF processing circuit 26 may detect the contrast in the image, for example, and set the AF so that the contrast becomes high. Further, as another example, the AE / AF processing circuit 26 may set AF so that the high frequency component of the spatial frequency becomes high.
　このAE、AFの各処理は、例えば、所定領域内における画素値の統計情報に基づいて実行されてもよい。所定領域は、例えば、画像全体としてもよいし、画像の中央付近の領域としてもよい。また、ユーザが領域を設定できる形態としてもよい。 Each of the AE and AF processes may be executed, for example, based on the statistical information of the pixel values in the predetermined area. The predetermined region may be, for example, the entire image or a region near the center of the image. Further, the user may set the area.
　これらの処理は、撮影前のタイミングにおいて自動で所定間隔のタイミングにおいて行われてもよいし、ユーザのインタフェースを介してのAE/AFロック要求に基づいて、実行されてもよい。例えば、固体撮像装置1が備えられるデジタルカメラ等の電子機器におけるシャッターボタンの半押し等により、ロック要求を受け付けてもよい。 These processes may be automatically performed at predetermined intervals at the timing before shooting, or may be executed based on the AE / AF lock request via the user interface. For example, the lock request may be accepted by half-pressing the shutter button in an electronic device such as a digital camera provided with the solid-state image sensor 1.
　AE/AF処理回路26は、このように算出されたAE、AFに関するパラメータを制御回路24へと出力する。また、適切な露出、フォーカスである場合には、その旨を制御回路24へと出力する。AE/AF処理回路26は、例えば、上記に示した露出、フォーカスに関する統計値に基づいて、適切なAE、AFのパラメータが設定されているか否かを判断し、制御回路24へと出力する。また、AE/AF処理回路26は、単純にパラメータを送信するだけでもよく、この場合、制御回路24が、適切にパラメータが設定されているか否かを判断してもよい。 The AE / AF processing circuit 26 outputs the parameters related to AE and AF calculated in this way to the control circuit 24. If the exposure and focus are appropriate, that fact is output to the control circuit 24. The AE / AF processing circuit 26 determines, for example, whether or not appropriate AE and AF parameters are set based on the above-mentioned statistics on exposure and focus, and outputs the result to the control circuit 24. Further, the AE / AF processing circuit 26 may simply transmit the parameters, and in this case, the control circuit 24 may determine whether or not the parameters are appropriately set.
　次に、制御回路24は、AE/AF処理回路26からの出力に基づいて、適切なAE/AF等のパラメータが設定されているか否かを判断する(S108)。 Next, the control circuit 24 determines whether or not appropriate parameters such as AE / AF are set based on the output from the AE / AF processing circuit 26 (S108).
　制御が完了していないと判断された場合(S108:NO)には、S102からの処理を繰り返す。この場合、S102の処理において、制御回路24は、AE/AF処理回路26が出力に基づいてパラメータを設定し、光学系12、受光素子14、及び、信号処理回路22、AE/AF処理回路26の制御を実行する。 If it is determined that the control is not completed (S108: NO), the process from S102 is repeated. In this case, in the processing of S102, in the control circuit 24, the AE / AF processing circuit 26 sets the parameters based on the output, and the optical system 12, the light receiving element 14, the signal processing circuit 22, and the AE / AF processing circuit 26. To control.
　制御回路24は、光学系12、受光素子14に対しては、例えば、露出時間、ピントの調整の制御信号を送信する。また、制御回路24は、信号処理回路22、AE/AF処理回路26に対しては、次の制御タイミングまでの間に使用するパラメータを送信することにより、受光素子14が出力した信号に対する処理についてのパラメータを制御する。 The control circuit 24 transmits, for example, a control signal for adjusting the exposure time and focus to the optical system 12 and the light receiving element 14. Further, the control circuit 24 processes the signal output by the light receiving element 14 by transmitting the parameters used until the next control timing to the signal processing circuit 22 and the AE / AF processing circuit 26. Control the parameters of.
　この後に、撮影と、AE/AF処理が実行される(S104、S106)。 After this, shooting and AE / AF processing are executed (S104, S106).
　制御が完了していると判断された場合(S108:YES)には、制御回路24は、読出モードを第3読出モードに設定する(S110)。この第3読出モードに設定することにより、上述したように、フレームレートは、第1読出モード、第2読出モードよりも下がるものの、フォーカルプレーン歪みが人間にとって他のモードよりも自然となるような画像を取得するモードへと移行する。 When it is determined that the control is completed (S108: YES), the control circuit 24 sets the read mode to the third read mode (S110). By setting to this third read mode, as described above, the frame rate is lower than that of the first read mode and the second read mode, but the focal plane distortion becomes more natural for humans than the other modes. It shifts to the mode to acquire the image.
　次に、制御回路24からの要求に基づいて、撮影、信号処理が実行される(S112)。光学系12及び受光素子14は、適切に設定された露出、フォーカス等に関するパラメータにより、第3読出モードで撮像する。信号処理回路22は、制御回路24から取得したパラメータに基づいて、信号処理、画像処理等の種々の処理を実行する。 Next, shooting and signal processing are executed based on the request from the control circuit 24 (S112). The optical system 12 and the light receiving element 14 take an image in the third read mode according to appropriately set parameters related to exposure, focus, and the like. The signal processing circuit 22 executes various processes such as signal processing and image processing based on the parameters acquired from the control circuit 24.
　次に、信号処理回路22は、適切な箇所に画像データを出力する(S114)。例えば、信号処理回路22は、固体撮像装置1の内部又は外部にあるメモリに画像データを格納する。また、同じタイミングにおいて、ディスプレイ等の表示部がある場合には、当該画像データを表示してもよい。 Next, the signal processing circuit 22 outputs image data to an appropriate location (S114). For example, the signal processing circuit 22 stores image data in a memory inside or outside the solid-state image sensor 1. Further, at the same timing, if there is a display unit such as a display, the image data may be displayed.
　次に、制御回路24は、撮像処理が完了下か否かを判断する(S116)。この判断は、ユーザからの指示に基づいて実行されてもよい。処理が完了していない、例えば、ユーザが撮影を継続する場合(S116:NO)には、再度S100からの処理を繰り返す。この場合、初期値としてS112、S114に設定されたパラメータを用いて、S100～S106の処理を実行してもよい。 Next, the control circuit 24 determines whether or not the imaging process is complete (S116). This determination may be made based on instructions from the user. If the process is not completed, for example, if the user continues shooting (S116: NO), the process from S100 is repeated again. In this case, the processes of S100 to S106 may be executed using the parameters set in S112 and S114 as initial values.
　以上のように、図9に示すフローチャートにしたがって固体撮像装置1が処理をすることにより、高速に適切なAE、AFの設定をするとともに、歪みが自然である高精度な画像を取得することが可能となる。 As described above, by processing the solid-state image sensor 1 according to the flowchart shown in FIG. 9, it is possible to set appropriate AE and AF at high speed and acquire a high-precision image with natural distortion. It will be possible.
　(第2実施形態)
　図10は、第2実施形態に係る固体撮像装置1の構成を示すブロック図である。固体撮像装置1は、第1実施形態における固体撮像装置1のAE/AF処理回路26の代わりに、認識処理回路28を備える。なお、本図は一例として示したものであり、さらにAE/AF処理回路26を備え、上記のAE/AF処理をも実行する構成であってもよい。 (Second embodiment)
FIG. 10 is a block diagram showing the configuration of the solid-state image sensor 1 according to the second embodiment. The solid-state image sensor 1 includes a recognition processing circuit 28 instead of the AE / AF processing circuit 26 of the solid-state image pickup device 1 in the first embodiment. It should be noted that this figure is shown as an example, and may be configured to further include an AE / AF processing circuit 26 and also execute the above-mentioned AE / AF processing.
　認識処理回路28は、例えば、図2におけるロジック回路210の一部として備えられる。この認識処理回路28は、例えば、訓練済の機械学習モデルを用いて種々の認識処理を実行する。 The recognition processing circuit 28 is provided, for example, as a part of the logic circuit 210 in FIG. The recognition processing circuit 28 executes various recognition processing using, for example, a trained machine learning model.
　例えば、認識処理回路28は、人間の顔を認識し、当該顔の領域を抽出する。人間の顔に限られず、認識処理回路28は、所定の物体を検出して認識してもよい。AE/AF処理回路26をさらに備える構成として、人物の顔を検出し、当該検出した顔を含む所定の大きさ、形状の領域において、AE、AFの制御をするためのパラメータを算出してもよい。この場合、顔の領域をフレームごとに検出して追跡をしてもよい。 For example, the recognition processing circuit 28 recognizes a human face and extracts the area of the face. Not limited to the human face, the recognition processing circuit 28 may detect and recognize a predetermined object. As a configuration further including the AE / AF processing circuit 26, even if a person's face is detected and parameters for controlling AE and AF are calculated in a region of a predetermined size and shape including the detected face. good. In this case, the facial area may be detected and tracked frame by frame.
　人物の顔を認識するタイミングにおいて、表情を読み取ってもよい。そして、読み取った表情が笑顔であるタイミングで撮像を行う制御を、制御回路24が実行してもよい。また、上記において、人物の顔を被写体としたが、これには限られず、任意のものを被写体として設定することが可能である。 The facial expression may be read at the timing of recognizing the face of the person. Then, the control circuit 24 may execute control to perform imaging at the timing when the read facial expression is a smile. Further, in the above, the face of a person is used as the subject, but the subject is not limited to this, and any object can be set as the subject.
　図11は、本実施形態に係る固体撮像装置1の処理を示すフローチャートである。同じ符号が付してある処理については、前述の実施形態と同様であるので詳しい説明は省略する。 FIG. 11 is a flowchart showing the processing of the solid-state image sensor 1 according to the present embodiment. Since the processes with the same reference numerals are the same as those in the above-described embodiment, detailed description thereof will be omitted.
　AE/AFの制御が完了後(S108:YES)、認識処理回路28は、信号処理回路22が出力した画像データに対して認識処理を実行する(S118)。認識処理は、例えば、訓練済のニューラルネットワークモデルに画像データを入力することにより実行される。なお、ニューラルネットワークモデルを用いずに、ルールベース等の処理により認識処理を実行してもよい。 After the AE / AF control is completed (S108: YES), the recognition processing circuit 28 executes the recognition processing on the image data output by the signal processing circuit 22 (S118). The recognition process is executed, for example, by inputting image data into a trained neural network model. Note that the recognition process may be executed by a rule-based process or the like without using the neural network model.
　次に、認識処理回路28は、所定の物体が認識、検知されたか否かを判断する(S120)。検知されていない場合(S120:NO)、S104からの処理を繰り返す。なお、点線の矢印で示すように、認識処理を所定回数、又は、所定時間の間繰り返し実行してもよい。その後、認識がさらにできないようであれば、S104からの処理を繰り返してもよい。 Next, the recognition processing circuit 28 determines whether or not a predetermined object has been recognized and detected (S120). If it is not detected (S120: NO), the process from S104 is repeated. As shown by the dotted arrow, the recognition process may be repeatedly executed a predetermined number of times or for a predetermined time. After that, if the recognition cannot be further performed, the process from S104 may be repeated.
　認識処理回路28が物体を検知すると、制御回路24は、固体撮像装置1の処理モードを、第3読出モードに遷移させる(S110)。 When the recognition processing circuit 28 detects an object, the control circuit 24 shifts the processing mode of the solid-state image sensor 1 to the third read mode (S110).
　次に、制御回路24は、認識処理回路28の検知結果に基づいて、ROI(Region of Interest)の制御を実行する(S122)。このROIの制御により、被写体が写っている領域を追跡してもよい。また、ROI内の統計情報に基づいて、AE、AFの処理を実行してもよい。 Next, the control circuit 24 executes ROI (Region of Interest) control based on the detection result of the recognition processing circuit 28 (S122). By controlling this ROI, the area where the subject is shown may be tracked. Further, AE and AF processing may be executed based on the statistical information in the ROI.
　その後は、前述の実施形態と同様に、画像を取得、出力して、処理を終了する。 After that, as in the above-described embodiment, the image is acquired and output, and the process is terminated.
　なお、上記においては、認識処理を必須のものとしたが、これには限られない。例えば、固体撮像装置1は、認識処理回路28を備える状態であっても、認識処理を実行しないことを選択してもよい。固体撮像装置1は、物体が検知できない状態であっても、設定されているAE、AFに基づいて、ユーザからの要求により、そのタイミングで設定されているパラメータに基づいて撮像、信号処理等の処理を実行してもよい。 In the above, recognition processing is essential, but it is not limited to this. For example, the solid-state image sensor 1 may choose not to execute the recognition process even when the recognition process circuit 28 is provided. Even if the solid-state image sensor 1 cannot detect an object, it can perform imaging, signal processing, etc. based on the parameters set at that timing according to the user's request based on the set AE and AF. The process may be executed.
　以上のように、本実施形態によれば、第2基板20に備えられるロジック回路210内において認識処理を実行してもよい。この認識処理をすることにより、被写体の画像データをよりよい状態で取得するとともに、ユーザビリティを向上させることも可能となる。固体撮像装置1は、認識処理を実行する間は、高速に被写体を検知するべくフレームレートの高いモードで読出を実行し、認識が完了後にはフォーカルプレーン歪みが不自然とならないように、高精度の画像を取得するモードへと切り替えることが可能となる。 As described above, according to the present embodiment, the recognition process may be executed in the logic circuit 210 provided in the second board 20. By performing this recognition process, it is possible to acquire the image data of the subject in a better state and improve the usability. The solid-state image sensor 1 performs reading in a mode with a high frame rate in order to detect the subject at high speed while executing the recognition process, and has high accuracy so that the focal plane distortion does not become unnatural after the recognition is completed. It is possible to switch to the mode to acquire the image of.
　上記においては、認識処理回路28は、所定の物体を検出するものとしたが、これには限られない。例えば、動きを検知するようなイベントドリブンのような動作を実現してもよい。 In the above, the recognition processing circuit 28 is supposed to detect a predetermined object, but the present invention is not limited to this. For example, an event-driven operation that detects movement may be realized.
　また、上記においては、AE/AF処理回路26が備えられる場合について説明したが、AE/AF処理回路26は、必須の構成ではない。この場合、認識処理回路28が認識した結果に基づいて、制御回路24が種々の制御、例えば、読出モードの切り替えを実行してもよい。 Further, in the above, the case where the AE / AF processing circuit 26 is provided has been described, but the AE / AF processing circuit 26 is not an indispensable configuration. In this case, the control circuit 24 may execute various controls, for example, switching of the read mode, based on the result recognized by the recognition processing circuit 28.
　なお、認識処理回路28は、訓練済のモデルを用いて認識するとしたが、これには限られない。例えば、認識処理回路28は、認識の結果に基づいて、又は、ユーザからの指示に基づいて、認識結果の精度を向上すべく機械学習を実行してもよい。この機械学習は、例えば、固体撮像装置1が撮影をしていないタイミングに実行されるものであってもよい。 The recognition processing circuit 28 was supposed to be recognized using a trained model, but it is not limited to this. For example, the recognition processing circuit 28 may execute machine learning to improve the accuracy of the recognition result based on the recognition result or the instruction from the user. This machine learning may be executed, for example, at a timing when the solid-state image sensor 1 is not taking a picture.
　(第3実施形態)
　前述した実施形態においては、画素分割部143が1つ備えられる構成であったが、これには限られない。すなわち、受光素子アレイ140は、より多くの領域に分割されてもよい。これに伴い、アナログ回路200もより多くの領域に分けて実装されてもよい。 (Third embodiment)
In the above-described embodiment, the configuration is provided with one pixel dividing unit 143, but the present invention is not limited to this. That is, the light receiving element array 140 may be divided into more regions. Along with this, the analog circuit 200 may also be mounted in more areas.
　図12は、本実施形態に係る受光素子アレイ140とアナログ回路200との積層状態を示す図である。受光素子アレイ140には、3つの画素分割部143A、143B、143Cが備えられる。 FIG. 12 is a diagram showing a laminated state of the light receiving element array 140 and the analog circuit 200 according to the present embodiment. The light receiving element array 140 is provided with three pixel dividing units 143A, 143B, and 143C.
　受光素子アレイ140は、画素分割部143Cにより、大きく2つの領域に分割される。これらの領域は、画素分割部143Aにより、第1領域141Aと、第2領域142A、及び、画素分割部143Bにより、第1領域141Bと、第2領域142B、に分割される。このように、受光素子アレイ140は、例えば、4つの領域に分割される。 The light receiving element array 140 is roughly divided into two regions by the pixel dividing unit 143C. These regions are divided into a first region 141A and a second region 142A by the pixel dividing unit 143A, and a first region 141B and a second region 142B by the pixel dividing unit 143B. In this way, the light receiving element array 140 is divided into, for example, four regions.
　前述した実施形態と同様に、第2方向に連続する受光素子14、すなわち、同じ行に属する画素に対しては、1つの第1信号線が配置される。これに対して、141A、142A、141B、142Bの各領域に属する第1方向に連続する受光素子14に接続される第2信号線は、それぞれの領域で前述した実施形態と同様に切断され、各接続部を介してアナログ回路200へと出力される。すなわち、図12の例においては、各列において、4本の第2信号線が備えられる。 Similar to the above-described embodiment, one first signal line is arranged for the light receiving element 14 continuous in the second direction, that is, the pixels belonging to the same row. On the other hand, the second signal line connected to the light receiving element 14 continuous in the first direction belonging to each region of 141A, 142A, 141B, 142B is cut in each region in the same manner as in the above-described embodiment. It is output to the analog circuit 200 via each connection. That is, in the example of FIG. 12, four second signal lines are provided in each row.
　図13は、本実施形態に係る受光素子アレイ140の概略を示す図である。受光素子アレイ140は、画素分割部143A、143B、143Cにより、領域141A、142A、141B、142Bに分割される。分割されたそれぞれの領域には、同じ行に属する受光素子14からの出力をするか否かを選択する第1信号線16が、受光素子14が存在する行数分備えられる。図4と同様に、画素間の間隔は、画素分割部をまたぐ箇所において広くなっているが、説明のためであり、実際には他の画素間の間隔と同等の間隔を有していてもよい。 FIG. 13 is a diagram showing an outline of the light receiving element array 140 according to the present embodiment. The light receiving element array 140 is divided into regions 141A, 142A, 141B, and 142B by the pixel dividing portions 143A, 143B, and 143C. Each of the divided regions is provided with a first signal line 16 for selecting whether or not to output from the light receiving element 14 belonging to the same line for the number of lines in which the light receiving element 14 exists. Similar to FIG. 4, the interval between pixels is wide at the portion straddling the pixel division portion, but for the sake of explanation, even if the interval is actually the same as the interval between other pixels. good.
　一方で第2信号線は、領域ごとに同じ列に属する受光素子14から出力が接続され、異なる領域同士において切断されるように備えられる。例えば、領域141Aに配置される複数の第2信号線181Aは、それぞれの列に属する受光素子14を接続する。一方で、他の領域142A、141B、142Bの第2信号線182A、181B、182Bとは電気的に接続されないように備えられる。 On the other hand, the second signal line is provided so that the output is connected from the light receiving element 14 belonging to the same row for each region and is cut off in different regions. For example, the plurality of second signal lines 181A arranged in the region 141A connect the light receiving elements 14 belonging to the respective rows. On the other hand, it is provided so as not to be electrically connected to the second signal lines 182A, 181B, 182B of the other regions 142A, 141B, 142B.
　それぞれの信号線は、接続部により第2基板20と接続される。例えば、第1領域141Aにあるそれぞれの第2信号線181Aは、第1接続部301Aを介して第1アナログ回路201に接続される。他も同様であり、第2領域142Aの第2信号線182Aは、第2接続部302Aを介して第2アナログ回路202と接続される。また、図の上側も下側と同じく、の第1領域141Bの第2信号線181Bは、第1接続部301Bを介し、第3アナログ回路203と接続され、第2領域142Bの第2信号線182Bは、第2接続部302Bを介し、第4アナログ回路204と接続される。 Each signal line is connected to the second board 20 by a connecting part. For example, each second signal line 181A in the first region 141A is connected to the first analog circuit 201 via the first connection portion 301A. The same applies to the others, and the second signal line 182A in the second region 142A is connected to the second analog circuit 202 via the second connection portion 302A. Further, the upper side of the figure is the same as the lower side, and the second signal line 181B of the first region 141B is connected to the third analog circuit 203 via the first connection portion 301B, and the second signal line of the second region 142B is connected. The 182B is connected to the fourth analog circuit 204 via the second connection portion 302B.
　受光素子アレイ140は、このように、複数の画素分割部143により、複数の領域に分割されてもよい。図13に示すように、それぞれの領域において第2信号線及び接続部が独立して備えられ、第2基板20のアナログ回路200とそれぞれが接続される。 The light receiving element array 140 may be divided into a plurality of regions by the plurality of pixel dividing units 143 in this way. As shown in FIG. 13, a second signal line and a connection portion are independently provided in each region, and each is connected to the analog circuit 200 of the second substrate 20.
　図12に戻り、第2基板20の説明をする。図12において接続部30が備えられる領域において、それぞれアナログ回路が備えられる。例えば、第2基板20は、第1アナログ回路201と、第2アナログ回路202と、第3アナログ回路203と、第4アナログ回路204と、を備える。 Returning to FIG. 12, the second board 20 will be explained. In the area where the connection portion 30 is provided in FIG. 12, analog circuits are provided respectively. For example, the second board 20 includes a first analog circuit 201, a second analog circuit 202, a third analog circuit 203, and a fourth analog circuit 204.
　それぞれのアナログ回路200は、前述した実施形態と同様に、積層された状態において、第1アナログ回路201と第4アナログ回路204が第3方向に受光素子アレイ140の第1方向における端部に備えられ、さらに、画素分割部143と重なるように第2アナログ回路202と第3アナログ回路203が配置される。それぞれの回路の構成は、図5と同等のものであるので詳細は、省略する。なお、第2アナログ回路202と、第3アナログ回路203とは、明確には区別される必要はなく、それぞれの領域に属する受光素子14から出力された信号を適切に処理できるのであれば、一体として形成されていてもよい。 As in the above-described embodiment, each analog circuit 200 is provided with the first analog circuit 201 and the fourth analog circuit 204 at the end in the first direction of the light receiving element array 140 in the third direction in a stacked state. Further, the second analog circuit 202 and the third analog circuit 203 are arranged so as to overlap the pixel dividing portion 143. Since the configuration of each circuit is the same as that shown in FIG. 5, details are omitted. It should be noted that the second analog circuit 202 and the third analog circuit 203 do not need to be clearly distinguished, and if the signal output from the light receiving element 14 belonging to each region can be appropriately processed, they are integrated. It may be formed as.
　これらのアナログ回路は、上述したように、第1読出モード及び第2読出モードにおいては、全てが起動する。一方で、第3読出モードにおいては、アナログ信号を出力する受光素子14似合わせて、不要なアナログ回路は、電源をオフ状態としてもよい。 As described above, all of these analog circuits are activated in the first read mode and the second read mode. On the other hand, in the third read mode, the power of the unnecessary analog circuit may be turned off in accordance with the light receiving element 14 that outputs an analog signal.
　このような積層においては、前述の実施形態では備えられなかった、受光素子14の下の一部の領域、より具体的には、画素分割部143の周辺において、図13に示すように接続部302A、301Bが備えられる必要がある。 In such a stack, as shown in FIG. 13, a part of the region under the light receiving element 14, more specifically, around the pixel dividing portion 143, which was not provided in the above-described embodiment, is connected. 302A and 301B need to be provided.
　ロジック回路210A、210Bは、例えば、図において第1アナログ回路201と第2アナログ回路202との間、及び、第3アナログ回路203と第4アナログ回路204との間にそれぞれ配置されてもよい。 The logic circuits 210A and 210B may be arranged, for example, between the first analog circuit 201 and the second analog circuit 202, and between the third analog circuit 203 and the fourth analog circuit 204 in the figure.
　以上のように、受光素子アレイ140の分割数を増やすことが可能である。このように分割数を増やすことにより、受光素子14の下方に接続部30を備えなくてはならない一方で、第2信号線の負荷をさらに下げることが可能となり、さらなる高速化及び低消費電力化を実現することが可能となる。 As described above, it is possible to increase the number of divisions of the light receiving element array 140. By increasing the number of divisions in this way, the connection portion 30 must be provided below the light receiving element 14, while the load on the second signal line can be further reduced, resulting in further speedup and lower power consumption. Can be realized.
　(第4実施形態)
　前述の各実施形態においては、1列に1つの第2信号線が備えられるものとしたが、これには限られない。例えば、一列に属する受光素子14において、複数の第2信号線が備えられていてもよい。複数の第2信号線には、それぞれに対して接続部が備えられていてもよい。 (Fourth Embodiment)
In each of the above-described embodiments, one second signal line is provided in one row, but the present invention is not limited to this. For example, the light receiving element 14 belonging to one row may be provided with a plurality of second signal lines. The plurality of second signal lines may be provided with a connection portion for each.
　図14は、本実施形態に係る画素アレイ、第2信号線、接続部の概略を模式的に示す図である。本図においては、画素と配線、接続部等が全て平面上に描かれているがこれには限られない。例えば、画素が上面にあり、その第3方向下方において、配線が備えられ、当該配線と接続部とが第1基板10内で接続する構成であってもよい。 FIG. 14 is a diagram schematically showing an outline of a pixel array, a second signal line, and a connection portion according to the present embodiment. In this figure, the pixels, wiring, connection parts, etc. are all drawn on a plane, but the present invention is not limited to this. For example, the pixel may be on the upper surface, wiring may be provided below the third direction, and the wiring and the connecting portion may be connected in the first substrate 10.
　受光素子アレイ140には、受光素子14が複数備えられる。複数の第2信号線181、182は、同じ列に属する受光素子14の出力がそれぞれ接続されるように備えられる。前述の実施形態とは異なり、各列の間には、複数の第2信号線181、182が備えられる。なお、説明のため、第1信号線は、図示していないが図4等と同様に備えられている。 The light receiving element array 140 is provided with a plurality of light receiving elements 14. The plurality of second signal lines 181, 182 are provided so that the outputs of the light receiving elements 14 belonging to the same row are connected to each other. Unlike the above-described embodiment, a plurality of second signal lines 181, 182 are provided between the rows. For the sake of explanation, the first signal line is provided in the same manner as in FIG. 4, although it is not shown.
　例えば、受光素子14の列と列の間には、それぞれ12本の第2信号線181、182が備えられていてもよい。この場合、第1方向に沿った12個以下の受光素子14から出力されるアナログ信号が並行して第2基板20のアナログ回路200へと出力されてもよい。すなわち、12行以下の行に属する受光素子14について同じタイミングで並行してアナログ信号の処理を実行することができる。言い換えると、複数行に属する受光素子14の信号を同じタイミングでアナログ回路200へと出力することが可能である。 For example, twelve second signal lines 181, 182 may be provided between the rows of the light receiving elements 14 and the rows, respectively. In this case, analog signals output from 12 or less light receiving elements 14 along the first direction may be output to the analog circuit 200 of the second substrate 20 in parallel. That is, analog signal processing can be executed in parallel for the light receiving elements 14 belonging to 12 rows or less at the same timing. In other words, it is possible to output the signals of the light receiving element 14 belonging to a plurality of lines to the analog circuit 200 at the same timing.
　図示しない第1信号線は、この12個以下の行を同じタイミングで指定する。図において、受光素子14から接続される配線と、第2信号線が黒点で示されている箇所は、電気的に接続される箇所であり、黒点がない箇所は、電気的に接続されていない箇所である。例えば、受光素子14からの配線と、第2信号線とが交差する点において、スイッチを備えておき、第1信号線が適切にこれらのスイッチの状態を切り替えることにより、アナログ信号の処理をする受光素子14を選択することが可能となる。 For the first signal line (not shown), specify these 12 or less lines at the same timing. In the figure, the wiring connected from the light receiving element 14 and the portion where the second signal line is indicated by a black dot are electrically connected, and the portion without a black dot is not electrically connected. It is a place. For example, a switch is provided at a point where the wiring from the light receiving element 14 and the second signal line intersect, and the first signal line appropriately switches the state of these switches to process the analog signal. The light receiving element 14 can be selected.
　以上のように、複数の行について同じタイミングでアナログ信号を出力することもの可能である。 As described above, it is possible to output analog signals at the same timing for multiple lines.
　(接続部の実装例)
　図1の固体撮像装置1のチップ構造について説明する。前述のように、固体撮像装置1は、第1基板10と第2基板20とを積層した積層体である。第1基板10、第2基板20は、ダイと呼ばれることもある。例えば、図2においては、第1基板10、第2基板20は、矩形状であるが、具体的な形状及びサイズについては任意である。また、第1基板10と第2基板20は、同じサイズでもよいし、互いに異なるサイズでもよい。 (Implementation example of connection part)
The chip structure of the solid-state image sensor 1 of FIG. 1 will be described. As described above, the solid-state image sensor 1 is a laminated body in which the first substrate 10 and the second substrate 20 are laminated. The first substrate 10 and the second substrate 20 are sometimes called dies. For example, in FIG. 2, the first substrate 10 and the second substrate 20 have a rectangular shape, but the specific shape and size are arbitrary. Further, the first substrate 10 and the second substrate 20 may have the same size or may be different sizes from each other.
　第1基板10には、図4等に示される受光素子アレイ140が配置される。また、第1基板10には、光学系12の少なくとも一部がオンチップで実装されてもよい。 The light receiving element array 140 shown in FIG. 4 and the like is arranged on the first substrate 10. Further, at least a part of the optical system 12 may be mounted on the first substrate 10 on-chip.
　第2基板20には、アナログ回路200と、ロジック回路210と、が少なくとも備えられ、その他必要となる回路、例えば、インタフェース回路等も備えられる。例えば、上記で説明した行選択信号、同期信号等のタイミングを図るクロック信号を出力するクロック生成回路等が備えられてもよい。また、各回路の包括的又は部分的な制御を行う制御回路が備えられてもよい。 The second board 20 is provided with at least an analog circuit 200 and a logic circuit 210, and is also provided with other necessary circuits such as an interface circuit. For example, a clock generation circuit or the like that outputs a clock signal for timing the row selection signal, synchronization signal, or the like described above may be provided. Further, a control circuit for comprehensively or partially controlling each circuit may be provided.
　第1基板10と第2基板20の貼り合わせの具体的形態として、第1基板10と第2基板20を、例えば、ウエハから切り出して個片化した後に、上下に重ねて張り合わされる、所謂CoC(Chip on Chip)方式を採用してもよい。あるいは、第1基板10と第2基板20の一方(例えば、第1基板10)をウエハから切り出して個片化した後、個片化した第1基板10を個片化前の第2基板20に貼り合わせる、所謂CoW(Chip on Wafer)方式を採用してもよい。あるいは、第1基板10と第2基板20をウエハの状態で貼り合わせる、所謂WoW(Wafer on Wafer)方式を採用してもよい。 As a specific form of bonding the first substrate 10 and the second substrate 20, for example, the first substrate 10 and the second substrate 20 are cut out from a wafer, separated into individual pieces, and then laminated one above the other, so-called. A CoC (Chip on Chip) method may be adopted. Alternatively, one of the first substrate 10 and the second substrate 20 (for example, the first substrate 10) is cut out from the wafer and individualized, and then the individualized first substrate 10 is separated into the second substrate 20 before individualization. The so-called CoW (Chip on Wafer) method may be adopted. Alternatively, a so-called WoW (Wafer on Wafer) method, in which the first substrate 10 and the second substrate 20 are bonded together in the state of a wafer, may be adopted.
　第1基板10と第2基板20の接合には種々の接合方法を用いてもよい。例えば、プラズマ接合等を用いることができる。 Various joining methods may be used for joining the first substrate 10 and the second substrate 20. For example, plasma junction or the like can be used.
　第1基板10と第2基板20の接合において、第1基板10と第2基板20とを電気的に接続する、接続部には、特に、以下の図で示すような接合を用いてもよい。なお、細かい回路の状態においては示さず、接続部の接続についてのみ示している。このため、図においては、種々の回路の要素等の描画は省略している。また、第2信号線181について記載するが、第2信号線182、・・・、等についても同様である。 In the joining of the first substrate 10 and the second substrate 20, the joining portion as shown in the following figure may be used for the connection portion for electrically connecting the first substrate 10 and the second substrate 20. .. It should be noted that it is not shown in the state of a detailed circuit, but only the connection of the connection part is shown. Therefore, in the figure, drawing of various circuit elements and the like is omitted. Further, the second signal line 181 will be described, but the same applies to the second signal line 182, ..., Etc.
　図15は、接続部の一例を示す図である。以下の図においては、第2信号線181が存在する領域において、例えば、アナログ回路200と、第2信号線181とが接続される様子を示す。光学系12により集光された光を光電変換する受光素子14は、第2信号線181で接続される。第2信号線181は、例えば、マイクロバンプを備えて形成される接続部30と接続され、アナログ回路200と接続される。例えば、受光素子14側と、アナログ回路200側の双方にマイクロパッドを形成し、これらのマイクロパッド同士をマイクロバンプで接続する。 FIG. 15 is a diagram showing an example of a connection portion. In the following figure, for example, the analog circuit 200 and the second signal line 181 are connected in the region where the second signal line 181 exists. The light receiving element 14 that photoelectrically converts the light collected by the optical system 12 is connected by a second signal line 181. The second signal line 181 is connected to, for example, a connection portion 30 formed with microbumps and is connected to an analog circuit 200. For example, micropads are formed on both the light receiving element 14 side and the analog circuit 200 side, and these micropads are connected to each other by microbumps.
　図16は、接続部の別の例を示す図である。接続部30は、例えば、図に示すように、マイクロパッドにより接続されてもよい。図15におけるマイクロバンプを介さずに、第基1板10と第2基板20とを接続することにより、直接マイクロパッドにより接続してもよい。 FIG. 16 is a diagram showing another example of the connection portion. The connection portion 30 may be connected by a micro pad, for example, as shown in the figure. By connecting the first base plate 10 and the second substrate 20 without using the micro bumps in FIG. 15, the micro pads may be directly connected.
　図17は、接続部の別の例を示す図である。接続部30は、例えば、ビアホールを形成し、当該ビアホールと、第2信号線181とアナログ回路200とのコンタクトを取ることにより、受光素子14とアナログ回路200とを接続させてもよい。 FIG. 17 is a diagram showing another example of the connection portion. The connecting portion 30 may form a via hole, for example, and connect the light receiving element 14 and the analog circuit 200 by making contact between the via hole, the second signal line 181 and the analog circuit 200.
　また、第1基板10と第2基板20とは、受光素子14に関しては接続部30を介して接続されるが、その他の信号を送受信するための接続線を必要に応じてさらに備えていてもよい。 Further, the first substrate 10 and the second substrate 20 are connected via the connection portion 30 with respect to the light receiving element 14, but even if a connection line for transmitting and receiving other signals is further provided as needed. good.
　(基板の積層例)
　図18は、固体撮像装置１が2層で形成される場合の一例を示す図である。第2基板20は、光学系12と、受光素子14を2次元のアレイ状に有する受光素子アレイ140と、を備える。さらに、第1信号線、第2信号線等、画素の情報を抽出するために必要となる配線等を備える。 (Example of board stacking)
FIG. 18 is a diagram showing an example of a case where the solid-state image sensor 1 is formed of two layers. The second substrate 20 includes an optical system 12 and a light receiving element array 140 having the light receiving elements 14 in a two-dimensional array. Further, it is provided with wiring and the like necessary for extracting pixel information such as the first signal line and the second signal line.
　第2基板20は、アナログ回路200と、ロジック回路210と、メモリ220と、入出力I/F 230と、を備える。この他、固体撮像装置1を制御するために必要な回路が備えられる。 The second board 20 includes an analog circuit 200, a logic circuit 210, a memory 220, and an input / output I / F 230. In addition, a circuit necessary for controlling the solid-state image sensor 1 is provided.
　図19は、固体撮像装置1が3層で形成される場合の一例を示す図である。第1基板10と第2基板20における要素はほぼ図18と同一である。ただし、第2基板20にはメモリが備えられておらず、第3基板40にメモリが備えられる。図19においては、第3基板40が第2基板20の下方にあるが、これには限られない。すなわち、第3基板40が第1基板10と第2基板20との間に備えられていてもよい。 FIG. 19 is a diagram showing an example of a case where the solid-state image sensor 1 is formed of three layers. The elements of the first substrate 10 and the second substrate 20 are almost the same as those in FIG. However, the second board 20 is not provided with the memory, and the third board 40 is provided with the memory. In FIG. 19, the third substrate 40 is below the second substrate 20, but is not limited to this. That is, the third substrate 40 may be provided between the first substrate 10 and the second substrate 20.
　固体撮像装置1が3層である場合にも、層間の接続は、上述の実施形態と同様であり、例えば、図15から図17に示すような接続方法により、各層間が接続される。 Even when the solid-state image sensor 1 has three layers, the connection between the layers is the same as that of the above-described embodiment. For example, the layers are connected by the connection method as shown in FIGS. 15 to 17.
　全ての実施形態は、CMOSセンサの例について説明したが、これには限られない。有機膜センサやその他の方式の受光装置にも応用できる。 All embodiments have described examples of CMOS sensors, but are not limited to this. It can also be applied to organic film sensors and other types of light receiving devices.
　固体撮像装置1は、前述の各実施形態において説明したように、複数のモードを用途、環境等に基づいて切り替えて撮像を実行する。この固体撮像装置1は、例えば、フィーチャーフォン、スマートフォン、タブレット型端末、デジタルカメラ、デジタルビデオカメラ、監視カメラ等の種々の電子機器に実装することが可能である。 As described in each of the above-described embodiments, the solid-state image sensor 1 switches a plurality of modes based on the application, environment, and the like to perform imaging. The solid-state imaging device 1 can be mounted on various electronic devices such as feature phones, smartphones, tablet terminals, digital cameras, digital video cameras, and surveillance cameras.
　固体撮像装置1において、上記の各動作を実行する回路は、それぞれ適切にアナログ回路又はデジタル回路により実装される。この回路は、例えば、その少なくとも一部がASIC(Application Specific Integrated Circuitry)等の回路で構成されてもよいし、少なくとも一部の動作が汎用のCPU(Central Processing Unit)等の回路においてソフトウェアで実装されるものであってもよい。ソフトウェアによる情報処理がハードウェア資源を用いて具体的に実現される場合には、当該ソフトウェア等に関する実行ファイル、プログラム等が記憶部に記憶されていてもよい。また、これらの回路のうち少なくとも一部は、FPGA(Field Programmable Gate Array)のようにプログラマブルな回路として実装されていてもよい。 In the solid-state image sensor 1, the circuit that executes each of the above operations is appropriately mounted by an analog circuit or a digital circuit. For example, at least a part of this circuit may be configured by a circuit such as an ASIC (Application Specific Integrated Circuitry), or at least a part of the operation may be implemented by software in a circuit such as a general-purpose CPU (Central Processing Unit). It may be what is done. When information processing by software is specifically realized by using hardware resources, an executable file, a program, or the like related to the software or the like may be stored in a storage unit. Further, at least a part of these circuits may be implemented as a programmable circuit such as an FPGA (Field Programmable Gate Array).
　前述した実施形態は、以下のような形態としてもよい。 The above-mentioned embodiment may be in the following form.
(１)
　光を光電変換してアナログ信号を出力する複数の受光素子が、第1方向に沿った列及び前記第1方向と交差する第2方向に沿った行として2次元のアレイ状に配置される、受光素子アレイを有する、第1基板と、
　前記第1基板に積層する第2基板であって、前記第1方向及び前記第2方向に交差する第3方向において、前記受光素子アレイと重なって配置され、前記受光素子から出力された前記アナログ信号を処理する、アナログ回路、を有する第2基板と、
　を備え、
　前記受光素子アレイは、
　　前記第2方向に沿った画素分割部により、それぞれが連続する前記受光素子を備える第1領域と、第2領域と、に分割され、
　前記アナログ回路は、
　　前記第3方向において前記受光素子アレイと重ならない領域に配置される第1接続部を介して前記第1領域に属する前記受光素子と接続される、第1アナログ回路と、
　　前記第3方向において前記受光素子アレイと重ならない領域に配置される第2接続部を介して前記第2領域に属する前記受光素子と接続される、第2アナログ回路と、
　を備える、
　固体撮像装置。 (1)
A plurality of light receiving elements that photoelectrically convert light and output an analog signal are arranged in a two-dimensional array as columns along the first direction and rows along the second direction intersecting the first direction. A first substrate with a light receiving element array and
A second substrate laminated on the first substrate, which is arranged so as to overlap the light receiving element array in a third direction intersecting the first direction and the second direction, and is an analog output from the light receiving element. A second board with an analog circuit, which processes the signal, and
Equipped with
The light receiving element array is
By the pixel dividing portion along the second direction, it is divided into a first region and a second region, each of which has a continuous light receiving element.
The analog circuit is
A first analog circuit connected to the light receiving element belonging to the first region via a first connecting portion arranged in a region not overlapping with the light receiving element array in the third direction.
A second analog circuit connected to the light receiving element belonging to the second region via a second connecting portion arranged in a region not overlapping with the light receiving element array in the third direction.
To prepare
Solid-state image sensor.
(２)
　前記受光素子アレイにおいて、
　　前記第2方向に連続する前記受光素子を備える前記行のうち、前記第1方向における1又は複数の前記行を選択する、前記第1方向に沿って複数配置される、第1信号線と、
　　前記第1方向に連続する前記受光素子を備える前記列のうち、前記第2方向における1又は複数の前記列を選択する、前記第2方向に沿って複数配置される、第2信号線と、
　を備え、
　前記第1信号線により選択された前記受光素子が出力する前記アナログ信号を、前記第2信号線を介して伝送して前記アナログ回路により処理し、
　前記第2信号線は、前記画素分割部において、電気的に切断される、
　(1)に記載の固体撮像装置。 (2)
In the light receiving element array
Among the rows having the light receiving element continuous in the second direction, a first signal line, which selects one or more of the rows in the first direction and is arranged along the first direction, and a first signal line.
A second signal line, which is arranged along the second direction, selects one or more of the rows having the light receiving element continuous in the first direction.
Equipped with
The analog signal output by the light receiving element selected by the first signal line is transmitted via the second signal line and processed by the analog circuit.
The second signal line is electrically cut off at the pixel dividing portion.
The solid-state image sensor according to (1).
(３)
　前記画素分割部は、前記第１方向において、前記受光素子アレイの中央付近に配置される、
　(2)に記載の固体撮像装置。 (3)
The pixel dividing portion is arranged near the center of the light receiving element array in the first direction.
The solid-state image sensor according to (2).
(４)
　前記第1接続部は、前記第1領域に属する前記第2信号線と接続し、前記第1領域に属する前記受光素子と、前記第1アナログ回路と、を接続し、
　前記第2接続部は、前記第2領域に属する前記第2信号線と接続し、前記第2領域に属する前記受光素子と、前記第2アナログ回路と、を接続する、
　(3)に記載の固体撮像装置。 (4)
The first connection portion is connected to the second signal line belonging to the first region, and the light receiving element belonging to the first region and the first analog circuit are connected to each other.
The second connection portion is connected to the second signal line belonging to the second region, and is connected to the light receiving element belonging to the second region and the second analog circuit.
The solid-state image sensor according to (3).
(５)
　前記第1接続部及び前記第2接続部は、それぞれ、前記第2方向に沿って少なくとも前記列の数だけ備えられる、
　(4)に記載の固体撮像装置。 (5)
The first connection and the second connection are each provided in at least the number of rows along the second direction.
The solid-state image sensor according to (4).
(６)
　前記第2基板は、前記受光素子から信号を出力する順番を制御する、制御回路、
　をさらに備える、(4)又は(5)に記載の固体撮像装置。 (6)
The second substrate is a control circuit that controls the order in which signals are output from the light receiving element.
The solid-state image pickup apparatus according to (4) or (5), further comprising.
(７)
　前記制御回路は、
　　前記受光素子アレイにおいて、外側に備えられる前記行から、前記画素分割部へと向かって読み出しの順番を制御する、第1読出モードと、
　　前記受光素子アレイにおいて、前記画素分割部から、外側に備えられる前記行へと向かって読み出しの順番を制御する、第2読出モードと、
　　前記受光素子アレイにおいて、第1方向の一方の端部にある前記行から、他方の端部にある前記行へと向かって読み出しの順番を制御する、第3読出モードと、
　を選択して制御する、
　(6)に記載の固体撮像装置。 (7)
The control circuit is
In the light receiving element array, a first read mode for controlling the order of reading from the row provided on the outside toward the pixel dividing portion.
In the light receiving element array, a second read mode for controlling the reading order from the pixel dividing portion toward the row provided on the outside,
In the light receiving element array, a third read mode for controlling the reading order from the row at one end in the first direction to the row at the other end.
To select and control,
The solid-state image sensor according to (6).
(８)
　前記第3読出モードの場合、前記第1アナログ回路と、前記第2アナログ回路は、排他的に駆動する、
　(7)に記載の固体撮像装置。 (8)
In the case of the third read mode, the first analog circuit and the second analog circuit are exclusively driven.
The solid-state image sensor according to (7).
(９)
　前記第2基板は、
　　前記アナログ回路が出力した信号の信号処理を実行する、信号処理回路と、
　　前記信号処理回路の出力に基づいて、露出及びフォーカスを調整するパラメータを算出する、AE/AF処理回路と、
　をさらに備え、
　前記制御回路は、前記AE/AF処理回路の出力に基づいて、前記受光素子の露出及びフォーカスを制御する、
　(7)又は(8)に記載の固体撮像装置。 (9)
The second substrate is
A signal processing circuit that executes signal processing of the signal output by the analog circuit, and
An AE / AF processing circuit that calculates parameters for adjusting exposure and focus based on the output of the signal processing circuit.
Further prepare
The control circuit controls the exposure and focus of the light receiving element based on the output of the AE / AF processing circuit.
The solid-state image sensor according to (7) or (8).
(１０)
　前記制御回路は、
　　前記AE/AF処理回路の出力に基づいて、前記第1読出モード、前記第2読出モード及び前記第3読出モードを切り替える、
　(9)に記載の固体撮像装置。 (10)
The control circuit is
The first read mode, the second read mode, and the third read mode are switched based on the output of the AE / AF processing circuit.
The solid-state image sensor according to (9).
(１１)
　前記制御回路は、
　　前記AE/AF処理回路の出力に基づいて、露出の制御及びフォーカスの制御が完了するまでは、前記第1読出モード又は前記第2読出モードを選択して制御し、
　　露出の制御及びフォーカスの制御が完了した後に、前記第3読出モードを選択して制御する、
　(10)に記載の固体撮像装置。 (11)
The control circuit is
Based on the output of the AE / AF processing circuit, the first read mode or the second read mode is selected and controlled until the exposure control and the focus control are completed.
After the exposure control and focus control are completed, the third read mode is selected and controlled.
The solid-state image sensor according to (10).
(１２)
　前記第2基板は、
　　前記アナログ回路が出力した信号の信号処理を実行する、信号処理回路と、
　　前記信号処理回路の出力に基づいて、物体認識処理を実行する、認識処理回路、
　をさらに備え、
　前記制御回路は、前記認識処理回路の出力に基づいて、前記第1読出モード、前記第2読出モード及び前記第3読出モードを切り替える、
　(7)又は(8)に記載の固体撮像装置。 (12)
The second substrate is
A signal processing circuit that executes signal processing of the signal output by the analog circuit, and
A recognition processing circuit that executes object recognition processing based on the output of the signal processing circuit.
Further prepare
The control circuit switches between the first read mode, the second read mode, and the third read mode based on the output of the recognition processing circuit.
The solid-state image sensor according to (7) or (8).
(１３)
　前記制御回路は、
　　前記認識処理回路の出力に基づいて、前記物体が検知されるまでは前記第1読出モード又は前記第2読出モードを選択して制御し、
　　前記物体が検知された後に、前記第3読出モードを選択して制御する、
　(12)に記載の固体撮像装置。 (13)
The control circuit is
Based on the output of the recognition processing circuit, the first read mode or the second read mode is selected and controlled until the object is detected.
After the object is detected, the third read mode is selected and controlled.
The solid-state image sensor according to (12).
(１４)
　前記第1アナログ回路及び前記第2アナログ回路は、前記第2方向に沿った1又は複数の前記行に属する異なる前記画素の前記アナログ信号を、同じタイミングで処理する、
　(1)から(13)のいずれかに記載の固体撮像装置。 (14)
The first analog circuit and the second analog circuit process the analog signals of one or a plurality of different pixels belonging to the row along the second direction at the same timing.
The solid-state image sensor according to any one of (1) to (13).
(１５)
　前記第1アナログ回路及び前記第2アナログ回路は、前記アナログ信号をデジタル信号へと変換し、
　前記第2基板は、前記デジタル信号を処理するロジック回路であって、前記第1アナログ回路及び前記第2アナログ回路に挟まれて配置される、ロジック回路、を備える、
　(1)に記載の固体撮像装置。 (15)
The first analog circuit and the second analog circuit convert the analog signal into a digital signal.
The second board is a logic circuit that processes the digital signal, and includes a logic circuit that is sandwiched between the first analog circuit and the second analog circuit.
The solid-state image sensor according to (1).
(１６)
　前記論理回路は、前記画素分割部と前記第3方向において重なるようにメモリを備える、
　(15)に記載の固体撮像装置。 (16)
The logic circuit includes a memory so as to overlap the pixel dividing portion in the third direction.
The solid-state image sensor according to (15).
(１７)
　複数の前記画素分割部と、
　複数の領域に分割された前記受光素子アレイの領域及びそれぞれに対応する前記アナログ回路と、
　を備える、
　(1)に記載の固体撮像装置。 (17)
The plurality of pixel dividing portions and
The regions of the light receiving element array divided into a plurality of regions, the analog circuits corresponding to the regions, and the analog circuit corresponding to each region.
To prepare
The solid-state image sensor according to (1).
(１８)
　前記第2基板は、
　　前記デジタル信号の信号処理を実行する、信号処理回路と、
　　画像情報である前記デジタル信号の画像処理を実行する、画像処理回路と、
　　前記デジタル信号、前記信号処理回路が出力したデータ、前記画像処理回路が出力したデータ、のうち任意のデータを格納する、メモリと、
　　前記信号処理回路が出力したデータ、前記画像処理回路が出力したデータ、及び、前記記憶部に格納されているデータのうち、少なくとも１つの任意のデータ若しくは任意の信号を外部へと出力し、又は、外部からデータ若しくは信号の入力を受け付ける、インタフェースと、
　を備える、(1)に記載の固体撮像装置。 (18)
The second substrate is
A signal processing circuit that executes signal processing of the digital signal, and
An image processing circuit that executes image processing of the digital signal, which is image information, and
A memory for storing arbitrary data among the digital signal, the data output by the signal processing circuit, and the data output by the image processing circuit.
Of the data output by the signal processing circuit, the data output by the image processing circuit, and the data stored in the storage unit, at least one arbitrary data or any signal is output to the outside, or An interface that accepts data or signal input from the outside,
The solid-state image sensor according to (1).
(１９)
　(1)から(18)のいずれかに記載の固体撮像装置を備える、電子機器。 (19)
An electronic device comprising the solid-state image sensor according to any one of (1) to (18).
(２０)
　スマートフォン、タブレット型端末、デジタルカメラ、又は、デジタルビデオカメラである、(19)に記載の電子機器。 (20)
The electronic device according to (19), which is a smartphone, a tablet terminal, a digital camera, or a digital video camera.
　本開示の態様は、前述した実施形態に限定されるものではなく、想到しうる種々の変形も含むものであり、本開示の効果も前述の内容に限定されるものではない。各実施形態における構成要素は、適切に組み合わされて適用されてもよい。すなわち、特許請求の範囲に規定された内容及びその均等物から導き出される本開示の概念的な思想と趣旨を逸脱しない範囲で種々の追加、変更及び部分的削除が可能である。 The aspect of the present disclosure is not limited to the above-mentioned embodiment, but also includes various possible modifications, and the effect of the present disclosure is not limited to the above-mentioned contents. The components in each embodiment may be applied in appropriate combinations. That is, various additions, changes and partial deletions are possible without departing from the conceptual idea and purpose of the present disclosure derived from the contents specified in the claims and their equivalents.
1:固体撮像装置、
10:第1基板、
12:光学系、14:受光素子、
140:受光素子アレイ、141:第1領域、142:第2領域、143:画素分割部、
16:第1信号線、181、182:第2信号線、
20:第2基板、
22:信号処理回路、24:制御回路、26:AE/AF処理回路、28:認識処理回路、
200:アナログ回路、201:第1アナログ回路、202:第2アナログ回路、203:第3アナログ回路、204:第4アナログ回路、210:ロジック回路、
220:メモリ、230:入出力I/F
30:接続部、
301:第1接続部、302:第2接続部 1: Solid-state image sensor,
10: 1st board,
12: Optical system, 14: Light receiving element,
140: Light receiving element array, 141: 1st area, 142: 2nd area, 143: Pixel dividing part,
16: 1st signal line, 181, 182: 2nd signal line,
20: 2nd board,
22: Signal processing circuit, 24: Control circuit, 26: AE / AF processing circuit, 28: Recognition processing circuit,
200: Analog circuit, 201: 1st analog circuit, 202: 2nd analog circuit, 203: 3rd analog circuit, 204: 4th analog circuit, 210: Logic circuit,
220: Memory, 230: I / O I / F
30: Connection,
301: 1st connection, 302: 2nd connection

Claims (19)

  1. 　光を光電変換してアナログ信号を出力する複数の受光素子が、第1方向に沿った列及び前記第1方向と交差する第2方向に沿った行として2次元のアレイ状に配置される、受光素子アレイを有する、第1基板と、
    　前記第1基板に積層する第2基板であって、前記第1方向及び前記第2方向に交差する第3方向において、前記受光素子アレイと重なって配置され、前記受光素子から出力された前記アナログ信号を処理する、アナログ回路、を有する第2基板と、
    　を備え、
    　前記受光素子アレイは、
    　　前記第2方向に沿った画素分割部により、前記受光素子を備える第1領域と、第2領域と、に分割され、
    　　前記第2方向に沿って備えられる前記受光素子が属する前記行のうち、前記第1方向における1又は複数の前記行を選択する、前記第1方向に沿って複数配置される第1信号線と、
    　　前記第1方向に沿って備えられる前記受光素子が属する前記列のうち、前記第2方向における1又は複数の前記列を選択する、前記第2方向に沿って複数配置され、前記画素分割部において電気的に切断される、第2信号線と、
    　を備え、
    　前記アナログ回路は、
    　　前記第1信号線により選択された前記受光素子が出力し、前記第2信号線を介して伝送された前記アナログ信号を処理する回路であって、
    　　前記第3方向において前記受光素子アレイと重ならない領域に配置される第1接続部を介して前記第1領域に属する前記受光素子と接続される、第1アナログ回路と、
    　　前記第3方向において前記受光素子アレイと重ならない領域に配置される第2接続部を介して前記第2領域に属する前記受光素子と接続される、第2アナログ回路と、
    　を備える、
    　固体撮像装置。     A plurality of light receiving elements that photoelectrically convert light and output an analog signal are arranged in a two-dimensional array as columns along the first direction and rows along the second direction intersecting the first direction. A first substrate with a light receiving element array and
    A second substrate laminated on the first substrate, which is arranged so as to overlap the light receiving element array in a third direction intersecting the first direction and the second direction, and is an analog output from the light receiving element. A second board with an analog circuit, which processes the signal, and
    Equipped with
    The light receiving element array is
    It is divided into a first region and a second region including the light receiving element by the pixel dividing portion along the second direction.
    A plurality of first signal lines arranged along the first direction for selecting one or more of the rows to which the light receiving element provided along the second direction belongs. ,
    A plurality of the rows to which the light receiving element provided along the first direction belongs, one or a plurality of the rows in the second direction are selected, and a plurality of the rows are arranged along the second direction, and the pixel division portion is used. The second signal line, which is electrically disconnected,
    Equipped with
    The analog circuit is
    A circuit that processes the analog signal output by the light receiving element selected by the first signal line and transmitted via the second signal line.
    A first analog circuit connected to the light receiving element belonging to the first region via a first connecting portion arranged in a region not overlapping with the light receiving element array in the third direction.
    A second analog circuit connected to the light receiving element belonging to the second region via a second connecting portion arranged in a region not overlapping with the light receiving element array in the third direction.
    To prepare
    Solid-state image sensor.
  2. 　前記画素分割部は、前記第１方向において、前記受光素子アレイの中央付近に配置される、
    　請求項1に記載の固体撮像装置。     The pixel dividing portion is arranged near the center of the light receiving element array in the first direction.
    The solid-state image sensor according to claim 1.
  3. 　前記第1接続部は、前記第1領域に属する前記第2信号線と接続し、前記第1領域に属する前記受光素子と、前記第1アナログ回路と、を接続し、
    　前記第2接続部は、前記第2領域に属する前記第2信号線と接続し、前記第2領域に属する前記受光素子と、前記第2アナログ回路と、を接続する、
    　請求項2に記載の固体撮像装置。     The first connection portion is connected to the second signal line belonging to the first region, and the light receiving element belonging to the first region and the first analog circuit are connected to each other.
    The second connection portion is connected to the second signal line belonging to the second region, and is connected to the light receiving element belonging to the second region and the second analog circuit.
    The solid-state image sensor according to claim 2.
  4. 　前記第1接続部及び前記第2接続部は、それぞれ、前記第2方向に沿って少なくとも前記列の数だけ備えられる、
    　請求項3に記載の固体撮像装置。     The first connection and the second connection are each provided in at least the number of rows along the second direction.
    The solid-state image sensor according to claim 3.
  5. 　前記第2基板は、前記受光素子から信号を出力する順番を制御する、制御回路、
    　をさらに備える、請求項3記載の固体撮像装置。     The second substrate is a control circuit that controls the order in which signals are output from the light receiving element.
    3. The solid-state image sensor according to claim 3.
  6. 　前記制御回路は、
    　　前記受光素子アレイにおいて、外側に備えられる前記行から、前記画素分割部へと向かって読み出しの順番を制御する、第1読出モードと、
    　　前記受光素子アレイにおいて、前記画素分割部から、外側に備えられる前記行へと向かって読み出しの順番を制御する、第2読出モードと、
    　　前記受光素子アレイにおいて、第1方向の一方の端部にある前記行から、他方の端部にある前記行へと向かって読み出しの順番を制御する、第3読出モードと、
    　を選択して制御する、
    　請求項5に記載の固体撮像装置。     The control circuit is
    In the light receiving element array, a first read mode for controlling the order of reading from the row provided on the outside toward the pixel dividing portion.
    In the light receiving element array, a second read mode for controlling the reading order from the pixel dividing portion toward the row provided on the outside,
    In the light receiving element array, a third read mode for controlling the reading order from the row at one end in the first direction to the row at the other end.
    To select and control,
    The solid-state image sensor according to claim 5.
  7. 　前記第3読出モードの場合、前記第1アナログ回路と、前記第2アナログ回路は、排他的に駆動する、
    　請求項6に記載の固体撮像装置。     In the case of the third read mode, the first analog circuit and the second analog circuit are exclusively driven.
    The solid-state image sensor according to claim 6.
  8. 　前記第2基板は、
    　　前記アナログ回路が出力した信号の信号処理を実行する、信号処理回路と、
    　　前記信号処理回路の出力に基づいて、露出及びフォーカスを調整するパラメータを算出する、AE/AF処理回路と、
    　をさらに備え、
    　前記制御回路は、前記AE/AF処理回路の出力に基づいて、前記受光素子の露出及びフォーカスを制御する、
    　請求項6に記載の固体撮像装置。     The second substrate is
    A signal processing circuit that executes signal processing of the signal output by the analog circuit, and
    An AE / AF processing circuit that calculates parameters for adjusting exposure and focus based on the output of the signal processing circuit.
    Further prepare
    The control circuit controls the exposure and focus of the light receiving element based on the output of the AE / AF processing circuit.
    The solid-state image sensor according to claim 6.
  9. 　前記制御回路は、
    　　前記AE/AF処理回路の出力に基づいて、前記第1読出モード、前記第2読出モード及び前記第3読出モードを切り替える、
    　請求項8に記載の固体撮像装置。     The control circuit is
    The first read mode, the second read mode, and the third read mode are switched based on the output of the AE / AF processing circuit.
    The solid-state image sensor according to claim 8.
  10. 　前記制御回路は、
    　　前記AE/AF処理回路の出力に基づいて、露出の制御及びフォーカスの制御が完了するまでは、前記第1読出モード又は前記第2読出モードを選択して制御し、
    　　露出の制御及びフォーカスの制御が完了した後に、前記第3読出モードを選択して制御する、
    　請求項9に記載の固体撮像装置。     The control circuit is
    Based on the output of the AE / AF processing circuit, the first read mode or the second read mode is selected and controlled until the exposure control and the focus control are completed.
    After the exposure control and focus control are completed, the third read mode is selected and controlled.
    The solid-state image sensor according to claim 9.
  11. 　前記第2基板は、
    　　前記アナログ回路が出力した信号の信号処理を実行する、信号処理回路と、
    　　前記信号処理回路の出力に基づいて、物体の認識処理を実行する、認識処理回路、
    　をさらに備え、
    　前記制御回路は、前記認識処理回路の出力に基づいて、前記第1読出モード、前記第2読出モード及び前記第3読出モードを切り替える、
    　請求項6に記載の固体撮像装置。     The second substrate is
    A signal processing circuit that executes signal processing of the signal output by the analog circuit, and
    A recognition processing circuit that executes object recognition processing based on the output of the signal processing circuit.
    Further prepare
    The control circuit switches between the first read mode, the second read mode, and the third read mode based on the output of the recognition processing circuit.
    The solid-state image sensor according to claim 6.
  12. 　前記制御回路は、
    　　前記認識処理回路の出力に基づいて、前記物体が検知されるまでは前記第1読出モード又は前記第2読出モードを選択して制御し、
    　　前記物体が検知された後に、前記第3読出モードを選択して制御する、
    　請求項11に記載の固体撮像装置。     The control circuit is
    Based on the output of the recognition processing circuit, the first read mode or the second read mode is selected and controlled until the object is detected.
    After the object is detected, the third read mode is selected and controlled.
    The solid-state image sensor according to claim 11.
  13. 　前記第1アナログ回路及び前記第2アナログ回路は、前記第2方向に沿った1又は複数の前記行に属する異なる前記受光素子の前記アナログ信号を、同じタイミングで処理する、
    　請求項1に記載の固体撮像装置。     The first analog circuit and the second analog circuit process the analog signals of different light receiving elements belonging to one or more of the rows along the second direction at the same timing.
    The solid-state image sensor according to claim 1.
  14. 　前記第1アナログ回路及び前記第2アナログ回路は、前記アナログ信号をデジタル信号へと変換し、
    　前記第2基板は、前記デジタル信号を処理するロジック回路であって、前記第1アナログ回路及び前記第2アナログ回路に挟まれて配置される、ロジック回路、を備える、
    　請求項1に記載の固体撮像装置。     The first analog circuit and the second analog circuit convert the analog signal into a digital signal.
    The second board is a logic circuit that processes the digital signal, and includes a logic circuit that is arranged between the first analog circuit and the second analog circuit.
    The solid-state image sensor according to claim 1.
  15. 　前記ロジック回路は、前記画素分割部と前記第3方向において重なるようにメモリを備える、
    　請求項14に記載の固体撮像装置。     The logic circuit includes a memory so as to overlap the pixel dividing portion in the third direction.
    The solid-state image sensor according to claim 14.
  16. 　複数の前記画素分割部と、
    　複数の領域に分割された前記受光素子アレイの領域及びそれぞれに対応する前記アナログ回路と、
    　を備える、
    　請求項1に記載の固体撮像装置。     The plurality of pixel dividing portions and
    The regions of the light receiving element array divided into a plurality of regions, the analog circuits corresponding to the regions, and the analog circuit corresponding to each region.
    To prepare
    The solid-state image sensor according to claim 1.
  17. 　前記第2基板は、
    　　処理された前記アナログ信号の信号処理を実行する、信号処理回路と、
    　　画像情報である処理された前記アナログ信号の画像処理を実行する、画像処理回路と、
    　　処理された前記アナログ信号、前記信号処理回路が出力したデータ、前記画像処理回路が出力したデータ、のうち任意のデータを格納する、メモリと、
    　　前記信号処理回路が出力したデータ、前記画像処理回路が出力したデータ、及び、前記メモリに格納されているデータのうち、少なくとも１つの任意のデータ若しくは任意の信号を外部へと出力し、又は、外部からデータ若しくは信号の入力を受け付ける、インタフェースと、
    　を備える、請求項1に記載の固体撮像装置。     The second substrate is
    A signal processing circuit that executes signal processing of the processed analog signal, and
    An image processing circuit that executes image processing of the processed analog signal, which is image information, and
    A memory for storing arbitrary data among the processed analog signal, the data output by the signal processing circuit, and the data output by the image processing circuit.
    Of the data output by the signal processing circuit, the data output by the image processing circuit, and the data stored in the memory, at least one arbitrary data or any signal is output to the outside, or An interface that accepts data or signal input from the outside,
    The solid-state image sensor according to claim 1.
  18. 　請求項1に記載の固体撮像装置を備える、電子機器。 An electronic device provided with the solid-state image sensor according to claim 1.
  19. 　スマートフォン、タブレット型端末、デジタルカメラ、又は、デジタルビデオカメラである、請求項18に記載の電子機器。 The electronic device according to claim 18, which is a smartphone, a tablet terminal, a digital camera, or a digital video camera.
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