JP2018078630A - Image pickup device and imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a circuit area involved in CDS and increase the CDS accuracy.SOLUTION: There is provided an image pickup device comprising: a photoelectric element which accumulates an electric charge according to a quantity of received light; a read line for sending signals according to the electric charge accumulated by the photoelectric element; a capacitor which is charged/discharged with a voltage according to a quantity of electric charge accumulated by the photoelectric element; a switch part operable to cause the state of the capacitor to transition to a first state in which a predetermined reference voltage is applied to a first electrode of the capacitor while a feedthrough voltage of the photoelectric element is applied to a second electrode of the capacitor, and a second state in which a voltage between the electrodes of the capacitor in the first state is kept while a signal voltage of the photoelectric element is applied to the second electrode; and a transmission part operable to control about whether or not to transmit a voltage of the first electrode of the capacitor to the read line.SELECTED DRAWING: Figure 3

Description

  The present invention relates to an imaging element and an imaging apparatus.

2. Description of the Related Art Conventionally, in a global shutter type imaging apparatus, an imaging apparatus is known in which two capacitors are provided in each pixel and correlated double sampling (CDS) is performed by pipeline processing (see, for example, Patent Document 1 and FIG. 9).
Patent Document 1 US Patent Application Publication No. 2012/193516

  However, the conventional imaging device uses two capacitors for correlated double sampling in each pixel. For this reason, the arrangement area of the circuit which performs the correlated double sampling provided for every pixel becomes large. In addition, since the feedthrough voltage and the signal voltage are held by different capacitors, errors due to variations in the capacitors occur. Moreover, in the circuit disclosed in Patent Document 1, gain loss occurs during the charge operation to C2. Specifically, the gain becomes half.

  In the first aspect of the present invention, a photoelectric element that accumulates charges according to the amount of received light, a readout line that transmits a signal according to the charges accumulated by the photoelectric elements, and a charge according to the amount of charges accumulated in the photoelectric elements A capacitor that is charged and discharged with a voltage, and a first state in which a predetermined reference voltage is applied to the first electrode of the capacitor while a feedthrough voltage of the photoelectric element is applied to the second electrode of the capacitor. , While maintaining the voltage between the electrodes of the capacitor in the first state, the switch unit for transitioning to the second state in which the signal voltage of the photoelectric element is applied to the second electrode, and the voltage of the first electrode of the capacitor to the readout line An image sensor including a transfer unit that controls whether or not to transfer is provided.

  According to a second aspect of the present invention, there is provided an imaging apparatus including the imaging element according to the first aspect.

  It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

1 is a diagram illustrating an overview of an image sensor 100 according to one embodiment. FIG. 3 is a diagram illustrating an outline of a light receiving unit 200 and a reading unit 210. It is a figure which shows the structural example of the pixel 202 which concerns on 1st Example. 4 is a timing chart illustrating an operation example of the pixel 202 illustrated in FIG. 3. It is a figure which shows the structural example of the pixel 202 which concerns on 2nd Example. 6 is a timing chart illustrating an operation example of the pixel 202 illustrated in FIG. 5. It is a figure which shows the structural example of the pixel 202 which concerns on 3rd Example. 8 is a timing chart illustrating an operation example of the pixel 202 illustrated in FIG. 7. 1 is a diagram illustrating an example of a cross section of an image sensor 100. FIG. It is a block diagram which shows the structural example of the imaging device 500 which concerns on one embodiment.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

  FIG. 1 is a diagram illustrating an overview of an image sensor 100 according to one embodiment. The image sensor 100 includes a light receiving unit 200 in which a plurality of pixels 202 are arranged, and a reading unit 210 that reads out pixel values of the pixels 202 that are sequentially selected. Each of the plurality of pixels 202 has a photoelectric element such as a photodiode, and accumulates electric charges according to the amount of received light. The reading unit 210 in this example reads the amount of charge accumulated in each pixel 202 and calculates the pixel value of each pixel 202.

  The plurality of pixels 202 in this example are arranged in a matrix. That is, the plurality of pixels 202 are arranged along a plurality of rows and a plurality of columns. In the present specification, the row direction is illustrated as the x-axis direction, and the column direction is illustrated as the y-axis direction. In addition, the reading unit 210 of this example selects the pixels 202 from which pixel values are read out in units of rows. The reading unit 210 of this example simultaneously reads the pixel values of the pixels 202 belonging to the selected row.

  FIG. 2 is a diagram illustrating an outline of the light receiving unit 200 and the reading unit 210. The light receiving unit 200 of this example includes a plurality of pixels 202 arranged in a matrix. In FIG. 2, some pixels 202 are shown, and other pixels 202 are omitted.

  A plurality of pixels 202 included in one column are connected to a common readout line 204. The readout line 204 transmits the output value in the selected pixel 202 to the readout unit 210 in order. A plurality of pixels 202 included in one row are connected to a common control line 206. The control line 206 controls the operation of the pixel 202 such as a reset timing for resetting the charge amount accumulated in the pixel 202 and a readout timing for outputting the pixel value of the pixel 202 to the readout line 204.

  The reading unit 210 includes a plurality of AD converters 212 and a plurality of CDS units 216. The AD converter 212 and the CDS unit 216 are provided for each column of the pixels 202. Each AD converter 212 is connected to a corresponding readout line 204. The AD converter 212 takes the output value of the selected pixel 202 out of the corresponding plurality of pixels 202 and converts it into a digital value.

  The CDS unit 216 generates a result of correlated double sampling of the output value of the corresponding pixel 202 based on the output of the corresponding AD converter 212. For example, the AD converter 212 sequentially detects the feedthrough voltage and the signal voltage in the pixel 202. The CDS unit 216 calculates a difference between the feedthrough voltage detected by the corresponding AD converter 212 and the signal voltage as a pixel value in the pixel 202. The reading unit 210 may include a memory that stores the pixel values calculated by the CDS unit 216.

  In FIG. 2, the reading unit 210 is disposed below the light receiving unit 200, but the position of the reading unit 210 is not limited to the lower side of the light receiving unit 200. The reading unit 210 may be provided in the same layer as the light receiving unit 200 in a distributed manner on all sides of the light receiving unit 200. Further, the reading unit 210 may be provided in a different layer from the light receiving unit 200.

  FIG. 3 is a diagram illustrating a configuration example of the pixel 202 according to the first embodiment. However, FIG. 3 shows two pixels 202 in FIG. The two pixels 202 are included in the same column. Each pixel 202 has a photoelectric element 214 and a selection transistor 61 individually. The photoelectric element 214 accumulates charges corresponding to the amount of received light. The selection transistor 61 is connected to the cathode of the corresponding photoelectric element 214 and switches whether to output a voltage corresponding to the amount of charge accumulated in the photoelectric element 214. The selection transistor 61 is controlled by a pixel selection signal given from the control line 206.

  Each pixel 202 has a reset transistor 59, an amplification transistor 60, a ground side transistor 65, a first transistor 78, a second transistor 63, an amplification transistor 66, a transfer transistor 64, and a capacitor 10 in common. The transistor provided in common functions as a switch unit that controls the state of the capacitor 10 (a state indicating what voltage is applied to both electrodes). The pixel 202 of this example holds the feedthrough voltage and the signal voltage at the output of each photoelectric element 214 in order by one capacitor 10. Thereby, the area of the CDS circuit of each pixel 202 can be reduced while providing the circuit for CDS in each pixel 202. In addition, since the feedthrough voltage and the signal voltage are held by the common capacitor 10, the pixel value can be detected with high accuracy.

  The reset transistor 59 is connected to the photoelectric element 214 via each selection transistor 61. The reset transistor 59 switches whether to connect the cathode of the photoelectric element 214 to the reference voltage VCC. The reset transistor 59 is controlled by a reset signal RST given from the control line 206.

  The gate of the amplification transistor 60 is connected to the photoelectric element 214 via each selection transistor 61. The amplification transistor 60 amplifies the voltage output from the photoelectric element 214 selected by the selection transistor 61. The amplification transistor 60 is provided between the reference voltage VCC and the ground potential. A ground side transistor 65 is provided between the amplification transistor 60 and the ground potential.

  The capacitor 10 is charged and discharged with a voltage corresponding to the amount of charge accumulated in the photoelectric element 214. The capacitor 10 of this example is a three-terminal capacitor having three electrodes. The first electrode and the second electrode are arranged to face each other, and the second electrode and the third electrode are arranged to face each other. The first electrode of the capacitor 10 is connected to the reference voltage VCC via the first transistor 78. The first transistor 78 functions as a first switch that switches whether to apply a reference voltage to the first electrode. The second electrode of the capacitor 10 is connected to the output terminal of the amplification transistor 60 through the second transistor 63. The second transistor 63 functions as a second switch for switching whether to connect the output of the photoelectric element 214 (in this example, the output amplified by the amplification transistor 60) to the second electrode. The first transistor 78 and the second transistor 63 are controlled by a first control signal SH1 and a second control signal SH2 provided from the control line 206. The third electrode of the capacitor 10 is connected to the reference potential. Due to the capacitance between the second electrode and the third electrode, the potential of the second electrode with respect to the reference potential is maintained. The capacitor 10 is formed by overlapping three electrodes at the same position. As a result, the area does not increase compared to a two-terminal capacitor. Capacitor 10 may be composed of a two-terminal capacitor provided between point B and point C, and a two-terminal capacitor provided between point B and the reference potential.

  The amplification transistor 66 amplifies and outputs the voltage at the first electrode of the capacitor 10. The transfer transistor 64 functions as a transfer unit that switches whether to transfer the voltage output from the amplification transistor 66 to the readout line 204. The transfer transistor 64 is controlled by a row selection signal SEL provided from the control line 206.

  The reading unit 210 controls each signal transmitted to the control line 206 to change the state of the capacitor 10 between the first state in which the feedthrough voltage is applied to the second electrode and the signal voltage to the second electrode. To the second state in turn. The reading unit 210 turns on the transfer transistor 64 at least in the second state, and transfers the voltage level of the first electrode of the capacitor 10 to the reading unit 210. The reading unit 210 calculates a pixel value based on the transferred voltage level.

  FIG. 4 is a timing chart showing an operation example of the pixel 202 shown in FIG. In FIG. 4, as shown in FIG. 3, signals at point A corresponding to the output terminal of the amplification transistor 60, point B corresponding to the second electrode of the capacitor 10, and point C corresponding to the first electrode of the capacitor 10. Waveform is shown.

  First, the output of the photoelectric element 214-1 is read. At this time, the reset signal RST becomes H level, and the reset transistor 59 is turned on. The selection transistor 61-1 is controlled to be in an on state. Thereby, the cathode voltage of the photoelectric element 214-1 is reset, and the voltage at the point A becomes the reference voltage VCC. The amplification factor in the amplification transistors 60 and 66 is 1.

  When a predetermined time elapses after resetting, the voltage at point A becomes the feedthrough voltage Vft. The reading unit 210 sets the first control signal SH1 and the second control signal SH2 to the H level after a predetermined time has elapsed after receiving the reset signal RST. As a result, both the first transistor 78 and the second transistor 63 are turned on. At this time, the reference voltage VCC is applied to the first electrode (point C) of the capacitor 10, and the feedthrough voltage Vft is applied to the second electrode (point B) (first state).

  Next, the first control signal SH1 and the second control signal SH2 are set to L level. Thereby, the 1st electrode of the capacitor | condenser 10 will be in a floating state, and the voltage between electrodes of the capacitor | condenser 10 is maintained. Then, at the timing when the light reception of the frame by the photoelectric element 214-1 is completed, the voltage at the point A becomes a voltage according to the voltage sig1 according to the accumulated charge amount in the photoelectric element 214-1. Specifically, the voltage is lower than the feedthrough voltage Vft by the voltage sig1.

  Then, the second control signal SH2 is set to the H level while maintaining the first control signal SH1 at the L level. As a result, the second transistor 63 is turned on (second state). When the capacitor 10 transitions to the second state, the first control signal SH1 is maintained at the L level, so the first electrode is in a floating state. Thereby, the signal voltage output from the photoelectric element 214-1 is applied to the second electrode while maintaining the voltage between the electrodes of the capacitor 10 in the first state. Since the voltage of the second electrode is decreased by the voltage sig1 compared to the first state, the voltage of the first electrode is also decreased by the voltage sig1 compared to the first state.

  The reading unit 210 reads the voltage of the first electrode (point C) at least in the second state. In addition, since the voltage of the 1st electrode in a 1st state is the reference voltage VCC, when the said reference voltage is known, the reading part 210 does not need to read the voltage of the 1st electrode in a 1st state. In this case, the reading unit 210 detects the voltage sig1 by subtracting the voltage of the first electrode in the second state from the known reference voltage VCC. The reading unit 210 may correct the value of the known reference voltage VCC according to the temperature of the image sensor 100 or the like. Note that the reading unit 210 may read the voltage of the first electrode (point C) and calculate the difference in each of the first state and the second state. As a result, the voltage sig1, that is, the pixel value corresponding to the accumulated charge amount in the photoelectric element 214-1 is calculated.

  Next, the output of the photoelectric element 214-2 is read out. At this time, the reset signal RST becomes H level, and the reset transistor 59 is turned on. The selection transistor 61-2 is controlled to be in an on state. Thereby, the cathode voltage of the photoelectric element 214-2 is reset, and the voltage at the point A becomes the reference voltage VCC. The subsequent operation is the same as that of the photoelectric element 214-1. The reading unit 210 calculates a voltage sig2 corresponding to the amount of accumulated charge in the photoelectric element 214-2 based on the voltage read in the second state.

  With such a configuration and operation, correlated double sampling can be performed on the output of the photoelectric element 214 using a single capacitor 10. As a result, the circuit area can be reduced, and errors due to capacitor variations can be eliminated. Further, in this embodiment, since the two photoelectric elements 214 share one capacitor 10 and the peripheral switch portion, the circuit area can be further reduced.

  The capacitor 10 and the switch unit are provided corresponding to each photoelectric element 214. However, as shown in FIG. 3, a set of capacitors 10 and a switch unit may be provided in common for a plurality of photoelectric elements 214, and a set of capacitors 10 and a switch unit for one photoelectric element 214. May be provided. The switch unit is provided for each capacitor 10. When the capacitor 10 is shared by two or more photoelectric elements 214, the capacitor 10 holds the output value of each photoelectric element 214 in order. The plurality of capacitors 10 simultaneously hold the output values of the corresponding photoelectric elements 214.

  FIG. 5 is a diagram illustrating a configuration example of the pixel 202 according to the second embodiment. The pixel 202 according to the second embodiment includes two second transistors 63 (63-1, 63-2). 5 illustrates an example in which a set of the capacitor 10 and the switch unit is provided for one photoelectric element 214. Similarly to the example illustrated in FIG. A set of capacitors 10 and a switch unit may be provided.

  In the pixel 202 of this example, two second transistors 63-1 and 63-2 are provided in parallel between the second electrode of the capacitor 10 and the output terminal of the amplification transistor 60. The first control signal SH1 is commonly applied to the gates of the first transistor 78 and the second transistor 63-1, and the second control signal SH2 is applied to the gate of the second transistor 63-2. Other configurations are the same as those of the pixel 202 according to the first embodiment shown in FIG.

  FIG. 6 is a timing chart showing an operation example of the pixel 202 shown in FIG. For the pixel 202 of this example, in the first state (the voltage at the point A indicates the feedthrough voltage), only the first control signal SH1 is at the H level and the second control signal SH2 is at the L level.

  In this example, the first control signal SH1 is applied in common to the first transistor 78 and the second transistor 63-1. Therefore, in the first state, the first transistor 78 and the second transistor 63-1 are turned on. Therefore, the voltage at the point B is the feedthrough voltage Vft, and the voltage at the Cth is the reference voltage VCC.

  In the second state (the voltage at point A indicates the signal voltage), the second control signal SH2 is at the H level, and the first control signal SH1 is at the L level. For this reason, the first transistor 78 is turned off and the second transistor 63-2 is turned on. Accordingly, the voltage at the point B decreases according to the amount of accumulated charge (voltage sig), and accordingly, the voltage at the point C also decreases according to the voltage sig. Other operations are the same as those in the timing chart shown in FIG.

  Even with such a configuration and operation, correlated double sampling can be performed on the output of the photoelectric element 214 using a single capacitor 10. As a result, the circuit area can be reduced, and errors due to capacitor variations can be eliminated. The plurality of capacitors 10 simultaneously hold the output values of the corresponding photoelectric elements 214. Further, the charges accumulated in the respective photoelectric elements 214 may be simultaneously reset. That is, the image sensor 100 can operate in a global shutter system in which the charge reset timing in each photoelectric element 214 and the holding timing for holding the voltage corresponding to the accumulated charge amount in the capacitor 10 are simultaneous.

  FIG. 7 is a diagram illustrating a configuration example of the pixel 202 according to the third embodiment. 7 illustrates an example in which a set of the capacitor 10 and the switch unit is provided for one photoelectric element 214. Like the example illustrated in FIG. 3, for two or more photoelectric elements 214, A set of capacitors 10 and a switch unit may be provided.

  In the pixel 202 according to the third example, the first transistor 78 is provided in parallel with the capacitor 10. That is, the source and drain of the first transistor 78 are connected to the corresponding electrodes of the capacitor 10. The first transistor 78 switches whether to connect the first electrode and the second electrode of the capacitor 10. In this example, the feedthrough voltage Vft is used as the reference voltage applied to the first electrode of the capacitor 10. Other configurations are the same as those of the pixel 202 according to the first embodiment shown in FIG.

  FIG. 8 is a timing chart showing an operation example of the pixel 202 shown in FIG. The reset signal, the first control signal SH1, and the second control signal SH2 in this example are the same as the reset signal, the first control signal SH1, and the second control signal SH2 in the first embodiment shown in FIG.

  In this example, the first transistor 78 is provided in parallel with the capacitor 10. For this reason, in the first state, the feedthrough voltage Vft is applied to the first electrode (point C) of the capacitor 10. Other operations are the same as those of the first embodiment shown in FIG.

  Even with such a configuration and operation, correlated double sampling can be performed on the output of the photoelectric element 214 using a single capacitor 10. As a result, the circuit area can be reduced, and errors due to capacitor variations can be eliminated.

  FIG. 9 is a diagram illustrating an example of a cross section of the image sensor 100. In this example, the back-illuminated image sensor 100 is shown, but the image sensor 100 is not limited to the back-illuminated image sensor. In this example, the multilayer image sensor 100 is shown, but the image sensor 100 may not be a multilayer image sensor. The imaging device 100 of this example includes an imaging chip 113 that outputs a signal corresponding to incident light, a signal processing chip 111 that processes a signal from the imaging chip 113, and a memory that stores image data processed by the signal processing chip 111. Chip 112. The imaging chip 113, the signal processing chip 111, and the memory chip 112 are stacked, and are electrically connected to each other by a conductive bump 109 such as Cu.

  As shown in the figure, incident light is incident mainly in the direction indicated by the white arrow. In the present embodiment, in the imaging chip 113, the surface on the side where incident light is incident is referred to as a back surface. An example of the imaging chip 113 is a back-illuminated MOS image sensor. The imaging chip 113 corresponds to the light receiving unit 200. The PD (photodiode) layer 106 is disposed on the back side of the wiring layer 108. The PD layer 106 includes a plurality of PD sections 104 that are two-dimensionally arranged and accumulate charges corresponding to incident light, and transistors 105 that are provided corresponding to the PD sections 104. In this example, one PD unit 104 is provided for one pixel 202. The transistor 105 may correspond to each transistor described in FIGS.

  Some transistors may be provided in the imaging chip 113 and other transistors may be provided in the signal processing chip 111. Thereby, the number of transistors provided in the imaging chip 113 can be reduced and the light receiving region can be enlarged. For example, the reset transistor 59, the amplification transistor 60, and the selection transistor 61 described in FIGS. 3, 5, and 7 are provided in the imaging chip 113 as the transistor 105, and other transistors are provided in the signal processing chip 111. The capacitor 10 is provided in the signal processing chip 111.

  A color filter 102 is provided on the incident side of incident light in the PD layer 106 via a passivation film 103. The color filter 102 has a plurality of types that transmit different wavelength regions, and has a specific arrangement corresponding to each of the PD units 104. The arrangement of the color filter 102 will be described later. A set of the color filter 102, the PD unit 104, and the plurality of transistors 105 forms one pixel 202. By controlling on / off of the plurality of transistors 105, the readout timing of each pixel 202, the light reception start timing (reset timing), and the like are controlled.

  On the incident light incident side of the color filter 102, a microlens 101 is provided corresponding to each pixel. The microlens 101 condenses incident light toward the corresponding PD unit 104.

  The wiring layer 108 includes a wiring 107 that transmits a signal from the PD layer 106 to the signal processing chip 111. The wiring 107 corresponds to the readout line 204 and the control line 206 shown in FIG. The wiring 107 may be multilayer, and a passive element and an active element may be provided. The signal processing chip 111 of this example includes a reading unit 210.

  A plurality of bumps 109 are disposed on the surface of the wiring layer 108. The plurality of bumps 109 are aligned with the plurality of bumps 109 provided on the opposing surfaces of the signal processing chip 111, and the imaging chip 113 and the signal processing chip 111 are pressed and aligned. The bumps 109 are joined and electrically connected.

  Similarly, a plurality of bumps 109 are disposed on the mutually facing surfaces of the signal processing chip 111 and the memory chip 112. The bumps 109 are aligned with each other, and the signal processing chip 111 and the memory chip 112 are pressurized, so that the aligned bumps 109 are joined and electrically connected.

  The bonding between the bumps 109 is not limited to Cu bump bonding by solid phase diffusion, and micro bump bonding by solder melting may be employed. Further, about one bump 109 may be provided for one unit block described later. Therefore, the size of the bump 109 may be larger than the pitch of the PD unit 104. Further, a bump larger than the bump 109 corresponding to the imaging region may be provided in a peripheral region other than the imaging region where the pixels are arranged.

  The signal processing chip 111 has a TSV (silicon through electrode) 110 that connects circuits provided on the front and back surfaces to each other. The TSV 110 is preferably provided in the peripheral area. The TSV 110 may also be provided in the peripheral area of the imaging chip 113 and the memory chip 112.

  FIG. 10 is a block diagram illustrating a configuration example of the imaging apparatus 500 according to an embodiment. The imaging apparatus 500 includes a photographic lens 520 as a photographic optical system, and the photographic lens 520 guides a subject luminous flux incident along the optical axis OA to the imaging element 100. The photographing lens 520 may be an interchangeable lens that can be attached to and detached from the imaging apparatus 500. The imaging apparatus 500 mainly includes an imaging device 100, a system control unit 501, a drive unit 502, a photometry unit 503, a work memory 504, a recording unit 505, a display unit 506, and a drive unit 514.

  The photographing lens 520 is composed of a plurality of optical lens groups, and forms an image of a subject light flux from the scene in the vicinity of its focal plane. In FIG. 10, the photographing lens 520 is representatively represented by a single virtual lens disposed in the vicinity of the pupil.

  The driving unit 514 drives the taking lens 520. More specifically, the drive unit 514 moves the optical lens group of the photographic lens 520 to change the focus position, and also drives the iris diaphragm in the photographic lens 520 to input the light amount of the subject luminous flux incident on the image sensor 100. To control.

  The drive unit 502 is a control circuit that executes charge accumulation control such as timing control and area control of the image sensor 100 in accordance with instructions from the system control unit 501. The driving unit 502 operates the light receiving unit 200 and the reading unit 210 of the image sensor 100 as described with reference to FIGS. 1 to 9. Further, the operation unit 508 receives an instruction from the photographer through a release button or the like.

  The image sensor 100 is the same as the image sensor 100 described with reference to FIGS. The image sensor 100 delivers the pixel signal to the image processing unit 511 of the system control unit 501. The image processing unit 511 performs various image processing using the work memory 504 as a work space, and generates image data. For example, when generating image data in JPEG file format, a compression process is executed after generating a color video signal from a signal obtained by the Bayer array. The generated image data is recorded in the recording unit 505, converted into a display signal, and displayed on the display unit 506 for a preset time.

  The photometric unit 503 detects the luminance distribution of the scene prior to a series of shooting sequences for generating image data. The photometry unit 503 includes, for example, an AE sensor having about 1 million pixels. The calculation unit 512 of the system control unit 501 receives the output of the photometry unit 503 and calculates the luminance for each area of the scene. The calculation unit 512 determines the shutter speed, aperture value, and ISO sensitivity according to the calculated luminance distribution. The light metering unit 503 may be shared by the image sensor 100. Note that the arithmetic unit 512 also executes various arithmetic operations for operating the imaging device 500. A part or all of the drive unit 502 may be mounted on the image sensor 100. A part of the system control unit 501 may be mounted on the image sensor 100.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  10 capacitor, 59 reset transistor, 60 amplification transistor, 61 selection transistor, 63 second transistor, 64 transfer transistor, 65 ground side transistor, 66 amplification transistor, 78 first transistor 100 image sensor, 101 microlens, 102 color filter, 103 Passivation film, 104 PD section, 105 transistor, 106 PD layer, 107 wiring, 108 wiring layer, 109 bump, 110 TSV, 111 signal processing chip, 112 memory chip, 113 imaging chip, 200 light receiving section, 202 pixels, 204 readout line , 206 control line, 210 reading unit, 212 AD converter, 214 photoelectric element, 216 CDS unit, 500 imaging device, 501 system control unit, 502 driving unit 503, photometry unit, 504 work memory, 505 recording unit, 506 display unit, 508 operation unit, 511 image processing unit, 512 calculation unit, 514 drive unit, 520 photographing lens

Claims (12)

A photoelectric element that accumulates electric charge according to the amount of received light;
A capacitor charged and discharged at a voltage according to the amount of charge accumulated in the photoelectric element;
The state of the capacitor includes a first state in which a reference voltage is applied to the first electrode of the capacitor and a feedthrough voltage of the photoelectric element is applied to the second electrode of the capacitor, and the capacitor in the first state A switch unit that transitions to a second state in which a voltage based on charges accumulated in the photoelectric element is applied to the second electrode while maintaining the voltage between the electrodes;
An output unit that outputs a voltage of the first electrode of the capacitor to a signal line;
The switch unit uses the feedthrough voltage as the reference voltage. A plurality of the photoelectric elements are provided,
The capacitor corresponding to each of the photoelectric elements,
The charges accumulated in each of the photoelectric elements are simultaneously reset,
The imaging device according to claim 1, wherein each of the capacitors simultaneously holds an output value of the corresponding photoelectric device. An imaging chip on which the photoelectric element is formed;
The imaging device according to claim 2, further comprising: a signal processing chip on which the capacitor is formed and the imaging chip is stacked. The imaging device according to claim 2, wherein the capacitor is provided in common to two or more of the photoelectric elements, and sequentially holds output values of the photoelectric elements. The imaging device according to claim 4, wherein the switch unit is provided for each capacitor. The switch unit applies a voltage based on charges accumulated in the photoelectric element to the second electrode in a state where the first electrode is in a floating state when the capacitor is transitioned to the second state. The imaging device according to any one of 1 to 5. The switch part is
A first switch for switching whether to apply the reference voltage to the first electrode;
The imaging device according to claim 1, further comprising: a second switch that switches whether to connect the output of the photoelectric element to the second electrode. In the first state, the first switch and the second switch are turned on,
The imaging device according to claim 7, wherein in the second state, the first switch is turned off and the second switch is turned on. A photoelectric element that accumulates electric charge according to the amount of received light;
A capacitor charged and discharged at a voltage according to the amount of charge accumulated in the photoelectric element;
The state of the capacitor includes a first state in which a reference voltage is applied to the first electrode of the capacitor and a feedthrough voltage of the photoelectric element is applied to the second electrode of the capacitor, and the capacitor in the first state A switch unit that transitions to a second state in which a voltage based on charges accumulated in the photoelectric element is applied to the second electrode while maintaining the voltage between the electrodes;
An output unit that outputs a voltage of the first electrode of the capacitor to a signal line;
The switch section includes: a first switch that switches whether to apply the reference voltage to the first electrode; and a second switch that switches whether to connect the output of the photoelectric element to the second electrode. Have
In the first state, the first switch and the second switch are turned on,
In the second state, the first switch is turned off, the second switch is turned on,
The first switch switches whether to connect the first electrode and the second electrode;
Image sensor. A photoelectric element that accumulates electric charge according to the amount of received light;
A capacitor charged and discharged at a voltage according to the amount of charge accumulated in the photoelectric element;
The state of the capacitor includes a first state in which a reference voltage is applied to the first electrode of the capacitor and a feedthrough voltage of the photoelectric element is applied to the second electrode of the capacitor, and the capacitor in the first state A switch unit that transitions to a second state in which a voltage based on charges accumulated in the photoelectric element is applied to the second electrode while maintaining the voltage between the electrodes;
An output unit for outputting the voltage of the first electrode of the capacitor to a signal line;
An imaging device comprising: a readout unit that reads out a signal based on the charge accumulated in the photoelectric device based on the voltage of the first electrode in the second state and the known reference voltage. A photoelectric element that accumulates electric charge according to the amount of received light;
A capacitor charged and discharged at a voltage according to the amount of charge accumulated in the photoelectric element;
The state of the capacitor includes a first state in which a reference voltage is applied to the first electrode of the capacitor and a feedthrough voltage of the photoelectric element is applied to the second electrode of the capacitor, and the capacitor in the first state A switch unit that transitions to a second state in which a voltage based on charges accumulated in the photoelectric element is applied to the second electrode while maintaining the voltage between the electrodes;
An output unit that outputs a voltage of the first electrode of the capacitor to a signal line;
The imaging device includes a third electrode that is provided to overlap the first electrode and the second electrode, and that maintains a voltage applied to the second electrode.   An imaging device comprising the imaging device according to any one of claims 1 to 11.

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