JP2017163588A - Imaging device, imaging element, and reading method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem in which: when the number of pixels included in cells is increased in response to a requirement for high resolution, a so-called rolling shutter system is employed in which pixels are controlled for every column in the cells, which results in occurrence of distortion when a moving body is photographed for every cell.SOLUTION: An imaging unit includes: an imaging section that has a plurality of unit groups in which a plurality of pixels is two-dimensionally arranged; and a control section that selects at least two adjacent pixels included in each of the unit groups in order in which the two adjacent pixels are not continuously selected from the plurality of pixels, and outputs a pixel signal.SELECTED DRAWING: Figure 6

Description

  The present invention relates to an imaging element, an imaging apparatus, and a control method.

There is known an imaging unit in which a back-illuminated imaging chip and a signal processing chip are connected via a micro bump for each cell unit in which a plurality of pixels are combined.
[Prior art documents]
[Patent Literature]
[Patent Document 1] Japanese Patent Application Laid-Open No. 2006-49361

  In the imaging unit, charge accumulation time control and pixel signal readout control are performed for each cell. However, when the number of pixels included in a cell is increased in response to a demand for high resolution, a so-called rolling shutter system is used in which the pixels are controlled for each row in the cell. There is a problem of appearing in units.

  According to a first aspect of the present invention, there is provided an imaging device that includes a first region in which a plurality of pixels are disposed and a second region that is different from the first region in which the plurality of pixels are disposed; A control unit that controls the image sensor so that signals from the pixels arranged in the first area are read out in a different order from the signals from the pixels arranged in the second area.

  In a second aspect of the present invention, the imaging device includes a first region in which a plurality of pixels are disposed, and a second region that is different from the first region in which the plurality of pixels are disposed, Signals from the pixels arranged in the first area are read out in a different order from the signals from the pixels arranged in the second area.

  In the third aspect of the present invention, there is provided a readout method, in which a plurality of signals from pixels arranged in the first area of the image sensor and a plurality of signals are arranged in a second area different from the first area of the image sensor. A readout method for reading out signals from pixels, wherein signals from pixels arranged in the first area are read out in a different order from signals from pixels arranged in the second area.

  It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

It is a sectional view of a back irradiation type image sensor concerning this embodiment. It is a figure explaining the pixel arrangement | sequence and unit group of an imaging chip. An equivalent circuit diagram of a pixel is shown. It is a circuit diagram which shows the connection relation of the said pixel in a unit group. It is a block diagram which shows the structure of the imaging device which concerns on this embodiment. It is an example of an order table. It is a block diagram which shows the functional structure of an image pick-up element. It is a conceptual diagram which shows the order of control of the charge accumulation of a several unit group. The equivalent circuit of another pixel is shown. It is a block diagram which shows the structure of the imaging device which has another drive part.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

  FIG. 1 is a cross-sectional view of a back-illuminated image sensor 100 according to this embodiment. The imaging element 100 includes an imaging chip 113 that outputs a pixel signal corresponding to incident light, a signal processing chip 111 that processes the pixel signal, and a memory chip 112 that stores the pixel signal. The imaging chip 113, the signal processing chip 111, and the memory chip 112 are stacked, and are electrically connected to each other by a conductive bump 109 such as Cu.

  As shown in the figure, incident light is incident mainly in the positive direction of the Z-axis indicated by a white arrow. In the present embodiment, in the imaging chip 113, the surface on the side where incident light is incident is referred to as a back surface. Further, as indicated by the coordinate axes, the right direction on the paper orthogonal to the Z axis is the X axis plus direction, and the front side of the paper orthogonal to the Z axis and the X axis is the Y axis plus direction. In the following several figures, the coordinate axes are displayed so that the orientation of each figure can be understood with reference to the coordinate axes of FIG.

  An example of the imaging chip 113 is a back-illuminated MOS image sensor. The PD layer is disposed on the back side of the wiring layer 108. The PD layer 106 includes a plurality of PDs (photodiodes) 104 arranged two-dimensionally and a transistor 105 provided corresponding to the PD 104. The PD 104 is an example of a photoelectric conversion element.

  A color filter 102 is provided on the incident side of incident light in the PD layer 106 via a passivation film 103. The color filter 102 has a plurality of types that transmit different wavelength regions, and has a specific arrangement corresponding to each of the PDs 104. The arrangement of the color filter 102 will be described later. A set of the color filter 102, the PD 104, and the transistor 105 forms one pixel.

  On the incident light incident side of the color filter 102, a microlens 101 is provided corresponding to each pixel. The microlens 101 condenses incident light toward the corresponding PD 104.

  The wiring layer 108 includes a wiring 107 that transmits the pixel signal from the PD layer 106 to the signal processing chip 111. The wiring 107 may be multilayer, and a passive element and an active element may be provided.

  A plurality of bumps 109 are disposed on the surface of the wiring layer 108. The plurality of bumps 109 are aligned with the plurality of bumps 109 provided on the opposing surfaces of the signal processing chip 111, and the imaging chip 113 and the signal processing chip 111 are pressed and aligned. The bumps 109 are joined and electrically connected.

  Similarly, a plurality of bumps 109 are disposed on the mutually facing surfaces of the signal processing chip 111 and the memory chip 112. The bumps 109 are aligned with each other, and the signal processing chip 111 and the memory chip 112 are pressurized, so that the aligned bumps 109 are joined and electrically connected.

  The bonding between the bumps 109 is not limited to Cu bump bonding by solid phase diffusion, and micro bump bonding by solder melting may be employed. Further, for example, about one bump 109 may be provided for one output wiring described later. Therefore, the size of the bump 109 may be larger than the pitch of the PD 104. Further, a bump larger than the bump 109 corresponding to the pixel region may be provided in a peripheral region other than the pixel region where the pixels are arranged.

  The signal processing chip 111 has a TSV (silicon through electrode) 110 that connects circuits provided on the front and back surfaces to each other. The TSV 110 is preferably provided in the peripheral area. The TSV 110 may also be provided in the peripheral area of the imaging chip 113 and the memory chip 112.

  FIG. 2 is a diagram for explaining the pixel array and the unit group 131 of the imaging chip 113. In particular, a state where the imaging chip 113 is observed from the back side is shown. In the pixel area, 20 million or more pixels are arranged in a matrix. In the example of FIG. 2, 16 pixels of 4 pixels × 4 pixels adjacent to each other form one group. The grid lines in the figure indicate the concept that adjacent pixels are grouped to form a unit group 131. In other words, the pixel region is formed by two-dimensionally arranging the plurality of unit groups 131.

  As shown in the partially enlarged view of the pixel region, the unit group 131 includes four so-called Bayer arrays composed of four pixels, ie, green pixels Gb, Gr, blue pixels B, and red pixels R, vertically and horizontally. The green pixels Gb and Gr have a green filter as the color filter 102 and receive light in the green wavelength band of incident light. Similarly, the blue pixel B has a blue filter as the color filter 102 and receives light in the blue wavelength band, and the red pixel R has a red filter as the color filter 102 and receives light in the red wavelength band. .

  FIG. 3 shows an equivalent circuit diagram of the pixel 150. Each of the plurality of pixels 150 includes the PD 104, the transfer transistor 152, the reset transistor 154, the amplification transistor 156, and the selection transistor 158. At least some of these transistors correspond to the transistor 105 in FIG. Further, the pixel 150 includes a reset wiring 300 to which an ON signal of the reset transistor 154 is supplied, a transfer wiring 302 to which an ON signal of the transfer transistor 152 is supplied, a power supply wiring 304 that receives power supply from the power supply Vdd, and a selection transistor 158. A selection wiring 306 to which the ON signal is supplied and an output wiring 308 for outputting a pixel signal are arranged.

  The source, gate, and drain of the transfer transistor 152 are connected to one end of the PD 104, the transfer wiring 302, and the gate of the amplification transistor 156, respectively. The drain of the reset transistor 154 is connected to the power supply wiring 304, and the source is connected to the gate of the amplification transistor 156. A so-called floating diffusion FD is formed between the drain of the transfer transistor 152 and the source of the reset transistor 154.

  The drain of the amplification transistor 156 is connected to the power supply wiring 304, and the source is connected to the drain of the selection transistor 158. The gate of the selection transistor 158 is connected to the selection wiring 306, and the source is connected to the output wiring 308. The load current source 309 supplies current to the output wiring 308. That is, the output wiring 308 for the selection transistor 158 is formed by a source follower. Note that the load current source 309 may be provided on the imaging chip 113 side or may be provided on the signal processing chip 111 side.

  Here, the flow from the start of charge accumulation to pixel output after the end of accumulation will be described. When a reset pulse is applied to the reset transistor 154 through the reset wiring 300 and simultaneously a transfer pulse is applied to the transfer transistor 152 through the transfer wiring 302, the potentials of the PD 104 and the floating diffusion FD are reset.

  When the application of the transfer pulse is canceled, the PD 104 accumulates charges corresponding to the incident light received. Thereafter, when the transfer pulse is applied again without the reset pulse being applied, the accumulated charge is transferred to the floating diffusion FD, and the potential of the floating diffusion FD changes from the reset potential to the signal potential after the charge accumulation. . When a selection pulse is applied to the selection transistor 158 through the selection wiring 306, a change in the signal potential of the floating diffusion FD is transmitted to the output wiring 308 via the amplification transistor 156 and the selection transistor 158. Thereby, a pixel signal corresponding to the reset potential and the signal potential is output from the unit pixel to the output wiring 308.

  FIG. 4 is a circuit diagram showing the connection relationship of the pixels 150 in the unit group 133. Note that reference numbers of the respective transistors are omitted for the sake of easy understanding of the drawings, but each transistor of each pixel in FIG. 4 has the same configuration and function as each transistor arranged at a corresponding position in the pixel 150 in FIG. .

  The unit group 133 in FIG. 4 is formed by 9 pixels of 3 pixels × 3 pixels adjacent to each other. Note that the number of pixels included in the unit group 133 is not limited to this. A two-dimensional position of the unit group 133 is indicated by a pixel A or the like, and an order of controlling the pixel A or the like is indicated by (1) or the like.

  The reset transistors of the pixels included in the unit group 133 are individually turned on / off for each pixel. In the example shown in FIG. 4, a reset wiring 300 for turning on / off the reset transistor of the pixel A is provided, and a reset wiring 310 for turning on / off the reset transistor of the pixel B is provided separately from the reset wiring 300. Similarly, a reset line 320 for turning on and off the reset transistor of the pixel C is provided separately from the reset lines 300 and 310. Also for the other pixels D to I, dedicated lines for turning on and off the respective reset transistors are arranged.

  The transfer transistors of the pixels included in the unit group 133 are also turned on / off individually for each pixel. In the example shown in FIG. 4, a transfer wiring 302 for turning on / off the transfer transistor of the pixel A, a transfer wiring 312 for turning on / off the transfer transistor of the pixel B, and a transfer wiring 322 for turning on / off the transfer transistor of the pixel C are separately provided. . Also for the other pixels D to I, dedicated lines for selecting the respective transfer transistors are arranged.

  The selection transistors of the pixels included in the unit group 133 are also turned on / off individually for each pixel. In the example shown in FIG. 4, a selection wiring 306 for turning on / off the selection transistor of the pixel A, a selection wiring 316 for turning on / off the selection transistor of the pixel B, and a selection wiring 326 for turning on / off the selection transistor of the pixel C are separately provided. . Also for the other pixels D to I, dedicated lines for selecting the respective selection transistors are arranged.

  Note that the power supply wiring 304 is commonly connected to the pixels A to I included in the unit group 133. Similarly, the output wiring 308 is commonly connected to each pixel A to I included in the unit group 133. Furthermore, the power supply wiring 304 is commonly connected among a plurality of unit groups, but the output wiring 308 is provided for each unit group.

  By individually turning on and off the reset transistor and the transfer transistor of the unit group 133, the charge including the charge accumulation start time, the accumulation end time, and the transfer timing independently for each of the pixels A to I included in the unit group 133 Accumulation can be controlled. In addition, by individually turning on and off the selection transistors of the unit group 133, the pixel signals of the pixels A to I can be output via the common output wiring 308.

  Here, for each of the pixels A to I included in the unit group 133, there is a so-called rolling shutter system in which charge accumulation is controlled in a regular order with respect to rows and columns. In the rolling shutter method, since a pixel is selected for each row and then a column is designated, pixel signals are output in the order of “ABCDEFGHI” in the example of FIG. However, in the rolling shutter system, when a moving object is imaged, an image in which the moving object is obliquely distorted is generated for the pixels in the unit group 133.

  On the other hand, in the present embodiment, pixel signals are output in an order in which at least two pixels adjacent to each other are not successively selected as an order different from the rolling shutter system. In the example illustrated in FIG. 4, pixel signals are output in the order of “AICGFDHBE”. As a result, it is possible to disperse the distortion when the moving object is imaged and to make it inconspicuous on the image.

  FIG. 5 is a block diagram illustrating a configuration of the imaging apparatus 500 according to the present embodiment. The imaging apparatus 500 includes a photographic lens 520 as a photographic optical system, and the photographic lens 520 guides a subject luminous flux incident along the optical axis OA to the imaging element 100. The photographing lens 520 may be an interchangeable lens that can be attached to and detached from the imaging apparatus 500. The imaging apparatus 500 mainly includes an imaging device 100, a system control unit 501, a drive unit 502, a photometry unit 503, a work memory 504, a recording unit 505, and a display unit 506.

  The photographing lens 520 is composed of a plurality of optical lens groups, and forms an image of a subject light flux from the scene in the vicinity of its focal plane. In FIG. 5, a representative single lens arranged in the vicinity of the pupil is shown as a representative. The drive unit 502 is a control circuit that executes charge accumulation control such as timing control and area control of the image sensor 100 in accordance with instructions from the system control unit 501. In this sense, it can be said that the drive unit 502 functions as an image sensor control unit that causes the image sensor 100 to perform charge accumulation and output a pixel signal. The driving unit 502 is combined with the imaging device 100 to form an imaging unit. The control circuit forming the driving unit 502 may be formed into a chip and stacked on the image sensor 100.

  The image sensor 100 delivers the pixel signal to the image processing unit 511 of the system control unit 501. The image processing unit 511 performs various image processing using the work memory 504 as a work space, and generates image data. For example, when generating image data in JPEG file format, compression processing is executed after white balance processing, gamma processing, and the like are performed. The generated image data is recorded in the recording unit 505, converted into a display signal, and displayed on the display unit 506 for a preset time.

  The photometric unit 503 detects the luminance distribution of the scene prior to a series of shooting sequences for generating image data. The photometry unit 503 includes, for example, an AE sensor having about 1 million pixels. The calculation unit 512 of the system control unit 501 receives the output of the photometry unit 503 and calculates the luminance for each area of the scene. The calculation unit 512 determines the shutter speed, aperture value, and ISO sensitivity according to the calculated luminance distribution. Note that the pixels used in the AE sensor may be provided in the image sensor 100. In this case, the photometric unit 503 separate from the image sensor 100 may not be provided.

  The driving unit 502 includes an order setting unit 514 and an order table 516. The order setting unit 514 sets an order for controlling each pixel A and the like included in the unit group 133 with reference to the order table 516 when receiving an instruction for imaging of the image sensor 100 from the system control unit 501.

  FIG. 6 is an example of the order table 516. The order table 516 stores information for identifying pixel positions in association with the order in which the pixels are controlled. In the example of FIG. 6, information A to I for identifying pixel positions is stored in association with the order corresponding to the unit group 133 of FIG.

  The order includes an order in which at least two pixels adjacent to each other in the unit group are not selected. For example, the order 1 includes the order of the pixel A, the pixel I, and the pixel C. The pixel A is arranged in the first row and the first column in the unit group 133, the pixel I is arranged in the third row and the third column, and the pixel C is arranged in the first row and the third column. Therefore, neither pixel B nor pixel D is selected after pixel A. Further, the order of the pixel A, the pixel I, and the pixel C is an order that goes back and forth at least between rows. Further, the order is preferably such that the same row or column is not continuously arranged.

  In order 1, pixel I is controlled next to pixel A, but any pixel is controlled in any order. Thus, although the order of the order table 516 is different from so-called thinning-out reading, it may be applied to the case of thinning-out reading. In this case, for example, when thinning out half of the pixels, the first to fifth pixels may be controlled and the pixel signals may be read out therefrom.

  FIG. 7 is a block diagram showing a functional configuration of the image sensor 100. The analog multiplexer 411 sequentially selects each pixel A to I of the unit group 133 in the order determined by the order setting unit 514 with reference to the order table 516 and outputs each pixel signal to the output wiring 308. .

  The pixel signal output via the multiplexer 411 is subjected to CDS and A / D conversion by a signal processing circuit 412 that performs correlated double sampling (CDS) / analog / digital (A / D) conversion via an output wiring 308. Is done. The pixel signal digitized by A / D conversion is delivered to the demultiplexer 413 via the output wiring 330 and stored in the pixel memory 414 corresponding to each pixel. In this case, the pixel memory 414 is associated with the position of a two-dimensional array of pixels.

  In the example illustrated in FIG. 7, the multiplexer 411 controls charge accumulation of the pixels A and the like of the unit group 133 according to the order 1 of the order table 516 in FIG. 6 and outputs a pixel signal. For example, the multiplexer 411 outputs the pixel signal of the pixel A first, and outputs the pixel signal of the pixel I second. The demultiplexer 413 stores the A / D converted pixel signal of the pixel A in the memory A, and then stores the A / D converted pixel signal of the pixel I in the memory I.

  The multiplexer 411 is formed on the imaging chip 113. The signal processing circuit 412 is formed in the signal processing chip 111. The demultiplexer 413 and the pixel memory 414 are formed in the memory chip 112.

  Output wirings 308 and 330 are provided corresponding to the unit group 133. Since the image pickup device 100 has the image pickup chip 113, the signal processing chip 111, and the memory chip 112 laminated, by making these wirings electrically connected between the chips using the bumps 109, each chip is enlarged in the surface direction. The wiring can be routed without doing.

  The arithmetic circuit 415 processes the pixel signal stored in the pixel memory 414 and passes it to the subsequent image processing unit. The arithmetic circuit 415 may be provided in the signal processing chip 111 or may be provided in the memory chip 112. In addition, although the connection for 1 group is shown in the figure, these actually exist for every group and operate | move in parallel. However, the arithmetic circuit 415 may not exist for each group. For example, one arithmetic circuit 415 may perform sequential processing while sequentially referring to the values of the pixel memory 414 corresponding to each group.

  FIG. 8 is a conceptual diagram showing an order of charge accumulation control of the plurality of unit groups 133 and 135. The unit group 133 and the unit group 135 have different charge storage control orders for at least some of the pixels at the corresponding positions.

  In the example illustrated in FIG. 8, the control order of the unit group 133 is “AICGDHBE” according to the order 1 of the order table 516 in FIG. 6. On the other hand, the control order of the unit group 135 is “IAGCFDFBHIE” in accordance with order 2 of the order table 516. The pixel A of the unit group 133 is controlled first, while the pixel A of the unit group 133 is controlled second.

  According to the embodiment shown in FIG. 8, the order of charge accumulation control differs for at least some of the pixels at corresponding positions in the plurality of unit groups 133 and 135. Therefore, it is possible to further disperse the distortion when the moving object is imaged and to make it inconspicuous on the image.

  FIG. 9 shows an equivalent circuit of another pixel 170. 9, the same components as those of the pixel 150 in FIG. 3 are denoted by the same reference numerals, and description thereof is omitted. The output wiring 308 is connected to a load current source as in the example of FIG.

  In the pixel 170, a row selection transistor 171 and a column selection transistor 172 are provided between the transfer wiring 302 and the gate of the transfer transistor 152. The gate of the row selection transistor 171 is connected to the row selection wiring 391, and the gate of the column selection transistor 172 is connected to the column selection wiring 392. In the row selection wiring 391, for example, gates of row selection transistors of at least a plurality of pixels arranged in the row direction in the unit group 133 are arranged in common. Similarly, the column selection wiring 392 has, for example, at least the gates of column selection transistors of a plurality of pixels arranged in the column direction in the unit group 133 in the column direction.

  According to the above configuration, when an on signal is added to the row selection wiring 391 and the column selection wiring 392, the transfer transistor 152 of the pixel 170 specified by the wiring can be turned on. Thereby, on / off of the transfer transistor can be controlled in units of pixels.

  Further, the pixel 170 is provided with a row selection transistor 174 and a column selection transistor 175 instead of the single selection transistor 158 of the pixel 150. The gate of the row selection transistor 174 is connected to the row selection wiring 394, and the gate of the column selection transistor 175 is connected to the column selection wiring 395. In the row selection wiring 394, for example, the gates of the row selection transistors of a plurality of pixels aligned in the row direction with at least the pixel 170 in the unit group 133 are arranged in common. Similarly, the column selection wiring 395 has, for example, at least the gates of column selection transistors of a plurality of pixels aligned in the column direction with the pixel 170 in the unit group 133.

  According to the above configuration, when an ON signal is added to the row selection wiring 394 and the column selection wiring 395, the pixel signal of the pixel 170 specified by the wiring can be output to the output wiring 308. Accordingly, the number of wirings can be reduced as compared with the selection wiring 306 corresponding to the selection transistor 158 on a one-on-one basis like the pixel 150.

  In the pixel 170, a row selection transistor 176 and a column selection transistor 177 are provided instead of the single reset transistor 154 of the pixel 150. The gate of the row selection transistor 176 is connected to the row selection wiring 396, and the gate of the column selection transistor 177 is connected to the column selection wiring 397. In the row selection wiring 396, for example, the gates of row selection transistors of a plurality of pixels aligned in the row direction with at least the pixel 170 in the unit group 133 are arranged in common. Similarly, the column selection wiring 397 has, for example, at least the gates of the column selection transistors of a plurality of pixels arranged in the column direction in the unit group 133 in the column direction.

  According to the above configuration, when an ON signal is added to the row selection wiring 396 and the column selection wiring 397, the pixel 170 specified by the wiring can be reset. Thereby, the reset can be controlled in units of pixels.

  Note that the row selection wiring 391 and the column selection wiring 392 for the transfer transistor 152, the row selection wiring 396 and the column selection wiring 397 for resetting, and the row selection wiring 394 and the column selection wiring 395 for the output wiring 308 are used in pairs. It doesn't have to be done. The configuration of the pixel 150 may be used for either. In the case where the transfer and output are not performed simultaneously, the row selection wirings 391 and 394 are used in common for the transfer and output, and the column selection wirings 392 and 395 are also used in the transfer and output. And may be used in common.

  In any of the above embodiments, the power supply wiring 304 is common to the unit group 133. In addition, the power supply wiring 304 may be common among the plurality of unit groups 131.

  FIG. 10 is a block diagram illustrating a configuration of an imaging apparatus 500 having another driving unit 522. In the imaging apparatus 500 of FIG. 10, the same components as those of the imaging apparatus 500 of FIG.

  The drive unit 522 includes a random number generation unit 518 instead of the order table 516 of the drive unit 502 in FIG. The random number generation unit 518 generates a pseudo random number according to an instruction from the system control unit 501. The order setting unit 514 sets the order in which the pixels A and the like included in the unit group 133 are controlled based on the pseudo random number generated by the random number generation unit 518.

  The order setting unit 514 controls the pixel indicated by the pseudo random number generated by the random number generation unit 518 by associating the numerical value indicated by the pseudo random number with the two-dimensional position of the pixel in advance. Thereby, using the pseudo random number, each pixel is controlled in an order in which at least two adjacent pixels included in each unit group are not selected in succession.

  Instead of or in addition to this, the order setting unit 514 determines which one of a plurality of orders is used in the order table 516 shown in FIG. 6 by using the pseudo random number generated by the random number generation unit 518. May be.

  As described above, according to the present embodiment, the pixel signals are output in an order in which at least two pixels adjacent to each other in the unit group are not selected in succession. Therefore, the distortion when the moving object is imaged is dispersed on the image. It can be inconspicuous.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  The order of execution of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior to”. It should be noted that the output can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the description, and the drawings, even if it is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

  100 imaging device, 101 microlens, 102 color filter, 103 passivation film, 104 PD, 105 transistor, 106 PD layer, 107 wiring, 108 wiring layer, 109 bump, 110 TSV, 111 signal processing chip, 112 memory chip, 113 imaging Chip, 131 unit group, 133 unit group, 135 unit group, 150 pixels, 152 transfer transistor, 154 reset transistor, 156 amplification transistor, 158 selection transistor, 170 pixel, 171 row selection transistor, 172 column selection transistor, 174 row selection transistor 175 column selection transistor, 176 row selection transistor, 177 column selection transistor, 300 reset wiring, 302 transfer wiring, 3 4 power supply wiring, 306 selection wiring, 308 output wiring, 309 load current source, 310 reset wiring, 312 transfer wiring, 316 selection wiring, 320 reset wiring, 322 transfer wiring, 326 selection wiring, 330 output wiring, 391 row selection wiring, 392 column selection wiring, 394 row selection wiring, 395 column selection wiring, 396 row selection wiring, 397 column selection wiring, 411 multiplexer, 412 signal processing circuit, 413 demultiplexer, 414 pixel memory, 415 arithmetic circuit, 500 imaging device, 520 Photographic lens, 501 system control unit, 502 drive unit, 503 photometry unit, 504 work memory, 505 recording unit, 506 display unit, 511 image processing unit, 512 calculation unit, 514 sequence setting unit, 516 sequence table, 518 random number generation unit 522 WD Moving part

Claims (1)

A plurality of pixels arranged in a first direction and a second direction different from the first direction and including a pixel that generates a signal by photoelectrically converted charges and an output wiring that outputs the signal generated by the pixel An image sensor having a plurality of pixel regions arranged in the first direction and the second direction;
Of the plurality of regions arranged in the pixel region, a signal from the pixel arranged in the first region out of the plurality of regions arranged in the pixel region is different from the first region among the plurality of regions arranged in the pixel region. A control unit that controls the imaging device to output the signals from the pixels arranged in the region to the output wiring in the first region in an order different from the order in which the signals are output to the output wiring in the second region; ,
An imaging apparatus comprising:

Images