JP6998693B2 - Image sensor and image sensor - Google Patents

Description

The present invention relates to an image pickup device.

In an image pickup device in which pixels are arranged in a matrix, there is an image pickup device that electronically realizes a global shutter by simultaneously transferring charges using a memory circuit composed of a transistor and a storage capacity (see, for example, Patent Document 1). ).
Patent Document 1 Japanese Patent Application Laid-Open No. 2011-119950

However, after the charges are transferred all at once, the pixel signals based on the charges are sequentially read. Therefore, as the number of pixels increases, the time from when the charge is transferred until the pixel signal is read becomes longer, the charge increases or decreases, and noise is likely to be added to the pixel signal.

In the first aspect of the present invention, in the image pickup device, a unit block in which a plurality of pixels are arranged in a matrix is provided with an image pickup unit in which a plurality of pixels are arranged in a matrix, and at least one unit block is provided. It is provided with an A / D conversion unit that converts a pixel signal from a pixel included in the unit block into a digital signal, and a reading unit that sequentially reads out the digital signal of the pixel included in the image pickup unit across a plurality of unit blocks.

The outline of the above invention does not list all the necessary features of the present invention. A subcombination of these feature groups can also be an invention.

It is sectional drawing of the back-illuminated type image sensor which concerns on this embodiment. It is a figure explaining the pixel arrangement and the unit block of an image pickup chip. It is a circuit diagram corresponding to a pixel. The outline of the unit block and its peripheral circuits and their connection relations is shown. The outline of the connection relation of the peripheral circuit etc. is shown. It is a block diagram which shows the structure of the image pickup apparatus which concerns on this embodiment. It is a block diagram which shows the specific structure of a drive part. The timing chart of the operation such as charge accumulation and transfer of a pixel is shown. The timing chart of the operation of reading a pixel signal of a pixel is shown. It is a timing chart which shows the reading timing of a plurality of pixels included in an image pickup part. Another example of connection relations such as peripheral circuits is shown.

Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention to which the claims are made. Also, not all combinations of features described in the embodiments are essential to the means of solving the invention.

FIG. 1 is a cross-sectional view of a back-illuminated image sensor 100 according to the present embodiment. The image pickup device 100 includes an image pickup chip and 113 that output a pixel signal corresponding to incident light, a signal processing chip 111 that processes the pixel signal, and a memory chip 112 that stores the pixel signal. The image pickup chip 113, the signal processing chip 111, and the memory chip 112 are laminated and electrically connected to each other by a conductive bump 109 such as Cu.

As shown in the figure, the incident light is mainly incident in the Z-axis plus direction indicated by the white arrow. In the present embodiment, in the image pickup chip 113, the surface on the side where the incident light is incident is referred to as a back surface. Further, as shown in the coordinate axes, the right direction of the paper surface orthogonal to the Z axis is defined as the X-axis plus direction, and the Z-axis and the front direction of the paper surface orthogonal to the X-axis are defined as the Y-axis plus direction. In some of the subsequent figures, the coordinate axes are displayed so that the orientation of each figure can be understood with reference to the coordinate axes of FIG.

An example of the image pickup chip 113 is a back-illuminated MOS image sensor. The PD layer is arranged on the back surface side of the wiring layer 108. The PD layer 106 has a plurality of PDs (photodiodes) 104 arranged two-dimensionally, and a transistor 105 provided corresponding to the PD 104.

A color filter 102 is provided on the incident side of the incident light in the PD layer 106 via the passivation film 103. The color filter 102 has a plurality of types that transmit different wavelength regions from each other, and has a specific arrangement corresponding to each of the PD 104. The arrangement of the color filters 102 will be described later. A set of a color filter 102, a PD 104, and a transistor 105 forms one pixel.

A microlens 101 is provided on the incident side of the incident light in the color filter 102 corresponding to each pixel. The microlens 101 collects incident light toward the corresponding PD 104.

The wiring layer 108 has a wiring 107 that transmits a pixel signal from the PD layer 106 to the signal processing chip 111. The wiring 107 may have multiple layers, and may be provided with passive elements and active elements.

A plurality of bumps 109 are arranged on the surface of the wiring layer 108. The plurality of bumps 109 are aligned with the plurality of bumps 109 provided on the facing surfaces of the signal processing chip 111, and the image pickup chip 113 and the signal processing chip 111 are aligned by being pressurized or the like. The bumps 109 are joined together and electrically connected.

Similarly, a plurality of bumps 109 are arranged on the surfaces of the signal processing chip 111 and the memory chip 112 facing each other. These bumps 109 are aligned with each other, and the signal processing chip 111 and the memory chip 112 are pressurized, so that the aligned bumps 109 are joined to each other and electrically connected.

The bonding between the bumps 109 is not limited to the Cu bump bonding by solid phase diffusion, but the micro bump bonding by solder melting may be adopted. Further, for example, about one bump 109 may be provided for one output wiring described later. Therefore, the size of the bump 109 may be larger than the pitch of the PD 104. Further, in the peripheral region other than the pixel region in which the pixels are arranged, a bump larger than the bump 109 corresponding to the pixel region may be provided together.

The signal processing chip 111 has TSVs (Through Silicon Vias) 110 that connect circuits provided on the front and back surfaces to each other. The TSV 110 is preferably provided in the peripheral region. Further, the TSV 110 may also be provided in the peripheral area of the image pickup chip 113 and the memory chip 112.

FIG. 2 is a diagram illustrating a pixel arrangement of the image pickup chip 113 and a unit block 131. In particular, the state in which the image pickup chip 113 is observed from the back surface side is shown. The image pickup chip 113 has an image pickup unit in which more than 20 million pixels are arranged in a matrix. In the example of FIG. 2, 16 pixels of adjacent 4 pixels × 4 pixels form one unit block 131. The grid lines in the figure show the concept that adjacent pixels are grouped to form a unit block 131.

As shown in the partially enlarged view of the image pickup unit, the unit block 131 includes four so-called Bayer arrays including four pixels of green pixels Gb, Gr, blue pixels B, and red pixels R in the vertical and horizontal directions. The green pixels Gb and Gr have a green filter as a color filter 102, and receive light in the green wavelength band among the incident light. Similarly, the blue pixel B has a blue filter as a color filter 102 and receives light in the blue wavelength band, and the red pixel R has a red filter as the color filter 102 and receives light in the red wavelength band. ..

In FIG. 2, for simplification of the description, an example in which the unit block 131 is composed of 16 pixels of 4 pixels × 4 pixels has been described. Hereinafter, an example in which the unit block 131 has a total of (L × P) pixels arranged in L rows and P columns will be described. The number of rows and columns is not particularly limited, but when the total number of pixels of the imaging unit is about 20 million pixels, for example, 64 rows and 32 columns. Further, an example will be described in which the unit blocks 131 are arranged in m rows and n columns in total (m × n) to form an imaging unit.

FIG. 3 is a circuit diagram corresponding to the pixel 150. In FIG. 3, a rectangle typically surrounded by a dotted line represents a circuit corresponding to one pixel 150. It should be noted that at least a part of each transistor described below corresponds to the transistor 105 of FIG.

The PD 104 is connected to the transfer transistor 154, and the gate of the transfer transistor 154 is connected to the wiring Tx_i_j to which the transfer pulse is supplied. The subscript i is a serial number of the entire imaging unit that identifies the unit block 131. The subscript j is a serial number in the unit block 131 that identifies the line number in the unit block 131.

The drain of the transfer transistor 154 is connected to the source of the reset transistor 152. As a result, a so-called FD (floating diffusion) 156 is formed between the drain of the transfer transistor 154 and the source of the reset transistor 152. The drain of the reset transistor 152 is connected to the wiring Vdd to which the power supply voltage is supplied, and the gate thereof is connected to the wiring Rst_i_j to which the reset pulse is supplied.

One end of the FD 156 is further connected to the source of the pass transistor 158. The gate of the pass transistor 158 is connected to the wiring Wrt_i_j to which the pass pulse is supplied, and the drain is connected to one end of the storage capacity 160. These pass transistors 158 and storage capacity 160 form a so-called memory circuit.

The one end of the storage capacity 160 is further connected to the gate of the amplification transistor 162. The drain of the amplification transistor 162 is connected to the wiring Vdd to which the power supply voltage is supplied. The source of the amplification transistor 162 is connected to the drain of the corresponding selection transistor 164. The gate of the selection transistor 164 is connected to the wiring Ser_i_j to which the selection pulse is supplied.

The source of the selection transistor 164 is connected to the column transmission line 170. The load current source 166 supplies current to the column transmission line 170. That is, the column transmission line 170 for the selection transistor 164 is formed by the source follower.

FIG. 4 shows an outline of the unit block 131 and its peripheral circuits 133, and their connection relationships. In the unit block 131 of FIG. 4, a total of (P × L) pixels 150 are arranged in L rows and P columns.

The wiring Rst_i_l (where l is an integer from 1 to L) is connected to the row control unit 200 and is commonly connected to the P pixels 150 in the first row in the unit block 131. Similarly, the wiring Tx_i_l, the wiring Wrt_i_l, and the wiring Self_i_l are also connected to the row control unit 200 and are commonly connected to the P pixels 150 in the first row in the unit block 131.

The row control unit 200 may be referred to as a row selection unit, a vertical scanning circuit, or the like. The row control unit 200 is provided for each unit block 131. The row control unit 200 may be provided on the signal processing chip 111 side.

The column transmission line 170 is provided for each pixel 150 in the same row. These column transmission lines 170_p (where p is an integer from 1 to P) are commonly connected to the L pixels 150 in the p-th column in the unit block 131. As a result, the column transmission line 170 is shared by the pixels 150 in the same column in the unit block 131, and the signal from the pixels 150 included in the column is transmitted.

These column transmission lines 170_p are connected from the image pickup chip 113 side to the peripheral circuit 133 provided on the signal processing chip 111 side via the bump 109. The peripheral circuit 133 is provided for each unit block 131, and is arranged so as to overlap the unit block 131 in the image pickup chip 113 when viewed from the stacking direction.

The peripheral circuit 133 includes a CDS circuit 202 and an A / D conversion circuit 204 connected in series for each column transmission line 170_p. In the example shown in FIG. 4, P pairs of the CDS circuit 202 and the A / D conversion circuit 204 are provided per unit block 131.

The peripheral circuit 133 further has a shift register 206 arranged on the output side of the P A / D conversion circuits 204. In the example of FIG. 4, one shift register 206 is arranged for each unit block 131. The output of the shift register 206 is connected to the shift register 210 via the column bus line 172.

FIG. 5 shows an outline of the connection relationship between peripheral circuits 133 and the like. Corresponding to the fact that the unit block 131 is arranged in m rows and n columns, the peripheral circuit 133 is also arranged in m rows and n columns.

The row bus line 172 is provided for each peripheral circuit 133 in the same row. This row bus line 172_u (where u is an integer from 1 to n) is commonly connected to m peripheral circuits 133 in the uth row. As a result, the column bus line 172 is shared by the unit block 131 of the same column, and the signal from the unit block 131 included in the column is transmitted.

Since the row bus line 172 is shared by peripheral circuits 133 in the same row, the output of each peripheral circuit 133 is configured to be controlled by an output selection circuit (not shown). For example, the output of 172 in FIG. 4 is enabled or disabled. When it is not effective, it is controlled by setting it to high impedance.

A shift register 210 is arranged on the output side of the n column bus lines 172. In the example of FIG. 5, one shift register 210 is arranged as the entire image sensor 100. The shift register 210 holds the signals transmitted from the n column bus lines 172 and outputs them sequentially. The shift registers 206 and 210 may be referred to as a horizontal scanning circuit, a multiplexer, or the like.

FIG. 6 is a block diagram showing the configuration of the image pickup apparatus according to the present embodiment. The image pickup device 500 includes a photographing lens 520 as a photographing optical system, and the photographing lens 520 guides a subject light flux incident along the optical axis OA to the image pickup element 100. The photographing lens 520 may be an interchangeable lens that can be attached to and detached from the image pickup apparatus 500. The image pickup device 500 mainly includes an image pickup element 100, a system control unit 501, a drive unit 502, a photometric unit 503, a work memory 504, a recording unit 505, and a display unit 506.

The photographing lens 520 is composed of a plurality of optical lens groups, and forms a subject light flux from the scene in the vicinity of the focal plane thereof. In addition, in FIG. 6, it is represented by one virtual lens arranged in the vicinity of the pupil. The drive unit 502 executes charge storage control of the image pickup device 100, pixel signal readout control, and the like according to instructions from the system control unit 501.

The image sensor 100 passes the pixel signal to the image processing unit 511 of the system control unit 501. The image processing unit 511 performs various image processing using the work memory 504 as a workspace to generate image data. For example, when generating image data in JPEG file format, a compression process is executed after performing a white balance process, a gamma process, or the like. The generated image data is recorded in the recording unit 505, converted into a display signal, and displayed on the display unit 506 for a preset time.

The photometric unit 503 detects the luminance distribution of the scene prior to a series of shooting sequences that generate image data. The photometric unit 503 includes, for example, an AE sensor having about 1 million pixels. The calculation unit 512 of the system control unit 501 receives the output of the photometric unit 503 and calculates the brightness for each area of the scene. The calculation unit 512 determines the shutter speed, the aperture value, and the ISO sensitivity according to the calculated luminance distribution. The pixels used in the AE sensor may be provided in the image sensor 100, and in this case, the light measuring unit 503 separate from the image sensor 100 may not be provided.

FIG. 7 is a block diagram showing a specific configuration of the drive unit 502. The drive unit 502 controls the sensor control unit 441, the block control unit 442, the synchronization control unit 443, the signal control unit 444, the pixel memory 414, the arithmetic circuit 415, and each of these control units as shared control functions. The drive control unit 420 and the like are included. The drive unit 502 further includes an I / F circuit 418 between the drive control unit 420 and the system control unit 501 of the image pickup device 500 main body.

The drive control unit 420 refers to the timing memory 430, converts the instruction from the system control unit 501 into a control signal that can be executed by each control unit, and delivers it to each of them. The timing memory 430 is formed by a flash RAM or the like.

The sensor control unit 441 is responsible for controlling the transmission of control pulses related to charge accumulation and charge readout of each pixel to be transmitted to the image pickup chip 113. Specifically, the sensor control unit 441 controls the start and end of charge accumulation of the target pixel by sending a reset pulse, a transfer pulse, and a pass pulse to the row control unit 200 of each unit block 131, and the read pixel is used. By transmitting the selection pulse to the column transmission path 170, the pixel signal is output to the column transmission line 170.

The block control unit 442 executes transmission of a specific pulse for specifying the unit block 131 to be controlled, which is transmitted to the image pickup chip 113. The transfer pulse or the like received by each pixel via the wiring Tx_i_j or the like is a logical product of each pulse transmitted by the sensor control unit 441 and a specific pulse transmitted by the block control unit 442. In this way, each region can be controlled as a block independent of each other. When a pulse synchronized with a plurality of unit blocks 131 is used, or when an operation straddling a plurality of unit blocks 131 is performed, the block control unit 442 sets a specific pulse for specifying each of the plurality of unit blocks. Is sent at the same time.

The synchronization control unit 443 sends a synchronization signal to the image pickup chip 113. Each pulse becomes active in the imaging chip 113 in synchronization with the synchronization signal. For example, by adjusting the synchronization signal, random control, thinning control, etc., in which only specific pixels of pixels belonging to the same unit block 131 are controlled targets are realized. Further, the signal control unit 444 is responsible for timing control for the CDS circuit 202, the A / D conversion circuit 204, and the shift registers 206 and 210.

The calculation circuit 415 calculates an AE evaluation value or the like based on the pixel value stored in the pixel memory 414. The calculation circuit 415 outputs the calculation result to the drive control unit 420.

The pixel memory 414 has a memory space that can store the pixel values from the pixels 150 of the imaging unit, and stores the pixel values read from each pixel and digitized. The pixel memory 414 is provided with a data transfer interface for transmitting a pixel signal in accordance with a delivery request. The data transfer interface is connected to a data transfer line connected to the image processing unit 511. The data transfer line is composed of, for example, the data bus of the bus lines. In this case, the delivery request from the system control unit 501 to the drive control unit 420 is executed by address designation using the address bus.

The transmission of the pixel signal by the data transfer interface is not limited to the address designation method, and various methods can be adopted. For example, when performing data transfer, it is possible to adopt a double data rate method in which processing is performed by utilizing both the rising edge and the falling edge of the clock signal used for synchronization of each circuit. Further, it is possible to adopt a burst transfer method in which data is transferred at once by omitting a part of a procedure such as address specification to increase the speed. Further, a bus method using a line in which a control unit, a memory unit, and an input / output unit are connected in parallel, a serial method in which data is transferred bit by bit in series, and the like can be adopted in combination.

With this configuration, the image processing unit 511 can receive only the necessary pixel values, so that the image processing can be completed at high speed, especially when forming a low-resolution image. The drive unit 502, the row control unit 200 of FIG. 4, the peripheral circuit 133, and the shift register 210 of FIG. 5 straddle a plurality of unit blocks 131 and sequentially read out the pixel signals of the pixels 150 included in the image pickup unit. Functions as.

FIG. 8 shows a timing chart of operations such as charge storage and transfer of the pixel 150. Hereinafter, the operation of charge storage and transfer in the pixel 150 of FIG. 3 will be described with reference to FIG.

As an initial state, at time t0, the drive unit 502 turns on the reset transistor 152, the transfer transistor 154, and the pass transistor 158 by setting the voltages of the wirings Rst_i_j, Tx_i_j, and Wrt_i_j to high via the row control unit 200. .. This resets the PD 104, FD 156 and storage capacity 160.

At time t1 when there is an input to start imaging by pressing the release button or the like, the drive unit 502 turns off the transfer transistor 154 by setting the wiring Tx_i_j to low. As a result, the light incident on the PD 104 is photoelectrically converted and begins to be accumulated as an electric charge.

The drive unit 502 performs wiring from the end time t3 to the time t4 after turning off the reset transistor 152 and the pass transistor 158 by setting the voltages of the wirings Rst_i_j and Wrt_i_j to low at the time t2 immediately before the set end time t3 of the charge accumulation. Send a transfer pulse that makes Tx_i_j high. As a result, the charge photoelectrically converted by the PD 104 is accumulated in the FD 156.

After the time t4, the drive unit 502 sends a transfer pulse that makes the wiring Wrt_i_j high from the time t5 to the time t6. As a result, the charge stored in the FD 156 is transferred to the storage capacity 160, isolated from the subsequent charge storage in the PD 104, and the charge is retained. By setting the wiring Rst_i_j to high at the subsequent time t7, the charge storage and transfer operations are terminated.

The operation of one pixel 150 in FIG. 3 has been described above. However, as shown in FIG. 4, in the unit block 131, the wiring Rst_i_j and the like are commonly connected by P pixels 150 in the same row. Therefore, the operation of FIG. 8 is executed all at once on the pixels 150 in the same row in at least the unit block 131.

Further, at the time of the global shutter, the operation of FIG. 8 is executed all at once for the pixels 150 of the L row in the unit block 131 of m rows and n columns. That is, for the wiring in which the subscript i is 1 to m × n and the subscript j is 1 to L in the wiring Rst_i_j or the like, high and low are simultaneously switched according to FIG. As a result, the image light incident on each pixel 150 at the same time can be photoelectrically converted to retain the electric charge. Unless otherwise specified, it is assumed that the global shutter has been executed.

FIG. 9 shows a timing chart of an operation of reading a pixel signal of the pixel 150. Hereinafter, an operation in which the pixel signal of the pixel 150 is read out to the column transmission line 170 will be described with reference to FIG.

The drive unit 502 turns on the selection transistor 164 by setting the wiring Sel_i_j to high at a time t8 after the time t7. As a result, the voltage as a pixel signal corresponding to the voltage generated by the electric charge stored in the storage capacity 160 is output to the column transmission line 170. Further, the drive unit 502 sends a pass pulse that makes the wiring Wrt_i_j high while the wiring Sel_i_j is high. As a result, the voltage as a reset signal at the node with the amplification transistor 162 in the storage capacity 160 is output to the column transmission line 170. At the subsequent time t9, the drive unit 502 ends the reading with respect to the pixel 150 by setting the wiring Sel_i_j to low.

The CDS circuit 202 removes noise based on the pixel signal and the reset signal. The A / D conversion circuit 204 converts the pixel signal from which noise has been removed by the CDS circuit 202 into a digital signal and outputs it.

FIG. 10 is a timing chart showing the readout timings of the plurality of pixels 150 included in the image pickup unit. As described with reference to FIG. 9, the pass pulse for the wiring Wrt_i_j is sent with the wiring Sel_i_j set to high. Therefore, for the purpose of simplifying the explanation, only the timing chart of the wiring Sel_i_j is shown in FIG.

In the readout of the entire image pickup unit, first, the pixel 150 in the first row of the entire image pickup unit is selected. That is, the pixel 150 in the first row in the unit block 131 in the first row is selected. In the example of FIG. 5, in the unit block 131 on the first line, the subscripts i correspond to 1 to n. Therefore, the drive unit 502 sends a selection pulse that simultaneously sets the wiring Ser_i_1 (where i is 1 to n) high to the row control unit 200 of the corresponding unit block 131.

As described above, in the unit block 131, the wiring Cell_i_1 is commonly connected by the pixel 150 in the first row. Further, a selection pulse is sent to the unit block 131 on the first row. Therefore, the pixel signal of the pixel 150 in the first row is read out to each column transmission line 170 across the plurality of unit blocks 131.

Each of the column transmission lines 170 transmits a pixel signal from the pixel 150 selected by the row control unit 200 to the CDS circuit 202 of the corresponding column in the unit block 131. The pixel signal is noise-removed by the CDS circuit 202, converted into a digital signal by the A / D conversion circuit 204, and input to the shift register 206. The shift register 206 receives and temporarily holds P digital signals in the first row in the unit block 131 via each of the column transmission lines 170 by the read operation.

The shift register 206 sequentially outputs P digital signals to the shift register 210 via the column bus line 172. In this case, it is preferable that the unit blocks 131 on the first row are transmitted synchronously with each other. The shift register 210 receives the pixels 150 in the first row of the entire imaging unit, that is, P × n digital signals by the read operation.

The shift register 210 sequentially outputs P × n digital signals to the pixel memory 414, and the pixel memory 414 stores the digital signals as pixel values. In this case, it is preferable that the shift register 210 outputs digital signals in the order in which the pixels 150 are arranged in the entire imaging unit. In the examples shown in FIGS. 4 and 5, P digital signals of the pixels 150 in the first row in the unit block 131 of the first (i = 1) are output from left to right, and then P pieces are output from the second (i = 2). ), P digital signals of the pixels 150 in the first row in the unit block 131 are output from left to right, and so on.

As a result, the reading of the pixel 150 in the first row of the entire imaging unit is completed. Next, the pixel 150 in the second row in the entire imaging unit is selected. That is, the pixel 150 in the second row in the unit block 131 in the first row is selected. The drive unit 502 sends a selection pulse that simultaneously sets the wiring Ser_i_2 (where i is 1 to n) high to the row control unit 200 of the corresponding unit block 131. As a result, the pixel signal of the pixel 150 in the second row is read out in the same manner as the pixel 150 in the first row, and is output to the pixel memory 414 as a pixel value.

After that, the above operation is repeated from the third line to the Lth line, which is the last line in the unit block 131. As a result, the reading of the pixel 150 included in the unit block 131 of the first row is completed.

Next, the pixel 150 in the (L + 1) th row in the entire imaging unit is selected. That is, the pixel 150 in the first row in the unit block 131 in the second row is selected. The drive unit 502 sends a selection pulse that simultaneously sets the wiring Ser_i_1 (where i is (n + 1) to 2n) high to the row control unit 200 of the corresponding unit block 131. As a result, the pixel signal of the pixel 150 in the first row of the unit block 131 in the second row is read out and output to the pixel memory 414 as a pixel value, as in the case of the unit block 131 in the first row. Similarly, from the (L + 2) th row to the 2Lth row in the entire image pickup unit, that is, from the second row to the Lth row of the unit block 131 of the second row are sequentially read out. As a result, the reading of the pixel 150 included in the unit block 131 on the second row is completed.

After that, from the (2L + 1) th line to the L × m line in the entire imaging unit, that is, from the first line of the unit block 131 on the third line to the Lth line of the unit block 131 on the mth line, sequentially. Read out. As a result, the reading of the (L × P) × (n × m) pixels 150 included in the entire image pickup unit, that is, the unit block 131 of m rows and n columns is completed.

In the above embodiment, the pixel signal is converted into a digital signal by the peripheral circuit 133 before the input to the shift register 210 that sequentially outputs the pixels to the pixel memory 414. Therefore, it is possible to prevent noise from being superimposed while being held by the shift register 210. Further, since the pixel signal is converted into a digital signal before the input to the shift register 206 of the peripheral circuit 133, it is possible to suppress the superposition of noise in the state held by the shift register 206.

Further, by dividing the imaging unit into a plurality of unit blocks 131 and arranging the peripheral circuit 133 corresponding to the unit block 131 on the signal processing chip 111 side, the shift registers 206 and 210 can be reached without reducing the area of the PD 104. A / D conversion can be performed before inputting. Further, even if the unit blocks 131 are arranged in a matrix and the pixels 150 in the unit block 131 are also arranged in a matrix, it is possible to output a pixel signal according to the arrangement of the pixels 150 in the entire imaging unit in a matrix. can. As a result, in the pixel memory 414, the image processing unit 511, and the like, it is not necessary to use additional circuits, processing, and the like due to the imaging unit being divided into the unit blocks 131.

FIG. 11 shows another example of the connection relationship of the peripheral circuit 133 and the like. In FIG. 11, the same configuration as in FIG. 5 is assigned the same number, and the description thereof will be omitted.

A matrix switch 220 is connected to the output side of the n row bus lines 172. The output side of the matrix switch 220 is connected from the shift register 206_1 to the shift register 206_k.

The matrix switch 220 inputs the digital signal transmitted to the column bus line 172 to one of the plurality of shift registers 206 for each unit block 131 included in the corresponding column. For example, the digital signals from the column bus lines 172_1 and 172_2 are input to the shift register 206_1, and the digital signals from the column bus lines 172_3 and 172_2 are input to the shift register 206_1.

Further, the matrix switch 220 may dynamically change the combination of the column bus line 172 and the shift register 206_1 and the like. For example, in moving image shooting, live view (also called through image display, etc.), crop shooting, etc., when reading from a part of the unit block 131 of the imaging unit, the row bus line 172 of the unit block 131 to be read is read. And the shift register 206_1 or the like may be set. For example, when reading out n / 2 unit blocks 131, these unit blocks 131 may be allocated from the shift register 206_1 to the shift register 206_k as evenly as possible. As a result, the pixel signal is output at the preset maximum transmission frequency regardless of whether the pixel signal is output from the unit block 131 of m rows and n columns or the pixel signal is output from a smaller number of unit blocks 131. Can be transmitted.

Although the example of using the global shutter in the above embodiment has been described, the global shutter may not be used instead. In this case, charges are accumulated and transferred all at once in the unit block 131, and they may change in time between the plurality of unit blocks 131. Instead, the charge accumulation and transfer may be temporally back and forth between the pixels 150 in the unit block 131. Whether or not to use the global shutter may be automatically set by the user's choice or based on the shooting conditions.

Although the memory circuit is used in the pixel 150 of FIG. 3, the memory circuit may not be used. In that case, for example, a mechanical shutter may be used as the global shutter.

The peripheral circuit 133 of FIG. 4 has a CDS circuit 202 and an A / D conversion circuit 204 for each row. The number of pairs of the CDS circuit 202 and the A / D conversion circuit 204 may be larger or smaller than this. For example, a pair of the CDS circuit 202 and the A / D conversion circuit 204 may be provided for one pixel 150. In this case, a pair of the CDS circuit 202 and the A / D conversion circuit 204 is provided on the signal processing chip 111 side, and the output line for each pixel 150 is connected via the bump 109, and the signal processing chip. A column transmission line for transmitting the output of the A / D conversion circuit 204 for each column may be provided on the 111 side.

In the peripheral circuit 133 of FIG. 4, the shift register 206 sequentially inputs P digital signals for one line to the shift register 210. Instead of this, a row bus line 172 may be provided in a P system for each row, and the peripheral circuit 133 may simultaneously input P digital data to the shift register 210 via the row bus line 172. Further, the column bus line 172 is provided with the number of lines corresponding to the number of bits per row, and digital signals may be transmitted all at once with respect to the number of bits, or may be provided with a number less than the number of bits per row and sequentially transmitted with respect to the number of bits. May be good.

In FIG. 10, selection pulses are sequentially sent row by row in the unit block 131. Instead of this, the selection pulse may be sent all at once to the unit block 131 of m rows and n columns. That is, the transfer pulse may be sent all at once from 1 to m × n in i in the wiring Ser_i_j. In this case, the drive unit 502 sends out P digital signals from the shift register 206 corresponding to one unit block 131 to each shift register 206 of the unit block 131 in the same row according to the order of the columns. After that, the timing is controlled so that P digital signals are sent from the shift register 206 corresponding to the next unit block 131.

Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the description of the claims that the form with such changes or improvements may be included in the technical scope of the present invention.

The order of execution of each process such as operation, procedure, step, and step in the apparatus, system, program, and method shown in the claims, specification, and drawings is particularly "before" and "prior to". It should be noted that it can be realized in any order unless the output of the previous process is used in the subsequent process. Even if the scope of claims, the specification, and the operation flow in the drawings are explained using "first", "next", etc. for convenience, it means that it is essential to carry out in this order. It's not a thing.

100 Imaging element, 101 Microlens, 102 Color filter, 103 Passion membrane, 104 PD, 105 Transistor, 106 PD layer, 107 Wiring, 108 Wiring layer, 109 Bump, 110 TSV, 111 Signal processing chip, 112 Memory chip, 113 Imaging Chip, 131 unit block, 133 peripheral circuit, 150 pixels, 152 reset transistor, 154 transfer transistor, 156 FD, 158 pass transistor, 160 storage capacity, 162 amplification transistor, 164 selection transistor, 166 load current source, 170 column transmission path, 172 column bus line, 200 line control unit, 202 CDS circuit, 204 A / D conversion circuit, 206 shift register, 210 shift register, 220 matrix switch, 414 pixel memory, 415 arithmetic circuit, 418 I / F circuit, 420 drive control 430 Timing memory, 441 sensor control unit, 442 block control unit, 443 synchronization control unit, 444 signal control unit, 500 image pickup device, 520 shooting lens, 501 system control unit, 502 drive unit, 503 photometric unit, 504 work memory , 505 Recording unit, 506 Display unit, 511 Image processing unit, 512 Calculation unit

Claims (11)

A pixel block having a plurality of pixels, each of which is arranged side by side in three or more in a first direction and a second direction intersecting with the first direction and includes a photoelectric conversion unit that converts light into electric charges.
A signal processing circuit arranged for each of the pixel blocks arranged three or more side by side in the first direction and the second direction, respectively.
A control unit that is arranged for each of the pixel blocks arranged side by side in each of the first direction and the second direction, and outputs a control signal for reading a signal based on the charge photoelectrically converted from the pixel. And, with
Each of the signal processing circuits includes a plurality of conversion circuits for converting an analog signal into a digital signal.
The pixel blocks are arranged in a matrix on an imaging chip to which light is incident, and the pixel blocks are arranged in a matrix.
The signal processing circuit and the control unit are image pickup devices arranged on the signal processing chip connected to the image pickup chip. In the image pickup device according to claim 1,
The image pickup chip is an image pickup element laminated on the signal processing chip. In the image pickup device according to claim 1 or 2.
The pixel block has at least a first pixel and a second pixel among the plurality of the pixels.
The signal processing circuit has at least a first conversion circuit connected to the first pixel and a second conversion circuit connected to the second pixel among the plurality of conversion circuits.
The signal processing circuit is an image pickup element arranged in the first direction and the second direction, respectively. In the image pickup device according to claim 3,
The signal processing circuit has a first read circuit that reads out a digital signal converted by the plurality of conversion circuits.
The signal processing chip is connected to the signal processing circuit arranged in each of the first direction and the second direction, and has a second read circuit for reading a digital signal read by the first read circuit. element. In the image pickup device according to claim 4,
The first read circuit is an image pickup device that sequentially reads out digital signals converted by the plurality of conversion circuits. In the image pickup device according to claim 5,
The second read circuit is an image pickup device that sequentially reads out digital signals read by the plurality of first read circuits. The image sensor according to any one of claims 1 to 6.
The pixel has a transfer unit for transferring the electric charge converted by the photoelectric conversion unit.
The control unit is an image pickup device that controls the transfer unit. In the image pickup device according to claim 7,
The pixel has a reset unit connected to a floating diffusion in which the charge of the photoelectric conversion unit is transferred by the transfer unit and a supply unit to which a predetermined voltage is supplied.
The control unit is an image pickup device that controls the reset unit. In the image pickup device according to claim 7 or 8.
The pixel has a floating diffusion in which the electric charge of the photoelectric conversion unit is transferred by the transfer unit, and a memory circuit for accumulating the electric charge of the floating diffusion unit.
The control unit is an image pickup device that controls the memory circuit. The image sensor according to any one of claims 1 to 6.
The pixel has a reset unit connected to a floating diffusion to which electric charges from the photoelectric conversion unit are transferred and a supply unit to which a predetermined voltage is supplied.
The control unit is an image pickup device that controls the reset unit. The image pickup device according to any one of claims 1 to 10.
An image processing unit connected to the image sensor and for generating image data,
An image pickup device equipped with.

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