JP2019083550A - Electronic apparatus - Google Patents

Abstract

To solve the problem in which: a large amount of data slows processing in a plurality of times of imaging.SOLUTION: An electronic apparatus comprises: an imaging device including a first imaging area that has a plurality of first pixels each having a first photoelectric conversion unit that converts light into an electric charge, a second imaging area that has a plurality of second pixels each having a second photoelectric conversion unit that converts light into an electric charge, first output lines that output signals generated by the electric charges obtained through the photoelectric conversion performed by the plurality of first pixels, and second output lines that are different from the first output lines and output signals generated by the electric charges obtained through the photoelectric conversion performed by the plurality of second pixels, where the first imaging area and the second imaging area are arranged in a column direction; a setting unit that sets, to the second imaging area, an imaging condition different from that for the first imaging area; a correction unit that corrects a part of image data generated in the first imaging area and a part of image data generated in the second imaging area such that a boundary between an image of a subject picked up in the first imaging area and an image of the subject picked up in the second imaging area becomes inconspicuous; and an image creation unit that creates an image from the image data corrected by the correction unit.SELECTED DRAWING: Figure 9

Description

  The present invention relates to an electronic device.

There is an imaging apparatus which divides the inside of the effective pixel area into a plurality of small areas and calculates a focus evaluation value for each small area with respect to image data obtained by imaging (see, for example, Patent Document 1). In this imaging device, imaging is performed at a plurality of step positions of the focus lens. Furthermore, based on the focus evaluation value for each small area, image data corresponding to a plurality of small areas at different step positions or at the same step position are integrated to generate an image.
[Prior art document]
[Patent Document]
[Patent Document 1] JP-A-2009-260800

  However, in the above imaging apparatus, in imaging at each step position, image data of pixels in the effective pixel area is obtained and then divided into a plurality of small areas, so the amount of data is large and processing is delayed. There is.

  In the first aspect of the present invention, a second imaging region having a plurality of first pixels having a plurality of first pixels each having a first photoelectric conversion portion for converting light into electric charge, and a second photoelectric conversion portion for converting light into electric charge A second imaging region having a plurality of pixels, a first output line for outputting signals generated by charges converted by photoelectric conversion of the plurality of first pixels, and charges converted by photoelectric conversion of the plurality of second pixels An imaging element having a second output line different from the first signal line for outputting the generated signal, wherein the first imaging area and the second imaging area are arranged in the column direction, and the second imaging area A setting unit configured to set an imaging condition different from the first imaging area, a part of image data generated in the first imaging area, and a part of image data generated in the second imaging area The image of the subject imaged in the area and the image of the subject imaged in the second imaging area A correcting unit for correcting such boundary is inconspicuous, the image data corrected by the correction unit, an electronic apparatus including an image generator for generating an image, is provided.

  Note that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a subcombination of these feature groups can also be an invention.

FIG. 2 is a cross-sectional view of a backside illumination type MOS imaging device according to the present embodiment. It is a figure explaining the pixel array and unit block of an imaging chip. It is a circuit diagram corresponding to the unit block of an imaging chip. It is a block diagram showing composition of an imaging device concerning this embodiment. It is a block diagram showing the concrete composition as an example of a signal processing chip. 2 shows functional blocks of an arithmetic circuit. 5 shows an example of a subject used to explain the operation of the imaging device. Indicates the positional relationship between individual subjects included in the subject. It is an example of the flowchart which shows operation of an imaging device. An example of the image imaged is shown. An example of the image imaged is shown. An example of the image imaged is shown. An example of the image imaged is shown. An example of the image imaged is shown.

  Hereinafter, the present invention will be described through the embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Moreover, not all combinations of features described in the embodiments are essential to the solution of the invention.

  FIG. 1 is a cross-sectional view of a backside illumination type imaging device 100 according to the present embodiment. The imaging device 100 includes an imaging chip 113 which outputs a pixel signal corresponding to incident light, a signal processing chip 111 which processes the pixel signal, and a memory chip 112 which stores the pixel signal. The imaging chip 113, the signal processing chip 111, and the memory chip 112 are stacked and electrically connected to each other by the bump 109 having conductivity such as Cu.

  As illustrated, incident light is mainly incident in the Z-axis plus direction indicated by the outlined arrow. In the present embodiment, in the imaging chip 113, the surface on which incident light is incident is referred to as the back surface. Further, as indicated by the coordinate axes, the left direction in the drawing, which is orthogonal to the Z axis, is taken as the plus direction of the X axis, and the near direction in the drawing, which is orthogonal to the Z axis and the X axis, is taken as the plus direction. In the following several figures, coordinate axes are displayed so that the orientation of each figure can be known with reference to the coordinate axes in FIG.

  An example of the imaging chip 113 is a backside illumination type MOS image sensor. The PD layer 106 is disposed on the back side of the wiring layer 108. The PD layer 106 is two-dimensionally arranged, and includes a plurality of PDs (photodiodes) 104 that store charges according to incident light, and transistors 105 provided corresponding to the PDs 104.

  A color filter 102 is provided on the incident side of incident light in the PD layer 106 via a passivation film 103. The color filter 102 has a plurality of types that transmit different wavelength regions, and has a specific arrangement corresponding to each of the PDs 104. The arrangement of the color filters 102 will be described later. A combination of the color filter 102, the PD 104, and the transistor 105 forms one pixel.

  A microlens 101 is provided on the color filter 102 on the incident side of the incident light corresponding to each pixel. The microlenses 101 condense incident light toward the corresponding PDs 104.

  The wiring layer 108 has a wiring 107 for transmitting the pixel signal from the PD layer 106 to the signal processing chip 111. The wiring 107 may be a multilayer, and passive elements and active elements may be provided.

  A plurality of bumps 109 are disposed on the surface of the wiring layer 108. The plurality of bumps 109 are aligned with the plurality of bumps 109 provided on the facing surface of the signal processing chip 111, and the imaging chip 113 and the signal processing chip 111 are aligned by pressure or the like. The bumps 109 are joined to be electrically connected.

  Similarly, a plurality of bumps 109 are disposed on the surfaces facing each other of the signal processing chip 111 and the memory chip 112. These bumps 109 are aligned with each other, and the signal processing chip 111 and the memory chip 112 are pressurized or the like, whereby the aligned bumps 109 are joined and electrically connected.

  The bonding between the bumps 109 is not limited to Cu bump bonding by solid phase diffusion, and micro bump bonding by solder melting may be employed. Also, the bump 109 may be provided, for example, about one for one unit block described later. Therefore, the size of the bumps 109 may be larger than the pitch of the PDs 104. Further, in the peripheral area other than the imaging area in which the pixels are arranged, bumps larger than the bumps 109 corresponding to the imaging area may be provided.

  The signal processing chip 111 has TSVs (silicon through electrodes) 110 which mutually connect circuits respectively provided on the front and back surfaces. The TSVs 110 are preferably provided in the peripheral area. Also, the TSV 110 may be provided in the peripheral area of the imaging chip 113 and the memory chip 112.

  FIG. 2 is a diagram for explaining the pixel array of the imaging chip 113 and the unit block 131. As shown in FIG. In particular, a state in which the imaging chip 113 is observed from the back surface side is shown. In the imaging region, more than 20 million pixels are arranged in a matrix. The imaging region is divided into a plurality of unit blocks 131.

  In the example of FIG. 2, 16 adjacent 4 × 4 pixels form one unit block 131. The grid lines in the figure show the concept that adjacent pixels are grouped to form a unit block 131. The number of pixels forming the unit block 131 is not limited to this, and may be about 1000, for example, 32 pixels × 64 pixels, or more or less. The unit blocks 131 are arranged two-dimensionally to form the imaging region.

  As shown in the partial enlarged view of the pixel area, the unit block 131 includes four so-called Bayer arrays consisting of four pixels of green pixels Gb and Gr, blue pixels B and red pixels R in the top, bottom, left, and right. The green pixel is a pixel having a green filter as the color filter 102, and receives light in the green wavelength band of incident light. Similarly, the blue pixel is a pixel having a blue filter as the color filter 102 and receives light in the blue wavelength band, and the red pixel is a pixel having a red filter as the color filter 102 and having light in the red wavelength band Receive light.

  In the present embodiment, an evaluation value is calculated for each of the plurality of unit blocks 131, and it is determined whether the evaluation value satisfies a predetermined determination condition. Accumulation, reading, and the like of the unit blocks 131 satisfying the determination conditions are completed, and the imaging conditions are changed for the unit blocks 131 not satisfying the determination conditions, accumulation, readout, and determination of evaluation values are repeated. An example of the evaluation value is the contrast in the unit block 131, and an example of the determination condition is whether or not the maximum value is obtained. An example of the imaging condition to be changed in this case is the in-focus position. Another example of the evaluation value is the luminance in the unit block 131, and an example of the determination condition is whether or not the maximum value is obtained. Examples of imaging conditions to be changed in this case are the aperture, shutter speed, ISO sensitivity and the like.

  FIG. 3 is a circuit diagram corresponding to the unit block 131 of the imaging chip 113. As shown in FIG. In the drawing, a rectangle which is typically surrounded by a dotted line represents a circuit corresponding to one pixel. Note that at least a part of each of the transistors described below corresponds to the transistor 105 in FIG.

  As described above, the unit block 131 is formed of 16 pixels. The 16 PDs 104 corresponding to each pixel are connected to the transfer transistor 302, and each gate of each transfer transistor 302 is connected to the TX wiring 307 to which a transfer pulse is supplied. In the present embodiment, the TX wiring 307 is commonly connected to the sixteen transfer transistors 302.

  The drain of each transfer transistor 302 is connected to the source of the corresponding reset transistor 303, and a so-called floating diffusion FD between the drain of the transfer transistor 302 and the source of the reset transistor 303 is connected to the gate of the amplification transistor 304. The drain of the reset transistor 303 is connected to a Vdd wiring 310 supplied with a power supply voltage, and the gate thereof is connected to a reset wiring 306 supplied with a reset pulse. In the present embodiment, the reset wiring 306 is commonly connected to the sixteen reset transistors 303.

  The drain of each amplification transistor 304 is connected to a Vdd wiring 310 to which a power supply voltage is supplied. Also, the source of each amplification transistor 304 is connected to the drain of each corresponding selection transistor 305. Each gate of the selection transistor is connected to a decoder wiring 308 to which a selection pulse is supplied. In the present embodiment, the decoder wiring 308 is provided independently for each of the 16 selection transistors 305. The source of each selection transistor 305 is connected to the common output wiring 309. The load current source 311 supplies a current to the output wiring 309. That is, the output wiring 309 for the selection transistor 305 is formed by a source follower. The load current source 311 may be provided on the imaging chip 113 side or may be provided on the signal processing chip 111 side. Further, instead of providing the decoder wirings 308 for the number of pixels, transistors corresponding to the matrix selection lines and the lines may be provided to select individual pixels.

  Here, the flow from the start of charge accumulation to the output of the pixel signal after the end of accumulation will be described. When a reset pulse is applied to the reset transistor 303 through the reset wire 306 and a transfer pulse is simultaneously applied to the transfer transistor 302 through the TX wire 307, the potentials of the PD 104 and the floating diffusion FD are reset.

  When the application of the transfer pulse is released, the PD 104 converts incident light to be received into charge and accumulates it. Thereafter, when the transfer pulse is applied again in a state where the reset pulse is not applied, the accumulated charge is transferred to the floating diffusion FD, and the potential of the floating diffusion FD becomes a signal potential after charge accumulation from the reset potential. . Then, when a selection pulse is applied to the selection transistor 305 through the decoder wiring 308, a change in signal potential of the floating diffusion FD is transmitted to the output wiring 309 through the amplification transistor 304 and the selection transistor 305. Thus, the pixel signal corresponding to the reset potential and the signal potential is output from the unit pixel to the output wiring 309.

  As illustrated, in the present embodiment, the reset wiring 306 and the TX wiring 307 are common to 16 pixels forming the unit block 131. That is, the reset pulse and the transfer pulse are simultaneously applied to all 16 pixels. Therefore, all the pixels forming the unit block 131 start charge accumulation at the same timing and end charge accumulation at the same timing. However, the pixel signals corresponding to the accumulated charges are selectively applied to the output wiring 309 as the selection transistors 305 sequentially apply selection pulses. The reset wiring 306, the TX wiring 307, and the output wiring 309 are separately provided for each unit block 131.

  By configuring the circuit based on the unit block 131 as described above, the charge accumulation time can be controlled for each unit block 131. In other words, pixel signals with different charge accumulation times can be output between adjacent unit blocks 131, respectively. Furthermore, while causing one unit block 131 to perform one charge accumulation, the other unit block 131 repeats the charge accumulation many times and outputs the pixel signal each time. The unit blocks 131 can also output moving image frames at different frame rates. Further, the presence or absence of readout of the pixel signal can be controlled for each unit block 131.

  FIG. 4 is a block diagram showing the configuration of the imaging device according to the present embodiment. The imaging device 500 includes a shooting lens 520 as a shooting optical system, and the shooting lens 520 guides a subject light flux incident along the optical axis OA to the image sensor 100. The imaging lens 520 may be an interchangeable lens that can be attached to and detached from the imaging device 500. The imaging device 500 mainly includes an imaging element 100, a system control unit 501, a drive unit 502, a photometry unit 503, a work memory 504, a recording unit 505, a display unit 506, and a drive unit 514.

  The photographing lens 520 is composed of a plurality of optical lens groups, and focuses a subject light flux from a scene in the vicinity of its focal plane. In FIG. 4, the imaging lens 520 is represented by a single virtual lens disposed in the vicinity of the pupil.

  The drive unit 514 drives the photographing lens 520. More specifically, the drive unit 514 moves the optical lens group of the imaging lens 520 to change the in-focus position, and drives the iris diaphragm in the imaging lens 520 to change the light amount of the subject light flux incident on the imaging device 100 Control.

  The drive unit 502 is a control circuit that executes charge storage control such as timing control and area control of the imaging device 100 in accordance with an instruction from the system control unit 501. Also, the operation unit 508 receives an instruction from the imaging person by a release button or the like.

  The imaging element 100 delivers the pixel signal to the image processing unit 511 of the system control unit 501. The image processing unit 511 performs various image processing with the work memory 504 as a work space, and generates image data. For example, in the case of generating image data in the JPEG file format, compression processing is performed after generating a color video signal from the signal obtained by the Bayer arrangement. The generated image data is recorded in the recording unit 505, and is converted into a display signal and displayed on the display unit 506 for a preset time.

  The photometry unit 503 detects a luminance distribution of a scene prior to a series of imaging sequences for generating image data. The photometry unit 503 includes, for example, an AE sensor of about one million pixels. The calculation unit 512 of the system control unit 501 receives the output of the photometry unit 503 and calculates the luminance for each area of the scene. The computing unit 512 determines the shutter speed, the aperture value, and the ISO sensitivity in accordance with the calculated luminance distribution. The photometry unit 503 may be shared by the image sensor 100. The calculation unit 512 also executes various calculations for operating the imaging device 500.

  A part or all of the driving unit 502 may be mounted on the imaging chip 113, or a part or all of the driving unit 502 may be mounted on the signal processing chip 111. A part of the system control unit 501 may be mounted on the imaging chip 113 or the signal processing chip 111.

  FIG. 5 is a block diagram showing a specific configuration of the signal processing chip 111 as an example. The signal processing chip 111 bears the function of the drive unit 502.

  The signal processing chip 111 integrally controls the sensor control unit 441 as a shared control function, the block control unit 442, the synchronization control unit 443, the signal control unit 444, the individual circuit unit 450A, and the like. And a drive control unit 420. The signal processing chip 111 further includes an I / F circuit 418 between the drive control unit 420 and the system control unit 501 of the imaging device 500 main body. The sensor control unit 441, the block control unit 442, the synchronization control unit 443, the signal control unit 444, and the drive control unit 420 are provided one by one for the signal processing chip 111.

  On the other hand, the individual circuit units 450A, 450B, 450C, 450D, and 450E are provided for each of the unit blocks 131A, 131B, 131C, 131D, and 131E. Since the individual circuit units 450A, 450B, 450C, 450D, and 450E have the same configuration, the individual circuit unit 450A will be described below. The individual circuit unit 450A includes a CDS circuit 410, a multiplexer 411, an A / D conversion circuit 412, a demultiplexer 413, a pixel memory 414, and an arithmetic circuit 415. The arithmetic circuit 415 transmits and receives signals to and from the system control unit 501 via the I / F circuit 418.

  It is preferable that the individual circuit unit 450A be disposed in an area overlapping the area where the pixels of the corresponding unit block 131A are disposed. Thus, the individual circuit units 450A can be provided in each of the plurality of unit blocks 131A without enlarging each chip in the surface direction.

  The drive control unit 420 refers to the timing memory 430, converts an instruction from the system control unit 501 into a control signal executable by each control unit, and delivers the control signal to each control unit. In particular, the drive control unit 420 specifies a unit block 131A or the like that is to be stored and read in the timing memory 430, and passes control parameters to each control unit together with information for specifying the unit block 131A or the like. Examples of control parameters are a frame rate, a decimation rate, the number of addition rows or addition columns for adding pixel signals, the charge accumulation time or number of accumulation times, the number of bits for digitization, and the like.

  The sensor control unit 441 controls transmission of control pulses related to charge accumulation and charge readout of each pixel, which are sent to the imaging chip 113. Specifically, the sensor control unit 441 controls the start and end of charge accumulation by sending a reset pulse and a transfer pulse to the target pixel, and sends a selection pulse to the read pixel. The pixel signal is output to the output wiring 309.

  The block control unit 442 sends out a specific pulse that specifies the unit block 131 to be controlled, which is sent to the imaging chip 113. The transfer pulse and the reset pulse that each pixel receives through the TX wiring 307 and the reset wiring 306 are the logical product of each pulse sent out by the sensor control unit 441 and the specific pulse sent out by the block control unit 442. Thus, each area can be controlled as independent blocks.

  The synchronization control unit 443 sends a synchronization signal to the imaging chip 113. Each pulse becomes active in the imaging chip 113 in synchronization with the synchronization signal. For example, by adjusting the synchronization signal, random control, thinning control, and the like can be realized in which only specific pixels of pixels belonging to the same unit block 131A or the like are to be controlled.

  The signal control unit 444 mainly performs timing control on the A / D conversion circuit 412. The pixel signal output via the output wiring 309 is input to the A / D conversion circuit 412 via the CDS circuit 410 and the multiplexer 411. The CDS circuit 410 removes noise from the pixel signal.

  The A / D conversion circuit 412 is controlled by the signal control unit 444 to convert the input pixel signal into a digital signal. The pixel signals converted into digital signals are delivered to the demultiplexer 413 and stored as pixel values of digital data in the pixel memory 414 corresponding to each pixel.

  The arithmetic circuit 415 calculates an evaluation value based on the pixel value stored in the pixel memory 414 for the corresponding unit block 131A, and determines whether the evaluation value satisfies a predetermined determination condition. The arithmetic circuit 415 outputs the result of this determination to the drive control unit 420 in association with the information specifying the unit block 131A.

  The pixel memory 414 has a memory space capable of storing pixel values equal to or more than twice the number of pixels included in the unit block 131A, and stores the respective pixel values stored and read while changing the imaging conditions. . The pixel memory 414 is provided with a data transfer interface for transmitting a pixel signal in accordance with the delivery request. The data transfer interface is connected to a data transfer line connected to the image processing unit 511. The data transfer line is constituted by, for example, a data bus among bus lines. In this case, a delivery request from the system control unit 501 to the drive control unit 420 is executed by address specification using an address bus.

  The transmission of pixel signals by the data transfer interface is not limited to the addressing scheme, and various schemes may be adopted. For example, when data transfer is performed, a double data rate method may be employed in which processing is performed using both rising and falling of a clock signal used for synchronization of each circuit. In addition, a burst transfer method may be adopted in which data is transferred at once by omitting a part of the procedure such as the address designation and the like for speeding up. Alternatively, a bus method using a line in which a control unit, a memory unit, and an input / output unit are connected in parallel, or a serial method in which data is serially transferred one bit at a time can be used in combination.

  With this configuration, the image processing unit 511 can receive only the necessary pixel values, and can complete the image processing at high speed particularly when forming an image of low resolution.

  The signal processing chip 111 has a timing memory 430 formed of a flash RAM or the like. The timing memory 430 stores control parameters such as information on the number of times of charge accumulation repeated for which unit block 131A and the like in association with information specifying the unit block 131A and the like. Further, information indicating “whether or not the evaluation value satisfies the determination condition” output from the arithmetic circuit 415 such as the individual circuit unit 450A to the timing memory 430, for example, information indicating a unit block 131A etc. Stored in association with

  FIG. 6 shows functional blocks of the arithmetic circuit 415. The arithmetic circuit 415 includes a high frequency component calculation unit 460, a contrast calculation unit 462, and a maximum detection unit 464. The high frequency component calculation unit 460 reads out the G pixel signal of each pixel of the unit block 131A stored in the pixel memory 414, and extracts the spatial high frequency component Gh by performing high pass filter processing based on the two-dimensional array. Do. Similarly, the high frequency component calculation unit 460 calculates the high frequency component Rh of the R pixel and the high frequency component Bh of the B pixel.

  The contrast calculating unit 462 calculates the sum of the absolute values of the high frequency components Gh, Rh, and Bh for a plurality of pixels included in the unit block 131A. The contrast value is an example of an evaluation value. The method of calculating the contrast value is not limited to this.

  The maximum detection unit 464 detects whether the contrast value of the unit block 131A is the maximum. In this case, the maximum detection unit 464 stores the history of the contrast value and detects whether the maximum is obtained by comparing the newly calculated contrast value with the contrast value calculated in the past. Do. Whether or not the maximum value is obtained is an example of the determination condition for determining whether the evaluation value of the unit block 131A satisfies the determination condition.

  The maximum detection unit 464 outputs, to the drive control unit 420, information indicating whether or not the contrast value has reached a maximum. Alternatively or additionally, the maximum detection unit 464 may write the information directly to the timing memory 430.

  FIG. 7 shows an example of a subject 170 used to explain the operation of the imaging device 500. FIG. 8 shows the positional relationship of individual subjects included in the subject 170.

  In the example shown in FIGS. 7 and 8, the subject 170 includes subjects A, B, C, D, and E. As shown in FIG. 8, subjects A, B, C, D, and E are arranged in order of proximity to the imaging device 500.

  A thin line in FIG. 7 indicates the boundary of the unit block 131 when the subject 170 is imaged over the entire imaging area of the imaging device 100. A thick line indicates a boundary of a unit block group 132A or the like including a plurality of or a single unit block 131 including each of the subject A and the like.

  FIG. 9 is an example of a flowchart showing the operation of the imaging device 500. 10 to 14 show an example of an image captured by the operation. Although FIGS. 10 to 14 are referred to as images for the sake of explanation, these images may not be generated as a format that can be displayed on the imaging device 500.

  The flowchart of FIG. 9 starts, for example, when the release button of the imaging device 500 is half-depressed. The system control unit 501 sets imaging conditions such as an aperture value and a shutter speed (S100). These imaging conditions may give priority to the input from the photographer, or may be preset by the system control unit 501 side. In the case where the setting is performed by the system control unit 501, it is particularly preferable to set the aperture value to the open side and the shutter speed to the fast side.

  The system control unit 501 drives the photographing lens 520 by the drive unit 514 to set the in-focus position (S102). In this case, the system control unit 501 divides the area from the position of the imaging device 500 to infinity into a plurality of areas, and drives the imaging lens 520 such that the in-focus position is within each of the plurality of areas. As shown in FIG. 8, the area may be set to be longer as the distance from the imaging lens 520 increases. The system control unit 501 stores in advance a driving amount of the photographing lens 520 based on the above area in a table format or the like. In the example of FIG. 9, the in-focus position is set sequentially from the side closer to the imaging device 500 to the side farther from the side.

  The drive control unit 420 selects a unit block 131 to be stored and read based on an instruction from the system control unit 501 (S103). In this case, the drive control unit 420 refers to the timing memory 430 and specifies a unit block 131 to be stored. It is preferable that initial setting be performed so that all unit blocks 131 are selected.

  The drive control unit 420 instructs the sensor control unit 441 and the like to store and read the unit block 131 selected in step S103 (S104). The arithmetic circuit 415 calculates a contrast value in each of the unit blocks 131 based on the read pixel signal, and determines the contrast value (S106).

  When it is determined that the contrast value is the maximum value (S107: Yes), the arithmetic circuit 415 outputs the pixel value of the unit block 131 to the image processing unit 511 (S108). At the same time, the arithmetic circuit 415 writes the fact that the contrast value satisfies the determination condition in the timing memory 430 via the drive control unit 420 together with the information specifying the unit block 131.

  On the other hand, when it is determined that the contrast value is not the maximum value (S107: No), the arithmetic circuit 415 writes the pixel value of the unit block 131 to the pixel memory 414, and proceeds to step S110. Therefore, the fact that the contrast value satisfies the determination condition is not written to the timing memory 430 for the unit block 131.

  The system control unit 501 repeats the above steps S102 to S110 until the current focusing position becomes an area including infinity (S110: No). When the current in-focus position becomes an area including infinity (S110: Yes), the system control unit 501 refers to the timing memory 430 and identifies a unit block 131 that does not satisfy the determination condition at that time. The pixel value stored in each pixel memory 414 for the unit block is output to the image processing unit 511 (S112).

  The image processing unit 511 generates an image corresponding to the entire imaging region based on the pixel values output in steps S108 and S112 (S114). Thus, the flowchart of FIG. 9 ends.

  For example, in the first imaging, the in-focus position is set in the area on the left side of FIG. 8 in step S102, and the image 172 shown in FIG. 10 is obtained in step S104. Since this is the first imaging, all unit blocks 131 in the imaging region are selected in step S103. Since the subject A is in the area on the left side of FIG. 8, the subject A is in focus in the image 172, and has a high contrast value in the unit block group 132A. On the other hand, since the other subject B or the like is out of the area, the other unit block group 132B or the like has a low contrast value.

  Since there is no previous contrast value to be compared in the first imaging, the maximum detection unit 464 does not determine that any unit block 131 has reached the maximum value in step S107. Therefore, the arithmetic circuit 415 writes the pixel value of the unit block 131 to the pixel memory 414 in step S109.

  In the next imaging, the in-focus position is set in the second area from the left in FIG. 8 in step S102, and the image 174 shown in FIG. 11 is obtained in step S104. The drive control unit 420 refers to the timing memory 430, and the fact that the determination condition is satisfied for any unit block 131 is not stored. Perform a read of

  The unit block group 132A having a high contrast value in FIG. 10 has a low contrast value in FIG. Therefore, in step S107, the maximum detection unit 464 determines that the unit block 131 included in the unit block group 132A has a maximum value in the previous imaging. Therefore, in step S108, the arithmetic circuit 415 reads the pixel value of the unit block group 132A when the contrast value is maximum, that is, the pixel value of the first imaging from the pixel memory 414, and outputs the pixel value to the image processing unit 511. At the same time, the arithmetic circuit 415 writes the fact that the contrast value satisfies the determination condition in the timing memory 430 via the drive control unit 420 together with the information specifying the unit block 131.

  In the image 174 of FIG. 11, the subjects B and C are in focus and have a high contrast value in the unit block group 132A, but it is not determined that they have reached the maximum value yet. Further, since the subjects D and E are out of the area, they have low contrast values for the other unit block groups 132B and the like. Therefore, for the unit block groups 132B, 132C, 132D, 132E corresponding to the subjects B, C, D, E, the fact that the determination condition is satisfied is not written in the timing memory 430. In addition, for the unit block groups 132B, 132C, 132D, and 132E, the pixel values in the current imaging are written to the pixel memory 414 while the pixel values of the previous imaging are held.

  Further, in the next imaging, the in-focus position is set in the third area from the left in FIG. 8, and the image 176 shown in FIG. 12 is obtained. In this case, the drive control unit 420 refers to the timing memory 430 and does not store the charges of the unit block group 132A and read the pixel signal, but stores the charges of the unit blocks 131 other than the unit block group 132A and the pixel signal. Read out the

  Further, since the contrast value of the unit block groups 132B and 132C is lower than that of the previous time, the maximum detection unit 464 determines that the maximum value is taken in the previous imaging. Therefore, the arithmetic circuit 415 reads the pixel values of the unit block groups 132B and 132C when the contrast value is maximum, that is, the pixel values of the previous imaging from the pixel memory 414, and outputs the pixel values to the image processing unit 511. At the same time, the arithmetic circuit 415 writes the fact that the contrast value satisfies the determination condition in the timing memory 430 via the drive control unit 420 together with the information specifying the unit blocks 131B and 132C.

  Further, in the next imaging, the in-focus position is set in the fourth area from the left in FIG. 8, and an image 178 shown in FIG. 13 is obtained. In this case, the drive control unit 420 does not store the charges of the unit block groups 132A, 132B, and 132C and read the pixel signals with reference to the timing memory 430, and unit blocks other than the unit block groups 132A, 132B, and 132C. Accumulate charge of 131 and read out pixel signal.

  Further, since the contrast value of the unit block group 132D is lower than that of the previous time, the maximum detection unit 464 determines that the maximum value has been taken in the previous imaging. Further, the arithmetic circuit 415 reads the pixel value of the unit block group 132D when the contrast value is maximum from the pixel memory 414, and outputs the pixel value to the image processing unit 511. At the same time, the arithmetic circuit 415 writes the fact that the contrast value satisfies the determination condition in the timing memory 430 via the drive control unit 420 together with the information specifying the unit block 131D.

  Further, in the last imaging, the in-focus position is set in the region including the infinity in FIG. 8, and the image 180 shown in FIG. 14 is obtained. In this case, the drive control unit 420 refers to the timing memory 430 and does not store charge of the unit block group 132A or the like to which the determination condition is already written and does not read pixel signals, and other units It accumulates the charge of the block and reads out the pixel signal. For convenience of explanation, it is determined that the maximum value has been taken for some unit blocks other than unit block group 132D in FIG. 13, and unit blocks for which accumulation, reading and determination are not performed are indicated by hatching in FIG. It is done.

  Also in the image 176 of FIG. 14, it is assumed that the maximum detection unit 464 can not determine the maximum value for the unit block group 132E. In this case, in step S112, the arithmetic circuit 415 reads the pixel value of the current imaging in the unit block group 132E from the pixel memory 414 and outputs the pixel value to the image processing unit 511.

  As a result, pixel values are output from any unit block 131A or the like in the imaging region. The image processing unit 511 generates an image corresponding to the subject 170 based on the pixel value.

  As described above, according to the above-described embodiment, it is possible to generate an image in focus in each of the imaging regions by pressing the release button once. In this case, an image can be generated without reducing the exposure amount, as compared to the case where the f-number is increased and pan-focused. In addition, since the number of unit blocks 131 to be stored, read, and determined decreases as imaging is performed, the processing speed can be increased and power consumption can be reduced.

  Note that the number of areas from the imaging device 500 to infinity may be set in advance, or may be set by the imaging person. The regions may be equally divided from one another, or instead, the system control unit 501 calculates the depth of field from the focal length of the imaging lens 520 and the aperture value, and The in-focus position may be set such that the distance is also included within the depth of field from any of the in-focus positions. Further, in step S102 in FIG. 9, the in-focus position is set from the side closer to the imaging device 500 to the far side, but even if the in-focus position is sequentially set from the infinity side to the imaging device 500 Good.

  When an image is generated in step S114, it is preferable to match the brightness by averaging the brightness values of at least a few pixels at the boundaries of unit blocks where pixel values are output in different imaging. It is preferable that the boundary is made inconspicuous by intentionally adding blurring, noise or the like to the boundary.

  The unit block group 132A or the like corresponding to the subject A or the like may be selected in advance by face detection or the like, and the maximum of the contrast value may be evaluated for the entire unit block group 132A or the like. In this case, the unit block 131 which did not reach the maximum value in any of the imagings did not reach the maximum value in the imaging when the contrast value of the selected unit block group 132 etc. becomes the maximum. The pixel values of the unit block 131 may be output to the image processing unit 511.

  As still another example, unit block group 132A corresponding to subject A etc. is selected in advance by face detection etc., and the maximum of the contrast value is evaluated for each unit block 131 contained in the unit block group 132A etc. You may In this case, for unit blocks 131 other than the unit block group 132A etc., for example, the pixel value is output to the image processing unit 511 at the first photographing of the in-focus position including infinity, and the steps S102 to S110 are repeated. You may decide not to do it.

  In place of or in addition to the determination in step S110, when the number of unit blocks 131 determined to satisfy the determination condition exceeds a predetermined number, the system control unit 501 repeats the following process. It may stop.

  Further, the evaluation value may be calculated by thinning out some of the unit blocks 131 among the plurality of unit blocks 131 included in the unit block group 132A. Furthermore, in any of the above embodiments, the evaluation value may be calculated by thinning out the pixels in each unit block 131.

  In addition, when a phase difference pixel is included in the imaging element 100, it may be determined whether or not focusing is performed with the phase difference pixel. In this case, the output of the phase difference pixel is an evaluation value, which is a determination condition as to whether or not focusing is achieved.

  Further, instead of providing the individual circuit unit 450A or the like for each unit block 131, the individual circuit unit 450A or the like is provided for each unit block 131, and the evaluation value for each corresponding unit block 131 is obtained. May be calculated and determined. Further alternatively, one individual circuit unit 450A may be provided for a plurality of unit blocks 131 included in the imaging area, and the evaluation value of each of the plurality of unit blocks 131 included in the imaging area may be calculated and determined. .

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It is apparent to those skilled in the art that various changes or modifications can be added to the above embodiment. It is also apparent from the scope of the claims that the embodiments added with such alterations or improvements can be included in the technical scope of the present invention.

  The execution order of each process such as operations, procedures, steps, and steps in the apparatuses, systems, programs, and methods shown in the claims, the specification, and the drawings is particularly “before”, “preceding” It is to be noted that “it is not explicitly stated as“ etc. ”and can be realized in any order as long as the output of the previous process is not used in the later process. With regard to the flow of operations in the claims, the specification and the drawings, even if it is described using “first,” “next,” etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

  Reference Signs List 100 imaging device, 101 microlens, 102 color filter, 103 passivation film, 104 PD, 105 transistor, 106 PD layer, 107 wiring, 108 wiring layer, 109 bump, 110 TSV, 111 signal processing chip, 112 memory chip, 113 imaging Chip, 131 unit block, 131 A unit block, 131 B unit block, 131 C unit block, 131 D unit block, 131 E unit block, 132 A unit block group, 132 B unit block group, 132 C unit block group, 132 D unit block group, 132 E unit block group 170 objects, 172 images, 174 images, 176 images, 178 images, 180 images, 302 transfer transistors, 303 reset transistors, 04 amplification transistor 305 selection transistor 306 reset wiring 307 TX wiring 308 decoder wiring 309 output wiring 310 Vdd wiring 311 load current source 410 CDS circuit 411 multiplexer 412 A / D converter circuit 413 demultiplexer 414 pixel memory 415 arithmetic circuit 418 I / F circuit 420 drive controller 430 timing memory 441 sensor controller 442 block controller 443 synchronization controller 444 signal controller 450A individual circuit 450B Individual circuit unit, 450C individual circuit unit, 450D individual circuit unit, 450E individual circuit unit, 460 high frequency component calculation unit, 462 contrast calculation unit, 464 maximum detection unit, 500 imaging device, 501 system control unit, 502 Moving parts, 503 photometric unit, 504 a working memory, 505 a recording unit, 506 display unit, 508 operation unit, 511 image processing unit, 512 operation unit, 514 drive, 520 a photographing lens

Claims (8)

A first imaging region having a plurality of first pixels having a first photoelectric conversion portion for converting light into electric charge, and a second imaging region having a plurality of second pixels having a second photoelectric conversion portion for converting light to electric charge; A first output line for outputting a signal generated by charges converted by photoelectric conversion of the plurality of first pixels, and a signal generated by charges converted by photoelectric conversion of the plurality of second pixels; An imaging element having a second output line different from the first signal line, wherein the first imaging area and the second imaging area are arranged in the column direction;
A setting unit configured to set an imaging condition different from the first imaging region in the second imaging region;
A part of the image data generated in the first imaging area and a part of the image data generated in the second imaging area, an image of the subject imaged in the first imaging area, and the second imaging A correction unit that corrects so that the boundary between the subject and the image of the subject captured in the region is less noticeable
An image generation unit that generates an image from the image data corrected by the correction unit;
An electronic device comprising the A plurality of imaging regions having a plurality of pixels having photoelectric conversion units for converting light into charges, and a signal generated by the charges converted by photoelectric conversion of the pixels of the plurality of imaging regions for each of the plurality of imaging regions An imaging element having an output line for outputting a plurality of output areas provided for each of the imaging areas;
A setting unit capable of setting different imaging conditions for each of the plurality of imaging areas;
A part of the image data generated in the first imaging area of the plurality of imaging areas and a part of the image data generated in the second imaging area of the plurality of imaging areas A correction unit that corrects the boundary between the image of the subject imaged in the imaging area and the image of the subject imaged in the second imaging area to be less noticeable
An electronic apparatus comprising: an image generation unit that generates an image from the image data corrected by the correction unit. In the electronic device according to claim 1 or 2,
A part of the image data generated in the first imaging area and a part of the image data generated in the second imaging area capture an image near the boundary between the first imaging area and the second imaging area An electronic device that is image data generated in a region. The electronic device according to any one of claims 1 to 3.
The correction unit performs a process of averaging a part of image data generated in the first imaging area and a part of image data generated in the second imaging area as the correction that makes the boundary inconspicuous Electronics. The electronic device according to any one of claims 1 to 3.
The correction unit adds noise to a part of the image data generated in the first imaging area and a part of the image data generated in the second imaging area as the correction to make the boundary inconspicuous. Electronic equipment to do. The electronic device according to any one of claims 1 to 3.
The correction unit performs an electronic process of blurring a part of the image data generated in the first imaging area and a part of the image data generated in the second imaging area as the correction to make the boundary inconspicuous machine. In the electronic device according to any one of claims 1 to 6,
The imaging condition is a charge accumulation time of a pixel that outputs a signal generated by the photoelectrically converted charge of the imaging region,
The electronic device according to claim 1, wherein the imaging element has a charge accumulation time of pixels of the first imaging area different from an accumulation time of pixels of the second imaging area. In the electronic device according to claim 7,
The first imaging is performed by setting the time for transferring the charges of the pixels of the first imaging area and resetting the charges different from the time for transferring the charges of the pixels of the second imaging area and resetting the charges. The electronic device which makes charge storage time of an area | region different from charge storage time of a said 2nd imaging region.

Images