WO2022047950A1 - 阵列基板及其制备方法、显示面板 - Google Patents

阵列基板及其制备方法、显示面板 Download PDF

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Publication number
WO2022047950A1
WO2022047950A1 PCT/CN2020/123865 CN2020123865W WO2022047950A1 WO 2022047950 A1 WO2022047950 A1 WO 2022047950A1 CN 2020123865 W CN2020123865 W CN 2020123865W WO 2022047950 A1 WO2022047950 A1 WO 2022047950A1
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Prior art keywords
layer
radiation
light
oxide semiconductor
base substrate
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PCT/CN2020/123865
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English (en)
French (fr)
Inventor
段淼
李冬泽
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US17/056,011 priority Critical patent/US11830881B2/en
Publication of WO2022047950A1 publication Critical patent/WO2022047950A1/zh
Anticipated expiration legal-status Critical
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons

Definitions

  • the present invention relates to the field of display technology, and in particular, to an array substrate, a preparation method thereof, and a display panel.
  • TFT Thin Film Transistor
  • LCD liquid crystal display
  • OLED Organic Light-Emitting Diode
  • LTPS low temperature polysilicon
  • ITZO indium gallium zinc oxide
  • the array substrate, its preparation method, and the display panel provided by the present invention solve the problem in the prior art that free electrons are generated due to the excitation of IGZO by external high-energy photons to generate electron-hole pairs or oxygen vacancies, resulting in "negative drift" of the threshold voltage. This leads to technical problems such as poor light stability of IGZO.
  • An embodiment of the present invention provides an array substrate, including:
  • the thin film transistor array layer disposed on the base substrate, the thin film transistor array layer comprising an oxide semiconductor layer;
  • At least one anti-radiation layer including a light incident side and a light emitting side arranged oppositely, the light emitting side is arranged close to the oxide semiconductor layer, and the light incident side is configured to allow high-energy light waves to enter through the light incident side
  • the anti-radiation layer, the anti-radiation layer is configured to convert the high-energy light waves into visible light
  • the light exit side is configured to allow the visible light to enter the oxide semiconductor layer through the light exit side.
  • the anti-radiation layer is disposed on a side of the base substrate away from the thin film transistor array layer, and the light incident side is that the anti-radiation layer is away from the base substrate
  • the light-emitting side is the side of the anti-radiation layer close to the base substrate.
  • the thin film transistor array layer further includes:
  • a light-shielding layer disposed on the base substrate
  • a buffer layer covering the base substrate and the light shielding layer, and the oxide semiconductor layer is disposed on the buffer layer;
  • a gate insulating layer disposed on the oxide semiconductor layer
  • a gate layer disposed on the gate insulating layer
  • an interlayer dielectric layer covering the buffer layer, the oxide semiconductor layer, the gate insulating layer and the gate layer, the interlayer dielectric layer comprising a first through hole, a second through hole and a third through hole through hole;
  • a source electrode and a drain electrode are arranged on the interlayer dielectric layer, the source electrode is connected to the light shielding layer through the second through hole, and the source electrode is connected to the oxide layer through the third through hole connected to the oxide semiconductor layer, the drain is connected to the oxide semiconductor layer through the first through hole;
  • a passivation layer covering the interlayer dielectric layer, the source electrode and the drain electrode.
  • the anti-radiation layer is disposed on the side of the passivation layer away from the base substrate, and the light incident side is the side of the anti-radiation layer away from the base substrate. On one side, the light-emitting side is the side of the anti-radiation layer close to the base substrate.
  • the anti-radiation layer is disposed on the side of the base substrate close to the thin film transistor array layer, and the light shielding layer is disposed on the side of the anti-radiation layer away from the base substrate .
  • the high-energy light wave includes ultraviolet light.
  • the anti-radiation layer includes a anti-radiation resin
  • the anti-radiation resin includes a down conversion material, a resin, a fluorine-containing monomer or a fluorine-containing polymer, an ultraviolet photoinitiator, and a solvent
  • the mass percentages of the down-conversion material, the resin, the fluorine-containing monomer or the fluorine-containing polymer, the ultraviolet photoinitiator and the solvent are 0.1% to 5% and 50%, respectively. ⁇ 90%, 1% ⁇ 20%, 1% ⁇ 5% and 20% ⁇ 40%.
  • the material of the oxide semiconductor layer is IGZO.
  • the thickness of the anti-radiation layer is 1 um-10 um.
  • An embodiment of the present invention provides a display panel including an array substrate, and the display panel is a liquid crystal display panel or an organic light emitting diode display panel;
  • the array substrate includes:
  • the thin film transistor array layer disposed on the base substrate, the thin film transistor array layer comprising an oxide semiconductor layer;
  • At least one anti-radiation layer including a light incident side and a light emitting side arranged oppositely, the light emitting side is arranged close to the oxide semiconductor layer, and the light incident side is configured to allow high-energy light waves to enter through the light incident side
  • the anti-radiation layer, the anti-radiation layer is configured to convert the high-energy light waves into visible light
  • the light exit side is configured to allow the visible light to enter the oxide semiconductor layer through the light exit side.
  • the anti-radiation layer is disposed on a side of the base substrate away from the thin film transistor array layer, and the light incident side is that the anti-radiation layer is away from the base substrate
  • the light-emitting side is the side of the anti-radiation layer close to the base substrate.
  • the thin film transistor array layer further includes:
  • a light-shielding layer disposed on the base substrate
  • a buffer layer covering the base substrate and the light shielding layer, and the oxide semiconductor layer is disposed on the buffer layer;
  • a gate insulating layer disposed on the oxide semiconductor layer
  • a gate layer disposed on the gate insulating layer
  • an interlayer dielectric layer covering the buffer layer, the oxide semiconductor layer, the gate insulating layer and the gate layer, the interlayer dielectric layer comprising a first through hole, a second through hole and a third through hole through hole;
  • a source electrode and a drain electrode are arranged on the interlayer dielectric layer, the source electrode is connected to the light shielding layer through the second through hole, and the source electrode is connected to the oxide layer through the third through hole connected to the oxide semiconductor layer, the drain is connected to the oxide semiconductor layer through the first through hole;
  • a passivation layer covering the interlayer dielectric layer, the source electrode and the drain electrode.
  • the anti-radiation layer is disposed on a side of the passivation layer away from the base substrate, and the light incident side is a side of the anti-radiation layer away from the base substrate. On one side, the light-emitting side is the side of the anti-radiation layer close to the base substrate.
  • the anti-radiation layer is disposed on the side of the base substrate close to the thin film transistor array layer, and the light shielding layer is located on the side of the anti-radiation layer away from the base substrate .
  • the high-energy light wave includes ultraviolet light.
  • the anti-radiation layer includes a anti-radiation resin
  • the anti-radiation resin includes a down conversion material, a resin, a fluorine-containing monomer or a fluorine-containing polymer, an ultraviolet photoinitiator and a solvent
  • the mass percentages of the down-conversion material, the resin, the fluorine-containing monomer or the fluorine-containing polymer, the ultraviolet photoinitiator and the solvent are 0.1% to 5% and 50%, respectively. ⁇ 90%, 1% ⁇ 20%, 1% ⁇ 5% and 20% ⁇ 40%.
  • the material of the oxide semiconductor layer is IGZO.
  • the thickness of the anti-radiation layer is 1 um-10 um.
  • the array substrate includes two or more layers of the anti-radiation layer.
  • An embodiment of the present invention provides a method for preparing an array substrate, including the following steps:
  • S20 Prepare a radiation-resistant resin, coat the radiation-resistant resin on the base substrate or the thin film transistor array layer, and place it under an ultraviolet lamp for curing to form an array substrate with a radiation-resistant layer.
  • the beneficial effects of the present invention are as follows: in the array substrate, the preparation method thereof, and the display panel provided by the present invention, by arranging at least one anti-radiation layer with a down-conversion function on the array substrate, the anti-radiation layer can absorb high-energy rays in external light. , and convert it into low-energy visible light, so that it cannot reach the energy required to excite the oxide semiconductor layer to generate electron-hole pairs or oxygen holes, so as to avoid damage to oxide semiconductors (such as IGZO), which can improve oxidation The light stability of the material semiconductor layer.
  • FIG. 1 is a schematic cross-sectional structure diagram of a first array substrate according to an embodiment of the present invention
  • FIG. 2 is a schematic cross-sectional structure diagram of a second array substrate according to an embodiment of the present invention.
  • FIG. 3 is a schematic cross-sectional structure diagram of a third array substrate according to an embodiment of the present invention.
  • FIG. 4 is a schematic cross-sectional structure diagram of a fourth array substrate according to an embodiment of the present invention.
  • FIG. 5 is a schematic cross-sectional structure diagram of a display panel according to an embodiment of the present invention.
  • FIG. 6 is a schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention.
  • FIG. 7 is a flowchart of a method for fabricating an array substrate according to an embodiment of the present invention.
  • the present invention is aimed at the array substrate, preparation method and display panel of the prior art. Due to the excitation of IGZO by external high-energy photons to generate electron-hole pairs or oxygen vacancies, free electrons are generated, and the threshold voltage is "negatively drifted", thereby causing the IGZO to have a negative drift. The illumination stability is poor, and this embodiment can solve this defect.
  • an embodiment of the present invention provides an array substrate 1 , which includes a base substrate 10 , a thin film transistor array layer 20 and at least one anti-radiation layer 30 .
  • the base substrate 10 may be one of a glass substrate, a quartz substrate and a resin substrate.
  • the thin film transistor array layer 20 is disposed on the base substrate 10, the thin film transistor array layer 20 includes an oxide semiconductor layer 203, and the material of the oxide semiconductor layer 203 can be IGZO.
  • the anti-radiation layer 30 includes a light incident side 301 and a light exit side 302 disposed opposite to each other, the light exit side 302 is disposed close to the oxide semiconductor layer 203, and the light incident side 301 is configured to allow high-energy light waves to pass through the light source.
  • the light incident side 301 enters the anti-radiation layer 30, the anti-radiation layer 30 is configured to convert the high-energy light waves into visible light, and the light exit side 302 is configured to allow the visible light to pass through the light exit
  • the side 302 enters the oxide semiconductor layer 203 .
  • the external light when external light irradiates the array substrate 1 , the external light enters the anti-radiation layer 30 from the light incident side 301 and exits the anti-radiation layer 30 from the light exit side 302 .
  • the external light includes high-energy light waves. Since the anti-radiation layer 30 provided in the embodiment of the present invention has a down-conversion function, that is, the high-energy light waves entering the anti-radiation layer 30 through the light incident side 301 can be converted into visible light, Visible light enters the oxide semiconductor layer 203 through the light exit side 302 .
  • the layer 203 has a negative effect, thereby improving the light stability of the oxide semiconductor layer 203, thereby prolonging the life of the array substrate 1 to which the array substrate 1 is applied.
  • the high-energy light waves that affect the stability of the oxide semiconductor layer 203 include ultraviolet light.
  • light waves with higher energy than the ultraviolet light will cause the oxide semiconductor layer 203 to become unstable, such as X-rays. Wait.
  • the high-energy light wave is ultraviolet light as an example for illustration, but it does not mean that the anti-radiation layer 30 provided in the embodiment of the present invention cannot resist the radiation of high-energy rays other than ultraviolet light .
  • the thin film transistor array layer 20 further includes a light shielding layer 201 , a buffer layer 202 , a gate insulating layer 204 , a gate layer 205 , an interlayer dielectric layer 206 , a source electrode 207 , a drain electrode 208 and a passivation layer 209 .
  • the light shielding layer 201 is disposed on the base substrate 10 to reduce light leakage and achieve light shielding.
  • the buffer layer 202 covers the base substrate 10 and the light shielding layer 201 and plays a role of buffering and protection.
  • the oxide semiconductor layer 203 is disposed on the buffer layer 202 .
  • the gate insulating layer 204 is disposed on the oxide semiconductor layer 203 , and the gate layer 205 is disposed on the gate insulating layer 204 .
  • the interlayer dielectric layer 206 covers the buffer layer 202, the oxide semiconductor layer 203, the gate insulating layer 204 and the gate layer 205, and is used for insulating and protecting the gate layer 205,
  • the interlayer dielectric layer 206 includes a first through hole 2061 , a second through hole 2062 and a third through hole 2063 .
  • the source electrode 207 and the drain electrode 208 are disposed on the interlayer dielectric layer 206, the source electrode 207 is connected to the light shielding layer 201 through the second through hole 2062, and the source electrode 207 passes through the second through hole 2062.
  • the third through hole 2063 is connected to the oxide semiconductor layer 203 , and the drain electrode 208 is connected to the oxide semiconductor layer 203 through the first through hole 2061 .
  • the passivation layer 209 covers the interlayer dielectric layer 206 , the source electrode 207 and the drain electrode 208 for protecting the source electrode 207 and the drain electrode 208 .
  • the specific arrangement position of the anti-radiation layer 30 can be designed according to the irradiation direction of the external light. For example, when the external light is irradiated from bottom to top, the anti-radiation layer 30 can be disposed on the oxide semiconductor layer 203 in the underlying membrane structure. When external light is irradiated from top to bottom, the anti-radiation layer 30 may be disposed in the film layer structure above the oxide semiconductor layer 203 .
  • the anti-radiation layer 30 is disposed on the side of the base substrate 10 away from the thin film transistor array layer 20 , the The light incident side 301 is the side of the anti-radiation layer 30 away from the base substrate 10 , and the light exit side 302 is the side of the anti-radiation layer 30 close to the base substrate 10 .
  • the ultraviolet light in the external light passes through the anti-radiation layer 30 , the base substrate 10 , and the oxide semiconductor layer 203 in sequence.
  • the difference between FIG. 2 and FIG. 1 is that the anti-radiation layer 30 is disposed on the side of the base substrate 10 close to the thin film transistor array layer 20,
  • the light-shielding layer 201 is disposed on the anti-radiation layer 30
  • the light-incident side 301 is the side of the anti-radiation layer 30 close to the base substrate 10
  • the light-emitting side 302 is the anti-radiation layer 30 is away from the side of the base substrate 10 .
  • the ultraviolet light in the external light passes through the base substrate 10 , the anti-radiation layer 30 and the oxide semiconductor layer 203 in sequence.
  • the anti-radiation layer 30 is disposed on the passivation layer 209 away from the One side of the base substrate 10, the light incident side 301 is the side of the anti-radiation layer 30 away from the base substrate 10, and the light exit side 302 is the side of the anti-radiation layer 30 close to the base substrate 10 side.
  • the ultraviolet light in the external light passes through the anti-radiation layer 30 , the oxide semiconductor layer 203 and the base substrate 10 in sequence.
  • the anti-radiation layer 30 can be used as a flat layer of the thin film transistor array layer 20 , which is beneficial to reduce the overall thickness of the array substrate 1 .
  • the array substrate 1 includes a single layer of the anti-radiation layer 30 . Further, the array substrate 1 may further include two or more layers of the anti-radiation layer 30. For example, please refer to FIG. 4. The difference between FIG. 4 and FIG. 1 is that the array substrate 1 includes two layers of The anti-radiation layer 30, wherein one layer of the anti-radiation layer 30 is disposed on the side of the base substrate 10 away from the thin film transistor array layer 20, and the other layer of the anti-radiation layer 30 is disposed on the passivation The ionization layer 209 is away from the side of the thin film transistor array layer 20 . Using the double layer of the anti-radiation layer 30 can resist ultraviolet light from multiple directions, and has better anti-radiation performance.
  • the thickness of the anti-radiation layer 30 is 1 ⁇ m ⁇ 10 ⁇ m.
  • the anti-radiation layer 30 is formed by curing the anti-radiation resin, and the main components of the anti-radiation resin include down-conversion material, resin, fluorine-containing monomer or fluorine-containing polymer, ultraviolet photoinitiator and solvent.
  • the mass percentages of the down-conversion material, the resin, the fluorine-containing monomer or the fluorine-containing polymer, the ultraviolet photoinitiator and the solvent are respectively 0.1% to 5%, 50% ⁇ 90%, 1% ⁇ 20%, 1% ⁇ 5% and 20% ⁇ 40%.
  • the anti-radiation resin prepared according to the above formula can effectively resist the radiation of ultraviolet light.
  • the down-conversion material is used to convert ultraviolet light into visible light or photons of lower energy, and the down-conversion material can be an organic dye, such as Lumogen F Violet 570, the down-conversion material may also be an inorganic dye containing a metal element.
  • the resin acts as a carrier, and the resin can be an unsaturated polyester or an olefin-based, diene-based resin, such as an acrylic resin and the like.
  • the fluorine-containing monomer or fluorine-containing polymer is a macromolecule containing fluorine element, which plays the role of waterproof and moisture resistance.
  • the ultraviolet photoinitiator is used for crosslinking and curing of unsaturated polymers, or for initiating photopolymerization of monomers or oligomers.
  • the ultraviolet photoinitiator can be Irgacure-1173 and other materials.
  • the solvent plays the role of dissolving the polymer, and the solvent can be an organic solvent such as toluene or chloroform.
  • An embodiment of the present invention further provides a display panel, including the array substrate 1 in the above-mentioned embodiment, and the display panel may be a liquid crystal display panel or an organic light emitting diode display panel.
  • the display panel is a liquid crystal display panel, and the display panel further includes a color filter substrate 11 disposed opposite to the array substrate 1 and disposed between the array substrate 1 and the color filter substrate 11 the liquid crystal layer 12 .
  • FIG. 5 the display panel is a liquid crystal display panel, and the display panel further includes a color filter substrate 11 disposed opposite to the array substrate 1 and disposed between the array substrate 1 and the color filter substrate 11 the liquid crystal layer 12 .
  • the display panel is an organic light emitting diode display panel, and the display panel further includes a light-emitting device layer disposed on the array substrate 1 , and the light-emitting device layer is formed by inkjet printing or evaporation process deposition , the light-emitting device layer includes an anode, a hole injection layer 21, a hole transport layer 22, a light-emitting layer 23, an electron transport layer 24, an electron injection layer 25, etc., which are stacked in sequence, and the light-emitting layer includes a red light-emitting layer, a green light-emitting layer, and a green light-emitting layer. light-emitting layer and blue light-emitting layer.
  • an embodiment of the present invention further provides a method for preparing an array substrate 1 , which includes the following steps:
  • S10 Provide a base substrate 10 on which a thin film transistor array layer 20 is formed.
  • forming the thin film transistor array layer 20 on the base substrate 10 includes depositing and patterning a light shielding layer 201 on the base substrate 10, and forming the light shielding layer 201 on the base substrate 10 and the light shielding layer 201 is deposited to form a buffer layer 202, an oxide semiconductor layer 203 is deposited and patterned on the buffer layer 202, a gate insulating layer 204 is deposited on the oxide semiconductor layer 203, and a gate insulating layer is formed on the gate insulating layer 204 is deposited and patterned to form a gate layer 205, and an interlayer dielectric layer 206 is deposited on the buffer layer 202, the oxide semiconductor layer 203, the gate insulating layer 204 and the gate layer 205, And the first through hole 2061, the second through hole 2062 and the third through hole 2063 are formed by etching on the interlayer dielectric layer 206, and the source electrode 207 and the drain electrode are formed by depositing and patterning on the interlayer dielectric layer 206 electrode 208, the source
  • S20 preparing a radiation-resistant resin, coating the radiation-resistant resin on the base substrate 10 or the thin film transistor array layer 20 and placing it under an ultraviolet lamp for curing to form an array substrate with a radiation-resistant layer 30 1.
  • the anti-radiation resin is prepared according to a certain formula, and the formula includes components such as down-conversion material, resin, fluorine-containing monomer or fluorine-containing polymer, ultraviolet photoinitiator and solvent.
  • the mass percentages of the down-conversion material, the resin, the fluorine-containing monomer or the fluorine-containing polymer, the ultraviolet photoinitiator and the solvent are 0.1% to 5% and 50%, respectively. ⁇ 90%, 1% ⁇ 20%, 1% ⁇ 5% and 20% ⁇ 40%.
  • the anti-radiation layer 30 formed by curing can effectively absorb and resist ultraviolet light from external light.
  • the anti-radiation resin can be applied to the side of the base substrate 10 away from the thin film transistor array layer by a process such as slit coating, or the anti-radiation resin can be applied to the base substrate 10 is close to the side of the thin film transistor array layer 20 , or, the anti-radiation resin is applied to the side of the passivation layer 209 away from the base substrate 10 .
  • the subsequent process also includes the preparation of the color filter substrate, liquid crystal coating, box formation, module and Partial paste and other processes.
  • the subsequent process includes forming a light-emitting device layer on the prepared array substrate 1, and the light-emitting device layer can be deposited by inkjet printing or evaporation process .
  • the beneficial effects are as follows: in the array substrate, the preparation method thereof, and the display panel provided by the present invention, by arranging at least one anti-radiation layer with a down-conversion function on the array substrate, the anti-radiation layer can absorb the high-energy rays in the external light and transmit It is converted into low-energy visible light, so that it cannot reach the energy required to excite the oxide semiconductor layer to generate electron-hole pairs or oxygen holes, so as to avoid damage to the oxide semiconductor (such as IGZO), which can improve the oxide semiconductor layer. light stability.

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Abstract

一种阵列基板（1）及其制备方法、显示面板，阵列基板（1）包括至少一抗辐射层（30），抗辐射层（30）包括入光侧（301）和出光侧（302），出光侧（302）靠近氧化物半导体层（203）设置，入光侧（301）用于使高能量光波经由入光侧（301）进入抗辐射层（30），抗辐射层（30）用于将高能量光波转换为可见光，出光侧（302）用于使可见光经由出光侧（302）进入氧化物半导体层（203），提高氧化物半导体的光照稳定性。

Description

阵列基板及其制备方法、显示面板 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及其制备方法、显示面板。
 背景技术
薄膜晶体管（Thin Film Transistor，TFT）技术是平板显示器的核心技术之一，无论是液晶显示装置（Liquid Crystal Display，LCD），还是有机发光半导体显示装置（Organic Light-Emitting Diode，OLED），均需要TFT背板来进行驱动。由于非晶硅（α-Si）材料的迁移率较低，难以满足未来大尺寸高分辨的显示需求。虽然低温多晶硅（Low Temperature Poly-silicon，LTPS）材料的迁移率相对较高，但其具有成本高、均匀性差以及大面积化较为困难的缺陷。因此，以铟镓锌氧化物(indium gallium zinc oxide，IGZO)为代表的具有高迁移率的金属氧化物应用于TFT背板上，具有非常重要的意义。
然而，由于外界光线中的高能量光子（如：紫外光）会激发IGZO产生电子空穴对或氧空位，产生自由电子，引起阈值电压“负飘”，从而导致IGZO的光照稳定性较差。
综上所述，需要提供一种新的阵列基板及其制备方法、显示面板，来解决上述技术问题。
 技术问题
本发明提供的阵列基板及其制备方法、显示面板，以解决现有技术中由于外界高能量光子激发IGZO产生电子空穴对或氧空位，而产生自由电子，引起阈值电压“负飘”，从而导致IGZO的光照稳定性较差等技术问题。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明实施例提供一种阵列基板，包括：
衬底基板；
薄膜晶体管阵列层，设置于所述衬底基板上，所述薄膜晶体管阵列层包括氧化物半导体层；以及
至少一抗辐射层，包括相对设置的入光侧和出光侧，所述出光侧靠近所述氧化物半导体层设置，所述入光侧配置成用于使高能量光波经由所述入光侧进入所述抗辐射层，所述抗辐射层配置成用于将所述高能量光波转换为可见光，所述出光侧配置成用于使所述可见光经由所述出光侧进入所述氧化物半导体层。
根据本发明实施例提供的阵列基板，所述抗辐射层设置于所述衬底基板远离所述薄膜晶体管阵列层的一侧，所述入光侧为所述抗辐射层远离所述衬底基板的一侧，所述出光侧为所述抗辐射层靠近所述衬底基板的一侧。
根据本发明实施例提供的阵列基板，所述薄膜晶体管阵列层还包括：
遮光层，设置于所述衬底基板上；
缓冲层，覆盖所述衬底基板和所述遮光层，所述氧化物半导体层设置于所述缓冲层上；
栅极绝缘层，设置于所述氧化物半导体层上；
栅极层，设置于所述栅极绝缘层上；
层间介质层，覆盖所述缓冲层、所述氧化物半导体层、所述栅极绝缘层以及所述栅极层，所述层间介质层包括第一通孔、第二通孔以及第三通孔；
源极和漏极，设置于所述层间介质层上，所述源极通过所述第二通孔与所述遮光层相连接，所述源极通过所述第三通孔与所述氧化物半导体层相连接，所述漏极通过所述第一通孔与所述氧化物半导体层相连接；以及
钝化层，覆盖所述层间介质层、所述源极以及所述漏极。
根据本发明实施例提供的阵列基板，所述抗辐射层设置于所述钝化层远离所述衬底基板的一侧，所述入光侧为所述抗辐射层远离所述衬底基板的一侧，所述出光侧为所述抗辐射层靠近所述衬底基板的一侧。
根据本发明实施例提供的阵列基板，所述抗辐射层设置于所述衬底基板靠近薄膜晶体管阵列层的一侧，所述遮光层位于所述抗辐射层远离所述衬底基板的一侧。
根据本发明实施例提供的阵列基板，所述高能量光波包括紫外光。
根据本发明实施例提供的阵列基板，所述抗辐射层包括抗辐射树脂，所述抗辐射树脂包括下转换材料、树脂、含氟单体或含氟聚合物、紫外光引发剂以及溶剂；
其中，所述下转换材料、所述树脂、所述含氟单体或所述含氟聚合物、所述紫外光引发剂以及所述溶剂所占质量百分数分别为0.1%~5%、50%~90%、1%~20%、1%~5%以及20%~40%。
根据本发明实施例提供的阵列基板，所述氧化物半导体层的材料为IGZO。
根据本发明实施例提供的阵列基板，所述抗辐射层的厚度为1um~10um。
本发明实施例提供一种显示面板，包括阵列基板，所述显示面板为液晶显示面板或有机发光二极管显示面板；
所述阵列基板包括：
衬底基板；
薄膜晶体管阵列层，设置于所述衬底基板上，所述薄膜晶体管阵列层包括氧化物半导体层；以及
至少一抗辐射层，包括相对设置的入光侧和出光侧，所述出光侧靠近所述氧化物半导体层设置，所述入光侧配置成用于使高能量光波经由所述入光侧进入所述抗辐射层，所述抗辐射层配置成用于将所述高能量光波转换为可见光，所述出光侧配置成用于使所述可见光经由所述出光侧进入所述氧化物半导体层。
根据本发明实施例提供的显示面板，所述抗辐射层设置于所述衬底基板远离所述薄膜晶体管阵列层的一侧，所述入光侧为所述抗辐射层远离所述衬底基板的一侧，所述出光侧为所述抗辐射层靠近所述衬底基板的一侧。
根据本发明实施例提供的显示面板，所述薄膜晶体管阵列层还包括：
遮光层，设置于所述衬底基板上；
缓冲层，覆盖所述衬底基板和所述遮光层，所述氧化物半导体层设置于所述缓冲层上；
栅极绝缘层，设置于所述氧化物半导体层上；
栅极层，设置于所述栅极绝缘层上；
层间介质层，覆盖所述缓冲层、所述氧化物半导体层、所述栅极绝缘层以及所述栅极层，所述层间介质层包括第一通孔、第二通孔以及第三通孔；
源极和漏极，设置于所述层间介质层上，所述源极通过所述第二通孔与所述遮光层相连接，所述源极通过所述第三通孔与所述氧化物半导体层相连接，所述漏极通过所述第一通孔与所述氧化物半导体层相连接；以及
钝化层，覆盖所述层间介质层、所述源极以及所述漏极。
根据本发明实施例提供的显示面板，所述抗辐射层设置于所述钝化层远离所述衬底基板的一侧，所述入光侧为所述抗辐射层远离所述衬底基板的一侧，所述出光侧为所述抗辐射层靠近所述衬底基板的一侧。
根据本发明实施例提供的显示面板，所述抗辐射层设置于所述衬底基板靠近薄膜晶体管阵列层的一侧，所述遮光层位于所述抗辐射层远离所述衬底基板的一侧。
根据本发明实施例提供的显示面板，所述高能量光波包括紫外光。
根据本发明实施例提供的显示面板，所述抗辐射层包括抗辐射树脂，所述抗辐射树脂包括下转换材料、树脂、含氟单体或含氟聚合物、紫外光引发剂以及溶剂；
其中，所述下转换材料、所述树脂、所述含氟单体或所述含氟聚合物、所述紫外光引发剂以及所述溶剂所占质量百分数分别为0.1%~5%、50%~90%、1%~20%、1%~5%以及20%~40%。
根据本发明实施例提供的显示面板，所述氧化物半导体层的材料为IGZO。
根据本发明实施例提供的显示面板，所述抗辐射层的厚度为1um~10um。
根据本发明实施例提供的显示面板，所述阵列基板包括双层或多层所述抗辐射层。
本发明实施例提供一种阵列基板的制备方法，包括以下步骤：
S10：提供衬底基板，在所述衬底基板上形成薄膜晶体管阵列层；以及
S20：制备抗辐射树脂，在所述衬底基板或所述薄膜晶体管阵列层上涂布所述抗辐射树脂并置于紫外灯下进行固化处理，以形成具有抗辐射层的阵列基板。
 有益效果
本发明的有益效果为：本发明提供的阵列基板及其制备方法、显示面板，通过在阵列基板上设置至少一具有下转换功能的抗辐射层，抗辐射层能够吸收外界光线中的高能量射线，并将其转换为低能量的可见光，使其达不到激发氧化物半导体层产生电子空穴对或氧空穴所需能量，从而避免对氧化物半导体（例如IGZO）产生破坏，能够提高氧化物半导体层的光照稳定性。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的第一种阵列基板的截面结构示意图；
图2为本发明实施例提供的第二种阵列基板的截面结构示意图；
图3为本发明实施例提供的第三种阵列基板的截面结构示意图；
图4为本发明实施例提供的第四种阵列基板的截面结构示意图；
图5为本发明实施例提供的一种显示面板的截面结构示意图；
图6为本发明实施例提供的另一种显示面板的截面结构示意图；
图7为本发明实施例提供的一种阵列基板的制作方法的流程图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
本发明针对现有技术的阵列基板及其制备方法、显示面板，由于外界高能量光子激发IGZO产生电子空穴对或氧空位，而产生自由电子，引起阈值电压“负飘”，从而导致IGZO的光照稳定性较差，本实施例能够解决该缺陷。
请参阅图1，本发明实施例提供一种阵列基板1，包括衬底基板10、薄膜晶体管阵列层20以及至少一抗辐射层30。
所述衬底基板10可以为玻璃基板、石英基板以及树脂基板中的一种。所述薄膜晶体管阵列层20设置于所述衬底基板10上，所述薄膜晶体管阵列层20包括氧化物半导体层203，所述氧化物半导体层203的材料可以为IGZO。
所述抗辐射层30包括相对设置的入光侧301和出光侧302，所述出光侧302靠近所述氧化物半导体层203设置，所述入光侧301配置成用于使高能量光波经由所述入光侧301进入所述抗辐射层30，所述抗辐射层30配置成用于将所述高能量光波转换为可见光，所述出光侧302配置成用于使所述可见光经由所述出光侧302进入所述氧化物半导体层203。也就是说，外界光线照射至所述阵列基板1上时，外界光线从所述入光侧301进入所述抗辐射层30内部，并从所述出光侧302射出所述抗辐射层30。外界光线包括高能量光波，由于本发明实施例提供的所述抗辐射层30具有下转换功能，即能够将经由所述入光侧301进入所述抗辐射层30的高能量光波转换为可见光，可见光经由所述出光侧302进入所述氧化物半导体层203。由于可见光的能量较低，其达不到激发所述氧化物半导体层203产生电子空穴对或氧空穴所需能量，而无法产生自由电子，故能够避免高能量光波对所述氧化物半导体层203产生负面影响，从而提高了所述氧化物半导体层203的光照稳定性，进而延长了应用该阵列基板1的寿命。
需要说明的是，影响所述氧化物半导体层203稳定性的高能量光波包括紫外光，实际上，比紫外光能量更大的光波都会造成所述氧化物半导体层203不稳定，比如：X射线等。一般来说，由于所述阵列基板1在常规应用环境中很少会接触到高能射线，而主要是太阳光中的紫外光组分容易对其造成影响。因此，本发明实施例中，以高能量光波为紫外光为例进行阐述说明，但并不意味着，本发明实施例提供的所述抗辐射层30无法抵御除紫外光以外的高能射线的辐射。
具体地，所述薄膜晶体管阵列层20还包括遮光层201、缓冲层202、栅极绝缘层204、栅极层205、层间介质层206、源极207、漏极208以及钝化层209。
所述遮光层201设置于所述衬底基板10上，用于减少漏光，实现光屏蔽。所述缓冲层202覆盖所述衬底基板10和所述遮光层201，起到缓冲和保护的作用，所述氧化物半导体层203设置于所述缓冲层202上。所述栅极绝缘层204设置于所述氧化物半导体层203上，所述栅极层205设置于所述栅极绝缘层204上。所述层间介质层206覆盖所述缓冲层202、所述氧化物半导体层203、所述栅极绝缘层204以及所述栅极层205，其用于绝缘并保护所述栅极层205，所述层间介质层206包括第一通孔2061、第二通孔2062以及第三通孔2063。所述源极207和所述漏极208设置于所述层间介质层206上，所述源极207通过所述第二通孔2062与所述遮光层201连接，所述源极207通过所述第三通孔2063与所述氧化物半导体层203相连接，所述漏极208通过所述第一通孔2061与所述氧化物半导体层203相连接。所述钝化层209覆盖所述层间介质层206、所述源极207以及所述漏极208，用于保护所述源极207和所述漏极208。
关于所述抗辐射层30的具体设置位置，可以根据外界光线的照射方向设计，例如，当外界光线从下往上照射时，所述抗辐射层30可以设置于位于所述氧化物半导体层203下方的膜层结构中。当外界光线从上往下照射时，所述抗辐射层30可以设置于位于所述氧化物半导体层203上方的膜层结构中。
当外界光线从下往上照射时，在一种实施方式中，请参阅图1，所述抗辐射层30设置于所述衬底基板10远离所述薄膜晶体管阵列层20的一侧，所述入光侧301为所述抗辐射层30远离所述衬底基板10的一侧，所述出光侧302为所述抗辐射层30靠近所述衬底基板10的一侧。外界光线中的紫外光依次经过所述抗辐射层30、所述衬底基板10、以及所述氧化物半导体层203。
在另一种实施方式中，请参阅图2，图2与图1的不同之处在于，所述抗辐射层30设置于所述衬底基板10靠近所述薄膜晶体管阵列层20的一侧，所述遮光层201设置于所述抗辐射层30上，所述入光侧301为所述抗辐射层30靠近所述衬底基板10的一侧，所述出光侧302为所述抗辐射层30远离所述衬底基板10的一侧。外界光线中的紫外光依次经过所述衬底基板10、所述抗辐射层30以及所述氧化物半导体层203。
当外界光线从上往下照射时，在一种实施方式中，请参阅图3，图3与图1的不同之处在于，所述抗辐射层30设置于所述钝化层209远离所述衬底基板10的一侧，所述入光侧301为所述抗辐射层30远离所述衬底基板10的一侧，所述出光侧302为所述抗辐射层30靠近所述衬底基板10的一侧。外界光线中的紫外光依次经过所述抗辐射层30、所述氧化物半导体层203以及所述衬底基板10。此时，所述抗辐射层30可以作为所述薄膜晶体管阵列层20的平坦层，有利于减小所述阵列基板1的整体厚度。
在上述实施例中，所述阵列基板1包括单层所述抗辐射层30。进一步地，所述阵列基板1还可以包括双层或多层所述抗辐射层30，例如，请参阅图4，图4与图1的不同之处在于，所述阵列基板1包括双层所述抗辐射层30，其中，一层所述抗辐射层30设置于所述衬底基板10远离所述薄膜晶体管阵列层20的一侧，另一层所述抗辐射层30设置于所述钝化层209远离所述薄膜晶体管阵列层20的一侧。采用双层所述抗辐射层30能够抵御来自多个方向的紫外光，抗辐射性能更佳。
需要说明的是，对于所述抗辐射层30的具体设置位置，本发明实施例仅仅列举了几种情况，对于未列举的采用本发明构思的其它情况，也在本发明的保护范围之内。
具体地，所述抗辐射层30的厚度为1um~10um。
具体地，所述抗辐射层30由抗辐射树脂固化而成，所述抗辐射树脂的主要成分包括下转换材料、树脂、含氟单体或含氟聚合物、紫外光引发剂以及溶剂。其中，其中，所述下转换材料、所述树脂、所述含氟单体或所述含氟聚合物、所述紫外光引发剂以及所述溶剂所占质量百分数分别为0.1%~5%、50%~90%、1%~20%、1%~5%以及20%~40%。按照上述配方配制而成的所述抗辐射树脂能够有效抵御紫外光的辐射。
所述下转换材料用于将紫外光转换为可见光或者更低能量的光子，所述下转换材料可以为有机染料，例如Lumogen F Violet 570，所述下转换材料也可以为含有金属元素的无机染料。所述树脂起到载体的作用，所述树脂可以为不饱和聚酯或烯类、双烯类等树脂，例如丙烯酸树脂等。所述含氟单体或含氟聚合物为含氟元素的高分子，起到防水抗湿的作用。所述紫外光引发剂用于不饱和聚合物的交联固化，或引发单体或低聚物的光聚合反应。所述紫外光引发剂可以为Irgacure-1173等材料。所述溶剂起到溶解聚合物的作用，所述溶剂可以为甲苯或氯仿等有机溶剂。
本发明实施例还提供一种显示面板，包括上述实施例中的阵列基板1，所述显示面板可以为液晶显示面板或有机发光二极管显示面板。请参阅图5，所述显示面板为液晶显示面板，所述显示面板还包括与所述阵列基板1相对设置的彩膜基板11以及设置于所述阵列基板1和所述彩膜基板11之间的液晶层12。请参阅图6，所述显示面板为有机发光二极管显示面板，所述显示面板还包括设置于所述阵列基板1上的发光器件层，所述发光器件层通过喷墨打印或蒸镀工艺沉积形成，所述发光器件层包括依次层叠设置的阳极、空穴注入层21、空穴传输层22、发光层23、电子传输层24以及电子注入层25等，所述发光层包括红色发光层、绿色发光层以及蓝色发光层。
请参阅图7，本发明实施例还提供一种阵列基板1的制备方法，包括以下步骤：
S10：提供衬底基板10，在所述衬底基板10上形成薄膜晶体管阵列层20。
具体地，在所述衬底基板10上形成所述薄膜晶体管阵列层20，包括在所述衬底基板10上沉积并图案化形成遮光层201，在所述衬底基板10和所述遮光层201上沉积形成缓冲层202，在所述缓冲层202上沉积并图案化形成氧化物半导体层203，在所述氧化物半导体层203上沉积形成栅极绝缘层204，在所述栅极绝缘层204上沉积并图案化形成栅极层205，在所述缓冲层202、所述氧化物半导体层203、所述栅极绝缘层204以及所述栅极层205上沉积形成层间介质层206，并在所述层间介质层206上刻蚀形成第一通孔2061、第二通孔2062以及第三通孔2063，在所述层间介质层206上沉积并图案化形成源极207和漏极208，所述源极207通过所述第二通孔2062与所述遮光层201相连接，所述源极207通过所述第三通孔2063与所述氧化物半导体层203相连接，所述漏极208通过所述第一通孔2061与所述氧化物半导体层203相连接，以及在所述层间介质层206、所述源极207以及所述漏极208上沉积形成钝化层209。
S20：制备抗辐射树脂，在所述衬底基板10或所述薄膜晶体管阵列层20上涂布所述抗辐射树脂并置于紫外灯下进行固化处理，以形成具有抗辐射层30的阵列基板1。
具体地，按照一定的配方进行制备所述抗辐射树脂，该配方包括下转换材料、树脂、含氟单体或含氟聚合物、紫外光引发剂以及溶剂等组分。其中，所述下转换材料、所述树脂、所述含氟单体或所述含氟聚合物、所述紫外光引发剂以及所述溶剂所占质量百分数分别为0.1%~5%、50%~90%、1%~20%、1%~5%以及20%~40%。经过固化形成的所述抗辐射层30能够有效吸收并抵御来自外界光线中的紫外光。
可以通过狭缝涂布等工艺将所述抗辐射树脂涂布至所述衬底基板10远离所述薄膜晶体管阵列层的一侧，或者，将所述抗辐射树脂涂布至所述衬底基板10靠近所述薄膜晶体管阵列层20的一侧，或者，将所述抗辐射树脂涂布至所述钝化层209远离所述衬底基板10的一侧。
需要说明的是，当所述抗辐射层30制备完成之后，当所述阵列基板1应用至液晶显示面板上时，后续制程还包括彩膜基板的制备、液晶涂布、成盒、模组以及偏贴等制程。当所述阵列基板1应用至有机发光二极管显示面板时，后续制程包括在制备完成的所述阵列基板1上形成发光器件层，所述发光器件层可以通过喷墨打印或蒸镀工艺沉积而成。
有益效果为：本发明提供的阵列基板及其制备方法、显示面板，通过在阵列基板上设置至少一具有下转换功能的抗辐射层，抗辐射层能够吸收外界光线中的高能量射线，并将其转换为低能量的可见光，使其达不到激发氧化物半导体层产生电子空穴对或氧空穴所需能量，从而避免对氧化物半导体（例如IGZO）产生破坏，能够提高氧化物半导体层的光照稳定性。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种阵列基板，包括：
    衬底基板；
    薄膜晶体管阵列层，设置于所述衬底基板上，所述薄膜晶体管阵列层包括氧化物半导体层；以及
    至少一抗辐射层，包括相对设置的入光侧和出光侧，所述出光侧靠近所述氧化物半导体层设置，所述入光侧配置成用于使高能量光波经由所述入光侧进入所述抗辐射层，所述抗辐射层配置成用于将所述高能量光波转换为可见光，所述出光侧配置成用于使所述可见光经由所述出光侧进入所述氧化物半导体层。
  2. 根据权利要求1所述的阵列基板，其中所述抗辐射层设置于所述衬底基板远离所述薄膜晶体管阵列层的一侧，所述入光侧为所述抗辐射层远离所述衬底基板的一侧，所述出光侧为所述抗辐射层靠近所述衬底基板的一侧。
  3. 根据权利要求1所述的阵列基板，其中所述薄膜晶体管阵列层还包括：
    遮光层，设置于所述衬底基板上；
    缓冲层，覆盖所述衬底基板和所述遮光层，所述氧化物半导体层设置于所述缓冲层上；
    栅极绝缘层，设置于所述氧化物半导体层上；
    栅极层，设置于所述栅极绝缘层上；
    层间介质层，覆盖所述缓冲层、所述氧化物半导体层、所述栅极绝缘层以及所述栅极层，所述层间介质层包括第一通孔、第二通孔以及第三通孔；
    源极和漏极，设置于所述层间介质层上，所述源极通过所述第二通孔与所述遮光层相连接，所述源极通过所述第三通孔与所述氧化物半导体层相连接，所述漏极通过所述第一通孔与所述氧化物半导体层相连接；以及
    钝化层，覆盖所述层间介质层、所述源极以及所述漏极。
  4. 根据权利要求3所述的阵列基板，其中所述抗辐射层设置于所述钝化层远离所述衬底基板的一侧，所述入光侧为所述抗辐射层远离所述衬底基板的一侧，所述出光侧为所述抗辐射层靠近所述衬底基板的一侧。
  5. 根据权利要求3所述的阵列基板，其中所述抗辐射层设置于所述衬底基板靠近薄膜晶体管阵列层的一侧，所述遮光层位于所述抗辐射层远离所述衬底基板的一侧。
  6. 根据权利要求1所述的阵列基板，其中所述高能量光波包括紫外光。
  7. 根据权利要求6所述的阵列基板，其中所述抗辐射层包括抗辐射树脂，所述抗辐射树脂包括下转换材料、树脂、含氟单体或含氟聚合物、紫外光引发剂以及溶剂；
    其中，所述下转换材料、所述树脂、所述含氟单体或所述含氟聚合物、所述紫外光引发剂以及所述溶剂所占质量百分数分别为0.1%~5%、50%~90%、1%~20%、1%~5%以及20%~40%。
  8. 根据权利要求1所述的阵列基板，其中所述氧化物半导体层的材料为IGZO。
  9. 根据权利要求1所述的阵列基板，其中所述抗辐射层的厚度为1um~10um。
  10. 一种显示面板，包括阵列基板，所述显示面板为液晶显示面板或有机发光二极管显示面板；
    所述阵列基板包括：
    衬底基板；
    薄膜晶体管阵列层，设置于所述衬底基板上，所述薄膜晶体管阵列层包括氧化物半导体层；以及
    至少一抗辐射层，包括相对设置的入光侧和出光侧，所述出光侧靠近所述氧化物半导体层设置，所述入光侧配置成用于使高能量光波经由所述入光侧进入所述抗辐射层，所述抗辐射层配置成用于将所述高能量光波转换为可见光，所述出光侧配置成用于使所述可见光经由所述出光侧进入所述氧化物半导体层。
  11. 根据权利要求10所述的显示面板，其中所述抗辐射层设置于所述衬底基板远离所述薄膜晶体管阵列层的一侧，所述入光侧为所述抗辐射层远离所述衬底基板的一侧，所述出光侧为所述抗辐射层靠近所述衬底基板的一侧。
  12. 根据权利要求10所述的显示面板，其中所述薄膜晶体管阵列层还包括：
    遮光层，设置于所述衬底基板上；
    缓冲层，覆盖所述衬底基板和所述遮光层，所述氧化物半导体层设置于所述缓冲层上；
    栅极绝缘层，设置于所述氧化物半导体层上；
    栅极层，设置于所述栅极绝缘层上；
    层间介质层，覆盖所述缓冲层、所述氧化物半导体层、所述栅极绝缘层以及所述栅极层，所述层间介质层包括第一通孔、第二通孔以及第三通孔；
    源极和漏极，设置于所述层间介质层上，所述源极通过所述第二通孔与所述遮光层相连接，所述源极通过所述第三通孔与所述氧化物半导体层相连接，所述漏极通过所述第一通孔与所述氧化物半导体层相连接；以及
    钝化层，覆盖所述层间介质层、所述源极以及所述漏极。
  13. 根据权利要求12所述的显示面板，其中所述抗辐射层设置于所述钝化层远离所述衬底基板的一侧，所述入光侧为所述抗辐射层远离所述衬底基板的一侧，所述出光侧为所述抗辐射层靠近所述衬底基板的一侧。
  14. 根据权利要求12所述的显示面板，其中所述抗辐射层设置于所述衬底基板靠近薄膜晶体管阵列层的一侧，所述遮光层位于所述抗辐射层远离所述衬底基板的一侧。
  15. 根据权利要求10所述的显示面板，其中所述高能量光波包括紫外光。
  16. 根据权利要求15所述的显示面板，其中所述抗辐射层包括抗辐射树脂，所述抗辐射树脂包括下转换材料、树脂、含氟单体或含氟聚合物、紫外光引发剂以及溶剂；
    其中，所述下转换材料、所述树脂、所述含氟单体或所述含氟聚合物、所述紫外光引发剂以及所述溶剂所占质量百分数分别为0.1%~5%、50%~90%、1%~20%、1%~5%以及20%~40%。
  17. 根据权利要求10所述的显示面板，其中所述氧化物半导体层的材料为IGZO。
  18. 根据权利要求10所述的显示面板，其中所述抗辐射层的厚度为1um~10um。
  19. 根据权利要求10所述的显示面板，其中所述阵列基板包括双层或多层所述抗辐射层。
  20. 一种阵列基板的制备方法，包括以下步骤：
    S10：提供衬底基板，在所述衬底基板上形成薄膜晶体管阵列层；以及
    S20：制备抗辐射树脂，在所述衬底基板或所述薄膜晶体管阵列层上涂布所述抗辐射树脂并置于紫外灯下进行固化处理，以形成具有抗辐射层的阵列基板。
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