WO2022047932A1 - 栅极驱动电路和显示面板 - Google Patents

栅极驱动电路和显示面板 Download PDF

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Publication number
WO2022047932A1
WO2022047932A1 PCT/CN2020/123294 CN2020123294W WO2022047932A1 WO 2022047932 A1 WO2022047932 A1 WO 2022047932A1 CN 2020123294 W CN2020123294 W CN 2020123294W WO 2022047932 A1 WO2022047932 A1 WO 2022047932A1
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WIPO (PCT)
Prior art keywords
transistor
electrode
point
terminal
pull
Prior art date
Application number
PCT/CN2020/123294
Other languages
English (en)
French (fr)
Inventor
奚苏萍
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US17/055,617 priority Critical patent/US11645967B2/en
Publication of WO2022047932A1 publication Critical patent/WO2022047932A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0876—Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present application relates to the field of display technology, and in particular, to a gate driving circuit and a display panel.
  • GOA Gate Driver
  • On Array, array substrate row drive technology namely gate drive circuit
  • the GOA circuit is provided with a pull-up control circuit, a pull-up circuit, a pull-down circuit, a pull-down holding circuit, a bootstrap capacitor, and a signal transmission circuit, so that the GOA circuit can work normally.
  • the transistors due to the large number of transistors in the GOA circuit, the transistors occupy more Due to the large space, the bezel of the display panel is large, and a narrow bezel cannot be realized.
  • the transistors in the gate driving circuit of the existing display panel occupy a large space, resulting in a technical problem that the frame of the display panel is large.
  • Embodiments of the present application provide a gate driving circuit and a display panel, so as to alleviate the technical problem that transistors in the gate driving circuit of the existing display panel occupy a large space, resulting in a large frame of the display panel.
  • An embodiment of the present application provides a gate drive circuit, the gate drive circuit includes:
  • a pull-up control circuit connected to the first point, for pulling up the potential of the first point during the display period
  • a signal transmission circuit connected to the first point and the pull-up control circuit, for pulling up the potential of the first-stage transmission signal output terminal;
  • a pull-up circuit connected to the first point and the pull-up control circuit, for pulling up the potential of the first signal output terminal
  • a pull-down circuit connected to the first point, for pulling down the potential of the first point during the display period
  • a pull-down maintaining circuit connected to the first point, for maintaining the low potential of the first point
  • the pull-down maintaining circuit includes an inverter and a low-potential voltage terminal
  • the inverter includes a first transistor, a second transistor, and a third transistor
  • the gate of the third transistor is connected to the first point, so
  • the first electrode of the third transistor is connected to the second electrode of the first transistor
  • the first electrode of the third transistor is connected to the second electrode of the second transistor
  • the first electrode of the third transistor is connected is connected to the second signal output terminal
  • the second electrode of the third transistor is connected to the low-potential voltage input terminal.
  • the inverter further includes a high potential voltage terminal, a first low frequency clock signal terminal and a second low frequency clock signal terminal, and the gate of the first transistor is connected to the first low frequency clock signal terminal , the first electrode of the first transistor is connected to the high-potential voltage terminal, the gate of the second transistor is connected to the second low-frequency clock signal terminal, and the first electrode of the second transistor is connected to the The high potential voltage terminal is connected.
  • the pull-down sustaining circuit further includes a fourth transistor, a fifth transistor, a first point and a second signal output terminal, the gate of the fourth transistor is connected to the second signal output terminal, so The first electrode of the fourth transistor is connected to the first point, the second electrode of the fourth transistor is connected to the low-potential voltage input terminal, and the gate of the fifth transistor is connected to the second signal output The first electrode of the fifth transistor is connected to the first signal output end, and the second electrode of the fifth transistor is connected to the low potential input end.
  • the pull-up control circuit includes a sixth transistor, a first staging signal input terminal, and a first signal input terminal, and a gate of the sixth transistor is connected to the first staging signal input terminal , the first electrode of the sixth transistor is connected to the first signal input terminal, and the second electrode of the sixth transistor is connected to the first point.
  • the signal transmission circuit includes a seventh transistor and a first stage transmission signal output terminal, a gate of the seventh transistor is connected to the first point, and a first electrode of the seventh transistor is connected to the first point.
  • the first clock signal input terminal is connected, and the second electrode of the seventh transistor is connected to the first stage transmission signal output terminal.
  • the pull-up circuit includes an eighth transistor, a first clock signal input terminal, and a first signal output terminal, the gate of the eighth transistor is connected to the first point, and the sixth transistor of the eighth transistor is connected to the first point.
  • An electrode is connected to the first clock signal input terminal, and the second electrode of the eighth transistor is connected to the first signal output terminal.
  • the pull-down circuit includes a ninth transistor, a tenth transistor, and a second signal input terminal, the gate of the ninth transistor is connected to the second signal input terminal, and the ninth transistor has a second signal input terminal.
  • An electrode is connected to the low-potential voltage terminal, the second electrode of the ninth transistor is connected to the first signal output terminal, the gate of the tenth transistor is connected to the second signal input terminal, and the The first electrode of the tenth transistor is connected to the low potential voltage terminal, and the second electrode of the tenth transistor is connected to the first point.
  • the gate driving circuit further includes a bootstrap capacitor, a first plate of the bootstrap capacitor is connected to the first point, and a second plate of the bootstrap capacitor is connected to the first point.
  • a signal output terminal is connected.
  • the gate driving circuit further includes a reset circuit
  • the reset circuit further includes a reset signal terminal and a reset transistor
  • the gate of the reset transistor is connected to the reset signal terminal
  • the reset transistor has a gate connected to the reset signal terminal.
  • the first electrode is connected to the first point
  • the second electrode of the reset transistor is connected to the low-potential voltage terminal.
  • the third transistor is one of an amorphous silicon thin film transistor and an indium gallium zinc oxide thin film transistor.
  • the third transistor is one of an N-type transistor and a P-type transistor.
  • an embodiment of the present application provides a display panel, the display panel includes a gate drive circuit, and the gate drive circuit includes:
  • a pull-up control circuit connected to the first point, for pulling up the potential of the first point during the display period
  • a signal transmission circuit connected to the first point and the pull-up control circuit, for pulling up the potential of the first-stage transmission signal output terminal;
  • a pull-up circuit connected to the first point and the pull-up control circuit, for pulling up the potential of the first signal output terminal
  • a pull-down circuit connected to the first point, for pulling down the potential of the first point during the display period
  • a pull-down maintaining circuit connected to the first point, for maintaining the low potential of the first point
  • the pull-down maintaining circuit includes an inverter and a low-potential voltage terminal
  • the inverter includes a first transistor, a second transistor, and a third transistor
  • the gate of the third transistor is connected to the first point, so
  • the first electrode of the third transistor is connected to the second electrode of the first transistor
  • the first electrode of the third transistor is connected to the second electrode of the second transistor
  • the first electrode of the third transistor is connected is connected to the second signal output terminal
  • the second electrode of the third transistor is connected to the low-potential voltage input terminal.
  • the inverter further includes a high potential voltage terminal, a first low frequency clock signal terminal and a second low frequency clock signal terminal, and the gate of the first transistor is connected to the first low frequency clock signal terminal , the first electrode of the first transistor is connected to the high-potential voltage terminal, the gate of the second transistor is connected to the second low-frequency clock signal terminal, and the first electrode of the second transistor is connected to the The high potential voltage terminal is connected.
  • the pull-down sustaining circuit further includes a fourth transistor, a fifth transistor, a first point and a second signal output terminal, the gate of the fourth transistor is connected to the second signal output terminal, so The first electrode of the fourth transistor is connected to the first point, the second electrode of the fourth transistor is connected to the low-potential voltage input terminal, and the gate of the fifth transistor is connected to the second signal output The first electrode of the fifth transistor is connected to the first signal output end, and the second electrode of the fifth transistor is connected to the low potential input end.
  • the pull-up control circuit includes a sixth transistor, a first staging signal input terminal, and a first signal input terminal, and a gate of the sixth transistor is connected to the first staging signal input terminal , the first electrode of the sixth transistor is connected to the first signal input terminal, and the second electrode of the sixth transistor is connected to the first point.
  • the signal transmission circuit includes a seventh transistor and a first stage transmission signal output terminal, a gate of the seventh transistor is connected to the first point, and a first electrode of the seventh transistor is connected to the first point.
  • the first clock signal input terminal is connected, and the second electrode of the seventh transistor is connected to the first stage transmission signal output terminal.
  • the pull-up circuit includes an eighth transistor, a first clock signal input terminal, and a first signal output terminal, the gate of the eighth transistor is connected to the first point, and the sixth transistor of the eighth transistor is connected to the first point.
  • An electrode is connected to the first clock signal input terminal, and the second electrode of the eighth transistor is connected to the first signal output terminal.
  • the pull-down circuit includes a ninth transistor, a tenth transistor, and a second signal input terminal, the gate of the ninth transistor is connected to the second signal input terminal, and the ninth transistor has a second signal input terminal.
  • An electrode is connected to the low-potential voltage terminal, the second electrode of the ninth transistor is connected to the first signal output terminal, the gate of the tenth transistor is connected to the second signal input terminal, and the The first electrode of the tenth transistor is connected to the low potential voltage terminal, and the second electrode of the tenth transistor is connected to the first point.
  • the gate driving circuit further includes a bootstrap capacitor, a first plate of the bootstrap capacitor is connected to the first point, and a second plate of the bootstrap capacitor is connected to the first point.
  • a signal output terminal is connected.
  • the gate driving circuit further includes a reset circuit
  • the reset circuit further includes a reset signal terminal and a reset transistor
  • the gate of the reset transistor is connected to the reset signal terminal
  • the reset transistor has a gate connected to the reset signal terminal.
  • the first electrode is connected to the first point
  • the second electrode of the reset transistor is connected to the low-potential voltage terminal.
  • Embodiments of the present application provide a gate driving circuit and a display panel.
  • the gate driving circuit includes a pull-up control circuit, a signal transmission circuit, a pull-up circuit, a pull-down circuit, and a pull-down maintaining circuit.
  • the pull-up control circuit is the same as the first point connection, used to pull up the potential of the first point during the display time period;
  • the signal transmission circuit is connected to the first point and the pull-up control circuit, used for the first stage transmission signal output terminal the potential is pulled high;
  • the pull-up circuit is connected to the first point and the pull-up control circuit, and is used to pull up the potential of the first signal output terminal;
  • the pull-down circuit is connected to the first point for Pull down the potential of the first point during the display period;
  • the pull-down maintaining circuit is connected to the first point for maintaining the low potential of the first point, wherein the pull-down maintaining circuit includes an inverting phase
  • the inverter includes a first transistor, a second transistor, and a third
  • the second electrode of the first transistor is connected to the second electrode of the third transistor, the first electrode of the third transistor is connected to the second electrode of the second transistor, the first electrode of the third transistor is connected to the second signal output terminal, and the The second electrode of the third transistor is connected to the low-potential voltage input terminal; by reducing the number of transistors of the inverter in the pull-down maintaining circuit, the number of signal output terminals connected to the inverter is reduced, so that other output terminals in the pull-down maintaining circuit are reduced.
  • the number of transistors is reduced, thereby reducing the number of transistors and signal output terminals in the pull-down sustain circuit, thereby reducing the number of transistors and signal output terminals in the gate driving circuit, thereby alleviating the existing display panel existing in the gate driving circuit.
  • the transistor occupies a large space, which leads to a technical problem of a large frame of the display panel.
  • FIG. 1 is a schematic diagram of a conventional gate driving circuit.
  • FIG. 2 is a schematic diagram of a gate driving circuit according to an embodiment of the present application.
  • FIG. 3 is a timing diagram of a display period of a gate driving circuit provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a display panel according to an embodiment of the present application.
  • the embodiments of the present application aim at the technical problem that transistors in the gate driving circuit of the existing display panel occupy a large space, resulting in a large frame of the display panel.
  • the embodiments of the present application are used to alleviate the above technical problems.
  • the existing gate driving circuit includes a pull-up control circuit 111 , a pull-up circuit 112 , a pull-down circuit 113 , a pull-down maintaining circuit 114 , a bootstrap capacitor Cb, a pull-up control circuit 111 and a stage transmission signal input terminal ST (n-4) is connected to the signal input terminal G (n-4), the pull-up control circuit is connected to point Qn, the pull-up circuit 112 is connected to the clock signal CKn, the pull-up circuit 112 is connected to the transistor T22 and the bootstrap capacitor Cb,
  • the transistor T22 is connected to the stage transmission signal output terminal STn, the pull-down circuit 113 is connected to the signal output terminal Gn, the pull-down circuit 113 is connected to the signal input terminal G(n+4), and the pull-down maintaining circuit 114 includes an inverter, a transistor T33, and a transistor T43.
  • the inverter includes high potential voltage terminal VGH, low frequency clock signal terminal LC1, low frequency clock signal terminal LC2, transistor T51, transistor T61, transistor T52, transistor T62 , the transistor T51 is connected to the high potential voltage terminal VGH, the transistor T52 and the low frequency clock signal terminal LC1, the transistor T61 is connected to the high potential voltage terminal VGH, the transistor T62 and the low frequency clock signal terminal LC2, and the transistor T52 is connected to the Qn point and the low potential voltage terminal VSS The transistor T62 is connected to the Qn point and the low-potential voltage terminal VSS.
  • the gate drive circuit It can be seen from the gate drive circuit that the number of transistors in the gate drive circuit is large, and the space occupied by the transistors is large, resulting in the border of the display panel.
  • an embodiment of the present application provides a gate drive circuit
  • the gate drive circuit includes:
  • the pull-up control circuit 211 connected to the first point Qn, is used to pull up the potential of the first point Qn during the display period;
  • the signal transmission circuit 212 is connected to the first point Qn and the pull-up control circuit 211, and is used to pull up the potential of the first stage transmission signal output terminal STn;
  • a pull-down circuit 214 connected to the first point Qn, for pulling down the potential of the first point Qn during the display period;
  • the pull-down maintaining circuit 215 includes an inverter 217 and a low-potential voltage terminal VSS.
  • the inverter 217 includes a first transistor T1, a second transistor T2, and a third transistor T3.
  • the gate of the third transistor T3 is connected to The first point Qn is connected, the first electrode of the third transistor T3 is connected to the second electrode of the first transistor T1, and the first electrode of the third transistor T3 is connected to the second electrode of the second transistor T2.
  • Two electrodes are connected, the first electrode of the third transistor T3 is connected to the second signal output terminal Kn, and the second electrode of the third transistor T3 is connected to the low-potential voltage input terminal VSS.
  • An embodiment of the present application provides a gate drive circuit
  • the gate drive circuit includes a pull-up control circuit, a signal transmission circuit, a pull-up circuit, a pull-down circuit and a pull-down maintaining circuit
  • the pull-up control circuit is connected to the first point, used to pull up the potential of the first point during the display period
  • the signal transmission circuit is connected to the first point and the pull-up control circuit, and used to pull up the potential of the first-stage transmission signal output terminal
  • the pull-up circuit is connected to the first point and the pull-up control circuit for pulling up the potential of the first signal output terminal
  • the pull-down circuit is connected to the first point for displaying time
  • the segment pulls down the potential of the first point
  • the pull-down maintaining circuit is connected to the first point for maintaining the low potential of the first point
  • the pull-down maintaining circuit includes an inverter and a low Potential voltage terminal
  • the inverter includes a first transistor, a second transistor, and a third transistor
  • the gate of the third transistor is
  • Qn in FIG. 2 includes multiple connection ends, but in practice, multiple connections of Qn are one point. For the convenience of illustration and description, Qn is divided into multiple connection ends. The actual multiple connection ends are For the same point, similarly, multiple connection ends of Kn are also the same point.
  • the inverter 217 further includes a high-potential voltage terminal VGH, a first low-frequency clock signal terminal LC1 and a second low-frequency clock signal terminal LC2, and the first transistor T1 has a The gate is connected to the first low frequency clock signal terminal LC1, the first electrode of the first transistor T1 is connected to the high potential voltage terminal VGH, and the gate of the second transistor T2 is connected to the second low frequency clock The signal terminal LC2 is connected, and the first electrode of the second transistor T2 is connected to the high-potential voltage terminal VGH.
  • the frame is reduced by reducing the number of transistors in the inverter, but in order to make the The inverter operates normally, so that the inverter includes a high potential voltage terminal, a first low frequency clock signal terminal, a second low frequency clock signal terminal, a first transistor, a second transistor and a third transistor.
  • the pull-down maintaining circuit 215 further includes a fourth transistor T4, a fifth transistor T5, a first point Qn and a second signal output terminal Kn.
  • the gate is connected to the second signal output terminal Kn
  • the first electrode of the fourth transistor T4 is connected to the first point Qn
  • the second electrode of the fourth transistor T4 is connected to the low-potential voltage input terminal VSS is connected
  • the gate of the fifth transistor T5 is connected to the second signal output terminal Kn
  • the first electrode of the fifth transistor T5 is connected to the first signal output terminal Gn
  • the first electrode of the fifth transistor T5 is connected to the first signal output terminal Gn.
  • the two electrodes are connected to the low-potential input terminal VSS.
  • the pull-down sustain circuit since the number of transistors in the inverter is reduced, the number of signal output terminals connected to the inverter is reduced, so that the number of transistors connected to the signal output terminal is reduced. , that is, the number of transistors and signal output terminals of the pull-down sustain circuit is reduced, thereby reducing the frame of the display panel.
  • the pull-up control circuit 211 includes a sixth transistor T6 , a first stage transmission signal input terminal ST(n ⁇ 4), and a first signal input terminal G(n ⁇ 4). ), the gate of the sixth transistor T6 is connected to the first stage signal input terminal ST(n-4), and the first electrode of the sixth transistor T6 is connected to the first signal input terminal G(n -4) Connection, the second electrode of the sixth transistor T6 is connected to the first point Qn, when the pull-up control circuit is set, only one transistor can be included in the pull-up control circuit, thereby reducing the number of transistors, Thereby, the frame of the display panel is reduced.
  • the signal transmission circuit 212 includes a seventh transistor T7 and a first stage transmission signal output terminal STn, and the gate of the seventh transistor T7 is connected to the first point Qn connection, the first electrode of the seventh transistor T7 is connected to the first clock signal input terminal CKn, the second electrode of the seventh transistor T7 is connected to the first stage transmission signal output terminal STn, in the signal transmission circuit , through the control of the voltage of the first point and the signal transmission of the clock signal, the signal at the output end of the first stage transmission signal is controlled.
  • the pull-up circuit 213 includes an eighth transistor T8, a first clock signal input terminal CKn and a first signal output terminal Gn, and the gate of the eighth transistor T8 is connected to the The first point Qn is connected, the first electrode of the eighth transistor T8 is connected to the first clock signal input terminal CKn, the second electrode of the eighth transistor T8 is connected to the first signal output terminal Gn, and the pull-up In the circuit, one eighth transistor is used for control, thereby reducing the number of transistors in the pull-up circuit, thereby reducing the frame of the display panel.
  • the pull-down circuit 214 includes a ninth transistor T9 , a tenth transistor T10 and a second signal input terminal G(n+4), and the gate of the ninth transistor T9 Connected to the second signal input terminal G(n+4), the first electrode of the ninth transistor T9 is connected to the low-potential voltage terminal VSS, and the second electrode of the ninth transistor T9 is connected to the first electrode of the ninth transistor T9.
  • a signal output terminal Gn is connected, the gate of the tenth transistor T10 is connected to the second signal input terminal G(n+4), and the first electrode of the tenth transistor T10 is connected to the low-potential voltage terminal VSS connection, the second electrode of the tenth transistor T10 is connected to the first point Qn, by using the ninth transistor and the tenth transistor to control the potential of the first point and the first signal output terminal respectively, so that the pull-down circuit is reduced the number of transistors in the display panel, thereby reducing the bezel of the display panel.
  • the gate driving circuit further includes a bootstrap capacitor Cb, the first plate of the bootstrap capacitor Cb is connected to the first point Qn, and the bootstrap capacitor Cb is connected to the first point Qn.
  • the second plate of the capacitor Cb is connected to the first signal output terminal Gn.
  • the gate driving circuit further includes a reset circuit 216
  • the reset circuit 216 further includes a reset signal terminal Reset and a reset transistor Reset TFT
  • the gate of the reset transistor Reset TFT is The pole is connected to the reset signal terminal Reset
  • the reset transistor Reset The first electrode of the TFT is connected to the first point Qn
  • the reset transistor Reset The second electrode of the TFT is connected to the low-potential voltage terminal VSS.
  • the potential of the first point can be reset, so as to prevent the potential of the first point from being at a high potential for a long time, thereby avoiding The gate of the transistor is pressed for a long time to avoid the problem of threshold voltage drift of the transistor.
  • the third transistor is one of an amorphous silicon thin film transistor and an indium gallium zinc oxide thin film transistor, that is, when the third transistor is set, the third transistor may be an amorphous silicon thin film transistor, or It can be an indium gallium zinc oxide thin film transistor, and at the same time, the first transistor and the second transistor can also be one of an amorphous silicon thin film transistor and an indium gallium zinc oxide thin film transistor.
  • the third transistor is one of an N-type transistor and a P-type transistor.
  • the third transistor may be an N-type transistor or a P-type transistor.
  • the embodiment of the present application provides a timing diagram of each signal terminal and each point of a certain display period of the gate drive circuit.
  • the working process of the gate drive circuit is described.
  • the first time period t1 the first stage transmission signal input terminal ST(n-4) is at a high level
  • the sixth transistor T6 is turned on
  • the first signal input terminal G(n-4) is at a high level
  • the pull-up control circuit outputs
  • the first potential voltage makes the voltage of the Qn point rise to the first potential
  • the second time period t2 the first stage transmission signal input terminal ST(n-4) is lowered to a low potential
  • the sixth transistor T6 is turned off, this
  • the eighth transistor T8 is turned on, so that the voltage of the first point Qn rises to the second potential, and then in the third time period t3, the second signal input terminal G(
  • the signal of the second signal output terminal Kn output by 217 is at a high level, so that the fourth transistor and the fifth transistor are turned on, the first point Qn maintains a low level, and then in the fourth time period t4, the second signal input terminal G (n+ 4)
  • the signal at the second signal output terminal Kn output by the inverter 217 maintains a high level, so that the first point Qn maintains a low level.
  • t1 to t4 belong to the display time period, and the blank time period is not shown in FIG. 3 .
  • the working state of the inverter is described. As shown in FIG. 2 , taking the working state of the first low-frequency clock signal terminal LC1 as an example, since the high-potential voltage terminal VGH is always at a high potential, when the first low-frequency clock signal terminal LC1 When a low frequency clock signal terminal LC1 is at a high level and the second low frequency clock signal terminal LC2 is at a low level, if the first point Qn is at a low level, the first transistor T1 is turned on, the second transistor T2 is turned off, and the third transistor T3 is turned off , at this time, the second signal output terminal Kn outputs a high potential, so that the fourth transistor T4 is turned on, and the first point Qn is pulled to a low potential, that is, the first point Qn maintains a low potential; if the first point Qn is at a high potential, then The first transistor T1 is turned on, the second transistor T2 is turned off, and the third transistor T3 is turned on.
  • the first transistor T1 and the third transistor T3 are both turned on, the second signal output terminal Kn outputs a high potential, and the fourth transistor T4 is turned off.
  • the first point Qn maintains a high potential, so that the inverter in the embodiment of the present application achieves the original function, and at the same time, the number of transistors is reduced, and the frame of the display panel is reduced.
  • an embodiment of the present application provides a display panel.
  • the display panel 3 includes a gate driving circuit 31 , and the gate driving circuit 31 includes:
  • the pull-up control circuit 211 connected to the first point Qn, is used to pull up the potential of the first point Qn during the display period;
  • the signal transmission circuit 212 is connected to the first point Qn and the pull-up control circuit 211, and is used to pull up the potential of the first stage transmission signal output terminal STn;
  • a pull-down circuit 214 connected to the first point Qn, for pulling down the potential of the first point Qn during the display period;
  • the pull-down maintaining circuit 215 includes an inverter 217 and a low-potential voltage terminal VSS.
  • the inverter 217 includes a first transistor T1, a second transistor T2, and a third transistor T3.
  • the gate of the third transistor T3 is connected to The first point Qn is connected, the first electrode of the third transistor T3 is connected to the second electrode of the first transistor T1, and the first electrode of the third transistor T3 is connected to the second electrode of the second transistor T2.
  • Two electrodes are connected, the first electrode of the third transistor T3 is connected to the second signal output terminal Kn, and the second electrode of the third transistor T3 is connected to the low-potential voltage input terminal VSS.
  • An embodiment of the present application provides a display panel, the display panel includes a gate drive circuit, the gate drive circuit includes a pull-up control circuit, a signal transmission circuit, a pull-up circuit, a pull-down circuit and a pull-down maintenance circuit, the pull-up circuit
  • the control circuit is connected to the first point for pulling up the potential of the first point during the display period;
  • the signal transmission circuit is connected to the first point and the pull-up control circuit for pulling the first point high
  • the potential of the output terminal of the staging signal is pulled high;
  • the pull-up circuit is connected to the first point and the pull-up control circuit, and is used to pull up the potential of the first signal output terminal;
  • the pull-down circuit is connected to the first point and the pull-up control circuit.
  • the maintenance circuit includes an inverter and a low-potential voltage terminal, the inverter includes a first transistor, a second transistor, and a third transistor, the gate of the third transistor is connected to the first point, and the third transistor is connected to the first point.
  • the first electrode is connected to the second electrode of the first transistor, the first electrode of the third transistor is connected to the second electrode of the second transistor, and the first electrode of the third transistor and the second signal output
  • the second electrode of the third transistor is connected to the low-potential voltage input terminal; by reducing the number of transistors of the inverter in the pull-down maintaining circuit, the number of signal output terminals connected to the inverter is reduced, so that the pull-down circuit is reduced.
  • the number of other transistors in the sustain circuit is reduced, thereby reducing the number of transistors and signal output terminals in the pull-down sustain circuit, thereby reducing the number of transistors and signal output terminals in the gate drive circuit, thereby alleviating the existing display panel.
  • the transistors in the polar driving circuit take up a large space, which leads to a technical problem that the frame of the display panel is large.
  • the inverter further includes a high-potential voltage terminal, a first low-frequency clock signal terminal and a second low-frequency clock signal terminal, and the gate of the first transistor is connected to the The first low frequency clock signal terminal is connected to the first electrode, the first electrode of the first transistor is connected to the high potential voltage terminal, the gate of the second transistor is connected to the second low frequency clock signal terminal, and the second transistor is connected to the second low frequency clock signal terminal.
  • the first electrode of the transistor is connected to the high potential voltage terminal.
  • the pull-down maintaining circuit further includes a fourth transistor, a fifth transistor, a first point and a second signal output terminal, and the gate of the fourth transistor is connected to the The second signal output terminal is connected, the first electrode of the fourth transistor is connected to the first point, the second electrode of the fourth transistor is connected to the low-potential voltage input terminal, and the gate of the fifth transistor is connected The electrode is connected to the second signal output terminal, the first electrode of the fifth transistor is connected to the first signal output terminal, and the second electrode of the fifth transistor is connected to the low potential input terminal.
  • the pull-up control circuit includes a sixth transistor, a first stage transmission signal input terminal, and a first signal input terminal, and the gate of the sixth transistor is connected to the gate of the sixth transistor.
  • the first stage transmission signal input terminal is connected
  • the first electrode of the sixth transistor is connected to the first signal input terminal
  • the second electrode of the sixth transistor is connected to the first point.
  • the signal transmission circuit includes a seventh transistor and a first level transmission signal output terminal, the gate of the seventh transistor is connected to the first point, and the The first electrode of the seventh transistor is connected to the first clock signal input end, and the second electrode of the seventh transistor is connected to the first stage transmission signal output end.
  • the pull-up circuit includes an eighth transistor, a first clock signal input terminal and a first signal output terminal, and a gate of the eighth transistor is connected to the first point , the first electrode of the eighth transistor is connected to the first clock signal input end, and the second electrode of the eighth transistor is connected to the first signal output end.
  • the pull-down circuit includes a ninth transistor, a tenth transistor and a second signal input terminal, and a gate of the ninth transistor is connected to the second signal input terminal , the first electrode of the ninth transistor is connected to the low-potential voltage terminal, the second electrode of the ninth transistor is connected to the first signal output terminal, and the gate of the tenth transistor is connected to the first signal output terminal.
  • Two signal input terminals are connected, the first electrode of the tenth transistor is connected to the low-potential voltage terminal, and the second electrode of the tenth transistor is connected to the first point.
  • the gate driving circuit further includes a bootstrap capacitor, the first plate of the bootstrap capacitor is connected to the first point, and the The second electrode plate is connected to the first signal output terminal.
  • the gate driving circuit further includes a reset circuit
  • the reset circuit further includes a reset signal terminal and a reset transistor
  • the gate of the reset transistor is connected to the reset signal terminal
  • the first electrode of the reset transistor is connected to the first point
  • the second electrode of the reset transistor is connected to the low-potential voltage terminal.
  • Embodiments of the present application provide a gate driving circuit and a display panel.
  • the gate driving circuit includes a pull-up control circuit, a signal transmission circuit, a pull-up circuit, a pull-down circuit, and a pull-down maintaining circuit.
  • the pull-up control circuit is the same as the first point connection, used to pull up the potential of the first point during the display time period;
  • the signal transmission circuit is connected to the first point and the pull-up control circuit, used for the first stage transmission signal output terminal the potential is pulled high;
  • the pull-up circuit is connected to the first point and the pull-up control circuit, and is used to pull up the potential of the first signal output terminal;
  • the pull-down circuit is connected to the first point for Pull down the potential of the first point during the display period;
  • the pull-down maintaining circuit is connected to the first point for maintaining the low potential of the first point, wherein the pull-down maintaining circuit includes an inverting phase
  • the inverter includes a first transistor, a second transistor, and a third
  • the second electrode of the first transistor is connected to the second electrode of the third transistor, the first electrode of the third transistor is connected to the second electrode of the second transistor, the first electrode of the third transistor is connected to the second signal output terminal, and the The second electrode of the third transistor is connected to the low-potential voltage input terminal; by reducing the number of transistors of the inverter in the pull-down maintaining circuit, the number of signal output terminals connected to the inverter is reduced, so that other output terminals in the pull-down maintaining circuit are reduced.
  • the number of transistors is reduced, thereby reducing the number of transistors and signal output terminals in the pull-down sustain circuit, thereby reducing the number of transistors and signal output terminals in the gate driving circuit, thereby alleviating the existing display panel existing in the gate driving circuit.
  • the transistor occupies a large space, which leads to a technical problem of a large frame of the display panel.

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Abstract

一种栅极驱动电路和显示面板，该栅极驱动电路通过将下拉维持电路（215）中的反相器（217）的晶体管减少，使得反相器（217）连接的信号输出端减少，从而使得下拉维持电路（215）中其他的晶体管的数量减少，从而减少了下拉维持电路（215）中的晶体管和信号输出端的数量，从而减少了栅极驱动电路中的晶体管和信号输出端的数量。

Description

栅极驱动电路和显示面板 技术领域
本申请涉及显示技术领域，尤其是涉及一种栅极驱动电路和显示面板。
 背景技术
现有显示器件中为了节省成本，降低边框，会在显示面板中设置GOA（Gate Driver On Array，阵列基板行驱动技术）电路，即栅极驱动电路，使得可以节省栅极驱动芯片和减小边框，但在栅极驱动电路中，为了保持栅极输出的电压的波形正常，会在GOA电路中设置上拉控制电路、上拉电路、下拉电路、下拉维持电路、自举电容、信号传输电路，使得GOA电路正常工作，但由于GOA电路中的晶体管的数量较多，而晶体管占用的空间较大，导致显示面板的边框较大，无法实现窄边框。
所以，现有显示面板存在栅极驱动电路中的晶体管占用空间较大，导致显示面板的边框较大的技术问题。
 技术问题
本申请实施例提供一种栅极驱动电路和显示面板，用以缓解现有显示面板存在栅极驱动电路中的晶体管占用空间较大，导致显示面板的边框较大的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供一种栅极驱动电路，该栅极驱动电路包括：
上拉控制电路，与第一点连接，用于在显示时间段将所述第一点的电位拉高；
信号传输电路，与所述第一点和所述上拉控制电路连接，用于将第一级传信号输出端的电位拉高；
上拉电路，与所述第一点和所述上拉控制电路连接，用于将第一信号输出端的电位拉高；
下拉电路，与所述第一点连接，用于在显示时间段将所述第一点的电位拉低；
下拉维持电路，与所述第一点连接，用于维持所述第一点的低电位；
其中，所述下拉维持电路包括反相器和低电位电压端，所述反相器包括第一晶体管、第二晶体管、第三晶体管，第三晶体管的栅极与所述第一点连接，所述第三晶体管的第一电极与所述第一晶体管的第二电极连接，所述第三晶体管的第一电极与所述第二晶体管的第二电极连接，所述第三晶体管的第一电极与第二信号输出端连接，所述第三晶体管的第二电极与所述低电位电压输入端连接。
在一些实施例中，所述反相器还包括高电位电压端、第一低频时钟信号端和第二低频时钟信号端，所述第一晶体管的栅极与所述第一低频时钟信号端连接，所述第一晶体管的第一电极与所述高电位电压端连接，所述第二晶体管的栅极与所述第二低频时钟信号端连接，所述第二晶体管的第一电极与所述高电位电压端连接。
在一些实施例中，所述下拉维持电路还包括第四晶体管、第五晶体管、第一点和第二信号输出端，所述第四晶体管的栅极与所述第二信号输出端连接，所述第四晶体管的第一电极与所述第一点连接，所述第四晶体管的第二电极与所述低电位电压输入端连接，所述第五晶体管的栅极与所述第二信号输出端连接，所述第五晶体管的第一电极与第一信号输出端连接，所述第五晶体管的第二电极与所述低电位输入端连接。
在一些实施例中，所述上拉控制电路包括第六晶体管、第一级传信号输入端、第一信号输入端，所述第六晶体管的栅极与所述第一级传信号输入端连接，所述第六晶体管的第一电极与所述第一信号输入端连接，所述第六晶体管的第二电极与所述第一点连接。
在一些实施例中，所述信号传输电路包括第七晶体管和第一级传信号输出端，所述第七晶体管的栅极与所述第一点连接，所述第七晶体管的第一电极与第一时钟信号输入端连接，所述第七晶体管的第二电极与所述第一级传信号输出端连接。
在一些实施例中，所述上拉电路包括第八晶体管、第一时钟信号输入端和第一信号输出端，所述第八晶体管的栅极与第一点连接，所述第八晶体管的第一电极与第一时钟信号输入端连接，所述第八晶体管的第二电极与所述第一信号输出端连接。
在一些实施例中，所述下拉电路包括第九晶体管、第十晶体管和第二信号输入端，所述第九晶体管的栅极与所述第二信号输入端连接，所述第九晶体管的第一电极与所述低电位电压端连接，所述第九晶体管的第二电极与所述第一信号输出端连接，所述第十晶体管的栅极与所述第二信号输入端连接，所述第十晶体管的第一电极与所述低电位电压端连接，所述第十晶体管的第二电极与所述第一点连接。
在一些实施例中，所述栅极驱动电路还包括自举电容，所述自举电容的第一极板与所述第一点连接，所述自举电容的第二极板与所述第一信号输出端连接。
在一些实施例中，所述栅极驱动电路还包括复位电路，所述复位电路还包括复位信号端和复位晶体管，所述复位晶体管的栅极与所述复位信号端连接，所述复位晶体管的第一电极与所述第一点连接，所述复位晶体管的第二电极与所述低电位电压端连接。
在一些实施例中，所述第三晶体管为非晶硅薄膜晶体管和氧化铟镓锌薄膜晶体管中的一种。
在一些实施例中，所述第三晶体管为N型晶体管和P型晶体管中的一种。
同时，本申请实施例提供一种显示面板，该显示面板包括栅极驱动电路，所述栅极驱动电路包括：
上拉控制电路，与第一点连接，用于在显示时间段将所述第一点的电位拉高；
信号传输电路，与所述第一点和所述上拉控制电路连接，用于将第一级传信号输出端的电位拉高；
上拉电路，与所述第一点和所述上拉控制电路连接，用于将第一信号输出端的电位拉高；
下拉电路，与所述第一点连接，用于在显示时间段将所述第一点的电位拉低；
下拉维持电路，与所述第一点连接，用于维持所述第一点的低电位；
其中，所述下拉维持电路包括反相器和低电位电压端，所述反相器包括第一晶体管、第二晶体管、第三晶体管，第三晶体管的栅极与所述第一点连接，所述第三晶体管的第一电极与所述第一晶体管的第二电极连接，所述第三晶体管的第一电极与所述第二晶体管的第二电极连接，所述第三晶体管的第一电极与第二信号输出端连接，所述第三晶体管的第二电极与所述低电位电压输入端连接。
在一些实施例中，所述反相器还包括高电位电压端、第一低频时钟信号端和第二低频时钟信号端，所述第一晶体管的栅极与所述第一低频时钟信号端连接，所述第一晶体管的第一电极与所述高电位电压端连接，所述第二晶体管的栅极与所述第二低频时钟信号端连接，所述第二晶体管的第一电极与所述高电位电压端连接。
在一些实施例中，所述下拉维持电路还包括第四晶体管、第五晶体管、第一点和第二信号输出端，所述第四晶体管的栅极与所述第二信号输出端连接，所述第四晶体管的第一电极与所述第一点连接，所述第四晶体管的第二电极与所述低电位电压输入端连接，所述第五晶体管的栅极与所述第二信号输出端连接，所述第五晶体管的第一电极与第一信号输出端连接，所述第五晶体管的第二电极与所述低电位输入端连接。
在一些实施例中，所述上拉控制电路包括第六晶体管、第一级传信号输入端、第一信号输入端，所述第六晶体管的栅极与所述第一级传信号输入端连接，所述第六晶体管的第一电极与所述第一信号输入端连接，所述第六晶体管的第二电极与所述第一点连接。
在一些实施例中，所述信号传输电路包括第七晶体管和第一级传信号输出端，所述第七晶体管的栅极与所述第一点连接，所述第七晶体管的第一电极与第一时钟信号输入端连接，所述第七晶体管的第二电极与所述第一级传信号输出端连接。
在一些实施例中，所述上拉电路包括第八晶体管、第一时钟信号输入端和第一信号输出端，所述第八晶体管的栅极与第一点连接，所述第八晶体管的第一电极与第一时钟信号输入端连接，所述第八晶体管的第二电极与所述第一信号输出端连接。
在一些实施例中，所述下拉电路包括第九晶体管、第十晶体管和第二信号输入端，所述第九晶体管的栅极与所述第二信号输入端连接，所述第九晶体管的第一电极与所述低电位电压端连接，所述第九晶体管的第二电极与所述第一信号输出端连接，所述第十晶体管的栅极与所述第二信号输入端连接，所述第十晶体管的第一电极与所述低电位电压端连接，所述第十晶体管的第二电极与所述第一点连接。
在一些实施例中，所述栅极驱动电路还包括自举电容，所述自举电容的第一极板与所述第一点连接，所述自举电容的第二极板与所述第一信号输出端连接。
在一些实施例中，所述栅极驱动电路还包括复位电路，所述复位电路还包括复位信号端和复位晶体管，所述复位晶体管的栅极与所述复位信号端连接，所述复位晶体管的第一电极与所述第一点连接，所述复位晶体管的第二电极与所述低电位电压端连接。
 有益效果
本申请实施例提供一种栅极驱动电路和显示面板，该栅极驱动电路包括上拉控制电路、信号传输电路、上拉电路、下拉电路和下拉维持电路，所述上拉控制电路与第一点连接，用于在显示时间段将所述第一点的电位拉高；所述信号传输电路与所述第一点和所述上拉控制电路连接，用于将第一级传信号输出端的电位拉高；所述上拉电路与所述第一点和所述上拉控制电路连接，用于将第一信号输出端的电位拉高；所述下拉电路与所述第一点连接，用于在显示时间段将所述第一点的电位拉低；所述下拉维持电路与所述第一点连接，用于维持所述第一点的低电位，其中，所述下拉维持电路包括反相器和低电位电压端，所述反相器包括第一晶体管、第二晶体管、第三晶体管，第三晶体管的栅极与所述第一点连接，所述第三晶体管的第一电极与所述第一晶体管的第二电极连接，所述第三晶体管的第一电极与所述第二晶体管的第二电极连接，所述第三晶体管的第一电极与第二信号输出端连接，所述第三晶体管的第二电极与所述低电位电压输入端连接；通过将下拉维持电路中的反相器的晶体管减少，使得反相器连接的信号输出端减少，从而使得下拉维持电路中其他的晶体管的数量减少，从而减少了下拉维持电路中的晶体管和信号输出端的数量，从而减少了栅极驱动电路中的晶体管和信号输出端的数量，从而缓解了现有显示面板存在栅极驱动电路中的晶体管占用空间较大，导致显示面板的边框较大的技术问题。
 附图说明
图1为现有栅极驱动电路的示意图。
图2为本申请实施例提供的栅极驱动电路的示意图。
图3为本申请实施例提供的栅极驱动电路的显示时间段的时序图。
图4为本申请实施例提供的显示面板的示意图。
 本发明的实施方式
本申请提供一种栅极驱动电路和显示面板，为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
本申请实施例针对现有显示面板存在栅极驱动电路中的晶体管占用空间较大，导致显示面板的边框较大的技术问题，本申请实施例用以缓解上述技术问题。
如图1所示，现有栅极驱动电路包括上拉控制电路111、上拉电路112、下拉电路113、下拉维持电路114、自举电容Cb，上拉控制电路111与级传信号输入端ST（n-4）和信号输入端G（n-4）连接，上拉控制电路与Qn点连接，上拉电路112与时钟信号CKn连接，上拉电路112与晶体管T22和自举电容Cb连接，晶体管T22与级传信号输出端STn连接，下拉电路113与信号输出端Gn连接，下拉电路113与信号输入端G（n+4）连接，下拉维持电路114包括反相器、晶体管T33、晶体管T43、晶体管T44、晶体管T34、信号输出端Kn和信号输出端Pn，反相器包括高电位电压端VGH、低频时钟信号端LC1、低频时钟信号端LC2、晶体管T51、晶体管T61、晶体管T52、晶体管T62，晶体管T51与高电位电压端VGH、晶体管T52、低频时钟信号端LC1连接，晶体管T61与高电位电压端VGH、晶体管T62、低频时钟信号端LC2连接，晶体管T52与Qn点和低电位电压端VSS连接，晶体管T62与Qn点和低电位电压端VSS连接，从栅极驱动电路中可以看出，栅极驱动电路中的晶体管的数量较多，而晶体管占用的空间较大，导致显示面板的边框较大，无法实现窄边框，即现有显示面板存在栅极驱动电路中的晶体管占用空间较大，导致显示面板的边框较大的技术问题。
如图2所示，本申请实施例提供一种栅极驱动电路，该栅极驱动电路包括：
上拉控制电路211，与第一点Qn连接，用于在显示时间段将所述第一点Qn的电位拉高；
信号传输电路212，与所述第一点Qn和所述上拉控制电路211连接，用于将第一级传信号输出端STn的电位拉高；
上拉电路213，与所述第一点Qn和所述上拉控制电路211连接，用于将第一信号输出端Gn的电位拉高；
下拉电路214，与所述第一点Qn连接，用于在显示时间段将所述第一点Qn的电位拉低；
下拉维持电路215，与所述第一点Qn连接，用于维持所述第一点Qn的低电位；
其中，所述下拉维持电路215包括反相器217和低电位电压端VSS，所述反相器217包括第一晶体管T1、第二晶体管T2、第三晶体管T3，第三晶体管T3的栅极与所述第一点Qn连接，所述第三晶体管T3的第一电极与所述第一晶体管T1的第二电极连接，所述第三晶体管T3的第一电极与所述第二晶体管T2的第二电极连接，所述第三晶体管T3的第一电极与第二信号输出端Kn连接，所述第三晶体管T3的第二电极与所述低电位电压输入端VSS连接。
本申请实施例提供一种栅极驱动电路，该栅极驱动电路包括上拉控制电路、信号传输电路、上拉电路、下拉电路和下拉维持电路，所述上拉控制电路与第一点连接，用于在显示时间段将所述第一点的电位拉高；所述信号传输电路与所述第一点和所述上拉控制电路连接，用于将第一级传信号输出端的电位拉高；所述上拉电路与所述第一点和所述上拉控制电路连接，用于将第一信号输出端的电位拉高；所述下拉电路与所述第一点连接，用于在显示时间段将所述第一点的电位拉低；所述下拉维持电路与所述第一点连接，用于维持所述第一点的低电位，其中，所述下拉维持电路包括反相器和低电位电压端，所述反相器包括第一晶体管、第二晶体管、第三晶体管，第三晶体管的栅极与所述第一点连接，所述第三晶体管的第一电极与所述第一晶体管的第二电极连接，所述第三晶体管的第一电极与所述第二晶体管的第二电极连接，所述第三晶体管的第一电极与第二信号输出端连接，所述第三晶体管的第二电极与所述低电位电压输入端连接；通过将下拉维持电路中的反相器的晶体管减少，使得反相器连接的信号输出端减少，从而使得下拉维持电路中其他的晶体管的数量减少，从而减少了下拉维持电路中的晶体管和信号输出端的数量，从而减少了栅极驱动电路中的晶体管和信号输出端的数量，从而缓解了现有显示面板存在栅极驱动电路中的晶体管占用空间较大，导致显示面板的边框较大的技术问题。
需要说明的是，图2中以黑色圆点218标出的点表示交叉设置的两条线在该点导通，但图2中并未标出所有的导通点，实际的连接在下述实施例中陈述。
需要说明的是，图2中的Qn包括多个连接端，但实际中Qn的多个连接为一个点，为了方便示出和叙述，将Qn分为多个连接端，实际多个连接端为相同的一个点，类似的，Kn的多个连接端也为同一点。
在一种实施例中，如图2所示，所述反相器217还包括高电位电压端VGH、第一低频时钟信号端LC1和第二低频时钟信号端LC2，所述第一晶体管T1的栅极与所述第一低频时钟信号端LC1连接，所述第一晶体管T1的第一电极与所述高电位电压端VGH连接，所述第二晶体管T2的栅极与所述第二低频时钟信号端LC2连接，所述第二晶体管T2的第一电极与所述高电位电压端VGH连接，在栅极驱动电路中，通过减少反相器中的晶体管的数量来减小边框，但为了使反相器正常工作，使得反相器包括高电位电压端、第一低频时钟信号端、第二低频时钟信号端、第一晶体管、第二晶体管和第三晶体管。
在一种实施例中，如图2所示，所述下拉维持电路215还包括第四晶体管T4、第五晶体管T5、第一点Qn和第二信号输出端Kn，所述第四晶体管T4的栅极与所述第二信号输出端Kn连接，所述第四晶体管T4的第一电极与所述第一点Qn连接，所述第四晶体管T4的第二电极与所述低电位电压输入端VSS连接，所述第五晶体管T5的栅极与所述第二信号输出端Kn连接，所述第五晶体管T5的第一电极与第一信号输出端Gn连接，所述第五晶体管T5的第二电极与所述低电位输入端VSS连接，在下拉维持电路中，由于反相器中的晶体管的数量减少，反相器连接的信号输出端的数量减少，使得信号输出端连接的晶体管的数量减少，即减少了下拉维持电路的晶体管和信号输出端的数量，从而减少了显示面板的边框。
在一种实施例中，如图2所示，所述上拉控制电路211包括第六晶体管T6、第一级传信号输入端ST（n-4）、第一信号输入端G（n-4），所述第六晶体管T6的栅极与所述第一级传信号输入端ST（n-4）连接，所述第六晶体管T6的第一电极与所述第一信号输入端G（n-4）连接，所述第六晶体管T6的第二电极与所述第一点Qn连接，在设置上拉控制电路时，可以使得上拉控制电路中仅包括一个晶体管，从而降低晶体管的数量，从而减小显示面板的边框。
在一种实施例中，如图2所示，所述信号传输电路212包括第七晶体管T7和第一级传信号输出端STn，所述第七晶体管T7的栅极与所述第一点Qn连接，所述第七晶体管T7的第一电极与第一时钟信号输入端CKn连接，所述第七晶体管T7的第二电极与所述第一级传信号输出端STn连接，在信号传输电路中，通过第一点电压的控制和时钟信号的信号传输，对第一级传信号输出端的信号进行控制。
在一种实施例中，如图2所示，所述上拉电路213包括第八晶体管T8、第一时钟信号输入端CKn和第一信号输出端Gn，所述第八晶体管T8的栅极与第一点Qn连接，所述第八晶体管T8的第一电极与第一时钟信号输入端CKn连接，所述第八晶体管T8的第二电极与所述第一信号输出端Gn连接，在上拉电路中，采用第八晶体管一个晶体管进行控制，从而减少了上拉电路中的晶体管的数量，从而减小了显示面板的边框。
在一种实施例中，如图2所示，所述下拉电路214包括第九晶体管T9、第十晶体管T10和第二信号输入端G（n+4），所述第九晶体管T9的栅极与所述第二信号输入端G（n+4）连接，所述第九晶体管T9的第一电极与所述低电位电压端VSS连接，所述第九晶体管T9的第二电极与所述第一信号输出端Gn连接，所述第十晶体管T10的栅极与所述第二信号输入端G（n+4）连接，所述第十晶体管T10的第一电极与所述低电位电压端VSS连接，所述第十晶体管T10的第二电极与所述第一点Qn连接，通过采用第九晶体管和第十晶体管分别对第一点和第一信号输出端的电位进行控制，使得减少了下拉电路中的晶体管的数量，从而减小了显示面板的边框。
在一种实施例中，如图2所示，所述栅极驱动电路还包括自举电容Cb，所述自举电容Cb的第一极板与所述第一点Qn连接，所述自举电容Cb的第二极板与所述第一信号输出端Gn连接。
在一种实施例中，如图2所示，所述栅极驱动电路还包括复位电路216，所述复位电路216还包括复位信号端Reset和复位晶体管Reset TFT，所述复位晶体管Reset TFT的栅极与所述复位信号端Reset连接，所述复位晶体管Reset TFT的第一电极与所述第一点Qn连接，所述复位晶体管Reset TFT的第二电极与所述低电位电压端VSS连接，通过在栅极驱动电路中设置复位电路，可以将第一点的电位复位，从而避免第一点的电位长时间处于高电位，从而避免晶体管的栅极长时间受压，避免晶体管出现阈值电压漂移的问题。
在一种实施例中，所述第三晶体管为非晶硅薄膜晶体管和氧化铟镓锌薄膜晶体管中的一种，即在设置第三晶体管时，第三晶体管可以为非晶硅薄膜晶体管，也可以为氧化铟镓锌薄膜晶体管，同时，第一晶体管、第二晶体管也可以为非晶硅薄膜晶体管和氧化铟镓锌薄膜晶体管中的一种。
在一种实施例中，所述第三晶体管为N型晶体管和P型晶体管中的一种，在设置第三晶体管时，第三晶体管可以为N型晶体管，也可以为P型晶体管。
如图3所示，本申请实施例提供栅极驱动电路的某一显示时间段的各个信号端和各点的时序图，结合图2、图3，对栅极驱动电路的工作过程进行叙述，在第一时间段t1，第一级传信号输入端ST（n-4）处于高电位，第六晶体管T6打开，第一信号输入端G（n-4）处于高电位，上拉控制电路输出第一电位电压，使得Qn点的电压升高至第一电位，然后在第二时间段t2，第一级传信号输入端ST（n-4）降低为低电位，第六晶体管T6关闭，此时第一时钟信号输入端CKn输入高电位电压，由于第一点Qn处于高电位，使得第八晶体管T8打开，从而使得第一点Qn的电压升高到第二电位，然后在第三时间段t3，第二信号输入端G（n+4）输入高电位电压，使得第九晶体管T9和第十晶体管T10打开，第一点Qn的电压被拉低到低电位，同时，此时反相器217输出的第二信号输出端Kn的信号为高电位，使得第四晶体管和第五晶体管打开，第一点Qn维持低电位，然后在第四时间段t4，第二信号输入端G（n+4）输入低电位电压，反相器217输出的第二信号输出端Kn的信号保持高电位，使得第一点Qn维持低电位。
需要说明的是，t1至t4均属于显示时间段，图3中未示出空白时间段。
在一种实施例中，对反相器的工作状态进行叙述，如图2所示，以第一低频时钟信号端LC1的工作状态为例，由于高电位电压端VGH一直处于高电位，当第一低频时钟信号端LC1处于高电位，第二低频时钟信号端LC2处于低电位时，若第一点Qn处于低电位，此时第一晶体管T1打开，第二晶体管T2关闭，第三晶体管T3关闭，此时第二信号输出端Kn输出高电位，使得第四晶体管T4打开，第一点Qn被拉到低电位，即第一点Qn维持低电位；若第一点Qn处于高电位，此时第一晶体管T1打开，第二晶体管T2关闭，第三晶体管T3打开，由于第一晶体管T1和第三晶体管T3均打开，使得第二信号输出端Kn输出高电位，第四晶体管T4关闭，此时第一点Qn维持高电位，从而使得本申请实施例中的反相器实现了原有的功能，同时减少了晶体管的数量，减小了显示面板的边框。
如图2、图4所示，本申请实施例提供一种显示面板，该显示面板3包括栅极驱动电路31，该栅极驱动电路31包括：
上拉控制电路211，与第一点Qn连接，用于在显示时间段将所述第一点Qn的电位拉高；
信号传输电路212，与所述第一点Qn和所述上拉控制电路211连接，用于将第一级传信号输出端STn的电位拉高；
上拉电路213，与所述第一点Qn和所述上拉控制电路211连接，用于将第一信号输出端Gn的电位拉高；
下拉电路214，与所述第一点Qn连接，用于在显示时间段将所述第一点Qn的电位拉低；
下拉维持电路215，与所述第一点Qn连接，用于维持所述第一点Qn的低电位；
其中，所述下拉维持电路215包括反相器217和低电位电压端VSS，所述反相器217包括第一晶体管T1、第二晶体管T2、第三晶体管T3，第三晶体管T3的栅极与所述第一点Qn连接，所述第三晶体管T3的第一电极与所述第一晶体管T1的第二电极连接，所述第三晶体管T3的第一电极与所述第二晶体管T2的第二电极连接，所述第三晶体管T3的第一电极与第二信号输出端Kn连接，所述第三晶体管T3的第二电极与所述低电位电压输入端VSS连接。
本申请实施例提供一种显示面板，该显示面板包括栅极驱动电路，所述栅极驱动电路包括上拉控制电路、信号传输电路、上拉电路、下拉电路和下拉维持电路，所述上拉控制电路与第一点连接，用于在显示时间段将所述第一点的电位拉高；所述信号传输电路与所述第一点和所述上拉控制电路连接，用于将第一级传信号输出端的电位拉高；所述上拉电路与所述第一点和所述上拉控制电路连接，用于将第一信号输出端的电位拉高；所述下拉电路与所述第一点连接，用于在显示时间段将所述第一点的电位拉低；所述下拉维持电路与所述第一点连接，用于维持所述第一点的低电位，其中，所述下拉维持电路包括反相器和低电位电压端，所述反相器包括第一晶体管、第二晶体管、第三晶体管，第三晶体管的栅极与所述第一点连接，所述第三晶体管的第一电极与所述第一晶体管的第二电极连接，所述第三晶体管的第一电极与所述第二晶体管的第二电极连接，所述第三晶体管的第一电极与第二信号输出端连接，所述第三晶体管的第二电极与所述低电位电压输入端连接；通过将下拉维持电路中的反相器的晶体管减少，使得反相器连接的信号输出端减少，从而使得下拉维持电路中其他的晶体管的数量减少，从而减少了下拉维持电路中的晶体管和信号输出端的数量，从而减少了栅极驱动电路中的晶体管和信号输出端的数量，从而缓解了现有显示面板存在栅极驱动电路中的晶体管占用空间较大，导致显示面板的边框较大的技术问题。
在一种实施例中，在所述显示面板中，所述反相器还包括高电位电压端、第一低频时钟信号端和第二低频时钟信号端，所述第一晶体管的栅极与所述第一低频时钟信号端连接，所述第一晶体管的第一电极与所述高电位电压端连接，所述第二晶体管的栅极与所述第二低频时钟信号端连接，所述第二晶体管的第一电极与所述高电位电压端连接。
在一种实施例中，在所述显示面板中，所述下拉维持电路还包括第四晶体管、第五晶体管、第一点和第二信号输出端，所述第四晶体管的栅极与所述第二信号输出端连接，所述第四晶体管的第一电极与所述第一点连接，所述第四晶体管的第二电极与所述低电位电压输入端连接，所述第五晶体管的栅极与所述第二信号输出端连接，所述第五晶体管的第一电极与第一信号输出端连接，所述第五晶体管的第二电极与所述低电位输入端连接。
在一种实施例中，在所述显示面板中，所述上拉控制电路包括第六晶体管、第一级传信号输入端、第一信号输入端，所述第六晶体管的栅极与所述第一级传信号输入端连接，所述第六晶体管的第一电极与所述第一信号输入端连接，所述第六晶体管的第二电极与所述第一点连接。
在一种实施例中，在所述显示面板中，所述信号传输电路包括第七晶体管和第一级传信号输出端，所述第七晶体管的栅极与所述第一点连接，所述第七晶体管的第一电极与第一时钟信号输入端连接，所述第七晶体管的第二电极与所述第一级传信号输出端连接。
在一种实施例中，在所述显示面板中，所述上拉电路包括第八晶体管、第一时钟信号输入端和第一信号输出端，所述第八晶体管的栅极与第一点连接，所述第八晶体管的第一电极与第一时钟信号输入端连接，所述第八晶体管的第二电极与所述第一信号输出端连接。
在一种实施例中，在所述显示面板中，所述下拉电路包括第九晶体管、第十晶体管和第二信号输入端，所述第九晶体管的栅极与所述第二信号输入端连接，所述第九晶体管的第一电极与所述低电位电压端连接，所述第九晶体管的第二电极与所述第一信号输出端连接，所述第十晶体管的栅极与所述第二信号输入端连接，所述第十晶体管的第一电极与所述低电位电压端连接，所述第十晶体管的第二电极与所述第一点连接。
在一种实施例中，在所述显示面板中，所述栅极驱动电路还包括自举电容，所述自举电容的第一极板与所述第一点连接，所述自举电容的第二极板与所述第一信号输出端连接。
在一种实施例中，在所述显示面板中，所述栅极驱动电路还包括复位电路，所述复位电路还包括复位信号端和复位晶体管，所述复位晶体管的栅极与所述复位信号端连接，所述复位晶体管的第一电极与所述第一点连接，所述复位晶体管的第二电极与所述低电位电压端连接。
根据以上实施例可知：
本申请实施例提供一种栅极驱动电路和显示面板，该栅极驱动电路包括上拉控制电路、信号传输电路、上拉电路、下拉电路和下拉维持电路，所述上拉控制电路与第一点连接，用于在显示时间段将所述第一点的电位拉高；所述信号传输电路与所述第一点和所述上拉控制电路连接，用于将第一级传信号输出端的电位拉高；所述上拉电路与所述第一点和所述上拉控制电路连接，用于将第一信号输出端的电位拉高；所述下拉电路与所述第一点连接，用于在显示时间段将所述第一点的电位拉低；所述下拉维持电路与所述第一点连接，用于维持所述第一点的低电位，其中，所述下拉维持电路包括反相器和低电位电压端，所述反相器包括第一晶体管、第二晶体管、第三晶体管，第三晶体管的栅极与所述第一点连接，所述第三晶体管的第一电极与所述第一晶体管的第二电极连接，所述第三晶体管的第一电极与所述第二晶体管的第二电极连接，所述第三晶体管的第一电极与第二信号输出端连接，所述第三晶体管的第二电极与所述低电位电压输入端连接；通过将下拉维持电路中的反相器的晶体管减少，使得反相器连接的信号输出端减少，从而使得下拉维持电路中其他的晶体管的数量减少，从而减少了下拉维持电路中的晶体管和信号输出端的数量，从而减少了栅极驱动电路中的晶体管和信号输出端的数量，从而缓解了现有显示面板存在栅极驱动电路中的晶体管占用空间较大，导致显示面板的边框较大的技术问题。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种栅极驱动电路，其包括：
    上拉控制电路，与第一点连接，用于在显示时间段将所述第一点的电位拉高；
    信号传输电路，与所述第一点和所述上拉控制电路连接，用于将第一级传信号输出端的电位拉高；
    上拉电路，与所述第一点和所述上拉控制电路连接，用于将第一信号输出端的电位拉高；
    下拉电路，与所述第一点连接，用于在显示时间段将所述第一点的电位拉低；
    下拉维持电路，与所述第一点连接，用于维持所述第一点的低电位；
    其中，所述下拉维持电路包括反相器和低电位电压端，所述反相器包括第一晶体管、第二晶体管、第三晶体管，第三晶体管的栅极与所述第一点连接，所述第三晶体管的第一电极与所述第一晶体管的第二电极连接，所述第三晶体管的第一电极与所述第二晶体管的第二电极连接，所述第三晶体管的第一电极与第二信号输出端连接，所述第三晶体管的第二电极与所述低电位电压输入端连接。
  2. 如权利要求1所述的栅极驱动电路，其中，所述反相器还包括高电位电压端、第一低频时钟信号端和第二低频时钟信号端，所述第一晶体管的栅极与所述第一低频时钟信号端连接，所述第一晶体管的第一电极与所述高电位电压端连接，所述第二晶体管的栅极与所述第二低频时钟信号端连接，所述第二晶体管的第一电极与所述高电位电压端连接。
  3. 如权利要求2所述的栅极驱动电路，其中，所述下拉维持电路还包括第四晶体管、第五晶体管、第一点和第二信号输出端，所述第四晶体管的栅极与所述第二信号输出端连接，所述第四晶体管的第一电极与所述第一点连接，所述第四晶体管的第二电极与所述低电位电压输入端连接，所述第五晶体管的栅极与所述第二信号输出端连接，所述第五晶体管的第一电极与第一信号输出端连接，所述第五晶体管的第二电极与所述低电位输入端连接。
  4. 如权利要求3所述的栅极驱动电路，其中，所述上拉控制电路包括第六晶体管、第一级传信号输入端、第一信号输入端，所述第六晶体管的栅极与所述第一级传信号输入端连接，所述第六晶体管的第一电极与所述第一信号输入端连接，所述第六晶体管的第二电极与所述第一点连接。
  5. 如权利要求4所述的栅极驱动电路，其中，所述信号传输电路包括第七晶体管和第一级传信号输出端，所述第七晶体管的栅极与所述第一点连接，所述第七晶体管的第一电极与第一时钟信号输入端连接，所述第七晶体管的第二电极与所述第一级传信号输出端连接。
  6. 如权利要求5所述的栅极驱动电路，其中，所述上拉电路包括第八晶体管、第一时钟信号输入端和第一信号输出端，所述第八晶体管的栅极与第一点连接，所述第八晶体管的第一电极与第一时钟信号输入端连接，所述第八晶体管的第二电极与所述第一信号输出端连接。
  7. 如权利要求6所述的栅极驱动电路，其中，所述下拉电路包括第九晶体管、第十晶体管和第二信号输入端，所述第九晶体管的栅极与所述第二信号输入端连接，所述第九晶体管的第一电极与所述低电位电压端连接，所述第九晶体管的第二电极与所述第一信号输出端连接，所述第十晶体管的栅极与所述第二信号输入端连接，所述第十晶体管的第一电极与所述低电位电压端连接，所述第十晶体管的第二电极与所述第一点连接。
  8. 如权利要求7所述的栅极驱动电路，其中，所述栅极驱动电路还包括自举电容，所述自举电容的第一极板与所述第一点连接，所述自举电容的第二极板与所述第一信号输出端连接。
  9. 如权利要求1所述的栅极驱动电路，其中，所述栅极驱动电路还包括复位电路，所述复位电路还包括复位信号端和复位晶体管，所述复位晶体管的栅极与所述复位信号端连接，所述复位晶体管的第一电极与所述第一点连接，所述复位晶体管的第二电极与所述低电位电压端连接。
  10. 如权利要求1所述的栅极驱动电路，其中，所述第三晶体管为非晶硅薄膜晶体管和氧化铟镓锌薄膜晶体管中的一种。
  11. 如权利要求1所述的栅极驱动电路，其中，所述第三晶体管为N型晶体管和P型晶体管中的一种。
  12. 一种显示面板，其中，所述显示面板还包括栅极驱动电路，所述栅极驱动电路包括：
    上拉控制电路，与第一点连接，用于在显示时间段将所述第一点的电位拉高；
    信号传输电路，与所述第一点和所述上拉控制电路连接，用于将第一级传信号输出端的电位拉高；
    上拉电路，与所述第一点和所述上拉控制电路连接，用于将第一信号输出端的电位拉高；
    下拉电路，与所述第一点连接，用于在显示时间段将所述第一点的电位拉低；
    下拉维持电路，与所述第一点连接，用于维持所述第一点的低电位；
    其中，所述下拉维持电路包括反相器和低电位电压端，所述反相器包括第一晶体管、第二晶体管、第三晶体管，第三晶体管的栅极与所述第一点连接，所述第三晶体管的第一电极与所述第一晶体管的第二电极连接，所述第三晶体管的第一电极与所述第二晶体管的第二电极连接，所述第三晶体管的第一电极与第二信号输出端连接，所述第三晶体管的第二电极与所述低电位电压输入端连接。
  13. 如权利要求12所述的显示面板，其中，所述反相器还包括高电位电压端、第一低频时钟信号端和第二低频时钟信号端，所述第一晶体管的栅极与所述第一低频时钟信号端连接，所述第一晶体管的第一电极与所述高电位电压端连接，所述第二晶体管的栅极与所述第二低频时钟信号端连接，所述第二晶体管的第一电极与所述高电位电压端连接。
  14. 如权利要求13所述的显示面板，其中，所述下拉维持电路还包括第四晶体管、第五晶体管、第一点和第二信号输出端，所述第四晶体管的栅极与所述第二信号输出端连接，所述第四晶体管的第一电极与所述第一点连接，所述第四晶体管的第二电极与所述低电位电压输入端连接，所述第五晶体管的栅极与所述第二信号输出端连接，所述第五晶体管的第一电极与第一信号输出端连接，所述第五晶体管的第二电极与所述低电位输入端连接。
  15. 如权利要求14所述的显示面板，其中，所述上拉控制电路包括第六晶体管、第一级传信号输入端、第一信号输入端，所述第六晶体管的栅极与所述第一级传信号输入端连接，所述第六晶体管的第一电极与所述第一信号输入端连接，所述第六晶体管的第二电极与所述第一点连接。
  16. 如权利要求15所述的显示面板，其中，所述信号传输电路包括第七晶体管和第一级传信号输出端，所述第七晶体管的栅极与所述第一点连接，所述第七晶体管的第一电极与第一时钟信号输入端连接，所述第七晶体管的第二电极与所述第一级传信号输出端连接。
  17. 如权利要求16所述的显示面板，其中，所述上拉电路包括第八晶体管、第一时钟信号输入端和第一信号输出端，所述第八晶体管的栅极与第一点连接，所述第八晶体管的第一电极与第一时钟信号输入端连接，所述第八晶体管的第二电极与所述第一信号输出端连接。
  18. 如权利要求17所述的显示面板，其中，所述下拉电路包括第九晶体管、第十晶体管和第二信号输入端，所述第九晶体管的栅极与所述第二信号输入端连接，所述第九晶体管的第一电极与所述低电位电压端连接，所述第九晶体管的第二电极与所述第一信号输出端连接，所述第十晶体管的栅极与所述第二信号输入端连接，所述第十晶体管的第一电极与所述低电位电压端连接，所述第十晶体管的第二电极与所述第一点连接。
  19. 如权利要求18所述的显示面板，其中，所述栅极驱动电路还包括自举电容，所述自举电容的第一极板与所述第一点连接，所述自举电容的第二极板与所述第一信号输出端连接。
  20. 如权利要求12所述的显示面板，其中，所述栅极驱动电路还包括复位电路，所述复位电路还包括复位信号端和复位晶体管，所述复位晶体管的栅极与所述复位信号端连接，所述复位晶体管的第一电极与所述第一点连接，所述复位晶体管的第二电极与所述低电位电压端连接。
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CN111312146A (zh) * 2020-03-04 2020-06-19 Tcl华星光电技术有限公司 Goa电路及显示面板

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