WO2022047899A1 - 显示面板及显示面板制作方法 - Google Patents

显示面板及显示面板制作方法 Download PDF

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Publication number
WO2022047899A1
WO2022047899A1 PCT/CN2020/121028 CN2020121028W WO2022047899A1 WO 2022047899 A1 WO2022047899 A1 WO 2022047899A1 CN 2020121028 W CN2020121028 W CN 2020121028W WO 2022047899 A1 WO2022047899 A1 WO 2022047899A1
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WIPO (PCT)
Prior art keywords
area
signal line
line
display panel
display
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2020/121028
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English (en)
French (fr)
Inventor
赵迎春
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US17/056,651 priority Critical patent/US11935900B2/en
Publication of WO2022047899A1 publication Critical patent/WO2022047899A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/56—After-treatment
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H10K50/11—OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers
    • H10K50/115—OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers comprising active inorganic nanostructures, e.g. luminescent quantum dots
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H10K50/14—Carrier transporting layers
    • H10K50/16—Electron transporting layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present application relates to the field of display technology, and in particular, to a display panel and a method for fabricating the display panel.
  • the thin film transistor needs to receive control signals and data signals from the outside through gate lines and data lines, and further transmit the data signals to the display unit to control the display function of the display unit.
  • the gate lines and the data lines are connected to the driving chip through transmission lines disposed in the non-display area of the display device, so as to receive control signals and data signals sent by the driving chip.
  • the data signal transmission lines are arranged on the upper end of the display device, and the control signal transmission lines are arranged on both sides of the display device.
  • This design method requires sufficient non-display on at least three sides of the display device. The area is used for the setting of transmission lines, which in turn leads to an excessively large frame of the display device, which is not conducive to realizing a narrow frame design.
  • the data signal transmission lines are arranged on the upper end of the display device, and the control signal transmission lines are arranged on both sides of the display device.
  • This design method requires sufficient non-display on at least three sides of the display device. The area is used for the setting of transmission lines, which in turn leads to an excessively large frame of the display device, which is not conducive to realizing a narrow frame design.
  • the present application provides a display panel, comprising a display area and a non-display area on one side of the display area, a plurality of data lines and a plurality of gate lines are arranged in the display area, and a plurality of gate lines are arranged in the non-display area Driver chip and fan-out routing area;
  • the fan-out routing area is provided with at least one fan-out module, the fan-out module includes a first routing area and a second routing area, and the first routing area is provided with an electrical connection to the driver chip and the first signal line of the data line, the second wiring area is provided with a second signal line electrically connecting the driving chip and the gate line and electrically connecting the driving chip and the the first signal line of the data line.
  • the first signal line is disposed on the first metal layer
  • the second signal line is disposed on the second metal layer
  • the first metal layer and the second metal layer are disposed between There is an insulating layer.
  • the second wiring area includes a plurality of the first signal lines and a plurality of the second signal lines, at least one of the second signal lines and at least one of the The first signal lines are parallel.
  • the first wiring area includes a first area and a second area, and the first area and the second area are respectively disposed on both sides of the second wiring area.
  • the widths of the first signal line and the second signal line are both greater than or equal to 3 microns.
  • the distance between two adjacent first signal lines is greater than or equal to 2.5 microns.
  • the second signal line in the second wiring area, is disposed between two adjacent first signal lines, and the first signal line is connected to the second signal line.
  • the spacing between the signal lines is greater than or equal to 2.5 microns.
  • the present application also provides a method for manufacturing a display panel, comprising the following steps:
  • a substrate is provided, the substrate includes a display area and a non-display area on one side of the display area;
  • the second metal layer is patterned to form the second signal line.
  • the method for patterning the first metal layer and the second metal layer includes the following steps:
  • the minimum line width of the signal line, the minimum line width of the second signal line, and the minimum line spacing between the adjacent first signal line and the second signal line are input into the computer;
  • the computer calculates the position and line width of the first signal line in the first routing area, and the distance between the first signal line and the second signal line in the second routing area. position and line width;
  • patterning is performed on the first metal layer and the second metal layer respectively.
  • the display area is further provided with a plurality of thin film transistors, the data line and the gate line are respectively electrically connected to the source and gate of the thin film transistors, and the thin film The drain of the transistor is electrically connected to the display unit.
  • the method for manufacturing the first metal layer and the second metal layer is a physical deposition method or a sputtering method.
  • the step of patterning the first metal layer includes exposure, development, and etching operations; the step of patterning the second metal layer includes exposure, development, etching operation.
  • the first signal line and the second signal line are electrically insulated.
  • the widths of the first signal line and the second signal line are both greater than or equal to 3 microns.
  • the distance between two adjacent first signal lines is greater than or equal to 2.5 microns; in the second wiring area, The second signal line is disposed between two adjacent first signal lines, and the distance between the first signal line and the second signal line is greater than or equal to 2.5 microns.
  • the present application also provides a display panel, which includes a display area and a non-display area located on one side of the display area, a plurality of data lines and a plurality of gate lines are arranged in the display area, and the non-display area is A driver chip and a fan-out routing area are provided;
  • the fan-out routing area is provided with at least one fan-out module, the fan-out module includes a first routing area and a second routing area, and the first routing area is provided with an electrical connection to the driver chip and a plurality of first signal lines of the data lines, a plurality of second signal lines electrically connected to the driving chip and the gate lines and electrically connected to the driver are provided in the second wiring area a plurality of the first signal lines of the chip and the data line, and the first signal lines and the second signal lines are electrically insulated;
  • the distance between two adjacent first signal lines is greater than or equal to 2.5 microns
  • the second signal line is disposed between two adjacent first signal lines, and the distance between the first signal line and the second signal line is greater than or is equal to 2.5 microns.
  • the display panel provided by the present application includes a display area and a non-display area located on one side of the display area.
  • the driving chip and the fan-out wiring area are arranged in the non-display area.
  • the second signal line of the line is arranged in the non-display area together, which is beneficial to realize the narrow border or no border of the three-side border of the display panel; at the same time, the fan-out line module is partitioned, and the first signal is produced
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of the fan-out line module shown in FIG. 1;
  • FIG. 4 is a schematic structural diagram of the adjacent first signal line and the second signal line in the second wiring area
  • Fig. 5 is the sectional view along D-D' of the second routing region shown in Fig. 2;
  • An embodiment of the present application provides a display panel.
  • the display panel includes a display area and a non-display area located on one side of the display area.
  • a driver chip and a fan-out wiring area are arranged in the non-display area.
  • the fan-out module is partitioned, and only the first signal line is in the first routing area, and the first signal line and the second signal line are set together in the second routing area.
  • the partition setting is beneficial to ensure the spacing of each signal line And the size is close to the design limit, thereby reducing the height of the fan-out routing area and achieving a narrow border.
  • FIG. 1 it is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • the display panel includes a display area 10 and a non-display area 20 located on one side of the display area 10.
  • a plurality of data lines 11 and a plurality of gate lines 12 are arranged in the display area 10.
  • the non-display area 20 A driver chip 21 and a fan-out wiring area 23 are arranged inside.
  • the display area 10 of the display panel is an area in the display panel used for displaying pictures, which may contain various components for realizing display functions, such as display units, pixel units, driving units, etc.
  • the display area 10 The internal data lines 11 and gate lines 12 are used to provide data signals and control signals to the display unit, so as to realize the controllability of the display screen; the non-display area 20 of the display panel is provided with peripheral wirings, components and control chips, etc.
  • the area is used to provide control signals, data signals, power supply, etc. for the display area. This area does not have display functions and is usually set at the edge of the display panel, thus determining the size of the display panel frame; the fan-out routing area 22 is used to set the connection display
  • the area 10 and the wiring area of the driving chip 21, one end of the wiring in this area is connected to the large-sized display area 10, and the other end is connected to the small-sized driving chip 21, forming a fan-shaped structure as a whole.
  • FIG. 2 is a schematic structural diagram of the fan-out line module shown in FIG. 1 .
  • the fan-out wiring area 22 is provided with at least one fan-out wiring module 23, the fan-out wiring module 23 includes a first wiring area 231 and a second wiring area 232, and the first wiring area 231 is provided with electrical wiring.
  • the first signal line 30 electrically connecting the driving chip 21 and the data line 11 is provided with a second signal electrically connecting the driving chip 21 and the gate line 22 in the second wiring area 232
  • the line 40 and the first signal line 30 electrically connect the driving chip 21 and the data line 11 .
  • the driver chip 21 may be a source driver chip for providing data signals or a gate driver chip for providing control signals, or an integrated chip providing both data signals and control signals,
  • the driving chip 21 is connected to the first signal line 30 to provide a data signal to the data line 11
  • the driving chip 21 is connected to the second signal line 40 to provide a control signal to the gate line 22 .
  • the fan-out line module 23 it is necessary to use a computer to calculate the setting position characteristics of each signal line in advance, and then make the signal line according to the calculation result; in this embodiment, since the fan-out line module 23 is divided into are the first wiring area 231 and the second wiring area 232 , and only the first signal line 30 is arranged in the first wiring area 231 , and the first signal line 30 is arranged in the second wiring area 232 together
  • the signal line 30 and the second signal line 40 therefore, when using a computer to calculate the position of each signal line, the dimensional characteristics of the first routing area 231, the dimensional characteristics of the second routing area 232, all The line width and line spacing characteristics of the first signal line 30 in the first routing area 231 , and the line width and line spacing of the first signal line 30 and the second signal line 40 in the second routing area 232
  • the characteristics are jointly input into the computer, thereby refining the position and size characteristics of each signal line in the fan-out line module 23, which is conducive to the computer to accurately calculate the
  • the first signal line 30 connected to the data line 11 and the second signal line 40 connected to the gate line 12 are disposed on the same side of the display area 10 , which is beneficial to realize the display area 10
  • the fan-out module 23 is partitioned, which is beneficial for the first signal line 30 and the second signal line 40 to have a design approaching the design limit.
  • the state distribution further reduces the display panel border.
  • the side close to the driving chip 21 is the short side
  • the side close to the display area 10 is the long side.
  • the length of the short side of the first area 2311 is a, the length of the long side is A; the length of the short side of the second area 2312 is c, and the length of the long side is C; the length of the short side of the second wiring area 232 is b, and the length of the long side is C; among them, a, b, and c can be equal or unequal, and A, B, and C can be equal or unequal.
  • the size of the short side and the long side of each area is an important parameter for the computer to calculate the distribution characteristics of the signal lines.
  • FIG. 3 is a schematic structural diagram of two adjacent first signal lines 30 in the first wiring area 231
  • FIG. 4 is the second wiring area 232
  • the width L1 of the first signal line 30 is greater than or equal to 3 ⁇ m
  • the width L2 of the second signal line 40 is greater than or equal to 3 ⁇ m
  • the distance S1 between a signal line 30 is greater than or equal to 2.5 microns
  • the second signal line 40 is disposed between two adjacent first signal lines 30, and the The distance S2 between the adjacent first signal lines 30 and the second signal lines 40 is greater than or equal to 2.5 microns.
  • the width of the first signal line 30, the width of the second signal line 40, the distance between two adjacent first signal lines 30, and the adjacent The minimum size of the distance between the first signal line 30 and the second signal line 40 is used to ensure that the first signal line 30 and the second signal line 40 work normally without short circuit, open circuit and other problems ; It should be noted that when the width of the first signal line 30, the width of the second signal line 40, the distance between two adjacent first signal lines 30, and the adjacent first signal lines 30 When the distance between a signal line 30 and the second signal line 40 keeps approaching the limit size, the vertical distance from the short side to the long side of the fan-out line module 23 is smaller, that is, the height of the fan-out line module 23 The smaller the height of the fan-out line module 23 is, the smaller the frame size of the display panel is, and the narrower frame is realized.
  • FIG. 5 is a cross-sectional view of the second wiring area 232 shown in FIG. 2 along D-D'.
  • the display panel further includes a substrate 01 disposed on the bottom layer; in the second wiring area 232 , the first signal lines 30 are disposed on the substrate 01 ; an insulating layer 02 is also disposed on the substrate 01 , the insulating layer 02 covers the first signal line 30 ; the second signal line 40 is disposed on the insulating layer 02 , so that the gap between the first signal line 30 and the second signal line 40 is Maintain electrical isolation.
  • the display panel provided by the embodiment of the present application includes a display area and a non-display area located on one side of the display area.
  • the driver chip and the fan-out wiring area are arranged in the non-display area.
  • the first signal line and the second signal line connected to the gate line are jointly disposed in the non-display area, which is beneficial to realize the narrow border or no border of the three-side border of the display panel; at the same time, the fan-out line is Partitioning of the module is beneficial to the distribution of the first signal line and the second signal line in a state approaching the design limit, thereby further reducing the frame of the display panel.
  • Step S1 providing a substrate 01
  • the substrate 01 includes a display area 10 and a non-display area 20 located on one side of the display area 10 .
  • the display area 10 is used to set various components that realize the display function of the display panel, such as display units, pixel units, driving units, etc., and is an effective display area of the display panel;
  • the non-display area 20 is used for Set peripheral wiring, components and control chips, etc. This area does not have display function.
  • the display area 10 is further provided with a plurality of thin film transistors, the data line 11 and the gate line 12 are respectively electrically connected to the source and gate of the thin film transistor, and the drain of the thin film transistor
  • the display unit is electrically connected.
  • the display unit is the most basic light-emitting display element in the display panel, and the display unit may be composed of a single pixel electrode, a common electrode, and a liquid crystal controlled by the pixel electrode and the common electrode.
  • the liquid crystal display unit can also be a single organic light emitting diode display unit.
  • Step S3 fabricating a driver chip 21 and a fan-out module 23 in the non-display area 20 of the substrate 01 .
  • the fan-out module 23 includes a first routing area 231 and a second routing area 232 .
  • a first signal line 30 electrically connecting the driving chip 21 and the data line 11 is disposed in the line area 231
  • a first signal line 30 electrically connecting the driving chip 21 and the gate is disposed in the second wiring area 232 .
  • the second signal line 40 of the pole line 12 and the first signal line 30 electrically connecting the driving chip 21 and the data line 11 are provided.
  • the method for making the fan-out module 23 includes the following steps:
  • a first wiring area 231 and a second wiring area 232 are divided in the non-display area 20 of the substrate 01 .
  • the first wiring area 231 includes a first area 2311 and a second area 2312 , and the first area 2311 and the second area 2312 are located on two sides of the second wiring area 232 respectively.
  • an insulating layer 02 covering the first signal line 30 is fabricated.
  • the insulating layer 02 may be silicon oxide or silicon nitride ceramics, and the method for fabricating the insulating layer 02 may be chemical vapor deposition or spray coating.
  • a second metal layer 40 a is formed on the insulating layer 02 in the second wiring region 232 .
  • the method for fabricating the second metal layer 40a may be a physical deposition method or a spraying method.
  • the second metal layer 40 a is patterned to form the second signal line 40 .
  • the step of patterning the second metal layer 40a includes operations such as exposure, development, and etching.
  • the minimum value of the width L1 of the first signal line 30 is set to 3 ⁇ m, and the minimum value of the width L2 of the second signal line 40 is set to 3 ⁇ m;
  • the minimum value of the distance S1 between the two first signal lines 30 is set to 2.5 ⁇ m; in the second wiring area 232 , the distance between the adjacent first signal lines 30 and the second signal lines 40 is The minimum value of the spacing S2 between them is set to 2.5 ⁇ m.
  • the feature is helpful for the computer to accurately calculate the signal line setting information that is closer to the design limit, so that the line width and position of the first signal line 30 and the second signal line 40 finally formed approach the design limit, and
  • the patterning process is performed on the first metal layer 30a and the second metal layer 40a respectively to form the first signal line 30a and the second signal line 40a.
  • the first signal line and the second signal line are arranged in the non-display area on the same side of the display panel, which is beneficial to realize the display panel
  • the three-side frame is narrowed or frameless; in addition, before the first signal line and the second signal line are fabricated, the fan-out line module is divided into partitions, and the computer equipment is based on the signal line size characteristics in each partition. It is easier to calculate the size and position of the first signal line and the second signal line that are close to the design limit, which is beneficial to further reduce the frame of the display panel.

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Abstract

一种显示面板和显示面板制作方法，显示面板包括显示区(10)和位于显示区(10)一侧的非显示区(20)，非显示区(20)内设置有驱动芯片(21)和扇出走线区(22)，扇出走线区(22)内设置有扇出线模块(23)，扇出线模块(23)包括第一走线区(231)和第二走线区(232)，第一走线区(231)内设置有连接数据线(11)的第一讯号线(30)，第二走线区(232)内设置有连接栅极线(22)的第二讯号线(40)和连接数据线(11)的第一讯号线(30)。

Description

显示面板及显示面板制作方法 技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板及显示面板制作方法。
 背景技术
液晶显示装置（Liquid Crystal Display，LCD）和有机电致发光显示装置（Organic Light-Emitting Diode，OLED）是目前应用最为广泛的两种显示技术。在这两种显示装置中，薄膜晶体管（Thin Film Transistor，TFT）被广泛用作显示驱动元件，直接关系到显示装置的显示性能。
薄膜晶体管需要通过栅极线和数据线从外部接收控制信号和数据信号，并进一步将数据信号传递给显示单元，以控制显示单元的显示功能。其中，栅极线和数据线通过设置于显示装置非显示区的传输走线连接至驱动芯片，以接收由驱动芯片发出的控制信号和数据信号。现有技术采用将数据信号传输走线设置于显示装置的上端，而将控制信号传输走线设置于显示装置的两侧，这种设计方式需要在显示装置的至少三侧边保留足够的非显示区，以供传输走线的设置，进而导致显示装置的边框过大，不利于实现窄边框设计。
 技术问题
现有技术采用将数据信号传输走线设置于显示装置的上端，而将控制信号传输走线设置于显示装置的两侧，这种设计方式需要在显示装置的至少三侧边保留足够的非显示区，以供传输走线的设置，进而导致显示装置的边框过大，不利于实现窄边框设计。
 技术解决方案
为了解决上述技术问题，本申请提供的技术方案如下：
本申请提供一种显示面板，包括显示区和位于所述显示区一侧的非显示区，所述显示区内设置有多条数据线和多条栅极线，所述非显示区内设置有驱动芯片和扇出走线区；
所述扇出走线区内设置有至少一个扇出线模块，所述扇出线模块包括第一走线区和第二走线区，所述第一走线区内设置有电性连接所述驱动芯片与所述数据线的第一讯号线，所述第二走线区内设置有电性连接所述驱动芯片与所述栅极线的第二讯号线以及电性连接所述驱动芯片与所述数据线的所述第一讯号线。
在本申请的显示面板中，在所述第二走线区内，所述第一讯号线与所述第二讯号线之间电性绝缘。
在本申请的显示面板中，所述第一讯号线设置于第一金属层，所述第二讯号线设置于第二金属层，所述第一金属层与所述第二金属层之间设置有绝缘层。
在本申请的显示面板中，还包括设置于底层的基板，在所述第二走线区内，所述第一讯号线设置于所述基板上。
在本申请的显示面板中，在所述的第二走线区内，包含多条所述第一讯号线和多条所述第二讯号线，至少一条所述第二讯号线与至少一条所述第一讯号线平行。
在本申请的显示面板中，所述第一走线区包括第一区域和第二区域，所述第一区域和所述第二区域分别设置于所述第二走线区两侧。
在本申请的显示面板中，所述第一讯号线和所述第二讯号线的宽度均大于或等于3微米。
在本申请的显示面板中，在所述第一走线区内，相邻两条所述第一讯号线之间的间距大于或等于2.5微米。
在本申请的显示面板中，在所述第二走线区内，所述第二讯号线设置于相邻两条所述第一讯号线之间，所述第一讯号线与所述第二讯号线之间的间距大于或等于2.5微米。
本申请还提供一种显示面板制作方法，包括以下步骤：
提供一基板，所述基板包括显示区和位于所述显示区一侧的非显示区；
在所述基板的显示区内制作显示单元以及电性连接所述显示单元的栅极线和数据线；
在所述基板的非显示区内制作驱动芯片和扇出线模块，所述扇出线模块包括第一走线区和第二走线区，所述第一走线区内设置有电性连接所述驱动芯片与所述数据线的第一讯号线，所述第二走线区内设置有电性连接所述驱动芯片与所述栅极线的第二讯号线以及电性连接所述驱动芯片与所述数据线的所述第一讯号线。
在本申请的显示面板制作方法中，制作所述扇出线模块的方法包括以下步骤：
在所述基板的非显示区内划分出第一走线区和第二走线区；
在所述第一走线区和所述第二走线区内的所述基板上制作第一金属层；
对所述第一金属层进行图案化处理，形成所述第一讯号线；
制作覆盖所述第一讯号线的绝缘层；
在所述第二走线区内的所述绝缘层上制作第二金属层；
对所述第二金属层进行图案化处理，形成所述第二讯号线。
在本申请的显示面板制作方法中，对所述第一金属层和所述第二金属层进行图案化处理的方法包括以下步骤：
将欲在所述第一走线区内形成的所述第一讯号线的线宽最小值和线间距最小值输入计算机，同时将欲在所述第二走线区内形成的所述第一讯号线的线宽最小值、所述第二讯号线的线宽最小值、以及相邻所述第一讯号线和所述第二讯号线之间的线间距最小值输入计算机；
所述计算机计算出所述第一走线区内的所述第一讯号线的位置和线宽，以及所述第二走线区内的所述第一讯号线和所述第二讯号线的位置和线宽；
根据所述计算机的计算结果，分别对所述第一金属层和所述第二金属层进行图案化处理。
在本申请的显示面板制作方法中，所述显示区还设置有多个薄膜晶体管，所述数据线和所述栅极线分别电性连接所述薄膜晶体管的源极和栅极，所述薄膜晶体管的漏极电性连接所述显示单元。
在本申请的显示面板制作方法中，所述第一走线区包括第一区域和第二区域，所述第一区域和所述第二区域分别位于所述第二走线区的两侧。
在本申请的显示面板制作方法中，制作所述第一金属层和所述第二金属层的方法是物理沉积法或喷镀法。
在本申请的显示面板制作方法中，对所述第一金属层进行图案化处理的步骤包括曝光、显影、刻蚀操作；对所述第二金属层进行图案化处理的步骤包括曝光、显影、刻蚀操作。
在本申请的显示面板制作方法中，制作形成的所述第一讯号线与所述第二讯号线之间电性绝缘。
在本申请的显示面板制作方法中，制作形成的所述第一讯号线和所述第二讯号线的宽度均大于或等于3微米。
在本申请的显示面板制作方法中，在所述第一走线区内，相邻两条所述第一讯号线之间的间距大于或等于2.5微米；在所述第二走线区内，所述第二讯号线设置于相邻两条所述第一讯号线之间，所述第一讯号线与所述第二讯号线之间的间距大于或等于2.5微米。
本申请还提供一种显示面板，其包括显示区和位于所述显示区一侧的非显示区，所述显示区内设置有多条数据线和多条栅极线，所述非显示区内设置有驱动芯片和扇出走线区；
所述扇出走线区内设置有至少一个扇出线模块，所述扇出线模块包括第一走线区和第二走线区，所述第一走线区内设置有电性连接所述驱动芯片与所述数据线的多条第一讯号线，所述第二走线区内设置有电性连接所述驱动芯片与所述栅极线的多条第二讯号线以及电性连接所述驱动芯片与所述数据线的多条所述第一讯号线，所述第一讯号线与所述第二讯号线之间电性绝缘；
所述第一讯号线和所述第二讯号线的宽度均大于或等于3微米；
在所述第一走线区内，相邻两条所述第一讯号线之间的间距大于或等于2.5微米；
在所述第二走线区内，所述第二讯号线设置于相邻两条所述第一讯号线之间，所述第一讯号线与所述第二讯号线之间的间距大于或等于2.5微米。
 有益效果
本申请提供的显示面板包括显示区和位于显示区一侧的非显示区，驱动芯片和扇出走线区设置于所述非显示区内，通过将连接数据线的第一讯号线和连接栅极线的第二讯号线共同设置于所述非显示区内，有利于实现显示面板的三侧边框的窄边框化或无边框化；同时，将扇出线模块进行分区，在制作所述第一讯号线和所述第二讯号线时，有利于所述第一讯号线和所述第二讯号线的设置位置和尺寸趋近于设计极限，进一步缩小显示面板边框。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的显示面板结构示意图；
图2是图1所示的扇出线模块的结构示意图；
图3是第一走线区内的相邻两条第一讯号线的结构示意图；
图4是第二走线区内的相邻的所述第一讯号线和所述第二讯号线的结构示意图；
图5是图2所示的第二走线区沿D-D’的截面图；
图6是本申请实施例提供的显示面板制作方法流程图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
本申请实施例提供一种显示面板，该显示面板包括显示区和位于显示区一侧的非显示区，驱动芯片和扇出走线区设置于所述非显示区内，通过将扇出走线区内的扇出线模块进行分区，在第一走线区内仅第一讯号线，在第二走线区内共同设置第一讯号线和第二讯号线，该分区设置有利于保证各个讯号线的间距和尺寸趋近于设计极限，从而缩小扇出走线区高度，实现窄边框。
如图1所示，是本申请实施例提供的显示面板结构示意图。所述显示面板包括显示区10和位于所述显示区10一侧的非显示区20，所述显示区10内设置有多条数据线11和多条栅极线12，所述非显示区20内设置有驱动芯片21和扇出走线区23。需要说明的是，显示面板的显示区10是显示面板中用于显示画面的区域，其内可以包含多种用于实现显示功能的元件，如显示单元、像素单元、驱动单元等，显示区10内的数据线11和栅极线12用于向显示单元提供数据信号和控制信号，以实现显示画面的可控性；显示面板的非显示区20是设置外围走线、元件和控制芯片等的区域，用于为显示区提供控制信号、数据信号、电源等，该区域不具备显示功能，通常设置于显示面板的边缘，因而决定了显示面板边框的大小；扇出走线区22是设置连接显示区10与驱动芯片21的走线的区域，该区域内的走线一端连接大尺寸的显示区10，另一端连接较小尺寸的驱动芯片21，整体形成扇形结构。
参考图1和图2所示，其中图2是图1所示的扇出线模块的结构示意图。所述扇出走线区22内设置有至少一个扇出线模块23，所述扇出线模块23包括第一走线区231和第二走线区232，所述第一走线区231内设置有电性连接所述驱动芯片21与所述数据线11的第一讯号线30，所述第二走线区232内设置有电性连接所述驱动芯片21与所述栅极线22的第二讯号线40以及电性连接所述驱动芯片21与所述数据线11的所述第一讯号线30。应当理解的是，所述驱动芯片21可以是用于提供数据信号的源极驱动芯片或用于提供的控制信号的栅极驱动芯片，也可以是兼具提供数据信号和控制信号的集成芯片，所述驱动芯片21连接所述第一讯号线30向所述数据线11提供数据信号，所述驱动芯片21连接所述第二讯号线40向所述栅极线22提供控制信号。
需要说明的是，制作所述扇出线模块23时需要使用计算机提前计算出各个讯号线的设置位置特征，然后根据计算结果制作讯号线；在本实施例中，由于所述扇出线模块23被划分为第一走线区231和第二走线区232，并且所述第一走线区231内仅设置所述第一讯号线30，所述第二走线区232内共同设置所述第一讯号线30和所述第二讯号线40，因而在使用计算机计算各个讯号线位置时，需要将所述第一走线区231的尺寸特征、所述第二走线区232的尺寸特征、所述第一走线区231内的第一讯号线30的线宽和线距特征、以及所述第二走线区232内的第一讯号线30和第二讯号线40的线宽和线距特征共同输入计算机，从而细化了各个讯号线在所述扇出线模块23内的位置和尺寸特征，有利于计算机准确计算出更加接近设计极限的讯号线设置信息，从而使最终形成的所述第一讯号线30和所述第二讯号线40趋近于设计极限。
本申请实施例通过将连接数据线11的所述第一讯号线30和连接栅极线12的所述第二讯号线40共同设置于显示区10的同一侧，有利于实现所述显示区10的其余三侧的窄边框或无边框设计；同时，将所述扇出线模块23进行分区，有利于所述第一讯号线30和所述第二讯号线40以一种趋近于设计极限的状态分布，进一步缩小显示面板边框。
可选地，所述第一走线区231包括第一区域2311和第二区域2312，所述第一区域2311和所述第二区域2312分别设置于所述第二走线区232两侧。通过将所述第一走线区231进一步细分为分布于所述第二走线区232两侧的两部分，使所述第一走线区231的结构特征更加细化，更有利于所述第一走线区231内的所述第一讯号线30趋近设计极限，进一步缩小边框尺寸。
进一步地，在所述扇出线模块23内，以靠近所述驱动芯片21一侧的边为短边，以靠近所述显示区10一侧的边为长边。所述第一区域2311的短边长度为a，长边长度为A；所述第二区域2312的短边长度为c，长边长度为C；所述第二走线区232的短边长度为b，长边长度为C；其中，a、b、c可以相等也可以不等，A、B、C可以相等也可以不等。需要说明的是，各个区域的短边和长边尺寸是计算机计算讯号线分布特征的重要参数。
参考图1至图4所示，其中，图3是所述第一走线区231内的相邻两条所述第一讯号线30的结构示意图，图4是所述第二走线区232内的相邻的所述第一讯号线30和所述第二讯号线40的结构示意图。所述第一讯号线30的宽度L1大于或等于3微米，所述第二讯号线40的宽度L2大于或等于3微米；在所述第一走线区231内，相邻两条所述第一讯号线30之间的间距S1大于或等于2.5微米；在所述第二走线区232内，所述第二讯号线40设置于相邻两条所述第一讯号线30之间，相邻的所述第一讯号线30与所述第二讯号线40之间的间距S2大于或等于2.5微米。在本实施例中，限定了所述第一讯号线30的宽度、所述第二讯号线40的宽度、相邻两条所述第一讯号线30之间的间距、以及相邻的所述第一讯号线30和所述第二讯号线40之间的间距的最小尺寸，用于保证所述第一讯号线30和所述第二讯号线40正常工作，而不发生短路、断路等问题；需要说明的是，当所述第一讯号线30的宽度、所述第二讯号线40的宽度、相邻两条所述第一讯号线30之间的间距、以及相邻的所述第一讯号线30和所述第二讯号线40之间的间距不断接近极限尺寸时，所述扇出线模块23由其短边至长边的垂直距离越小，即所述扇出线模块23的高度越小，所述扇出线模块23高度的减小，有利于缩小所述显示面板的边框尺寸，实现窄边框化。
可选地，在所述的第二走线区232内，所述第一讯号线30和所述第二讯号线40均包含有多条，每条所述第一讯号线30均有至少一条所述第二讯号线40与之平行。应当理解的是，相互平行的所述第二讯号线40与所述第一讯号线30之间的间距更容易维持极限尺寸，并且计算机根据所述第一讯号线30的位置较容易计算出所述第二讯号线40的位置特征，提高第二讯号线40的设置精度，进一步缩小所述扇出线模块23的高度，实现更窄边框。
可选地，参考图2及图5所示，其中图5是图2所示的第二走线区232沿D-D’的截面图。所述显示面板还包括设置于底层的基板01；在所述第二走线区232内，所述第一讯号线30设置于所述基板01上；所述基板01上还设置有绝缘层02，所述绝缘层02覆盖所述第一讯号线30；所述第二讯号线40设置于所述绝缘层02上，从而使所述第一讯号线30与所述第二讯号线40之间保持电性绝缘。
综上所述，本申请实施例提供的显示面板包括显示区和位于显示区一侧的非显示区，驱动芯片和扇出走线区设置于所述非显示区内，通过将连接数据线的所述第一讯号线和连接栅极线的所述第二讯号线共同设置于所述非显示区内，有利于实现显示面板的三侧边框的窄边框化或无边框化；同时，将扇出线模块进行分区，有利于所述第一讯号线和所述第二讯号线以一种趋近于设计极限的状态分布，进一步缩小显示面板边框。
本申请实施例还提供一种显示面板制作方法，如图6所示，所述显示面板制作方法包括以下步骤，参考图1至图5所示：
步骤S1、提供一基板01，所述基板01包括显示区10和位于所述显示区10一侧的非显示区20。需要说明的是，所述显示区10用于设置实现显示面板显示功能的多种元件，如显示单元、像素单元、驱动单元等，是显示面板的有效显示区域；所述非显示区20用于设置外围走线、元件和控制芯片等，该区域不具备显示功能。
步骤S2、在所述基板01的显示区10内制作显示单元以及电性连接所述显示单元的栅极线12和数据线11。所述数据线11和所述栅极线12用于向所述显示单元提供数据信号和控制信号，以实现控制所述显示单元的发光显示功能。
具体地，所述显示区10还设置有多个薄膜晶体管，所述数据线11和所述栅极线12分别电性连接所述薄膜晶体管的源极和栅极，所述薄膜晶体管的漏极电性连接所述显示单元。需要说明的是，所述显示单元是所述显示面板中的最基本的发光显示元件，所述显示单元可以是由单个像素电极、公共电极、及像素电极和公共电极共同控制的液晶所组成的液晶显示单元，也可以是单个有机发光二极管显示单元。
步骤S3、在所述基板01的非显示区20内制作驱动芯片21和扇出线模块23，所述扇出线模块23包括第一走线区231和第二走线区232，所述第一走线区231内设置有电性连接所述驱动芯片21与所述数据线11的第一讯号线30，所述第二走线区232内设置有电性连接所述驱动芯片21与所述栅极线12的第二讯号线40以及电性连接所述驱动芯片21与所述数据线11的所述第一讯号线30。
具体地，制作所述扇出线模块23的方法包括以下步骤：
在所述基板01的非显示区20内划分出第一走线区231和第二走线区232。可选地，所述第一走线区231包括第一区域2311和第二区域2312，所述第一区域2311和所述第二区域2312分别位于所述第二走线区232两侧。
在所述第一走线区231和所述第二走线区232内的所述基板01上制作第一金属层30a。可选地，制作所述第一金属层30a的方法可以是物理沉积法或喷涂法。
对所述第一金属层30a进行图案化处理，形成所述第一讯号线30。可选地，对所述第一金属层30a进行图案化处理的步骤包括曝光、显影、刻蚀等操作。
制作覆盖所述第一讯号线30的绝缘层02。可选地，所述绝缘层02可以是氧化硅或氮化硅陶瓷，制作所述绝缘层02的方法可以是化学气相沉积法或喷涂法。
在所述第二走线区232内的所述绝缘层02上制作第二金属层40a。可选地，制作所述第二金属层40a的方法可以是物理沉积法或喷涂法。
对所述第二金属层40a进行图案化处理，形成所述第二讯号线40。可选地，对所述第二金属层40a进行图案化处理的步骤包括曝光、显影、刻蚀等操作。
进一步地，对所述第一金属层30a和所述第二金属层40a进行图案化处理之前，还需要借助计算机设备进行以下操作：
将欲在所述第一走线区231内形成的所述第一讯号线30的线宽L1最小值和线间距S1最小值输入计算机，同时将欲在所述第二走线区232内形成的所述第一讯号线30的线宽L1最小值、所述第二讯号线40的线宽L2最小值、以及相邻所述第一讯号线30和所述第二讯号线40之间的线间距S2最小值输入计算机。可选地，所述第一讯号线30的宽度L1最小值设为3微米，所述第二讯号线40的宽度L2最小值设为3微米；所述第一走线区231内，相邻两条所述第一讯号线30之间的间距S1最小值设为2.5微米；所述第二走线区232内，相邻的所述第一讯号线30与所述第二讯号线40之间的间距S2最小值设为2.5微米。需要说明的是，在上述极限值条件下，所述第一讯号线30和所述第二讯号线40可以正常工作，而不发生短路、断路等问题。
所述计算机计算出所述第一走线区231内的所述第一讯号线30的位置和线宽，以及所述第二走线区232内的所述第一讯号线30和所述第二讯号线40的位置和线宽。需要说明的是，在本实施例中，由于所述扇出线模块23被划分为第一走线区231和第二走线区232，并且所述第一走线区231内仅设置所述第一讯号线30，所述第二走线区232内共同设置所述第一讯号线30和所述第二讯号线40，细化了各个讯号线在所述扇出线模块23内的位置和尺寸特征，有利于计算机准确计算出更加接近设计极限的讯号线设置信息，从而使最终形成的所述第一讯号线30和所述第二讯号线40的线宽和位置趋近于设计极限，而当所述第一讯号线30和所述第二讯号线40的线宽和位置不断趋近于设计极限时，所述扇出线模块23的高度越小，越有利于进一步缩小显示面板边框。
根据所述计算机的计算结果，分别对所述第一金属层30a和所述第二金属层40a进行上述图案化处理，以形成所述第一讯号线30a和所述第二讯号线40a。
综上所述，本申请实施例提供的显示面板制作方法，将所述第一讯号线和所述第二讯号线设置于所述显示面板的同一侧的非显示区内，有利于实现显示面板的三侧边框的窄边框化或无边框化；此外，在制作所述第一讯号线和所述第二讯号线之前，将扇出线模块进行分区，计算机设备根据各分区内的讯号线尺寸特征更容易计算出趋近于设计极限的所述第一讯号线和所述第二讯号线的尺寸和位置，有利于进一步缩小显示面板边框。
需要说明的是，虽然本申请以具体实施例揭露如上，但上述实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种显示面板，其包括显示区和位于所述显示区一侧的非显示区，所述显示区内设置有多条数据线和多条栅极线，所述非显示区内设置有驱动芯片和扇出走线区；
    所述扇出走线区内设置有至少一个扇出线模块，所述扇出线模块包括第一走线区和第二走线区，所述第一走线区内设置有电性连接所述驱动芯片与所述数据线的第一讯号线，所述第二走线区内设置有电性连接所述驱动芯片与所述栅极线的第二讯号线以及电性连接所述驱动芯片与所述数据线的所述第一讯号线。
  2. 根据权利要求1所述的显示面板，其中，在所述第二走线区内，所述第一讯号线与所述第二讯号线之间电性绝缘。
  3. 根据权利要求2所述的显示面板，其中，所述第一讯号线设置于第一金属层，所述第二讯号线设置于第二金属层，所述第一金属层与所述第二金属层之间设置有绝缘层。
  4. 根据权利要求3所述的显示面板，其中，还包括设置于底层的基板，在所述第二走线区内，所述第一讯号线设置于所述基板上。
  5. 根据权利要求2所述的显示面板，其中，在所述的第二走线区内，包含多条所述第一讯号线和多条所述第二讯号线，至少一条所述第二讯号线与至少一条所述第一讯号线平行。
  6. 根据权利要求1所述的显示面板，其中，所述第一走线区包括第一区域和第二区域，所述第一区域和所述第二区域分别设置于所述第二走线区两侧。
  7. 根据权利要求1所述的显示面板，其中，所述第一讯号线和所述第二讯号线的宽度均大于或等于3微米。
  8. 根据权利要求1所述的显示面板，其中，在所述第一走线区内，相邻两条所述第一讯号线之间的间距大于或等于2.5微米。
  9. 根据权利要求8所述的显示面板，其中，在所述第二走线区内，所述第二讯号线设置于相邻两条所述第一讯号线之间，所述第一讯号线与所述第二讯号线之间的间距大于或等于2.5微米。
  10. 一种显示面板制作方法，其包括以下步骤：
    提供一基板，所述基板包括显示区和位于所述显示区一侧的非显示区；
    在所述基板的显示区内制作显示单元以及电性连接所述显示单元的栅极线和数据线；
    在所述基板的非显示区内制作驱动芯片和扇出线模块，所述扇出线模块包括第一走线区和第二走线区，所述第一走线区内设置有电性连接所述驱动芯片与所述数据线的第一讯号线，所述第二走线区内设置有电性连接所述驱动芯片与所述栅极线的第二讯号线以及电性连接所述驱动芯片与所述数据线的所述第一讯号线。
  11. 根据权利要求10所述的显示面板制作方法，其中，制作所述扇出线模块的方法包括以下步骤：
    在所述基板的非显示区内划分出第一走线区和第二走线区；
    在所述第一走线区和所述第二走线区内的所述基板上制作第一金属层；
    对所述第一金属层进行图案化处理，形成所述第一讯号线；
    制作覆盖所述第一讯号线的绝缘层；
    在所述第二走线区内的所述绝缘层上制作第二金属层；
    对所述第二金属层进行图案化处理，形成所述第二讯号线。
  12. 根据权利要求11所述的显示面板制作方法，其中，对所述第一金属层和所述第二金属层进行图案化处理的方法包括以下步骤：
    将欲在所述第一走线区内形成的所述第一讯号线的线宽最小值和线间距最小值输入计算机，同时将欲在所述第二走线区内形成的所述第一讯号线的线宽最小值、所述第二讯号线的线宽最小值、以及相邻所述第一讯号线和所述第二讯号线之间的线间距最小值输入计算机；
    所述计算机计算出所述第一走线区内的所述第一讯号线的位置和线宽，以及所述第二走线区内的所述第一讯号线和所述第二讯号线的位置和线宽；
    根据所述计算机的计算结果，分别对所述第一金属层和所述第二金属层进行图案化处理。
  13. 根据权利要求10所述的显示面板制作方法，其中，所述显示区还设置有多个薄膜晶体管，所述数据线和所述栅极线分别电性连接所述薄膜晶体管的源极和栅极，所述薄膜晶体管的漏极电性连接所述显示单元。
  14. 根据权利要求11所述的显示面板制作方法，其中，所述第一走线区包括第一区域和第二区域，所述第一区域和所述第二区域分别位于所述第二走线区的两侧。
  15. 根据权利要求11所述的显示面板制作方法，其中，制作所述第一金属层和所述第二金属层的方法是物理沉积法或喷镀法。
  16. 根据权利要求11所述的显示面板制作方法，其中，对所述第一金属层进行图案化处理的步骤包括曝光、显影、刻蚀操作；对所述第二金属层进行图案化处理的步骤包括曝光、显影、刻蚀操作。
  17. 根据权利要求10所述的显示面板制作方法，其中，制作形成的所述第一讯号线与所述第二讯号线之间电性绝缘。
  18. 根据权利要求10所述的显示面板制作方法，其中，制作形成的所述第一讯号线和所述第二讯号线的宽度均大于或等于3微米。
  19. 根据权利要求10所述的显示面板制作方法，其中，在所述第一走线区内，相邻两条所述第一讯号线之间的间距大于或等于2.5微米；在所述第二走线区内，所述第二讯号线设置于相邻两条所述第一讯号线之间，所述第一讯号线与所述第二讯号线之间的间距大于或等于2.5微米。
  20. 一种显示面板，其包括显示区和位于所述显示区一侧的非显示区，所述显示区内设置有多条数据线和多条栅极线，所述非显示区内设置有驱动芯片和扇出走线区；
    所述扇出走线区内设置有至少一个扇出线模块，所述扇出线模块包括第一走线区和第二走线区，所述第一走线区内设置有电性连接所述驱动芯片与所述数据线的多条第一讯号线，所述第二走线区内设置有电性连接所述驱动芯片与所述栅极线的多条第二讯号线以及电性连接所述驱动芯片与所述数据线的多条所述第一讯号线，所述第一讯号线与所述第二讯号线之间电性绝缘；
    所述第一讯号线和所述第二讯号线的宽度均大于或等于3微米；
    在所述第一走线区内，相邻两条所述第一讯号线之间的间距大于或等于2.5微米；
    在所述第二走线区内，所述第二讯号线设置于相邻两条所述第一讯号线之间，所述第一讯号线与所述第二讯号线之间的间距大于或等于2.5微米。
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