WO2022047849A1 - 一种基于rtl源码的fpga切割方法及系统 - Google Patents

一种基于rtl源码的fpga切割方法及系统 Download PDF

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WO2022047849A1
WO2022047849A1 PCT/CN2020/116885 CN2020116885W WO2022047849A1 WO 2022047849 A1 WO2022047849 A1 WO 2022047849A1 CN 2020116885 W CN2020116885 W CN 2020116885W WO 2022047849 A1 WO2022047849 A1 WO 2022047849A1
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fpga
source code
resource
target
rtl source
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PCT/CN2020/116885
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French (fr)
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魏鹏远
周立兵
林铠鹏
黄小立
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国微集团(深圳)有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/333—Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • the invention relates to the field of FPGA design, in particular to an FPGA cutting method and system based on RTL source code.
  • the purpose of the present invention is to solve the problems existing in the above-mentioned prior art, and to provide an FPGA cutting method and system based on RTL source code, which can automatically divide a large-scale FPGA design into multiple small FPGAs for compilation and operation, thereby reducing large-scale Compile time for the FPGA.
  • a kind of FPGA cutting method based on RTL source code is provided, and it comprises:
  • Analyze the RTL source code designed by the user generate a resource table corresponding to the RTL source code, and calculate the resource weight occupied by each bottom-level design module in the RTL source code and the connection resource weight between the bottom-level design modules;
  • the amount of resources that can be accommodated by a plurality of target FPGAs for accommodating the RTL source code and the connection resources between the plurality of target FPGAs are digitized to form a target FPGA matrix data structure diagram;
  • the resource corresponding to the RTL source code is cut according to the target FPGA matrix data structure diagram and the resource weight occupied by each bottom-level design module in the RTL source code and the connection resource weight between the bottom-level design modules, and divided into Multiple FPGA resource files.
  • the resource table corresponding to the RTL source code is split into multiple FPGA resource files, which specifically include:
  • the resource table corresponding to the RTL source code is cut into various split combinations in the lowest-level module unit, and each split combination is placed in the multiple target FPGAs, and each split combination is calculated.
  • the resource occupancy ratio of each target FPGA and the IO connection resources between each target FPGA are further calculated.
  • the cutting conditions are adjusted and the cutting is performed again according to the new cutting conditions.
  • the described FPGA cutting method based on RTL source code also includes:
  • the described FPGA cutting method based on RTL source code also includes:
  • a kind of FPGA cutting system based on RTL source code which comprises:
  • the resource analysis module is used to analyze the RTL source code designed by the user, and calculate the resource weight occupied by each bottom-level design module in the RTL source code and the connection resource weight between the bottom-level design modules;
  • the FPGA matrix resource generation module is used to digitize the amount of resources that can be accommodated by a plurality of target FPGAs for accommodating the RTL source code and the connection resources between the plurality of target FPGAs to form a target FPGA matrix data structure diagram;
  • the resource cutting module is used to cut the resources corresponding to the RTL source code according to the target FPGA matrix data structure diagram and the resource weight occupied by each bottom-level design module in the RTL source code and the connection resource weight between the bottom-level design modules , split it into multiple FPGA resource files.
  • the resource cutting module cuts the resource table corresponding to the RTL source code into various splitting combinations according to the restriction conditions set by the user and takes the bottommost module as a unit, and places each splitting combination in the In the multiple target FPGAs, calculate the total value of the occupied resource weight of each of the target FPGAs and the total value of the connection resources between the multiple target FPGAs in each split combination. Under the condition that the total value of the occupied resource weight of each of the target FPGAs can be accommodated, the splitting combination with the lowest total value of connection resources is selected as the splitting result.
  • the described FPGA cutting system based on RTL source code also includes:
  • the resource balance adjustment module is used to calculate the resource occupancy ratio of each target FPGA and the IO connection resources between the FPGAs after the resource cutting module completes the cutting. Adjust the cutting conditions.
  • the described FPGA cutting system based on RTL source code also includes:
  • the data structure is transferred to the project engineering module, which is used to generate multiple FPGA source codes that can be loaded into the multiple target FPGAs according to the split multiple FPGA resource files;
  • a compilation and synthesis module is used to comprehensively compile each FPGA source code that can be loaded into the target FPGA to generate an executable binary file;
  • a download and run module is used to download the binary file generated by the compilation and synthesis module to a corresponding target FPGA for testing.
  • the described FPGA cutting system based on RTL source code also includes:
  • the cutting report generation module is used to generate a FPGA resource occupation report, a connection report between FPGAs, and a timing constraint report after the cutting is completed.
  • the cutting process is placed before compilation and synthesis, and the RTL source code written by the user is cut, and the cutting process is faster; in the user RTL source code design, The modules are more cohesive, the coupling between modules is weaker, and the system performance after cutting is better; after the source code cutting is completed, a user design is divided into multiple projects, which can be compiled synchronously by multiple servers, which greatly speeds up the compilation speed.
  • FIG. 1 is a schematic structural diagram of an application environment of an FPGA cutting method based on RTL source code according to an embodiment of the present invention.
  • FIG. 2 is a schematic flowchart of an FPGA cutting method based on RTL source code according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of an FPGA cutting process based on RTL source code according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of RTL source code resource analysis in an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of an FPGA cutting system based on RTL source code according to an embodiment of the present invention.
  • the present invention is suitable for the user's large-scale or ultra-large-scale chip design, when the user's design cannot be placed in one FPGA and needs to be cut into multiple FPGAs for coordinated operation.
  • the system hardware requirements are as follows:
  • the system hardware consists of multiple FPGAs
  • the available resources of the FPGA are clear.
  • the number of available IOs or BUS bus parameters for each two FPGAs is clear.
  • an FPGA cutting method based on RTL source code is provided, which includes steps S1-S7. Each of them will be described below.
  • Step S1 Parse the RTL source code designed by the user, generate a resource table corresponding to the RTL source code, and calculate the resource weight occupied by each bottom-level design module (module) in the RTL source code and the connection resource weight between the bottom-level design modules.
  • the weight of resources occupied by a module includes the type and quantity of FPGA resources occupied by the module.
  • the weight of connection resources between modules includes the number of connected IOs between modules or the bandwidth of the BUS bus.
  • the analysis of the RTL source code resource designed by the user follows the process of refinement to coarsening:
  • Refinement Perform source code analysis on the RTL source code designed by the user, and convert the FPGA resource type and resource quantity occupied by each line of source code to form a detailed resource list.
  • Coarsening Take the lowest module in the RTL source code as the unit, count the resource quantity weight and resource connection weight in each lowest module, and use the corresponding mathematical structure to represent.
  • the user needs to provide a module configuration file to describe the resources occupied by the module, and describe the third-party black box module as an independent unit in the subsequent processing.
  • Step S2 digitize the amount of resources that can be accommodated by multiple target FPGAs set for accommodating the RTL source code and the connection resources between the multiple target FPGAs to form a target FPGA matrix data structure diagram.
  • Step S3 according to the target FPGA matrix data structure diagram and the RTL source code, the resource weight occupied by each bottom-level design module and the connection resource weight between the bottom-level design modules are cut to the resources corresponding to the RTL source code, and the corresponding resources of the RTL source code are cut.
  • Split into multiple FPGA resource files FPGA1, FPGA2, FPGA3 shown in Figure 3).
  • the cutting process specifically includes: according to the constraints set by the user, cutting the resource table corresponding to the RTL source code into various split combinations with the lowest module as a unit, and placing each split combination in the In the multiple target FPGAs, calculate the total value of the occupied resource weight of each of the target FPGAs and the total value of the connection resources between the multiple target FPGAs in each split combination. Under the condition that the total value of the occupied resource weight of each of the target FPGAs can be accommodated, the splitting combination with the lowest total value of connection resources is selected as the splitting result.
  • Step S4 After the cutting is completed, the resource occupancy ratio of each target FPGA and the IO connection resources between each target FPGA are further calculated. If resource overflow occurs, or the number of IO connection resources is insufficient, the cutting conditions of the RTL source code are carried out. Adjust and re-cut according to the new cutting conditions.
  • Step S5 Generate a FPGA resource occupation report, a connection report between FPGAs, and generate a timing constraint report.
  • Step S6 Generate multiple FPGA source codes that can be loaded into the multiple target FPGAs according to the multiple split FPGA resource files.
  • Step S7 Comprehensively compile each FPGA source code that can be loaded into the target FPGA to generate an executable binary file.
  • Step S8 Download the binary file to the corresponding target FPGA for testing.
  • an FPGA cutting system based on RTL source code which includes a resource analysis module 1, an FPGA matrix resource generation module 2, Resource cutting module 3 , resource balance adjustment module 4 , cutting report generation module 5 , data structure transfer project engineering module 6 , compilation and synthesis module 7 and download and operation module 8 .
  • a resource analysis module 1 an FPGA matrix resource generation module 2
  • Resource cutting module 3 Resource cutting module 3
  • resource balance adjustment module 4 a cutting report generation module 5
  • data structure transfer project engineering module 6 6
  • compilation and synthesis module 7 compilation and synthesis module 7 and download and operation module 8 .
  • the resource analysis module 1 is used to parse the RTL source code designed by the user, and calculate the resource weight occupied by each bottom-level design module in the RTL source code and the connection resource weight between the bottom-level design modules.
  • the FPGA matrix resource generation module 2 is used to digitize the amount of resources that can be accommodated by multiple target FPGAs configured to accommodate the RTL source code and the connection resources between the multiple target FPGAs to form target FPGA matrix data Structure diagram.
  • the resource cutting module 3 is used to correspond to the RTL source code according to the resource weight occupied by each bottom-level design module in the target FPGA matrix data structure diagram and the RTL source code and the connection resource weight between the bottom-level design modules.
  • the resource is cut and split into multiple FPGA resource files.
  • the resource cutting module 3 cuts the resource table corresponding to the RTL source code into various split combinations according to the restriction conditions set by the user and takes the bottommost module as a unit, and places each split combination in the In the multiple target FPGAs, in each split combination, the total value of the occupied resource weight of each of the target FPGAs and the total value of the connection resources between the multiple target FPGAs are calculated. Under the condition that the total value of the occupied resource weight of each target FPGA can be accommodated, the splitting combination with the lowest total value of connection resources is selected as the splitting result.
  • the resource balancing adjustment module 4 is used to calculate the resource occupancy ratio of each target FPGA and the IO connection resources between the FPGAs after the resource cutting module completes the cutting. If resource overflow occurs, or the number of IO connection resources is insufficient, the The cutting conditions of the RTL source code are adjusted.
  • the cutting report generating module 5 is used to generate an FPGA resource occupation report, a connection report between FPGAs, and a timing constraint report after the cutting is completed.
  • the data structure transfer project engineering module 6 is used to generate multiple FPGA source codes that can be loaded into the multiple target FPGAs according to the multiple split FPGA resource files.
  • the compiling and synthesizing module 7 is used for synthesizing and compiling each FPGA source code that can be loaded into the target FPGA to generate an executable binary file.
  • the downloading and running module 8 is used for downloading the binary file generated by the compiling and synthesizing module to the corresponding target FPGA for testing.
  • the cutting process is placed before compilation and synthesis, and the RTL source code written by the user is cut, and the cutting process is faster; in the user RTL source code design, the module is more Cohesion, weaker coupling between modules, and better system performance after cutting; after the source code cutting is completed, a user design is divided into multiple projects, which can be compiled synchronously by multiple servers, greatly speeding up the compilation speed.

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Abstract

一种基于RTL源码的FPGA切割方法及系统，所述方法包括：解析用户设计的RTL源码，生成所述RTL源码对应的资源表，并计算所述RTL源码中每个最底层设计模块占用资源权重及最底层设计模块间的连接资源权重；将设置用于容纳所述RTL源码的多个目标FPGA可容纳的资源量及所述多个目标FPGA之间的连接资源数据化，形成目标FPGA矩阵数据结构图；根据所述目标FPGA矩阵数据结构图和所述RTL源码中每个最底层设计模块占用资源权重及最底层设计模块间的连接资源权重对所述RTL源码对应的资源进行切割，将其拆分成多个FPGA资源文件。采用上述技术方案，可自动将大规模FPGA设计拆分成到多个小规模FPGA中进行编译运行。

Description

一种基于RTL源码的FPGA切割方法及系统 技术领域
本发明涉及FPGA设计领域，尤其涉及一种基于RTL源码的FPGA切割方法及系统。
背景技术
当前，电子技术飞速发展，程序设计规模越来越大，一颗处理器已经难以容下完整的用户设计。这种状况在FPGA开发过程中尤其明显。受限于逻辑资源的规模限制，用户在一颗FPGA中无法实现超大规模的复杂设计，严重制约用户开发工作。
当用户设计在一颗FPGA中放不下时，通常情况下，用户会手动切割设计，将功能分成几个模块，评估资源，放在多个FPGA中，同时根据FPGA之间的IO连线，设计通信协议，来实现整个系统的多FPGA协同工作。手动切割对工程师要求极高，要保证运行时多个FPGA的逻辑配合正确，功能正常，性能达标难度很大，小型工程勉强还可以，对大型工程几乎无法实现。
发明内容
本发明的目的是针对上述现有技术存在的问题，提供一种基于RTL源码的FPGA切割方法及系统，可自动将大规模FPGA设计拆分成到多个小型FPGA中进行编译运行，降低大规模FPGA的编译时间。
本发明实施例中，提供了一种基于RTL源码的FPGA切割方法，其包括：
解析用户设计的RTL源码，生成所述RTL源码对应的资源表，并计算所述RTL源码中每个最底层设计模块占用资源权重及最底层设计模块间的连接资源权重；
将设置用于容纳所述RTL源码的多个目标FPGA可容纳的资源量及所述多个目标FPGA之间的连接资源数据化，形成目标FPGA矩阵数据结构图；
根据所述目标FPGA矩阵数据结构图和所述RTL源码中每个最底层设计模块占用资源权重及最底层设计模块间的连接资源权重对所述RTL源码对应的资源进行切割，将其拆分成多个FPGA资源文件。
本发明实施例中，将所述RTL源码对应的资源表拆分成多个FPGA资源文件，具体包括：
根据用户设置的限制条件以最底层模块为单位将所述RTL源码对应的资源表切割成的各种拆分组合，将每种拆分组合放置在所述多个目标FPGA中，计算每种拆分组合中，每个所述目标FPGA的占用资源权重总值及所述多个目标FPGA之间的连接资源总值，遍历循环结束以后，在满足每个所述目标FPGA的占用资源权重总值能被容纳的情况下，选取连接资源总值最低的拆分组合作为拆分的结果。
本发明实施例中，在切割完成以后，进一步计算各个目标FPGA的资源占用比和各个目标FPGA之间的IO连接资源，若出现资源溢出，或者IO连接资源数量不足，则对所述RTL源码的切割条件进行调整，并根据新的切割条件重新进行切割。
本发明实施例中，所述的基于RTL源码的FPGA切割方法，还包括：
根据拆分后的多个FPGA资源文件生成多个可加载到所述多个目标FPGA中的FPGA源码；
对每个可加载到所述目标FPGA中的FPGA源码进行综合编译，生成可运行的二进制文件；
将所述二进制文件下载到对应的目标FPGA中进行测试。
本发明实施例中，所述的基于RTL源码的FPGA切割方法，还包括：
生成FPGA资源占用报告、FPGA间连接报告及生成时序约束报告。
本发明实施例中，还提供了一种基于RTL源码的FPGA切割系统，其包括：
资源分析模块，用于解析用户设计的RTL源码，计算所述RTL源码中每个最底层设计模块占用资源权重及最底层设计模块间的连接资源权重；
FPGA矩阵资源生成模块，用于将设置用于容纳所述RTL源码的多个目标FPGA可容纳的资源量及所述多个目标FPGA之间的连接资源数据化，形成目标FPGA矩阵数据结构图；
资源切割模块，用于根据所述目标FPGA矩阵数据结构图和所述RTL源码中每个最底层设计模块占用资源权重及最底层设计模块间的连接资源权重对所 述RTL源码对应的资源进行切割，将其拆分成多个FPGA资源文件。
本发明实施例中，所述资源切割模块根据用户设置的限制条件以最底层模块为单位将所述RTL源码对应的资源表切割成的各种拆分组合，将每种拆分组合放置在所述多个目标FPGA中，计算每种拆分组合中，每个所述目标FPGA的占用资源权重总值及所述多个目标FPGA之间的连接资源总值，遍历循环结束以后，在满足每个所述目标FPGA的占用资源权重总值能被容纳的情况下，选取连接资源总值最低的拆分组合作为拆分的结果。
本发明实施例中，所述的基于RTL源码的FPGA切割系统，还包括：
资源均衡调整模块，用于在资源切割模块完成切割以后，计算各个目标FPGA的资源占用比与FPGA之间的IO连接资源，若出现资源溢出，或者IO连接资源数量不足，对所述RTL源码的切割条件进行调整。
本发明实施例中，所述的基于RTL源码的FPGA切割系统，还包括：
数据结构转项目工程模块，用于根据拆分后的多个FPGA资源文件生成多个可加载到所述多个目标FPGA中的FPGA源码；
编译综合模块，用于对每个可加载到所述目标FPGA中的FPGA源码进行综合编译，生成可运行的二进制文件；
下载运行模块，用于将所述编译综合模块生成的二进制文件下载到对应的目标FPGA中进行测试。
本发明实施例中，所述的基于RTL源码的FPGA切割系统，还包括：
切割报告生成模块，用于切割完成以后，生成FPGA资源占用报告、FPGA间连接报告及生成时序约束报告。
与现有技术相比较，采用本发明的基于RTL源码的FPGA切割方法及系统，将切割流程放在编译综合之前，对用户编写的RTL源码进行切割，切割过程更快；用户RTL源码设计中，模块更内聚，模块之间耦合性更弱，切割完成系统性能更好；源码切割完成以后将一个用户设计分割成多个工程，可以多服务器同步进行编译，大大加快编译速度。
附图说明
图1是本发明实施例的基于RTL源码的FPGA切割方法的应用环境的结构示意图。
图2是本发明实施例的基于RTL源码的FPGA切割方法的流程示意图。
图3是本发明实施例的基于RTL源码的FPGA切割过程的示意图。
图4是本发明实施例中RTL源码资源解析的示意图。
图5是本发明实施例的基于RTL源码的FPGA切割系统的结构示意图。
具体实施方式
本发明适用于用户大规模或超大规模的芯片设计，当用户的设计在一个FPGA中放置不下，需要切割到多个FPGA中协同运行的情况。如图1所示，系统硬件要求如下：
1，系统硬件由多个FPGA组成；
2，每个FPGA之间有IO或者总线与其他FPGA进行连接；
3，FPGA可用资源明确。每两个FPGA可用IO数量或者BUS总线参数明确。
下面对本发明实施例的基于RTL源码的FPGA切割方法及系统进行详细说明。
如图1及图2所示，本发明实施例中，提供了一种基于RTL源码的FPGA切割方法，其包括步骤S1-S7。下面分别进行说明。
步骤S1：解析用户设计的RTL源码，生成所述RTL源码对应的资源表，并计算所述RTL源码中每个最底层设计模块(module)占用资源权重及最底层设计模块间的连接资源权重。
需要说明的是，模块占用资源权重包括模块占用的FPGA资源类型以及资源数量。模块间连接资源权重包括模块间的连接IO数量或者BUS总线带宽。
如图3所示，本发明实施例中，用户设计的RTL源码资源解析遵循细化到粗化的过程：
细化：将用户设计RTL源码进行源码解析，将每行源码占用的FPGA资源类型以及资源数量进行转换，形成一个详细的资源列表。
粗化：以RTL源码中的最底层模块为单位，统计每个最底层模块中的资源数量权重以及资源连接权重，并使用相应的数学结构来表示。
对于用户使用的第三方黑盒模块，需要用户提供模块配置文件，来说明模块占用的资源，并在后续处理中将此第三方黑盒模块作为一个独立的单元进行描述。
步骤S2：将设置用于容纳所述RTL源码的多个目标FPGA可容纳的资源量及所述多个目标FPGA之间的连接资源数据化，形成目标FPGA矩阵数据结构图。
需要说明的是，在对所述RTL源码进行切割前，首先需要设置多个目标FPGA来分别容纳切割后的RTL源码。这些目标FPGA可容纳的资源量及这些目标FPTA之间的连接资源量是确定的。在切割之前，需要确保切割后的RTL源码能被这些目标FPGA容纳。因此，需要将多个目标FPGA可容纳的资源量及所述多个目标FPGA之间的连接资源数据化。
步骤S3：根据所述目标FPGA矩阵数据结构图和所述RTL源码中每个最底层设计模块占用资源权重及最底层设计模块间的连接资源权重对所述RTL源码对应的资源进行切割，将其拆分成多个FPGA资源文件(图3中所示的FPGA1、FPGA2、FPGA3)。
需要说明的是，切割的过程具体包括：根据用户设置的限制条件以最底层模块为单位将所述RTL源码对应的资源表切割成的各种拆分组合，将每种拆分组合放置在所述多个目标FPGA中，计算每种拆分组合中，每个所述目标FPGA的占用资源权重总值及所述多个目标FPGA之间的连接资源总值，遍历循环结束以后，在满足每个所述目标FPGA的占用资源权重总值能被容纳的情况下，选取连接资源总值最低的拆分组合作为拆分的结果。
步骤S4：在切割完成以后，进一步计算各个目标FPGA的资源占用比和各个目标FPGA之间的IO连接资源，若出现资源溢出，或者IO连接资源数量不足，则对所述RTL源码的切割条件进行调整，并根据新的切割条件重新进行切割。
需要说明的是，在切割完成以后，还需要对切割后的多个PFGA资源文件 进行验证，检测所述多个目标FPGA是否可以满足所述多个FPGA资源文件的资源要求，若不能满足，则需要用户重新设置切割条件，比如，增加目标FPGA的数量、调整目标FPGA的规格或者调整对所述资源表中的一些模块的切割限制条件。
步骤S5:生成FPGA资源占用报告、FPGA间连接报告及生成时序约束报告。
步骤S6：根据拆分后的多个FPGA资源文件生成多个可加载到所述多个目标FPGA中的FPGA源码。
步骤S7：对每个可加载到所述目标FPGA中的FPGA源码进行综合编译，生成可运行的二进制文件。
步骤S8：将所述二进制文件下载到对应的目标FPGA中进行测试。
如图5所示，相应于上述基于RTL源码的FPGA切割方法，本发明实施例中，还提供了一种基于RTL源码的FPGA切割系统，其包括资源分析模块1、FPGA矩阵资源生成模块2、资源切割模块3、资源均衡调整模块4、切割报告生成模块5、数据结构转项目工程模块6、编译综合模块7及下载运行模块8。下面分别进行说明。
所述资源分析模块1，用于解析用户设计的RTL源码，计算所述RTL源码中每个最底层设计模块占用资源权重及最底层设计模块间的连接资源权重。
所述FPGA矩阵资源生成模块2，用于将设置用于容纳所述RTL源码的多个目标FPGA可容纳的资源量及所述多个目标FPGA之间的连接资源数据化，形成目标FPGA矩阵数据结构图。
所述资源切割模块3，用于根据所述目标FPGA矩阵数据结构图和所述RTL源码中每个最底层设计模块占用资源权重及最底层设计模块间的连接资源权重对所述RTL源码对应的资源进行切割，将其拆分成多个FPGA资源文件。
本发明实施例中，所述资源切割模块3根据用户设置的限制条件以最底层模块为单位将所述RTL源码对应的资源表切割成的各种拆分组合，将每种拆分组合放置在所述多个目标FPGA中，计算每种拆分组合中，每个所述目标FPGA的占用资源权重总值及所述多个目标FPGA之间的连接资源总值，遍历循环结束以后，在满足每个所述目标FPGA的占用资源权重总值能被容纳的情况下， 选取连接资源总值最低的拆分组合作为拆分的结果。
所述资源均衡调整模块4，用于在资源切割模块完成切割以后，计算各个目标FPGA的资源占用比与FPGA之间的IO连接资源，若出现资源溢出，或者IO连接资源数量不足，对所述RTL源码的切割条件进行调整。
所述切割报告生成模块5，用于切割完成以后，生成FPGA资源占用报告、FPGA间连接报告及生成时序约束报告。
所述数据结构转项目工程模块6，用于根据拆分后的多个FPGA资源文件生成多个可加载到所述多个目标FPGA中的FPGA源码。
所述编译综合模块7，用于对每个可加载到所述目标FPGA中的FPGA源码进行综合编译，生成可运行的二进制文件。
所述下载运行模块8，用于将所述编译综合模块生成的二进制文件下载到对应的目标FPGA中进行测试。
综上所述，采用本发明的基于RTL源码的FPGA切割方法及系统，将切割流程放在编译综合之前，对用户编写的RTL源码进行切割，切割过程更快；用户RTL源码设计中，模块更内聚，模块之间耦合性更弱，切割完成系统性能更好；源码切割完成以后将一个用户设计分割成多个工程，可以多服务器同步进行编译，大大加快编译速度。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种基于RTL源码的FPGA切割方法，其特征在于，包括：
    解析用户设计的RTL源码，生成所述RTL源码对应的资源表，并计算所述RTL源码中每个最底层设计模块占用资源权重及最底层设计模块间的连接资源权重；
    将设置用于容纳所述RTL源码的多个目标FPGA可容纳的资源量及所述多个目标FPGA之间的连接资源数据化，形成目标FPGA矩阵数据结构图；
    根据所述目标FPGA矩阵数据结构图和所述RTL源码中每个最底层设计模块占用资源权重及最底层设计模块间的连接资源权重对所述RTL源码对应的资源进行切割，将其拆分成多个FPGA资源文件。
  2. 如权利要求1所述的基于RTL源码的FPGA切割方法，其特征在于，将所述RTL源码对应的资源表拆分成多个FPGA资源文件，具体包括：
    根据用户设置的限制条件以最底层模块为单位将所述RTL源码对应的资源表切割成的各种拆分组合，将每种拆分组合放置在所述多个目标FPGA中，计算每种拆分组合中，每个所述目标FPGA的占用资源权重总值及所述多个目标FPGA之间的连接资源总值，遍历循环结束以后，在满足每个所述目标FPGA的占用资源权重总值能被容纳的情况下，选取连接资源总值最低的拆分组合作为拆分的结果。
  3. 如权利要求1所述的基于RTL源码的FPGA切割方法，其特征在于，在切割完成以后，进一步计算各个目标FPGA的资源占用比和各个目标FPGA之间的IO连接资源，若出现资源溢出，或者IO连接资源数量不足，则对所述RTL源码的切割条件进行调整。
  4. 如权利要求1所述的基于RTL源码的FPGA切割方法，其特征在于，还包括：
    根据拆分后的多个FPGA资源文件生成多个可加载到所述多个目标FPGA中的FPGA源码；
    对每个可加载到所述目标FPGA中的FPGA源码进行综合编译，生成可运行的二进制文件；
    将所述二进制文件下载到对应的目标FPGA中进行测试。
  5. 如权利要求4所述的基于RTL源码的FPGA切割方法，其特征在于，还包括：
    生成FPGA资源占用报告、FPGA间连接报告及生成时序约束报告。
  6. 一种基于RTL源码的FPGA切割系统，其特征在于，包括：
    资源分析模块，用于解析用户设计的RTL源码，计算所述RTL源码中每个最底层设计模块占用资源权重及最底层设计模块间的连接资源权重；
    FPGA矩阵资源生成模块，用于将设置用于容纳所述RTL源码的多个目标FPGA可容纳的资源量及所述多个目标FPGA之间的连接资源数据化，形成目标FPGA矩阵数据结构图；
    资源切割模块，用于根据所述目标FPGA矩阵数据结构图和所述RTL源码中每个最底层设计模块占用资源权重及最底层设计模块间的连接资源权重对所述RTL源码对应的资源进行切割，将其拆分成多个FPGA资源文件。
  7. 如权利要求6所述的基于RTL源码的FPGA切割系统，其特征在于，所述资源切割模块将根据用户设置的限制条件以最底层模块为单位将所述RTL源码对应的资源表切割成的各种拆分组合，将每种拆分组合放置在所述多个目标FPGA中，计算每种拆分组合中，每个所述目标FPGA的占用资源权重总值及所述多个目标FPGA之间的连接资源总值，遍历循环结束以后，在满足每个所述目标FPGA的占用资源权重总值能被容纳的情况下，选取连接资源总值最低的拆分组合作为拆分的结果。
  8. 如权利要求6所述的基于RTL源码的FPGA切割系统，其特征在于，还包括：
    资源均衡调整模块，用于在资源切割模块完成切割以后，计算各个目标FPGA的资源占用比与FPGA之间的IO连接资源，若出现资源溢出，或者IO连接资源数量不足，对所述RTL源码的切割条件进行调整。
  9. 如权利要求6所述的基于RTL源码的FPGA切割系统，其特征在于，还包括：
    数据结构转项目工程模块，用于根据拆分后的多个FPGA资源文件生成多 个可加载到所述多个目标FPGA中的FPGA源码；
    编译综合模块，用于对每个可加载到所述目标FPGA中的FPGA源码进行综合编译，生成可运行的二进制文件；
    下载运行模块，用于将所述编译综合模块生成的二进制文件下载到对应的目标FPGA中进行测试。
  10. 如权利要求9所述的基于RTL源码的FPGA切割系统，其特征在于，还包括：
    切割报告生成模块，用于切割完成以后，生成FPGA资源占用报告、FPGA间连接报告及生成时序约束报告。
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