CN111125975A - 一种fpga时分复用多路数据传输的方法、存储介质及终端 - Google Patents
一种fpga时分复用多路数据传输的方法、存储介质及终端 Download PDFInfo
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111651951A (zh) * | 2020-06-04 | 2020-09-11 | 思尔芯(上海)信息科技有限公司 | 一种fpga端口扩展的方法 |
CN112329368A (zh) * | 2020-10-30 | 2021-02-05 | 盛科网络(苏州)有限公司 | 自动调整分割方案的方法、设备和存储介质 |
CN112329367A (zh) * | 2020-12-02 | 2021-02-05 | 国微集团(深圳)有限公司 | 一种基于图卷积神经网络的逻辑设计切割方法及系统 |
CN112486248A (zh) * | 2020-11-20 | 2021-03-12 | 芯原微电子(上海)股份有限公司 | 基于多fpga互联的收发信号恢复方法、系统以及终端 |
CN112732636A (zh) * | 2021-01-11 | 2021-04-30 | 上海金卓科技有限公司 | 基于多fpga的芯片原型验证系统的配置方法、装置和设备 |
CN113504463A (zh) * | 2021-07-02 | 2021-10-15 | 芯启源(上海)半导体科技有限公司 | 一种fpga原型验证中探针信号复用方法 |
CN117521573A (zh) * | 2023-11-23 | 2024-02-06 | 苏州异格技术有限公司 | 一种fpga芯片的eda前端工具集成设计方法及装置 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5761484A (en) * | 1994-04-01 | 1998-06-02 | Massachusetts Institute Of Technology | Virtual interconnections for reconfigurable logic systems |
US20020152060A1 (en) * | 1998-08-31 | 2002-10-17 | Tseng Ping-Sheng | Inter-chip communication system |
WO2003017099A1 (en) * | 2001-08-14 | 2003-02-27 | Axis Systems, Inc. | Vcd-on-demand system and method |
US7701252B1 (en) * | 2007-11-06 | 2010-04-20 | Altera Corporation | Stacked die network-on-chip for FPGA |
US8225259B1 (en) * | 2004-09-15 | 2012-07-17 | Altera Corporation | Apparatus and methods for time-multiplex field-programmable gate arrays with multiple clocks |
CN106487395A (zh) * | 2016-10-18 | 2017-03-08 | 哈尔滨工业大学 | 基于fpga的多模式解调系统 |
-
2019
- 2019-12-09 CN CN201911247066.XA patent/CN111125975A/zh active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5761484A (en) * | 1994-04-01 | 1998-06-02 | Massachusetts Institute Of Technology | Virtual interconnections for reconfigurable logic systems |
US20020152060A1 (en) * | 1998-08-31 | 2002-10-17 | Tseng Ping-Sheng | Inter-chip communication system |
WO2003017099A1 (en) * | 2001-08-14 | 2003-02-27 | Axis Systems, Inc. | Vcd-on-demand system and method |
US8225259B1 (en) * | 2004-09-15 | 2012-07-17 | Altera Corporation | Apparatus and methods for time-multiplex field-programmable gate arrays with multiple clocks |
US7701252B1 (en) * | 2007-11-06 | 2010-04-20 | Altera Corporation | Stacked die network-on-chip for FPGA |
CN106487395A (zh) * | 2016-10-18 | 2017-03-08 | 哈尔滨工业大学 | 基于fpga的多模式解调系统 |
Non-Patent Citations (3)
Title |
---|
冯伟 等: "动态局部可重构的FFT算法研究与优化", 计算机测量与控制, pages 779 - 784 * |
张倩莉 等: "结合用户约束文件的高效多FPGA系统分割方法", 哈尔滨工业大学学报, pages 144 - 148 * |
程耀林: "FPGA的系统设计方法解析", 现代电子技术, pages 90 - 93 * |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111651951A (zh) * | 2020-06-04 | 2020-09-11 | 思尔芯(上海)信息科技有限公司 | 一种fpga端口扩展的方法 |
CN112329368A (zh) * | 2020-10-30 | 2021-02-05 | 盛科网络(苏州)有限公司 | 自动调整分割方案的方法、设备和存储介质 |
CN112329368B (zh) * | 2020-10-30 | 2024-04-12 | 苏州盛科通信股份有限公司 | 自动调整分割方案的方法、设备和存储介质 |
CN112486248A (zh) * | 2020-11-20 | 2021-03-12 | 芯原微电子(上海)股份有限公司 | 基于多fpga互联的收发信号恢复方法、系统以及终端 |
CN112329367A (zh) * | 2020-12-02 | 2021-02-05 | 国微集团(深圳)有限公司 | 一种基于图卷积神经网络的逻辑设计切割方法及系统 |
CN112732636A (zh) * | 2021-01-11 | 2021-04-30 | 上海金卓科技有限公司 | 基于多fpga的芯片原型验证系统的配置方法、装置和设备 |
CN112732636B (zh) * | 2021-01-11 | 2023-05-30 | 北京东土军悦科技有限公司 | 基于多fpga的芯片原型验证系统的配置方法、装置和设备 |
CN113504463A (zh) * | 2021-07-02 | 2021-10-15 | 芯启源(上海)半导体科技有限公司 | 一种fpga原型验证中探针信号复用方法 |
CN117521573A (zh) * | 2023-11-23 | 2024-02-06 | 苏州异格技术有限公司 | 一种fpga芯片的eda前端工具集成设计方法及装置 |
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