WO2022040859A1 - 互补型存储单元及其制备方法、互补型存储器 - Google Patents

互补型存储单元及其制备方法、互补型存储器 Download PDF

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WO2022040859A1
WO2022040859A1 PCT/CN2020/110791 CN2020110791W WO2022040859A1 WO 2022040859 A1 WO2022040859 A1 WO 2022040859A1 CN 2020110791 W CN2020110791 W CN 2020110791W WO 2022040859 A1 WO2022040859 A1 WO 2022040859A1
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diode
memory cell
pull
complementary memory
control transistor
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PCT/CN2020/110791
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English (en)
French (fr)
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罗庆
陈冰
吕杭炳
刘明
路程
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中国科学院微电子研究所
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Priority to US18/042,574 priority Critical patent/US20230335182A1/en
Priority to PCT/CN2020/110791 priority patent/WO2022040859A1/zh
Publication of WO2022040859A1 publication Critical patent/WO2022040859A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2273—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2275—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/36—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using diodes, e.g. as threshold elements, i.e. diodes assuming a stable ON-stage when driven above their threshold (S- or N-characteristic)
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01728—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals
    • H03K19/01742—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals by means of a pull-up or down element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region

Definitions

  • the present disclosure relates to the technical field of microelectronics, and in particular, to a complementary memory cell, a preparation method thereof, and a complementary memory.
  • multi-level storage architecture In the current mainstream computer architecture, limited by the characteristics and technological development of storage media, multi-level storage architecture is widely used.
  • On-chip cache and DRAM memory have fast read and write speeds, but have small storage capacity and cannot retain data after power failure.
  • the read and write speed of external memory based on hard disk/solid state disk is slow, but the storage capacity is large, and data can be retained after power failure.
  • the above-mentioned multi-level storage architecture causes current computer systems to frequently transfer data between different storage levels, which reduces computing efficiency.
  • the development of high-speed, high-density non-volatile memory can effectively solve the above problems.
  • RRAM Resistive Random Access Memory
  • PCM Phase Change Memory
  • STT-MRAM Spin Transfer Torque- Megnetic Random Access Memory
  • One aspect of the present disclosure provides a complementary memory cell, which includes: a control transistor, a pull-up diode and a pull-down diode, the control transistor is used to control reading and writing of the memory cell; the pull-up diode, one end of which is connected to a positive selection line , the other end is connected to the source end of the control transistor to control the high-level input; the pull-down diode, one end is connected to the negative selection line, and the other end is connected to the source end of the control transistor to control the low-level input; among them, the upper The pull-down diode and the pull-down diode are arranged symmetrically with each other in the first direction.
  • the drain terminal of the control transistor is connected with the bit line, and the gate is connected with the word line.
  • the turn-on directions of the pull-up diode and the pull-down diode point to the source end of the control transistor; when the storage state of the complementary memory cell is 0, the pull-up diode The turn-on direction of the pull-down diode points to the positive select line, and the turn-on direction of the pull-down diode points to the negative select line.
  • the turn-on voltage V DD is applied to the word line, the write voltage V write is applied to the bit line, and the positive selection line and the negative selection line are grounded;
  • the turn-on voltage V DD is applied to the word line, the bit line is grounded, and the write voltage V write is applied to the positive select line and the negative select line.
  • the word line when the complementary memory cell is in the read state, the word line applies the turn-on voltage V DD , the positive selection line applies the input voltage V in , and the negative selection line is grounded, wherein: when the complementary memory cell is in the storage state of When it is 1, the output voltage output by the bit line is high level; when the storage state of the complementary memory cell is 0, the output voltage output by the bit line is low level.
  • control transistor is a MOS transistor; the pull-up diode and the pull-down diode are the same programmable diode.
  • the programmable diode includes: a lower electrode layer, a dielectric layer and an upper electrode layer, the lower electrode layer is used to support the programmable diode and provide a lower electrode of the programmable diode; the dielectric layer is formed on the lower electrode layer , which is used as the functional layer of the programmable diode to maintain a stable state after the electrical signal is removed; the upper electrode layer is formed on the dielectric layer and used to provide the upper electrode of the programmable diode.
  • the lower electrode layer is composed of at least one of W, Al, Ti, Ta, Ni, Hf, TiN and TaN;
  • the dielectric layer is composed of perovskite ferroelectric material, ferroelectric polymer-PVDF At least one of the material and HfO 2 -based ferroelectric material is composed of a material with ferroelectric properties, or is composed of a dielectric material with charged defects;
  • the upper electrode layer is composed of W, Al, Cu, Ru, Ti, Ta, TiN, TaN, It consists of at least one of IrO 2 , ITO and IZO.
  • the HfO 2 -based ferroelectric material is a HfO 2 -based material doped with at least one element of Zr, Al, Si, and La.
  • Another aspect of the present disclosure provides a complementary memory having an array structure composed of a plurality of the above-mentioned complementary memory cells.
  • Another aspect of the present disclosure provides a method for fabricating the above-mentioned complementary memory cell, including: forming a control transistor for controlling reading and writing of the memory cell; forming symmetrically on the control transistor in a first direction Pull-up and pull-down diodes.
  • FIG. 1 is a schematic structural composition diagram of a complementary memory cell according to an embodiment of the present disclosure
  • FIG. 2A is a schematic diagram of an opening direction of a state of storing weight 1 in a complementary memory cell according to an embodiment of the present disclosure
  • FIG. 2B is a schematic diagram of an opening direction of a storage weight 0 state in a complementary memory cell according to an embodiment of the present disclosure
  • 3A is a schematic structural diagram of a programmable diode according to an embodiment of the present disclosure.
  • 3B is a schematic diagram of a technical principle of a programmable diode according to an embodiment of the present disclosure
  • 3C is a schematic diagram of another technical principle of another programmable diode according to an embodiment of the present disclosure.
  • 3D is a graph of current-voltage characteristics of a programmable diode according to an embodiment of the present disclosure
  • FIG. 4 is a schematic flowchart of a method for fabricating a complementary memory cell according to an embodiment of the present disclosure.
  • modules in the device in the embodiment can be adaptively changed and arranged in one or more devices different from the embodiment.
  • the modules or units or components in the embodiments may be combined into one module or unit or component, and furthermore they may be divided into multiple sub-modules or sub-units or sub-assemblies. All features disclosed in this specification (including accompanying claims, abstract and drawings) and any method so disclosed may be employed in any combination unless at least some of such features and/or procedures or elements are mutually exclusive. All processes or units of equipment are combined.
  • Each feature disclosed in this specification may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
  • a unit claim enumerating several means several of these means can be embodied by one and the same item of hardware.
  • the present disclosure provides a complementary memory cell, a preparation method thereof, and a complementary memory.
  • an aspect of the present disclosure provides a complementary memory cell 100 , which includes: a control transistor 101 , a pull-up diode 201 and a pull-down diode 301 , and the control transistor 101 is used to control the complementary memory cell.
  • one end of the pull-up diode 201 is connected to the positive selection line 401, and the other end is connected to the source end of the control transistor 101 for controlling high-level input; one end of the pull-down diode 301 is connected to the negative selection line 501, and the other end is connected to the control
  • the source terminal of the transistor 101 is used to control the low level input; wherein, the pull-up diode 201 and the pull-down diode 301 are arranged symmetrically with each other in the first direction.
  • the drain terminal of the control transistor 101 is connected to the bit line 601 , and the gate is connected to the word line 701 .
  • the complementary memory unit 100 of the present disclosure is formed by controlling the transistor 101 and two diodes arranged symmetrically with each other, so that it can be used as an input unit with a weight of 1 or 0, that is, a weight unit. Based on the design of the above-mentioned complementary memory cells, the current output signal can be converted into a voltage output to increase the noise tolerance, and the problems of power consumption and operation delay caused by complex circuits such as sense amplifiers in the resistive memory can be solved.
  • the turn-on directions of the pull-up diode 201 and the pull-down diode 301 point to the source terminal of the control transistor 101 .
  • the turn-on direction can be understood as the flow direction of the respective currents in the pull-up diode 201 and the pull-down diode 301 , that is, the turn-on direction points to the source end of the control transistor 101 , which means that the current of the pull-up diode 201 flows to the source end of the control transistor 101 . , the current of the pull-down diode 301 also flows to the source terminal of the control transistor 101 .
  • the turn-on direction of the pull-up diode 201 points to the positive selection line 401
  • the turn-on direction of the pull-down diode 301 points to the negative direction Line 501 is selected.
  • the turn-on direction can be understood as the flow direction of the respective currents in the pull-up diode 201 and the pull-down diode 301, that is, the turn-on direction points to the positive selection line 401, which means that the current of the pull-up diode 201 flows to the positive selection line 401; the turn-on direction points to the negative Select line 501, the current of the pull-down diode 301 flows to the negative select line 501 correspondingly.
  • the word line 701 applies the turn-on voltage V DD
  • the bit line 601 applies the write voltage V write
  • the positive select line 401 and the negative select line 501 are grounded.
  • the write state of the complementary memory cell 100 is 0, the turn-on voltage V DD is applied to the word line 701 , the bit line 601 is grounded, and the write voltage V write is applied to the positive selection line 401 and the negative selection line 501 .
  • the word line when the complementary memory cell 100 is in the read state, the word line applies the turn-on voltage V DD , the positive selection line 401 applies the input voltage V in , and the negative The selection line 501 is grounded, wherein: when the storage state of the complementary memory cell 100 is 1, the output voltage output by the bit line 601 is a high level; when the storage state of the complementary memory cell 100 is 0, the output voltage output by the bit line 601 to low level.
  • the weight stored when the complementary storage unit is in the storage state is 1 or 0.
  • the word line 701 is grounded.
  • the control transistor 101 is a MOS transistor, that is, a metal oxide semiconductor (Metal Oxide Semiconductor, or MOS) structure transistor, such as a PMOS transistor or an NMOS transistor; the pull-up diode 201 and the pull-down diode 301 are the same programmable diode.
  • MOS Metal Oxide Semiconductor
  • the programmable diode 300 includes: a lower electrode layer 330 , a dielectric layer 320 and an upper electrode layer 310 , the lower electrode layer 330 is used to support the programmable diode 300 and provide the programmable diode
  • the lower electrode of the diode 300 the dielectric layer 320 is formed on the lower electrode layer 330 and is used as a functional layer of the programmable diode 300 to maintain a stable state after the electrical signal is removed;
  • the upper electrode layer 310 is formed on the dielectric layer 320, with to provide the upper electrode of the programmable diode 300 .
  • the programmable diode when the positive read voltage Vr is applied to the lower electrode layer 330, the programmable diode has at least the following two states:
  • the state with the largest ratio of the absolute value of the forward current to the negative current is the highest positive state
  • the state with the smallest ratio of the absolute value of the forward current to the negative current is the highest negative state.
  • the programmable diode needs to be in different internal states, when a read voltage of a specific absolute value is applied, the ratio of the absolute value of the forward current and the negative current can take multiple values of the highest positive state and the highest negative state. Or a continuously changing value, so that the programmable diode can be in different multiple states or continuously changing states, so as to realize the regulation of the current flow.
  • the forward voltage can be used as the read voltage
  • the forward conduction state can be regarded as a low resistance state
  • the reverse conduction state is a high resistance state, which are used to store 0 and 1.
  • the programmable diode 300 may be a programmable diode having a ferroelectric material, ie, a ferroelectric diode.
  • the lower electrode layer 330 is composed of at least one of W, Al, Ti, Ta, Ni, Hf, TiN and TaN;
  • the dielectric layer 320 is composed of a perovskite type ferroelectric material, a ferroelectric polymer-PVDF material and a HfO 2 based material At least one of the ferroelectric materials is composed of a material with ferroelectric properties, or a dielectric material with charged defects;
  • the upper electrode layer 310 is composed of W, Al, Cu, Ru, Ti, Ta, TiN, TaN, IrO 2 , ITO and at least one of IZO.
  • the ferroelectric thin film of the dielectric layer 320 will form Schottky junctions at the places in contact with the upper electrode and the lower electrode. , the Schottky contact.
  • the polarizing electric field causes directional movement of the electrons.
  • the electrons on the left move to the inside of the ferroelectric film, resulting in the enhancement of the Schottky barrier at the interface; the electrons on the right move toward the interface, reducing the Schottky barrier.
  • the above-mentioned ferroelectric diode since the above-mentioned ferroelectric diode has the power-off retention characteristic realized by ferroelectric inversion (that is, when the ferroelectric diode loses the electrical signal, it still has the characteristic of maintaining a stable state), so that the The operation response speed of the above-mentioned complementary memory reaches the nanosecond level, so as to realize the application of the memory.
  • the programmable diode 300 may also be a diode having a dielectric material with more charging defects. Since the dielectric film in the dielectric layer 320 is prepared by using a dielectric material with many charged defects, a large number of charged defects, such as positively charged oxygen vacancies, may exist in the dielectric layer 320 . Under the action of the electric field, the defects gather to the interface region, which leads to the destruction of the original Schottky contact. As a result, a Schottky contact on one side and an ohmic contact on the other side are formed, thereby forming a unidirectional conduction characteristic of the diode, as shown in FIG. 3C(a). After the reverse voltage is applied to the diode, the defects gather to the other side, and the conduction direction of the diode is reversed, as shown in Fig. 3C(b).
  • the voltage is Vr
  • the absolute value of the current flowing through the diode 300 is greater than the absolute value of the current when the negative reading voltage -Vr of the same magnitude is applied, and the corresponding stable characteristics are maintained after the power is turned off;
  • the diode 300 When the voltage reaches the threshold voltage -V 0 , the diode 300 is negatively polarized, which means that when a positive read voltage Vr is applied to the lower electrode 330, the absolute value of the current flowing through the diode 300 is smaller than that of the negative read voltage of the same magnitude.
  • the programmable diode 300 can maintain good power-off retention characteristics in both positive polarization and negative polarization, as shown in FIG. 3D .
  • the power-off retention characteristic is a property that the programmable diode 300 can still maintain a stable state after the electrical signal is removed.
  • the HfO 2 -based ferroelectric material is a HfO 2 -based material doped with at least one element of Zr, Al, Si, and La, so as to better achieve the above-mentioned power-off retention characteristics.
  • the above-mentioned symmetrical memory cell of the present disclosure has a power-off retention characteristic, and the power-off retention characteristic is determined by its own material characteristics, so that its power consumption is reduced.
  • the symmetric memory unit of the present disclosure can effectively prevent the current of the weight unit from being too large while storing the weight value 1 or 0.
  • Another aspect of the present disclosure provides a complementary memory having an array structure composed of a plurality of the above-mentioned complementary memory cells 100 .
  • the complementary memory of the present disclosure can achieve an operation response speed of nanosecond level, thereby effectively solving the problem of operation delay.
  • the output of the current signal can be converted into the output of the voltage signal, so as to increase the noise tolerance, so that the complementary memory of the present disclosure directly omits the complex reading circuit such as the sense amplifier and saves the memory
  • the area greatly reduces the actual area of the memory and reduces the power consumption of the memory.
  • FIG. 1 and FIG. 4 another aspect of the present disclosure provides a method for fabricating the above-mentioned complementary memory cell 100 , including:
  • control transistor 101 is used to control the reading and writing of the storage unit 100;
  • the preparation process of the control transistor 101 may be performed according to the preparation process of the MOS transistor provided in the prior art, and may specifically involve the preparation process of the PMOS transistor and the NMOS transistor.
  • the programmable upper electrode layer 310 and the lower electrode layer 330 may be processed by one or at least one of electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, and various sputtering processes The two combined processes are used for preparation, and the thickness and shape of the prepared electrodes are various, which are not limited in the present disclosure.
  • the present disclosure takes the doped HfO 2 -based dielectric layer 320 as an example for description.
  • at least one of Zr, Al, Si, La and other elements can be doped with HfO 2 material in the preparation process to obtain the dielectric layer 320 .
  • the doping method may be the atomic layer deposition (ALD) cyclic growth method or the co-sputtered method.
  • the doping concentration of the elements varies from 0.1% to 50%.
  • annealing treatment is performed, the annealing temperature is between 400°C and 1000°C, and the annealing time is between 30s-300s.
  • the lower electrode layer 330 may be formed using an electroless plating process or a sputtering process. Preferably, a sputtering process can be used to form the lower electrode of the TiN material of the programmable diode.
  • the thickness of the lower electrode layer 330 may be between 10 nm and 500 nm.
  • the preparation process of the lower electrode layer 330 may specifically adopt the following process conditions: the sputtering power is 25W-500W; the reaction pressure is 0.1Pa-100Pa; the flow rate of Ar gas is 0.5sccm-100sccm.
  • the dielectric layer 320 is formed by mixing and depositing the two materials at a ratio of 1 : 1.
  • the annealing temperature is between 400°C and 1000°C, and the annealing time is between 30s and 300s.
  • an annealing temperature of 400° C. and an annealing time of 30 s can be used to form the final dielectric layer 320 of Hf 0.5 Zr 0.5 O 2 material.
  • the upper electrode layer 310 Similar to the preparation process of the lower electrode layer 330, as a preferred solution, TiN can be used as a preparation material, and the preparation is performed by a sputtering process.
  • the thickness of the upper electrode layer 310 may be between 10 nm and 500 nm.
  • the specific preparation process conditions of the upper electrode layer 310 are as follows: the sputtering power is 25W-500W; the reaction pressure is 0.1Pa-100Pa; the flow rate of Ar gas is 0.5sccm-100sccm.
  • the programmable diode device of the embodiment of the present disclosure as shown in FIG. 3A can be obtained.
  • FIG. 3D when a bias scanning voltage of 0 to 6V is applied to the programmable diode, the programmable diode exhibits a diode characteristic of forward turn-on; when a bias scanning voltage of 0 to -6V is applied to the programmable diode, Programmable diodes exhibit reverse-turn-on diode characteristics. That is, the programmable diode exhibits a good current flow regulation effect.
  • the complementary memory cell of the present disclosure realizes the adjustment of the current flow direction, so that the complementary memory of the present disclosure has extremely high practicality, scientific research and commercial value.
  • the present disclosure provides a complementary memory cell, a preparation method thereof, and a complementary memory.
  • the complementary storage unit includes: a control transistor, a pull-up diode and a pull-down diode, the control transistor is used to control the reading and writing of the storage unit; the pull-up diode, one end is connected to the positive selection line, and the other end is connected to the source end of the control transistor , used to control the high-level input; the pull-down diode, one end is connected to the negative selection line, and the other end is connected to the source end of the control transistor, used to control the low-level input; wherein, the pull-up diode and the pull-down diode are in the first direction Set symmetrically to each other.
  • the complementary memory of the present disclosure can realize voltage output and various operations of the memory without requiring complex circuits such as sensitive current amplifiers, which greatly reduces the circuit complexity of the memory. It reduces the area size of the memory, improves the storage density of the memory, and also reduces the power consumption of the memory.

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Abstract

一种互补型存储单元及其制备方法、互补型存储器。其中，互补型存储单元（100）包括：控制晶体管（101）、上拉二极管（201）和下拉二极管（301），控制晶体管（101），用于控制互补型存储单元（100）的读写；上拉二极管（201），一端连接于正选择线（401），另一端连接于控制晶体管（101）的源端，用于控制高电平输入；下拉二极管（301），一端连接于负选择线（501），另一端连接于控制晶体管（101）的源端，用于控制低电平输入；其中，上拉二极管（201）与下拉二极管（301）在第一方向上相互对称设置。基于上述互补型存储单元（100）的设计，互补型存储器能够实现原有功能特性的情况下，极大降低了存储器的电路复杂度，减小了存储器的面积尺寸，提高了存储器存储密度，而且还降低了存储器功耗。

Description

互补型存储单元及其制备方法、互补型存储器 技术领域
本公开涉及微电子技术领域，特别涉及一种互补型存储单元及其制备方法、互补型存储器。
背景技术
目前主流的计算机架构中，受限于存储介质的特性与技术发展，多级存储架构被广泛使用。片上缓存和DRAM内存读写速度快，但存储容量小，并且掉电后不能保持数据。基于硬盘/固态盘的外存读写速度慢，但存储容量大，并且掉电后可以保持数据。上述多级存储架构导致目前的计算机系统需要频繁地在不同存储层次间传递数据，降低了计算效率。研发高速、高密度的非易失存储器能够有效的解决上述问题。
为了提高存储密度，人们提出并广泛设计了一系列新型存储器，包括阻变存储器(Resistive Random Access Memory，RRAM)、相变存储器(Phase Change Memory，PCM)和自选转移矩磁性存储器(Spin Transfer Torque-Megnetic Random Access Memory，STT-MRAM)。然而，这些新型存储器器件具有双端结构和电阻式的开关，它们的输入不能与输出分隔开。因此，对它们进行读取操作，必须使用电流灵敏放大器(Current Sensitive Amplifier，CSA)。电流灵敏放大器占据了大量的芯片面积，使得整体的存储密度降低。
发明内容
本公开的一个方面提供了一种互补型存储单元，其中，包括：控制晶体管、上拉二极管和下拉二极管，控制晶体管，用于控制存储单元的读写；上拉二极管，一端连接于正选择线，另一端连接于控制晶体管的源端，用于控制高电平输入；下拉二极管，一端连接于负选择线，另一端连接于控制晶体管的源端，用于控制低电平输入；其中，上拉二极管与下拉二极管在第一方向上相互对称设置。
根据本公开的实施例，控制晶体管的漏端与位线连接，栅极与字线连接。
根据本公开的实施例，当互补型存储单元的存储状态为1时，上拉二极管和下拉二极管的开启方向指向控制晶体管的源端；当互补型存储单元的存储状态为0时，上拉二极管的开启方向指向正选择线，下拉二极管的开启方向指向负选择线。
根据本公开的实施例，当互补型存储单元的写入状态为1时，字线施加开启电压V DD，位线施加写入电压V write，正选择线和负选择线接地；当互补型存储单元的写入状态为0时，字线施加开启电压V DD，位线接地，正选择线和负选择线施加写入电压V write。
根据本公开的实施例，当互补型存储单元处于读取状态时，字线施加开启电压V DD，正选择线施加输入电压V in，负选择线接地，其中：当互补型存储单元存储状态为1时，位线输出的输出电压为高电平；当互补型存储单元存储状态为0时，位线输出的输出电压为低电平。
根据本公开的实施例，当互补型存储单元未被选中时，字线接地；或当互补型存储单元未被选中时，位线施加保护电压V B，V B＝(1/2)V write。
根据本公开的实施例，控制晶体管为MOS管；上拉二极管和下拉二极管为相同的可编程二极管。
根据本公开的实施例，可编程二极管包括：下电极层、介质层和上电极层，下电极层用于支撑可编程二极管，并提供可编程二极管的下电极；介质层形成于下电极层上，用于作为可编程二极管的功能层，以在撤销电信号后保持在稳定状态；上电极层形成于介质层上，用于提供可编程二极管的上电极。
根据本公开的实施例，下电极层由W、Al、Ti、Ta、Ni、Hf、TiN和TaN中的至少一种构成；介质层由钙钛矿型铁电材料、铁电聚合物-PVDF材料以及HfO 2基铁电材料中的至少一种具有铁电特性的材料构成，或由带电缺陷的介质材料构成；上电极层由W、Al、Cu、Ru、Ti、Ta、TiN、TaN、IrO 2、ITO和IZO中的至少一种构成。
根据本公开的实施例，HfO 2基铁电材料为掺杂Zr、Al、Si和La中至少一种元素的HfO 2基材料。
本公开的另一个方面提供了一种互补型存储器，具有多个上述的互补型存储单元组成的阵列结构。
本公开的另一个方面提供了一种上述的互补型存储单元的制备方法，包括：形成控制晶体管，控制晶体管用于控制存储单元的读写；在所述控制晶体管上在第一方向上对称形成上拉二极管和下拉二极管。
附图说明
图1是根据本公开实施例的互补型存储单元的结构组成示意图；
图2A是根据本公开实施例的互补型存储单元中存储权值1状态的开启方向的示意图；
图2B是根据本公开实施例的互补型存储单元中存储权值0状态的开启方向的示意图；
图3A是根据本公开实施例的可编程二极管的结构组成示意图；
图3B是根据本公开实施例的一可编程二极管的一技术原理示意图；
图3C是根据本公开实施例的另一可编程二极管的另一技术原理示意图；
图3D是根据本公开实施例的可编程二极管的电流-电压特性曲线图；
图4是根据本公开实施例的互补型存储单元的制备方法的流程示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本公开进一步详细说明。
需要说明的是，在附图或说明书正文中，未绘示或描述的实现方式，均为所属技术领域中普通技术人员所知的形式，并未进行详细说明。此外，上述对各元件和方法的定义并不仅限于实施例中提到的各种具体结构、形状或方式，本领域普通技术人员可对其进行简单地更改或替换。
还需要说明的是，实施例中提到的方向用语，例如“上”、“下”、“前”、“后”、“左”、“右”等，仅是参考附图的方向，并非用来限制本公开的保护范围。贯穿附图，相同的元素由相同或相近的附图标记来表示。在可能导致对本公开的理解造成混淆时，将省略常规结构或构造。
并且图中各部件的形状和尺寸不反映真实大小和比例，而仅示意本公开实施例的内容。另外，在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。
再者，单词“包含”不排除存在未列在权利要求中的元件或步骤。位 于元件之前的单词“一”或“一个”不排除存在多个这样的元件。
说明书与权利要求中所使用的序数例如“第一”、“第二”、“第三”等的用词，以修饰相应的元件，其本身并不意味着该元件有任何的序数，也不代表某一元件与另一元件的顺序或是制造方法上的顺序，这些序数的使用仅用来使具有某命名的一元件得以和另一具有相同命名的元件能做出清楚区分。
本领域那些技术人员可以理解，可以对实施例中的设备中的模块进行自适应性地改变并且把他们设置在与该实施例不同的一个或多个设备中。可以把实施例中的模块或单元或组件组合成一个模块或单元或组件，以及此外可以把他们分成多个子模块或子单元或子组件。除了这样的特征和/或过程或者单元中的至少一些是相互排斥之外，可以采用任何组合对本说明书(包括伴随的权利要求、摘要和附图)中公开的所有特征以及如此公开的任何方法或者设备的所有过程或单元进行组合。除非另外明确陈述，本说明书(包括伴随的权利要求、摘要和附图)中公开的每个特征可以由提供相同、等同或相似目的的代替特征来代替。并且，在列举了若干装置的单元权利要求中，这些装置中的若干个可以是通过同一个硬件项来具体体现。
类似地，应当理解，为了精简本公开并帮助理解各个公开方面的一个或多个，在上面对本公开的示例性实施例的描述中，本公开的各个特征有时被一起分组到单个实施例、图、或者对其的描述中。然而，并不应将该公开的方法解释成反映如下意图：即所要求保护的本公开要求比在每个权利要求中所明确记载的特征更多的特征。更确切地说，如下面的权利要求书所反映的那样，公开方面在于少于前面公开的单个实施例的所有特征。因此，遵循具体实施方式的权利要求书由此明确地并入该具体实施方式，其中每个权利要求本身都作为本公开的单独实施例。
为解决现有技术中新型存储器器件中需要采用CSA进行读取操作从而占据芯片面积造成存储密度降低的技术问题，本公开提供了一种互补型存储单元及其制备方法、互补型存储器。
如图1所示，本公开的一个方面提供了一种互补型存储单元100，其中，包括：控制晶体管101、上拉二极管201和下拉二极管301，控制晶 体管101用于控制该互补型存储单元的读写；上拉二极管201一端连接于正选择线401，另一端连接于控制晶体管101的源端，用于控制高电平输入；下拉二极管301一端连接于负选择线501，另一端连接于控制晶体管101的源端，用于控制低电平输入；其中，上拉二极管201与下拉二极管301在第一方向上相互对称设置。
根据本公开的实施例，控制晶体管101的漏端与位线601连接，栅极与字线701连接。
因此，通过控制晶体管101和两个相互对称设置的二极管，构成了本公开的互补型存储单元100，使得其可以作为权值1或0的输入单元，也即权值单元。基于上述互补型存储单元的设计，可以使得电流输出信号转化为电压输出，以增大噪声容限，可以解决电阻型存储器中因灵敏放大器等复杂电路造成功耗和操作延时问题。
Figure PCTCN2020110791-appb-000001
表1
如图2A和表1所示，根据本公开的实施例，当互补型存储单元100的存储状态为1时，上拉二极管201和下拉二极管301的开启方向指向控制晶体管101的源端。
其中，开启方向可以理解为该上拉二极管201和下拉二极管301中各自电流的流向，即开启方向指向控制晶体管101的源端，则意味着上拉二极管201的电流流向该控制晶体管101的源端，下拉二极管301的电流也流向该控制晶体管101的源端。
如图2B和表1所示，根据本公开的实施例，当互补型存储单元100的存储状态为0时，上拉二极管201的开启方向指向正选择线401，下拉二极管301的开启方向指向负选择线501。
其中，开启方向可以理解为该上拉二极管201和下拉二极管301中各自电流的流向，即开启方向指向正选择线401，则意味着上拉二极管201的电流流向正选择线401；开启方向指向负选择线501，下拉二极管301的电流对应流向负选择线501。
如图1-图2B和表1所示，根据本公开的实施例，当互补型存储单元100的写入状态为1时，字线701施加开启电压V DD，位线601施加写入电压V write，正选择线401和负选择线501接地。对应地，当互补型存储单元100的写入状态为0时，字线701施加开启电压V DD，位线601接地，正选择线401和负选择线501施加写入电压V write。
如图1-图2B和表1所示，根据本公开的实施例，当互补型存储单元100处于读取状态时，字线施加开启电压V DD，正选择线401施加输入电压V in，负选择线501接地，其中：当互补型存储单元100存储状态为1时，位线601输出的输出电压为高电平；当互补型存储单元100存储状态为0时，位线601输出的输出电压为低电平。
其中，在本公开的实施例中，当互补型存储单元100的存储状态为1或0时，即该互补型存储单元处于该存储状态时存储的权值为1或0。
如图1-图2B和表1所示，根据本公开的实施例，当互补型存储单元100未被选中时，字线701接地。或者，当互补型存储单元100未被选中时，位线601施加保护电压V B，V B＝(1/2)V write。
根据本公开的实施例，控制晶体管101为MOS管，即金属氧化物半 导体(Metal Oxide Semiconductor，即MOS)结构晶体管，例如PMOS管或NMOS管；上拉二极管201和下拉二极管301为相同的可编程二极管。
如图3A所示，根据本公开的实施例，可编程二极管300包括：下电极层330、介质层320和上电极层310，下电极层330用于支撑可编程二极管300，并提供可编程二极管300的下电极；介质层320形成于下电极层330上，用于作为可编程二极管300的功能层，以在撤销电信号后保持在稳定状态；上电极层310形成于介质层320上，用于提供可编程二极管300的上电极。
根据本公开的实施例，在向下电极层330施加正的读取电压Vr时，该可编程二极管至少存在以下两个状态：
状态1：流过二极管的电流绝对值小于施加同样大小的负读取电压-Vr的电流绝对值；
状态2：流过二极管的电流绝对值大于施加同样大小的负读取电压-Vr的电流绝对值。
在向该可编程二极管施加一个特定绝对值的读取电压Vr时，正向电流与负向电流绝对值比值最大的状态为正向最高态，正向电流与负向电流绝对值比值最小的状态为负向最高态。此外，可编程二极管需要在不同的内部状态下，被施加一个特定绝对值的读取电压时，正向电流和负向电流绝对值的比值可取正向最高态和负向最高态的多个值或者连续变化的值，使得该可编程二极管能够处于不同的多个状态或连续变化的状态，以实现对电流流向的调节。此外，当可编程二极管用于电阻型的存储器时，可以以正向电压作为读取电压，正向导通的状态可以视为低阻态，反向导通状态为高阻态，分别用于存储0和1。
根据本公开的实施例，可编程二极管300可以是可编程的具有铁电材料的二极管，即铁电二极管。下电极层330由W、Al、Ti、Ta、Ni、Hf、TiN和TaN中的至少一种构成；介质层320由钙钛矿型铁电材料、铁电聚合物-PVDF材料以及HfO 2基铁电材料中的至少一种具有铁电特性的材料构成，或由带电缺陷的介质材料构成；上电极层310由W、Al、Cu、Ru、Ti、Ta、TiN、TaN、IrO 2、ITO和IZO中的至少一种构成。
如图3B所示，在具有铁电特性的材料构成的介质层320中，该介质 层320的铁电薄膜在极化前，会在与上电极和下电极接触的地方各自形成肖特基结，即肖特基接触。当极化之后，极化电场会导致电子的定向移动。如图3B(a)所示，左侧的电子移动向铁电薄膜内部，导致界面处的肖特基势垒增强；右侧的电子移动向界面处，降低了肖特基势垒。当电子聚集到一定的量就形成了欧姆接触，这样一边是肖特基接触，另一边是欧姆接触，就形成了单向导通的二极管。当电畴翻转，极化电场方向发生变化，电子移动的方向也翻转，导致右侧是肖特基接触，左侧是欧姆接触，二极管导通方向也随即发生翻转，如图3B(b)所示。
在本公开的实施例中，由于上述的铁电二极管具有铁电翻转实现的断电保持特性(即当该铁电二极管在失去电信号时，仍然具有保持稳定状态的特性)，使得本公开的上述互补型存储器的操作响应速度达到纳秒级，以实现内存的应用。
如图3C所示，根据本公开的实施例，可编程二极管300还可以是具有带电缺陷较多的介质材料的二极管。由于介质层320中的介质薄膜采用了带电缺陷较多的介质材料制备，使得介质层320中可以存在大量带电的缺陷，如带正电的氧空位。在电场的作用下缺陷向界面区聚集，导致原本的肖特基接触被破坏。从而形成了一边为肖特基接触，另一边为欧姆接接触的情况，进而形成了二极管的单向导通特性，如图3C(a)所示。在该二极管被施加反向电压后，缺陷向另一侧聚集，该二极管导通方向发生翻转，如图3C(b)所示。
因此，当在下电极330与上电极310间施加一个大于该二极管300的正向阈值电压V 0＝6V的电压时，该二极管300被正向极化，表现为在下电极330上施加正的读取电压Vr时，流过二极管300的电流绝对值大于施加同样大小的负读取电压-Vr的电流绝对值，且断电后保持相应的稳定特性；而在电极101与电极102间施加一个小于负向阈值电压-V 0的电压时，二极管300被负向极化，表现为在下电极330上施加正的读取电压Vr时，流过二极管300的电流绝对值小于施加同样大小的负读取电压-Vr的电流绝对值，且断电后保持相应的特性。可见，可编程二极管300在正向极化时与负向极化时均可以保持良好的断电保持特性，具体如图3D所示。具体地，该断电保持特性为该可编程二极管300被撤销电信号后仍可以保持 稳定状态的性质。
根据本公开的实施例，HfO 2基铁电材料为掺杂Zr、Al、Si和La中至少一种元素的HfO 2基材料，以更好地达到上述的断电保持特性。
基于上述的可编程二极管，使得本公开的上述对称型存储单元具有断电保持特性，且该断电保持特性由于其自身材料特性决定使得其功耗降低，另一方面，通过第一控制晶体管和第二控制晶体管的配合之下，使得本公开的对称型存储单元在存储权值1或0的同时，可以有效防止权值单元的电流过大。
本公开的另一个方面提供了一种互补型存储器，具有多个上述的互补型存储单元100组成的阵列结构。
因此，通过上述的互补型存储单元100，使得本公开的互补型存储器可以达到纳秒级别的操作响应速度，从而有效解决操作延时的问题。而且，借助于该互补型存储单元100，可以实现电流信号输出转换为电压信号输出，以增大噪声容限，使得本公开的互补型存储器直接省去灵敏放大器等复杂的读取电路，节约存储器面积，极大地减小存储器的实际面积，降低存储器功耗。
如图1和图4所示，本公开的另一个方面提供了一种上述的互补型存储单元100的制备方法，包括：
S410：形成控制晶体管101，控制晶体管101用于控制存储单元100的读写；
S420：在所述控制晶体管101上在第一方向上对称形成上拉二极管201和下拉二极管301。
在S410中，对于控制晶体管101的制备过程可以依据现有技术中提供的关于MOS管的制备工艺进行，具体可以涉及PMOS管和NMOS管等制备工艺。
在S420中，对于控制晶体管101上的上拉二极管201和下拉二极管301的制备过程，由于上拉二极管201和下拉二极管301是在第一方向上对称设置，且二者为相同的可编程二极管。因此，可以考虑对上拉二极管201和下拉二极管301的同时制备，当然也可以先制备上拉二极管201，再制备下拉二极管301或者先制备下拉二极管301，再制备上拉二极管201。
在本公开的实施例中，可编程的上电极层310和下电极层330可以通过电子束蒸发、化学气相沉积、脉冲激光沉积、原子层沉积、以及各种溅射工艺中的一种或至少两种的组合工艺进行制备，其制备的电极厚度和形状多样，在本公开中不作限制。
对于介质层320的制备工艺，本公开以掺杂的HfO 2基介质层320为例进行说明。其中，可以将Zr、Al、Si、La等元素中至少之一在制备工艺中掺入HfO 2材料得到该介质层320。掺杂方式可以是原子层沉积(ALD)循环生长的方式，也可以是共溅射的(Co-sputtered)方法。元素的掺杂浓度从0.1％到50％不等。之后进行退火处理，退火温度在400℃～1000℃之间，退火时间在30s-300s之间。
为使得本领域技术人员能够更好的理解，在本公开的实施例中，如图3A所示，以TiN材料的下电极层330、Hf 0.5Zr 0.5O 2材料的介质层320和TiN材料的上电极层310为例，对上拉二极管201和下拉二极管301其中任一二极管的制备过程作详细的说明，具体如下：
S421：形成下电极层330。下电极层330可以采用化学电镀工艺或者溅射工艺形成。作为优选，可以采用溅射工艺形成该可编程二极管的TiN材料的下电极。其中，该下电极层330的厚度可以在10nm～500nm之间。下电极层330的制备工艺具体可以采用以下工艺条件：溅射功率为25W～500W；反应压强为0.1Pa～100Pa；通入Ar气流量为0.5sccm～100sccm。
S422：形成介质层320。在下电极层330上形成掺杂的HfO 2基铁电材料薄膜。作为优选，可以采用原子层沉积工艺循环生长HfO 2和ZrO 2的方式生长Hf 0.5Zr 0.5O 2层作为介质层320，具体可以采用以下工艺条件：制备功率为25W～500W；反应压强为0.1Pa～100Pa；通Ar气流量为60sccm；反应温度为250℃～300℃；介质层生长速率约0.07nm/cycle。其中，生长一个循环的(cycle)HfO 2，紧接着生长一个循环ZrO 2。如此往复，两种材料1 ∶1混合沉积形成该介质层320。
S423：退火。退火温度在400℃～1000℃之间，退火时间在30s～300s之间。作为优选，可以采用400℃退火温度、退火时长30s，以形成最终的Hf 0.5Zr 0.5O 2材料的介质层320。
S424：形成上电极层310。与下电极层330的制备工艺类似，作为优 选方案，可以采用TiN作为制备材料，通过溅射工艺进行制备。其中，该上电极层310的厚度可以在10nm～500nm之间。该上电极层310的具体制备工艺条件如下：溅射功率为25W～500W；反应压强为0.1Pa～100Pa；通入Ar气流量为0.5sccm～100sccm。
基于上述制备方法，可以得到如图3A所示本公开实施例的可编程二极管器件。如图3D所示，当对该可编程二极管外加偏扫描电压0到6V之后，该可编程二极管表现为正向开启的二极管特性；当对该可编程二极管外加偏扫描电压0到-6V之后，可编程二极管表现为反向开启的二极管特性。即该可编程二极管展现了良好的电流流向调节效果。借此，本公开的互补型存储单元实现了电流流向的调节，使得本公开的互补型存储器具有极高的实用性、科研和商业价值。
本公开提供了一种互补型存储单元及其制备方法、互补型存储器。其中，互补型存储单元包括：控制晶体管、上拉二极管和下拉二极管，控制晶体管，用于控制存储单元的读写；上拉二极管，一端连接于正选择线，另一端连接于控制晶体管的源端，用于控制高电平输入；下拉二极管，一端连接于负选择线，另一端连接于控制晶体管的源端，用于控制低电平输入；其中，上拉二极管与下拉二极管在第一方向上相互对称设置。基于上述互补型存储单元的设计，使得本公开的互补型存储器能够在不需要灵敏电流放大器等复杂电路的情况下，即可以实现电压输出和存储器的各种操作，极大地降低了存储器的电路复杂度，减小了存储器的面积尺寸，提高了存储器存储密度，而且还降低了存储器功耗。
至此，已经结合附图对本公开实施例进行了详细描述。
以上所述的具体实施例，对本公开的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本公开的具体实施例而已，并不用于限制本公开，凡在本公开的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (12)

  1. 一种互补型存储单元，其中，包括：
    控制晶体管，用于控制所述存储单元的读写；
    上拉二极管，一端连接于正选择线，另一端连接于所述控制晶体管的源端，用于控制高电平输入；
    下拉二极管，一端连接于负选择线，另一端连接于所述控制晶体管的源端，用于控制低电平输入；
    其中，所述上拉二极管与所述下拉二极管在第一方向上相互对称设置。
  2. 根据权利要求1所述的互补型存储单元，其中，所述控制晶体管的漏端与位线连接，栅极与字线连接。
  3. 根据权利要求2所述的互补型存储单元，其中，
    当所述互补型存储单元的存储状态为1时，所述上拉二极管和下拉二极管的开启方向指向所述控制晶体管的源端；
    当所述互补型存储单元的存储状态为0时，所述上拉二极管的开启方向指向正选择线，所述下拉二极管的开启方向指向负选择线。
  4. 根据权利要求2所述的互补型存储单元，其中，
    当所述互补型存储单元的写入状态为1时，所述字线施加开启电压V DD，所述位线施加写入电压V write，所述正选择线和负选择线接地；
    当所述互补型存储单元的写入状态为0时，所述字线施加开启电压V DD，所述位线接地，所述正选择线和负选择线施加写入电压V write。
  5. 根据权利要求2所述的互补型存储单元，其中，
    当所述互补型存储单元处于读取状态时，字线施加开启电压V DD，正选择线施加输入电压V in，负选择线接地，其中：
    当互补型存储单元存储状态为1时，位线输出的输出电压为高电平；
    当互补型存储单元存储状态为0时，位线输出的输出电压为低电平。
  6. 根据权利要求2所述的互补型存储单元，其中，当所述互补型存储单元未被选中时，
    所述字线接地；或
    所述位线施加保护电压V B，V B＝(1/2)V write。
  7. 根据权利要求1所述的互补型存储单元，其中，
    所述控制晶体管为MOS管；
    所述上拉二极管和所述下拉二极管为相同的可编程二极管。
  8. 根据权利要求7所述的互补型存储单元，其中，所述可编程二极管包括：
    下电极层，用于支撑所述可编程二极管，并提供所述可编程二极管的下电极；
    介质层，形成于所述下电极层上，用于作为所述可编程二极管的功能层，以在撤销电信号后保持在稳定状态；
    上电极层，形成于所述介质层上，用于提供所述可编程二极管的上电极。
  9. 根据权利要求8所述的互补型存储单元，其中，
    所述下电极层由W、Al、Ti、Ta、Ni、Hf、TiN和TaN中的至少一种构成；
    所述介质层由钙钛矿型铁电材料、铁电聚合物-PVDF材料以及HfO 2基铁电材料中的至少一种具有铁电特性的材料构成，或由带电缺陷的介质材料构成；
    所述上电极层由W、Al、Cu、Ru、Ti、Ta、TiN、TaN、IrO 2、ITO和IZO中的至少一种构成。
  10. 根据权利要求9所述的互补型存储单元，其中，所述HfO 2基铁电材料为掺杂Zr、Al、Si和La中至少一种元素的HfO 2基材料。
  11. 一种互补型存储器，具有多个权利要求1-11中任一项所述的互补型存储单元组成的阵列结构。
  12. 一种权利要求1-11中任一项所述的互补型存储单元的制备方法，其中，包括：
    形成控制晶体管，所述控制晶体管用于控制所述存储单元的读写；
    在所述控制晶体管上在第一方向上对称形成上拉二极管和下拉二极管。
PCT/CN2020/110791 2020-08-24 2020-08-24 互补型存储单元及其制备方法、互补型存储器 WO2022040859A1 (zh)

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