WO2022037222A1 - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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Publication number
WO2022037222A1
WO2022037222A1 PCT/CN2021/100700 CN2021100700W WO2022037222A1 WO 2022037222 A1 WO2022037222 A1 WO 2022037222A1 CN 2021100700 W CN2021100700 W CN 2021100700W WO 2022037222 A1 WO2022037222 A1 WO 2022037222A1
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conductive layer
substrate
layer
metal
sidewall
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PCT/CN2021/100700
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English (en)
French (fr)
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刘志拯
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长鑫存储技术有限公司
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Priority to US17/477,758 priority Critical patent/US11864377B2/en
Publication of WO2022037222A1 publication Critical patent/WO2022037222A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068—Formation and after-treatment of conductors

Definitions

  • the embodiments of the present application relate to the field of semiconductors, and in particular, to a semiconductor structure and a fabrication method thereof.
  • Memory is a memory component used to store programs and various data information. According to the use type of memory, it can be divided into read-only memory and random access memory.
  • a memory typically includes a capacitor, which is used to store charge representing the stored information, and a transistor connected to the capacitor, which is a switch that controls the flow of charge into and out of the capacitor. Among them, a source electrode, a drain electrode and a gate electrode are formed in the transistor, and the drain electrode is connected to the bit line.
  • Embodiments of the present application provide a semiconductor structure and a manufacturing method thereof, which are beneficial to improve the signal transmission performance of the semiconductor structure.
  • embodiments of the present application provide a semiconductor structure, including: a substrate and a first conductive layer on the substrate; a second conductive layer, where the second conductive layer is located on the first conductive layer a surface away from the substrate; a third conductive layer, the third conductive layer covering the sidewall of the first conductive layer and in contact with the second conductive layer, the third conductive layer and the second conductive layer
  • the contact resistance of the conductive layer is smaller than the contact resistance of the first conductive layer and the second conductive layer.
  • the top surface of the third conductive layer is in contact with the bottom surface of the second conductive layer. In this way, it is beneficial to reduce the contact resistance between the bottom surface of the second conductive layer and other active regions, so that the current signal flowing through the bottom surface of the second conductive layer has a better transmission effect.
  • the sidewall of the first conductive layer includes a first subsidewall and a second subsidewall extending upward from the bottom of the first conductive layer, and the first subsidewall is located on the second subsidewall Between the bottom of the first conductive layer and the third conductive layer, the second sub-sidewall is covered by the third conductive layer.
  • the ratio of the height of the second sub-sidewall to the height of the first sub-sidewall is 5 ⁇ 10. In this way, it is not only beneficial to ensure that the semiconductor structure has a good signal transmission effect, but also to avoid signal crosstalk between the substrate and the second conductive layer caused by the third conductive layer being too close to the substrate.
  • the first conductive layer is also located between the third conductive layer and the substrate.
  • the top width of the third conductive layer is greater than the bottom width of the third conductive layer.
  • the top width of the first conductive layer is smaller than the bottom width of the first conductive layer.
  • the sidewall surface of the first conductive layer is an arc surface, and in the direction of the second conductive layer facing the substrate, the first conductive layer in the direction parallel to the surface of the substrate The width is incremented.
  • the substrate has an active region, the first conductive layer is in contact with the active region, and the active region includes an N-type doped semiconductor layer.
  • the semiconductor structure further includes: a metal conductive layer and a top dielectric layer, the metal conductive layer is located on the side of the second conductive layer away from the first conductive layer, and the top dielectric layer is located away from the metal conductive layer One side of the substrate; the first conductive layer, the second conductive layer, the third conductive layer, the metal conductive layer, and the top dielectric layer constitute a bit line structure.
  • the material of the first conductive layer includes polysilicon
  • the material of the second conductive layer and the third conductive layer includes a metal compound.
  • the bit line structure is in contact with the active region through polysilicon, which can avoid the junction stress and junction leakage problems of the active region caused by the metal-silicon contact interface.
  • the material of the second conductive layer includes titanium nitride
  • the material of the third conductive layer includes cobalt silicide or titanium silicide.
  • embodiments of the present application further provide a method for fabricating a semiconductor structure, including: providing a substrate and a bit line structure on the substrate, wherein the bit line structure includes a first conductive layer, a second conductive layer and a second conductive layer stacked in sequence.
  • the contact resistance is smaller than the contact resistance between the first conductive layer and the second conductive layer.
  • bit line structure may be formed through a self-aligned double patterning process (SADP) and a self-aligned quadruple patterning process (SAQP).
  • SADP self-aligned double patterning process
  • SAQP self-aligned quadruple patterning process
  • an etching process is performed on the first conductive layer, so that the top width of the first conductive layer in a direction parallel to the surface of the substrate is smaller than the bottom width.
  • the material of the first conductive layer includes polysilicon
  • the material of the second conductive layer and the third conductive layer includes a metal compound
  • the process steps of forming the third conductive layer include: forming a metal layer covering the sidewalls of the first conductive layer; converting the metal layer into a metal silicide layer to form the third conductive layer.
  • the process step of forming the metal silicide layer includes: performing a high temperature process, so that the first conductive layer and the metal layer react to form the metal silicide layer.
  • the process steps of forming a metal layer covering the sidewall of the first conductive layer include: forming a metal film covering the substrate and the exposed surface of the bit line structure; removing the surface of the substrate A metal film is formed to form a metal layer, and the metal layer covers at least part of the sidewall of the first conductive layer, the sidewall of the second conductive layer and the sidewall of the metal conductive layer.
  • the method further includes: removing the unreacted metal layer on the sidewall of the bit line structure.
  • the total contact resistance between the second conductive layer and other active regions is reduced, thereby reducing the contact resistance between the second conductive layer and the lining.
  • the resistance on the current transmission path between the substrates ensures that the current signal flowing from the second conductive layer to the substrate has a better signal transmission effect.
  • FIGS. 1 to 5 are schematic cross-sectional structural diagrams of different semiconductor structures according to embodiments of the present application.
  • 6 to 9 are schematic cross-sectional structural diagrams corresponding to each step of a method for fabricating a semiconductor structure according to an embodiment of the present application.
  • FIG. 10 is a schematic cross-sectional structure diagram corresponding to a step in a method for fabricating a semiconductor structure provided by another embodiment of the present application;
  • FIG. 11 is a schematic cross-sectional structure diagram corresponding to a step in a method for fabricating a semiconductor structure provided by another embodiment of the present application.
  • the semiconductor structure includes: a substrate 10 and a first conductive layer 11 on the substrate 10; a second conductive layer 12, the second conductive layer 12 is located on the surface of the first conductive layer 11 away from the substrate 10; Conductive layer 13, the third conductive layer 13 covers the sidewall of the first conductive layer 11 and is in contact with the second conductive layer 12, the contact resistance between the third conductive layer 13 and the second conductive layer 12 is smaller than that of the first conductive layer 11 and the second conductive layer 12 Contact resistance of layer 12.
  • the substrate 10 has an active region 101, and two sides of the active region 101 also have isolation structures 102. Since the top width of the isolation structure 102 is generally larger than the bottom width in the direction perpendicular to the surface of the substrate 10, Therefore, the top width of the active region 101 between adjacent isolation structures 102 is generally smaller than the bottom width. In order to have a larger contact area between the first conductive layer 11 and the active region 101, the exposed area of the active region 101 can be increased by etching the substrate 10, thereby reducing the size of the first conductive layer 11 and the active region. The contact resistance between 101 improves the current transmission effect.
  • the setting of the third conductive layer 13 is equivalent to connecting a resistor in parallel between the second conductive layer 12 and the substrate 10 , and the parallel connection of the resistors will reduce the conduction between the second conductive layer 12 and the substrate 10
  • the contact resistance between the third conductive layer 13 and the second conductive layer 12 is relatively small
  • the setting of the third conductive layer 13 is equivalent to a parallel resistance
  • the setting of the third conductive layer 13 is conducive to further reducing the total resistance of the conductive path, thereby achieving better performance. Current transfer effect.
  • the top surface of the third conductive layer 13 is in contact with the bottom surface of the second conductive layer 12 , so that the contact resistance in the direction perpendicular to the bottom surface of the second conductive layer 12 is reduced, so that the flow through the bottom surface of the second conductive layer 12
  • the current signal has a better signal transmission effect; in other embodiments, referring to FIG. 2, the third conductive layer 23 is in contact with the sidewall of the second conductive layer 22. Due to the increased contact area, the third conductive layer 23 and the The contact between the sidewalls of the two conductive layers 22 can also play a role in reducing the total resistance of the conductive path.
  • the third conductive layer 13 is partially protruded relative to the second conductive layer 12 ; in other embodiments, referring to FIG. 3 , in the direction perpendicular to the surface of the substrate 30 In the direction, the orthographic projection of the third conductive layer 33 coincides with the orthographic projection boundary of the second conductive layer 32 ; in another embodiment, the orthographic projection of the third conductive layer may also be located within the orthographic projection of the second conductive layer.
  • the sidewall of the first conductive layer 11 includes a first sub-sidewall (not marked) and a second sub-sidewall (not marked) extending upward from the bottom of the first conductive layer 11 , and the first sub-sidewall is located at Between the second sub-sidewall and the bottom of the first conductive layer 11 , the third conductive layer 13 covers the second sub-sidewall.
  • the third conductive layer 13 only covers part of the sidewall of the first conductive layer 11 , which is beneficial to prevent the third conductive layer 13 from contacting the substrate 10 to form a new interface, thereby preventing the formation of a new interface from damaging the first conductive layer 11 and the substrate Signal transfer characteristics between base 10.
  • the ratio of the height of the second sub-sidewall to the height of the first sub-sidewall is 5 ⁇ 10, for example, 6, 8, or 9.
  • the height of the first sub-sidewall is in the range of 2 nm to 10 nm
  • the height of the second sub-side wall is in the range of 10 nm to 50 nm.
  • ratio within this range not only helps to ensure a larger contact area between the third conductive layer 13 and the first conductive layer 11 , so that the third conductive layer 13 has the effect of lowering the total resistance, but also helps Signal crosstalk between the substrate 10 and the third conductive layer 13 due to the third conductive layer 13 being too close to the substrate 10 is avoided, thereby preventing the signal in the substrate 10 from interfering with the signal in the second conductive layer 12 .
  • the first conductive layer 11 is also located between the third conductive layer 13 and the substrate 10 , for the purpose of blocking the third conductive layer 13 and the substrate 10 .
  • the active region 101 includes an N-type doped semiconductor layer.
  • the active region 101 is the drain
  • the first conductive layer 11 is the bit line contact
  • the second conductive layer 12 is the barrier layer
  • the signal in the bit line structure needs to pass through the second conductive layer 12 and the first conductive layer 11 is transferred to the drain for data storage.
  • the material of the active region 101 may be monocrystalline silicon, and the material of the first conductive layer 11 may be polysilicon; in addition, the material of the first conductive layer 11 may be N-type doped polysilicon, and the The ion doping may be heavy doping, which is beneficial to make the first conductive layer 11 have good conductivity.
  • the bit line structure is in contact with the active region through polysilicon, which can avoid the problems of junction stress and junction leakage in the active region caused by the contact interface formed by direct metal-silicon contact.
  • the thickness of the third conductive layer 13 at different positions on the sidewall of the first conductive layer 11 is the same. It should be noted that the expression “equal” does not refer to absolute equality in numerical value. It is limited by the limitation of the technological level. When the difference between the two is within the preset range and does not affect the structural performance, it can be considered that the thickness "" equal”.
  • the top width of the third conductive layer 43 is greater than the bottom width.
  • the width of the third conductive layer 43 is larger , the larger the cross-sectional area of the conductive path between the substrate 40 and the second conductive layer 42, the smaller the resistance of the conductive path.
  • the width of the top of the third conductive layer 43 By controlling the width of the top of the third conductive layer 43 to be greater than the width of the bottom, it is beneficial to make the conductive path have a lower resistance on the side close to the second conductive layer 42 and a higher resistance on the side close to the substrate 40 , and so on. , which is beneficial to ensure that the current signal in the second conductive layer 42 can be transmitted to the substrate 40, and is beneficial to prevent the signal in the substrate 40 from being transmitted to the second conductive layer 42, thereby avoiding the interference of the current signal in the substrate 40.
  • the current signal in the second conductive layer 42 The current signal in the second conductive layer 42 .
  • the top width of the first conductive layer 41 is smaller than the bottom width.
  • part of the third conductive layer 43 can be placed between the first conductive layer 41 and the second conductive layer 42, thereby reducing the protruding degree of the third conductive layer 43 relative to the second conductive layer 42, so that the overall structure occupies a larger area.
  • the small space position is beneficial for reserving more space for other structures located between adjacent bit line structures and reducing the size of the semiconductor structure.
  • the sidewall surface of the first conductive layer 51 is an arc surface, and in the direction of the second conductive layer 52 facing the substrate 50 , the first conductive layer 51 is parallel to the substrate
  • the width in the direction of the surface of the substrate 50 increases; correspondingly, in the direction of the second conductive layer 52 toward the substrate 50 , the width of the third conductive layer 53 in the direction parallel to the surface of the substrate 50 decreases.
  • the semiconductor structure further includes: a metal conductive layer 14 and a top dielectric layer 15 , the metal conductive layer 14 is located on the side of the second conductive layer 12 away from the first conductive layer 11 , and the second conductive layer 12 is used to block the metal conductive layer.
  • the metal in the layer 14 is diffused, the top dielectric layer 15 is located on the side of the metal conductive layer 14 away from the substrate 10 , and the top dielectric layer 15 plays the role of electrical isolation.
  • the first conductive layer 11 , the second conductive layer 12 , the third conductive layer 13 , the metal conductive layer 14 and the top dielectric layer 15 together form a bit line structure, wherein the first conductive layer 11 serves as a bit line contact,
  • the second conductive layer 12 is used as a barrier layer, the metal conductive layer 14 is used as a bit line conductive layer, and the top dielectric layer 15 is used as a bit line protection layer.
  • the material of the first conductive layer 11 is polysilicon
  • the materials of the second conductive layer 12 and the third conductive layer 13 include metal compounds
  • the contact resistance between the second conductive layer 12 and the third conductive layer 13 can be made smaller; in other embodiments, the material of the first conductive layer can also be other conductive materials.
  • the signal in the metal conductive layer 14 needs to be transmitted to the active area through the first conductive layer 11 and the second conductive layer 12 to realize data storage. Due to the reduction of the contact resistance, the read and write performance of the memory can be improved.
  • the contact resistance between the third conductive layer 13 and the first conductive layer 11 is smaller than the contact resistance between the second conductive layer 12 and the first conductive layer 11 . In this way, it is beneficial to further improve the signal transmission effect between the second conductive layer 12 and the substrate 10 .
  • the material of the second conductive layer 12 includes titanium nitride
  • the material of the third conductive layer 13 includes metal silicide
  • the metal silicide includes cobalt silicide or titanium silicide.
  • the total contact resistance between the second conductive layer and other active regions is reduced, thereby reducing the contact resistance between the second conductive layer and the substrate.
  • the resistance on the conductive path between them ensures that the current signal flowing from the second conductive layer to the substrate has a better signal transmission effect.
  • the embodiments of the present application further provide a method for fabricating a semiconductor structure, which can be used for fabricating the above-mentioned semiconductor structure.
  • 6 to 9 are schematic cross-sectional structural diagrams corresponding to each step of a method for fabricating a semiconductor structure according to an embodiment of the present application.
  • a substrate 10 and a first conductive layer 11 and a second conductive layer 12 sequentially stacked on the substrate 10 are provided, and the second conductive layer 12 is located on a surface of the first conductive layer 11 away from the substrate 10 .
  • the semiconductor structure further includes a metal conductive layer 14 located on the surface of the second conductive layer 12 away from the substrate 10, and a top dielectric layer 15 located on the surface of the metal conductive layer 14 away from the substrate 10.
  • the metal conductive layer 14 is used for transmitting bit line signals, which can be It is a metal material such as tungsten, titanium, and tantalum, and the top dielectric layer 15 is used for electrical isolation, and can be metal nitrides such as titanium nitride, tantalum nitride, and tungsten nitride.
  • the first conductive layer 11 , the second conductive layer 12 , the metal conductive layer 14 , the top dielectric layer 15 and the subsequently formed third conductive layer constitute the bit line structure.
  • the substrate 10 has an isolation structure 102 and an active region 101 between adjacent isolation structures 102 , and the first conductive layer 11 is electrically connected to the active region 101 .
  • the first conductive layer 11 may be N-type doped polysilicon, and the active region 101 may be N-type doped monocrystalline silicon.
  • the first conductive layer 11 can be divided into a bottom conductive layer 111 and a top conductive layer 112 according to the difference in the sidewall morphology at different positions of the first conductive layer 11 .
  • the bottom conductive layer 111 is in contact with the active region 101 .
  • the top conductive layer 112 is in contact with the second conductive layer 12 .
  • the orthographic projection of the top conductive layer 112 coincides with the orthographic projection boundary of the second conductive layer 12 or is located within the orthographic projection of the second conductive layer 12, and the orthographic projection of the top conductive layer 112 is located at the bottom within the orthographic projection of the conductive layer 111 .
  • the underlying conductive layer 111 completely covers the exposed surface of the active region 101, thereby blocking the subsequently formed third conductive layer and the active region 101 and avoiding direct contact between the third conductive layer and the active region 101; accordingly, since the bottom conductive layer is conductive
  • the layer 111 can play an isolation role, so the top conductive layer 112 can have a narrower width, thereby reducing the size of the bit line structure and reserving more space for other structures located in the middle of adjacent bit line structures.
  • the reasons for the formation of the bottom conductive layer 111 include: during the etching process, the etching components are reduced and the etching components are concentrated toward the etching center, so that part of the material of the first conductive layer 11 is not etched.
  • a metal film 131 to be etched is formed.
  • the metal film 131 covers the surface of the substrate 10 , the sidewalls of the first conductive layer 11 , the sidewalls of the second conductive layer 12 , the sidewalls of the metal conductive layer 14 , and the sidewalls and the top surface of the top dielectric layer 15 .
  • the metal film 131 can be formed by an atomic layer deposition process, so as to better control the thickness of the metal film 131 located on the sidewall of the first conductive layer 11, so as to control the thickness of the subsequently formed third conductive layer in the direction parallel to the surface of the substrate 10 .
  • the first conductive layer 51 is etched to form arc sidewalls.
  • the first conductive layer 51 In the direction of the second conductive layer 52 facing the substrate 50 , the first conductive layer 51 The width in the direction parallel to the surface of the substrate 50 decreases. In this way, the first conductive layer 51 can accommodate part of the third conductive layer formed subsequently, thereby reducing the width of the bit line structure in the direction parallel to the surface of the substrate 50 and the space volume occupied by the bit line structure.
  • the metal film 131 (refer to FIG. 7) is etched to form a metal layer 132 to be reacted.
  • a dry etching process may be used to remove the metal film 131 on the surface of the substrate 10 to form the metal layer 132 , and the etched metal layer 132 covers at least part of the sidewall of the first conductive layer 11 and the second conductive layer 12 sidewalls and metal conductive layer 14 sidewalls.
  • a dry etching process may be used to remove the metal film 131 on the surface of the substrate 10 to form the metal layer 132 , and the etched metal layer 132 covers at least part of the sidewall of the first conductive layer 11 and the second conductive layer 12 sidewalls and metal conductive layer 14 sidewalls.
  • part of the metal film 131 on the bottom sidewall of the first conductive layer 11 can also be removed to prevent the metal film at this position from reacting with the first conductive layer 11 between the metal layer 132 and the substrate 10 in the subsequent process. Further, the contact between the third conductive layer and the active region 101 caused by the consumption of the first conductive layer 11 is avoided.
  • a high temperature process is performed to convert the metal layer 132 covering the sidewall of the first conductive layer 11 into a metal silicide layer to form the third conductive layer 13 .
  • the material of the metal layer 132 includes cobalt or titanium, and the high temperature process causes the metal layer 132 covering the first conductive layer 11 to react with the silicon atoms in the first conductive layer 11 to form a metal silicide to form a third conductive layer 13;
  • an ion implantation process may be used to implant atoms such as silicon atoms into the metal layer, so as to convert part or all of the metal layer into a third conductive layer.
  • the use of a high temperature process to form the third conductive layer is beneficial to enable the third conductive layer 13 to be in contact with the bottom surface of the second conductive layer 12, and then the third conductive layer 13 is etched so that the surface is perpendicular to the substrate 10. In the direction of the surface, the orthographic projection of the third conductive layer 13 is located within the orthographic projection of the second conductive layer 12 .
  • the unreacted metal layer 132 on the sidewall of the bit line structure is removed to form the structure shown in FIG. 1 .
  • the structure shown in FIG. 5 or FIG. 11 can be finally formed.
  • the difference between FIG. 11 and FIG. In the direction of the two conductive layers 62 toward the substrate 60 , the widths of the third conductive layer 63 at different positions are equal, and in the direction parallel to the surface of the substrate 60 , the third conductive layer 63 has protrusions relative to the second conductive layer 62 If the part is removed, the structure is the same as that shown in FIG. 5 .
  • the total contact resistance between the second conductive layer and other active regions is reduced, thereby reducing the contact resistance between the second conductive layer and the substrate.
  • the resistance on the conductive path between them ensures that the current signal flowing from the second conductive layer to the substrate has a better signal transmission effect.

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Abstract

本申请实施例提供一种半导体结构及其制作方法，半导体结构包括：衬底和位于所述衬底上的第一导电层；第二导电层，所述第二导电层位于所述第一导电层远离所述衬底的表面；第三导电层，所述第三导电层覆盖所述第一导电层的侧壁且与所述第二导电层接触，所述第三导电层与所述第二导电层的接触电阻小于所述第一导电层与所述第二导电层的接触电阻。本申请有利于提高半导体结构的信号传输性能。

Description

半导体结构及其制作方法
相关申请的交叉引用
本申请基于申请号为202010843298.8、申请日为2020年08月20日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请实施例涉及半导体领域，特别涉及一种半导体结构及其制作方法。
背景技术
存储器是用来存储程序和各种数据信息的记忆部件，按存储器的使用类型可分为只读存储器和随机存取存储器。存储器通常包括电容器以及与电容器连接的晶体管，电容器用来存储代表存储信息的电荷，晶体管是控制电容器的电荷流入和释放的开关。其中，晶体管中形成有源极、漏极和栅极，漏极与位线连接。
然而，随着工艺节点的不断缩小，存储器信号传输受阻的问题越来越严重，如何解决这一问题已成为存储器工艺优化的重要方向。
发明内容
本申请实施例提供一种半导体结构及其制作方法，有利于提高半导体结构的信号传输性能。
为解决上述问题，本申请实施例提供一种半导体结构，包括：衬底和位于所述衬底上的第一导电层；第二导电层，所述第二导电层位于所述第一导电层远离所述衬底的表面；第三导电层，所述第三导电层覆盖所述第 一导电层的侧壁且与所述第二导电层接触，所述第三导电层与所述第二导电层的接触电阻小于所述第一导电层与所述第二导电层的接触电阻。
另外，所述第三导电层顶面与所述第二导电层底面接触。如此，有利于减小第二导电层底面与其他有源区的接触电阻，使得流经第二导电层底面的电流信号具有较好的传输效果。
另外，所述第一导电层的侧壁包括自所述第一导电层底部向上延伸的第一子侧壁以及第二子侧壁，所述第一子侧壁位于所述第二子侧壁与所述第一导电层底部之间，所述第三导电层覆盖所述第二子侧壁。
另外，在垂直于所述衬底表面的方向上，所述第二子侧壁的高度与所述第一子侧壁的高度的比值为5～10。如此，既有利于保证半导体结构具有较好的信号传输效果，又有利于避免第三导电层与衬底过近而造成衬底与第二导电层之间的信号串扰。
另外，在垂直于所述衬底表面的方向上，所述第一导电层还位于所述第三导电层和所述衬底之间。
另外，在平行于所述衬底表面的方向上，所述第三导电层的顶部宽度大于所述第三导电层的底部宽度。如此，有利于使得位于衬底与第二导电层之间的有源区在靠近第二导电层的一侧具有较低的电阻，在靠近衬底的一侧具有较高的电阻，从而使得电流信号更倾向于从第二导电层传输至衬底内，而不容易从衬底内传输至第二导电层中，从而避免衬底内的电流信号干扰第二导电层内的电流信号。
另外，在平行于所述衬底表面的方向上，所述第一导电层的顶部宽度小于所述第一导电层的底部宽度。
另外，所述第一导电层的侧壁表面为弧面，在所述第二导电层朝向所述衬底的方向上，所述第一导电层在平行于所述衬底表面的方向上的宽度递增。
另外，所述衬底内具有有源区，所述第一导电层与所述有源区接触， 所述有源区包括N型掺杂半导体层。
另外，半导体结构还包括：金属导电层和顶层介质层，所述金属导电层位于所述第二导电层远离所述第一导电层的一侧，所述顶层介质层位于所述金属导电层远离所述衬底的一侧；所述第一导电层、第二导电层、第三导电层、金属导电层、顶层介质层构成位线结构。
另外，所述第一导电层的材料包括多晶硅，所述第二导电层和第三导电层的材料包括金属化合物。位线结构通过多晶硅与有源区接触，能够避免金属-硅接触界面产生的有源区的结应力(junction stress)和结漏电(junction leakage)问题。
另外，所述第二导电层的材料包括氮化钛，所述第三导电层的材料包括硅化钴或硅化钛。
相应地，本申请实施例还提供一种半导体结构的制作方法，包括：提供衬底和位于所述衬底上的位线结构，所述位线结构包括依次层叠的第一导电层、第二导电层、金属导电层和顶层介质层；形成覆盖所述第一导电层的侧壁且与所述第二导电层接触的第三导电层，所述第三导电层与所述第二导电层的接触电阻小于所述第一导电层与所述第二导电层的接触电阻。
另外，位线结构可以通过自对准双重图案化工艺(SADP)和自对准四重图案化工艺(SAQP)形成。
另外，在形成所述第三导电层之前，对所述第一导电层进行刻蚀工艺，以使所述第一导电层在平行于所述衬底表面方向上的顶部宽度小于底部宽度。
另外，所述第一导电层的材料包括多晶硅，所述第二导电层和第三导电层的材料包括金属化合物。
另外，形成所述第三导电层的工艺步骤包括：形成覆盖所述第一导电层的侧壁的金属层；将所述金属层转换为金属硅化物层，形成所述第三导电层。
另外，形成所述金属硅化物层的工艺步骤包括：进行高温工艺，以使所述第一导电层与所述金属层发生反应，形成所述金属硅化物层。
另外，形成覆盖所述第一导电层的侧壁的金属层的工艺步骤包括：形成金属膜，所述金属膜覆盖所述衬底和所述位线结构暴露的表面；去除所述衬底表面的金属膜以形成金属层，所述金属层至少覆盖所述第一导电层的部分侧壁、所述第二导电层的侧壁以及所述金属导电层的侧壁。
另外，形成所述第三导电层之后还包括：去除所述位线结构的侧壁上未发生反应的金属层。
与现有技术相比，本申请实施例提供的技术方案具有以下优点：
上述技术方案中，通过设置与第二导电层接触电阻较小的第三导电层，减小第二导电层与其他有源区之间的接触总电阻，进而减小位于第二导电层与衬底之间的电流传输路径上的电阻，保证从第二导电层流向衬底的电流信号具有较好的信号传输效果。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1至图5为本申请实施例提供的不同半导体结构的剖面结构示意图；
图6至图9为本申请一实施例提供的半导体结构的制作方法各步骤对应的剖面结构示意图；
图10为本申请另一实施例提供的半导体结构的制作方法中一步骤对应的剖面结构示意图；
图11为本申请另一实施例提供的半导体结构的制作方法中一步骤对应的剖面结构示意图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
参考图1，半导体结构包括：衬底10和位于衬底10上的第一导电层11；第二导电层12，第二导电层12位于第一导电层11远离衬底10的表面；第三导电层13，第三导电层13覆盖第一导电层11侧壁且与第二导电层12接触，第三导电层13与第二导电层12的接触电阻小于第一导电层11与第二导电层12的接触电阻。
本实施例中，衬底10内具有有源区101，有源区101两侧还具有隔离结构102，由于在垂直于衬底10表面的方向上，隔离结构102的顶部宽度通常大于底部宽度，因此位于相邻隔离结构102之间的有源区101的顶部宽度通常小于底部宽度。为使得第一导电层11与有源区101之间具有较大的接触面积，可通过刻蚀衬底10增大有源区101的暴露面积，从而减小第一导电层11与有源区101之间的接触电阻，提高电流传输效果。
本实施例中，第三导电层13的设置相当于在第二导电层12与衬底10之间并联了一电阻，电阻的并联会减小第二导电层12与衬底10之间的导电路径上的总电阻，进而提高电流传输速率与增大电流裕度；此外，第三导电层13与第二导电层12的接触电阻较小，第三导电层13的设置相当于并联了一阻值较小的电阻，由于多个电阻并联后的总阻值小于多个电阻中最小的阻值，因此第三导电层13的设置有利于进一步减小导电路径的总电阻，从而实现更好的电流传输效果。
本实施例中，第三导电层13顶面与第二导电层12底面接触，如此， 有利于减小垂直于第二导电层12底面方向上的接触电阻，使得流经第二导电层12底面的电流信号具有较好的信号传输效果；在其他实施例中，参考图2，第三导电层23与第二导电层22侧壁相接触，由于增大接触面积，第三导电层23与第二导电层22侧壁接触也能够起到减小导电路径总电阻的作用。
本实施例中，在平行于衬底10表面的方向上，第三导电层13相对于第二导电层12部分凸出；在其他实施例中，参考图3，在垂直于衬底30表面的方向上，第三导电层33的正投影与第二导电层32的正投影边界重合；在另一实施例中，第三导电层的正投影还可以位于第二导电层的正投影内。
本实施例中，第一导电层11的侧壁包括自第一导电层11底部向上延伸的第一子侧壁(未标示)以及第二子侧壁(未标示)，第一子侧壁位于第二子侧壁与第一导电层11底部之间，第三导电层13覆盖第二子侧壁。第三导电层13仅覆盖第一导电层11的部分侧壁，有利于避免第三导电层13与衬底10接触而形成新的界面，进而避免新界面的形成破坏第一导电层11与衬底10之间的信号传输特性。
本实施例中，在垂直于衬底10表面的方向上，第二子侧壁的高度与第一子侧壁的高度的比值为5～10，例如为6、8或9。其中，第一子侧壁的高度范围为2nm～10nm，第二子侧壁的高度范围为10nm～50nm。采用该范围内的比值，既有利于保证第三导电层13与第一导电层11之间具有较大的接触面积，使得第三导电层13具有较好地降低总电阻的效果，又有利于避免第三导电层13与衬底10过近而造成衬底10与第三导电层13之间的信号串扰，进而避免衬底10内的信号对第二导电层12内的信号造成干扰。
本实施例中，在垂直于衬底10表面的方向上，第一导电层11还位于第三导电13和衬底10之间，以起到阻隔第三导电层13和衬底10的目的。
本实施例中，有源区101包括N型掺杂半导体层。
本实施例中，有源区101为漏极，第一导电层11为位线接触，第二导 电层12为阻挡层，位线结构内的信号需要通过第二导电层12和第一导电层11传输至漏极中以实现数据的存储。
其中，有源区101的材料可以是单晶硅，第一导电层11的材料可以是多晶硅；此外，第一导电层11的材料可以是N型掺杂的多晶硅，第一导电层11内的离子掺杂可以是重掺杂，如此，有利于使得第一导电层11具有良好的导电性能。位线结构通过多晶硅与有源区接触，能够避免由金属-硅直接接触形成的接触界面产生的有源区的结应力和结漏电问题。
本实施例中，在平行于衬底10表面的方向上，第一导电层11侧壁不同位置处的第三导电层13厚度相等。需要说明的是，“相等”这一表述并非指代数值上的绝对相等，限于工艺水平的限制，两者之间的差值处于预设范围内且不影响结构性能时，即可认为厚度“相等”。
在其他实施例中，参考图4，在平行于衬底40表面的方向上，第三导电层43的顶部宽度大于底部宽度。
由于电流的流动是具有倾向性的，在电流的流动方向上，电流更倾向于往电阻较低的方向流动，而在平行于衬底40表面的方向上，第三导电层43的宽度越大，位于衬底40和第二导电层42之间的导电路径的横截面积越大，导电路径的电阻越小。
通过控制第三导电层43的顶部宽度大于底部宽度，有利于使得导电路径在靠近第二导电层42的一侧具有较低的电阻，在靠近衬底40的一侧具有较高的电阻，如此，有利于保证第二导电层42内的电流信号能够传输至衬底40内，且有利于阻止衬底40内的信号传输至第二导电层42中，从而避免衬底40内的电流信号干扰第二导电层42内的电流信号。
需要说明的是，由于第三导电层43并不与有源区401接触，避免了产生有源区的结应力和结漏电问题。
此外，在平行于衬底40表面的方向上，第一导电层41的顶部宽度小于底部宽度。如此，部分第三导电层43可置于第一导电层41和第二导电 层42之间，从而减小第三导电层43相对于第二导电层42的凸出程度，使得整体结构占据较小的空间位置，有利于为位于相邻位线结构之间的其他结构预留更大的空间以及缩减半导体结构的尺寸。在本申请又一实施例中，参考图5，第一导电层51的侧壁表面为弧面，在第二导电层52朝向衬底50的方向上，第一导电层51在平行于衬底50表面方向上的宽度递增；相应的，在第二导电层52朝向衬底50的方向上，第三导电层53在平行于衬底50表面方向上的宽度递减。
本实施例中，半导体结构还包括：金属导电层14和顶层介质层15，金属导电层14位于第二导电层12远离第一导电层11的一侧，第二导电层12用于阻拦金属导电层14中的金属扩散，顶层介质层15位于金属导电层14远离衬底10的一侧，顶层介质层15起到电隔离的作用。
本实施例中，第一导电层11、第二导电层12、第三导电层13、金属导电层14和顶层介质层15共同构成位线结构，其中，第一导电层11作为位线接触，第二导电层12作为阻挡层，金属导电层14作为位线导电层，顶层介质层15作为位线保护层。
本实施例中，第一导电层11的材料为多晶硅，第二导电层12和第三导电层13的材料包括金属化合物，选用材料类型与第二导电层12的材料类型一致的第三导电层13，能够使得第二导电层12与第三导电层13之间具有较小的接触电阻；在其他实施例中，第一导电层的材料还可以是其他导电材料。金属导电层14内的信号需要通过第一导电层11和第二导电层12传输至有源区中以实现数据的存储，由于接触电阻的减小，可以使得存储器的读写性能得到提升。
此外，第三导电层13与第一导电层11之间的接触电阻小于第二导电层12与第一导电层11之间的接触电阻。如此，有利于进一步提高第二导电层12与衬底10之间的信号传输效果。
具体地，第二导电层12的材料包括氮化钛，第三导电层13的材料包 括金属硅化物，金属硅化物包括硅化钴或硅化钛。
本实施例中，通过设置与第二导电层接触电阻较小的第三导电层，减小第二导电层与其他有源区的接触总电阻，进而减小位于第二导电层与衬底之间的导电路径上的电阻，保证从第二导电层流向衬底的电流信号具有较好的信号传输效果。
相应地，本申请实施例还提供一种半导体结构的制作方法，可用于制作上述半导体结构。
图6至图9为本申请一实施例提供的半导体结构的制作方法各步骤对应的剖面结构示意图。
参考图6，提供衬底10和在衬底10上依次层叠的第一导电层11和第二导电层12，第二导电层12位于第一导电层11远离衬底10的表面。
半导体结构还包括位于第二导电层12远离衬底10表面的金属导电层14，以及位于金属导电层14远离衬底10表面的顶层介质层15，金属导电层14用于传输位线信号，可以是钨、钛、钽等金属材料，顶层介质层15用于起到电隔离的作用，可以是钛氮化物、钽氮化物、钨氮化物等金属氮化物。第一导电层11、第二导电层12、金属导电层14、顶层介质层15以及后续形成的第三导电层构成位线结构。
本实施例中，衬底10内具有隔离结构102和位于相邻隔离结构102之间的有源区101，第一导电层11与有源区101电连接。其中，第一导电层11可以是N型掺杂多晶硅，有源区101可以是N型掺杂单晶硅。
本实施例中，根据第一导电层11不同位置的侧壁形貌差异，可将第一导电层11分为底部导电层111和顶部导电层112，底部导电层111与有源区101接触，顶部导电层112与第二导电层12接触。在垂直于衬底10表面的方向上，顶部导电层112的正投影与第二导电层12的正投影边界重合或者位于第二导电层12的正投影内，顶部导电层112的正投影位于底部导电层111的正投影内。
底层导电层111完全覆盖有源区101被暴露的表面，从而可阻隔后续形成的第三导电层和有源区101，避免第三导电层和有源区101直接接触；相应地，由于底部导电层111可以起到隔离作用，因此顶部导电层112可以具有较窄的宽度，进而实现位线结构的尺寸缩减，为位于相邻位线结构中间的其他结构预留更大的空间。
底部导电层111的形成原因包括：刻蚀过程中刻蚀成分减少和刻蚀成分朝刻蚀中心聚集，从而导致部分第一导电层11的材料未刻蚀。
参考图7，形成待刻蚀的金属膜131。
金属膜131覆盖衬底10表面、第一导电层11侧壁、第二导电层12侧壁、金属导电层14侧壁以及顶层介质层15侧壁和顶面。金属膜131可由原子层沉积工艺形成，以较好地控制位于第一导电层11侧壁的金属膜131的厚度，从而控制后续形成的第三导电层在平行于衬底10表面方向上的厚度。
在其他实施例中，参考图8，在形成金属膜之前对第一导电层51进行刻蚀，形成弧面侧壁，在第二导电层52朝向衬底50的方向上，第一导电层51在平行于衬底50表面方向上的宽度递减。如此，第一导电层51可容纳部分后续形成的第三导电层，进而减小位线结构在平行于衬底50表面方向上的宽度以及位线结构占据的空间体积。
参考图9，刻蚀金属膜131(参考图7)，形成待反应的金属层132。
本实施例中，可采用干法刻蚀工艺去除衬底10表面的金属膜131以形成金属层132，刻蚀后的金属层132至少覆盖第一导电层11的部分侧壁、第二导电层12侧壁以及金属导电层14侧壁。如此，有利于避免刻蚀工艺对第二导电层12和金属导电层14造成损伤，以及避免后续的第三导电层形成工艺对第二导电层12和金属导电层14造成损伤，使得位线信号具有较好的传输效果。
此外，还可以去除第一导电层11底部侧壁的部分金属膜131，避免该 位置的金属膜在后续工艺制程中与位于金属层132和衬底10之间的第一导电层11发生反应，进而避免因第一导电层11被消耗而导致的第三导电层与有源区101相接触。
参考图10，进行高温工艺，将覆盖第一导电层11侧壁的金属层132转换为金属硅化物层，形成第三导电层13。
本实施例中，金属层132的材料包括钴或钛，高温工艺促使覆盖第一导电层11的金属层132与第一导电层11中的硅原子发生反应生成金属硅化物，形成第三导电层13；在其他实施例中，可采用离子注入工艺向金属层注入硅原子等原子，将部分或全部金属层转换为第三导电层。
相对于离子注入工艺，采用高温工艺形成第三导电层，有利于使得第三导电层13能够与第二导电层12底面接触，进而通过刻蚀第三导电层13，使得在垂直于衬底10表面的方向上，第三导电层13的正投影位于第二导电层12的正投影内。
在进行高温工艺之后，去除位线结构的侧壁上未反应的金属层132，即可形成图1所示结构。
在其他实施例中，参考图8，若在形成金属膜之前对第一导电层51进行刻蚀，则最终可形成图5或图11所示结构，图11与图5的区别在于，在第二导电层62朝向衬底60的方向上，第三导电层63在不同位置的宽度相等，在平行于衬底60表面的方向上，第三导电层63具有相对于第二导电层62凸出的部分，若将该部分去除，则与图5所示结构相同。
本实施例中，通过设置与第二导电层接触电阻较小的第三导电层，减小第二导电层与其他有源区的接触总电阻，进而减小位于第二导电层与衬底之间的导电路径上的电阻，保证从第二导电层流向衬底的电流信号具有较好的信号传输效果。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而 不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。

Claims (19)

  1. 一种半导体结构，包括：
    衬底和位于所述衬底上的第一导电层；
    第二导电层，所述第二导电层位于所述第一导电层远离所述衬底的表面；
    第三导电层，所述第三导电层覆盖所述第一导电层的侧壁且与所述第二导电层接触，所述第三导电层与所述第二导电层的接触电阻小于所述第一导电层与所述第二导电层的接触电阻。
  2. 根据权利要求1所述的半导体结构，其中，所述第三导电层顶面与所述第二导电层底面接触。
  3. 根据权利要求1所述的半导体结构，其中，所述第一导电层的侧壁包括自所述第一导电层底部向上延伸的第一子侧壁以及第二子侧壁，所述第一子侧壁位于所述第二子侧壁与所述第一导电层底部之间，所述第三导电层覆盖所述第二子侧壁。
  4. 根据权利要求3所述的半导体结构，其中，在垂直于所述衬底表面的方向上，所述第二子侧壁的高度与所述第一子侧壁的高度的比值为5～10。
  5. 根据权利要求3所述的半导体结构，其中，在垂直于所述衬底表面的方向上，所述第一导电层还位于所述第三导电层和所述衬底之间。
  6. 根据权利要求1所述的半导体结构，其中，在平行于所述衬底表面的方向上，所述第三导电层的顶部宽度大于所述第三导电层的底部宽度。
  7. 根据权利要求6所述的半导体结构，其中，在平行于所述衬底表面的方向上，所述第一导电层的顶部宽度小于所述第一导电层的底部宽度。
  8. 根据权利要求6所述的半导体结构，其中，所述第一导电层的侧壁表面为弧面，在所述第二导电层朝向所述衬底的方向上，所述第一导电层在平行于所述衬底表面的方向上的宽度递增。
  9. 根据权利要求1所述的半导体结构，其中，所述衬底内具有有源区，所述第一导电层与所述有源区接触，所述有源区包括N型掺杂半导体层。
  10. 根据权利要求1所述的半导体结构，其中，还包括：金属导电层和顶层介质层，所述金属导电层位于所述第二导电层远离所述第一导电层的一侧，所述顶层介质层位于金属导电层远离衬底的一侧；所述第一导电层、第二导电层、第三导电层、金属导电层、顶层介质层构成位线结构。
  11. 根据权利要求1或10所述的半导体结构，其中，所述第一导电层的材料包括多晶硅，所述第二导电层和第三导电层的材料包括金属化合物。
  12. 根据权利要求11所述的半导体结构，其中，所述第二导电层的材料包括氮化钛，所述第三导电层的材料包括硅化钴或硅化钛。
  13. 一种半导体结构的制作方法，包括：
    提供衬底和位于所述衬底上的位线结构，所述位线结构包括依次层叠的第一导电层、第二导电层、金属导电层和顶层介质层；
    形成覆盖所述第一导电层的侧壁且与所述第二导电层接触的第三导电层，所述第三导电层与所述第二导电层的接触电阻小于所述第一导电层与所述第二导电层的接触电阻。
  14. 根据权利要求13所述的半导体结构的制作方法，其中，在形成所述第三导电层之前，对所述第一导电层进行刻蚀工艺，以使所述第一导电层在平行于所述衬底表面方向上的顶部宽度小于底部宽度。
  15. 根据权利要求13所述的半导体结构的制作方法，其中，所述第一导电层的材料包括多晶硅，所述第二导电层和第三导电层的材料包括金属化合物。
  16. 根据权利要求13或15所述的半导体结构的制作方法，其中，形成所述第三导电层的工艺步骤包括：形成覆盖所述第一导电层的侧壁的金属层；将所述金属层转换为金属硅化物层，形成所述第三导电层。
  17. 根据权利要求16所述的半导体结构的制作方法，其中，形成所述金属硅化物层的工艺步骤包括：进行高温工艺，以使所述第一导电层与所述金属层发生反应，形成所述金属硅化物层。
  18. 根据权利要求16所述的半导体结构的制作方法，其中，形成覆盖所述第一导电层的侧壁的金属层的工艺步骤包括：形成金属膜，所述金属膜覆盖所述衬底和所述位线结构暴露的表面；去除所述衬底表面的金属膜以形成金属层，所述金属层至少覆盖所述第一导电层的部分侧壁、所述第二导电层的侧壁以及所述金属导电层的侧壁。
  19. 根据权利要求18所述的半导体结构的制作方法，其中，形成所述第三导电层之后还包括：去除所述位线结构的侧壁上未发生反应的金属层。
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