WO2022036547A1 - 功率放大器芯片以及通信设备 - Google Patents

功率放大器芯片以及通信设备 Download PDF

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Publication number
WO2022036547A1
WO2022036547A1 PCT/CN2020/109769 CN2020109769W WO2022036547A1 WO 2022036547 A1 WO2022036547 A1 WO 2022036547A1 CN 2020109769 W CN2020109769 W CN 2020109769W WO 2022036547 A1 WO2022036547 A1 WO 2022036547A1
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Prior art keywords
power amplifier
power
chip
terminal
switch
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PCT/CN2020/109769
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English (en)
French (fr)
Inventor
徐伟
史坡
杨正得
王余峰
邹俊浩
罗青全
上官声长
Original Assignee
华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2020/109769 priority Critical patent/WO2022036547A1/zh
Priority to CN202310810507.2A priority patent/CN117014027B/zh
Priority to CN202080011124.3A priority patent/CN114391180A/zh
Priority to EP20949759.3A priority patent/EP4184575A4/en
Publication of WO2022036547A1 publication Critical patent/WO2022036547A1/zh
Priority to US18/169,516 priority patent/US20230188104A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0211—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
    • H03F1/0216—Continuous control
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    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
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    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
    • H—ELECTRICITY
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    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
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    • H—ELECTRICITY
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    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/005—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W88/00—Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
    • H04W88/02—Terminal devices
    • H04W88/06—Terminal devices adapted for operation in multiple networks or having at least two operational modes, e.g. multi-mode terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6644—Packaging aspects of high-frequency amplifiers
    • H01L2223/6655—Matching arrangements, e.g. arrangement of inductive and capacitive components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6688—Mixed frequency adaptations, i.e. for operation at different frequencies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
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    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/102—A non-specified detector of a signal envelope being used in an amplifying circuit
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    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/111—Indexing scheme relating to amplifiers the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not
    • H—ELECTRICITY
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    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/231—Indexing scheme relating to amplifiers the input of an amplifier can be switched on or off by a switch to amplify or not an input signal
    • H—ELECTRICITY
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Definitions

  • the embodiments of the present application relate to the field of communication, and in particular, to a power amplifier chip and a communication device.
  • Wireless communication technology has undergone long-term evolution and development.
  • terminal equipment in order to improve the information transmission rate, terminal equipment usually supports dual-connection to access 4G network and 5G network at the same time.
  • the base station In the 4G network or 5G network, the base station can use the 4G frequency band or the 5G frequency band respectively for data transmission with the terminal equipment.
  • each set of radio frequency units includes such as power amplifier module and power supply module.
  • the two sets of independent radio frequency units usually occupy a relatively high layout area of the terminal equipment, which is not conducive to the development of the terminal equipment in the direction of small size and high integration.
  • multiple independent radio frequency units will also cause similar problems. Therefore, how to reduce the layout area occupied by the radio frequency unit in the terminal device supporting the dual-connection data transmission mode has become a problem to be solved.
  • the power amplifier chip and the communication device provided by the present application are beneficial to reduce the layout area of the electronic device occupied by the communication device.
  • the present application adopts the following technical solutions.
  • an embodiment of the present application provides a power amplifier chip, including: a packaging case; a plurality of power amplifier bare chips, the plurality of power amplifier bare chips are encapsulated in the packaging case; wherein the plurality of power amplifier bare chips
  • Each of the power amplifier die includes at least one stage of power amplifier.
  • the layout area of the terminal device occupied by the power amplifier can be reduced, which is beneficial to the realization of a highly integrated terminal device.
  • the multiple power amplifier bare chips respectively support different radio frequency frequency bands.
  • the different radio frequency bands may include, but are not limited to: N41 band (2496MHz-2690MHz), B39 band (1880MHz-1920MHz) or B1 band (1920MHz-1980MHz).
  • the power amplifier chip further includes: a first switch, located in the package shell, for connecting the first capacitor to a common ground with the plurality of power amplifiers The connection is or is disconnected between the power terminals of the first power amplifier bare chip in the bare chip.
  • the power amplifier chip further includes a second capacitor and a second switch, which are located in the package; the second switch is used to connect the second capacitor The connection is or is disconnected between the common ground and the power supply terminal of a second power amplifier die of the plurality of power amplifier die.
  • the second power amplifier bare chip may be the first power amplifier bare chip, and in addition, the second power amplifier bare chip may also be a power amplifier bare chip different from the first power amplifier bare chip.
  • the layout area of the terminal device occupied by the communication device can be further reduced.
  • the power amplifier chip further includes: a controller located in the package, the controller is configured to receive from the wireless radio frequency integrated circuit a signal indicating the configuration of the power amplifier indication information, based on the indication information, controlling at least one stage of power amplifiers in at least one power amplifier bare chip of the plurality of power amplifier bare chips to be enabled, and adjusting the gain of the enabled at least one stage of power amplifiers; wherein , the indication information includes at least one of the following: the enabled at least one stage of the power amplifier, the gain of the power amplifier, the power supply mode of the power amplifier, the moment when the power amplifier is controlled to start, the moment when the gain of the power amplifier is adjusted, or the output port of the power amplifier chip.
  • the power amplifier chip further includes: a plurality of switch groups located in the packaging case, and a first switch group of the plurality of switch groups includes a first input terminal and a plurality of output terminals; the output terminal of the third power amplifier bare chip in the plurality of power amplifier bare chips is connected to the first input terminal of at least one first switch group in the plurality of first switch groups, The multiple output terminals of each first switch group in the at least one first switch group are correspondingly connected to at least part of the output ports of the power amplifier chip.
  • the third power amplifier bare chip may be the first power amplifier bare chip or the second power amplifier bare chip.
  • the second switch group in the at least one first switch group includes a second input end; the second input end receives a radio frequency signal from the power amplifier chip
  • the switch in the second switch group connects the radio frequency signal receiving terminal with one of the output terminals in the second switch group based on the control signal.
  • the first power amplifier integrated with the second power amplifier bare chip in the plurality of power amplifier bare chips includes a first gain and a second gain; wherein the The first time period between the moment when the first power amplifier is started and the moment when the first power amplifier starts to transmit signals is greater than the time when the first power amplifier starts to be adjusted from the first gain to the second gain a second time period between the instant and the instant when the first power amplifier begins transmitting a signal using the second gain.
  • an embodiment of the present application provides a communication device, and the communication device may include a power supply device and the power amplifier chip according to the first aspect;
  • the first power amplifier bare chip in the power amplifier chip supplies power;
  • the second power supply device in the power amplifier chip is used for supplying power to the remaining power amplifier bare chips in the power amplifier chip.
  • the communication device further includes: a wireless radio frequency integrated circuit, configured to transmit a radio frequency signal to the power amplifier integrated in at least one of the multiple power amplifier bare chips .
  • the power supply device is further configured to: receive an indication signal from the wireless radio frequency integrated circuit, and based on the indication signal, use the power supply mode indicated by the indication signal to The power amplifier supplies power; the power supply mode includes an average power tracking mode or an envelope tracking mode.
  • the communication device further includes a first capacitor; the first capacitor is connected to the common ground and the first power amplifier bare chip based on the control of the first switch. or disconnect the connection between the power terminals.
  • the wireless radio frequency integrated circuit is further configured to: transmit indication information to the controller in the power amplifier chip.
  • FIG. 1 is a schematic diagram of an application scenario provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a power amplifier chip provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a communication device provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of an internal structure of a power supply device provided by an embodiment of the present application.
  • FIG. 5 is another schematic structural diagram of a power amplifier chip provided by an embodiment of the present application.
  • FIG. 6 is another schematic structural diagram of a communication device provided by an embodiment of the present application.
  • FIG. 7 is another schematic structural diagram of a power supply device provided by an embodiment of the present application.
  • FIG. 8 is another schematic structural diagram of a communication device provided by an embodiment of the present application.
  • FIG. 9 is another schematic structural diagram of a communication device provided by an embodiment of the present application.
  • FIG. 10 is another schematic structural diagram of a communication device provided by an embodiment of the present application.
  • FIG. 11 is a schematic diagram of a frame format delivered by a network device according to an embodiment of the present application.
  • Figure 12 is a timing diagram of the time for adjusting the gain of the power amplifier in the prior art
  • FIG. 13 is a timing chart of the time for adjusting the gain of the power amplifier provided by the embodiment of the present application.
  • the terminal equipment in the embodiments of the present application may also be referred to as: user equipment (user equipment, UE), mobile station (mobile station, MS), mobile terminal (mobile terminal, MT), access terminal, subscriber unit, subscriber station, Mobile station, mobile station, remote station, remote terminal, mobile device, user terminal, terminal, wireless communication device, user agent or user equipment, etc.
  • the terminal device may be a device that provides voice/data connectivity to the user, eg, a handheld device with a wireless connection function, a vehicle-mounted device, and the like.
  • terminals are: mobile phone (mobile phone), tablet computer, notebook computer, PDA, mobile internet device (MID), wearable device, virtual reality (virtual reality, VR) device, augmented reality (augmented reality, AR) equipment, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, and smart grids wireless terminal in transportation safety, wireless terminal in smart city, wireless terminal in smart home, cellular phone, cordless phone, session initiation protocol , SIP) telephones, wireless local loop (WLL) stations, personal digital assistants (PDAs), handheld devices with wireless communication capabilities, computing devices or other processing devices connected to wireless modems, automotive Devices, wearable devices, terminal devices in the future 5G network, or terminal devices in the future evolved public land mobile network (public land mobile network, PLMN), etc., are not limited in this embodiment of the present application.
  • the network device in this embodiment of the present application may be a device used to communicate with a terminal device, and the network device may also be referred to as an access network device or a radio access network device, and may be an evolved NodeB (evolved NodeB) in the LTE system.
  • the network device may also be referred to as an access network device or a radio access network device, and may be an evolved NodeB (evolved NodeB) in the LTE system.
  • evolved NodeB evolved NodeB
  • the eNB or eNodeB can also be a wireless controller in a cloud radio access network (CRAN) scenario, or the access device can be a relay station, an access point, an in-vehicle device, a wearable device, and future 5G
  • the access device in the network or the access device in the future evolved PLMN network, etc. can be an access point (access point, AP) in a WLAN, or a gNB native in a new wireless system (new radio, NR) system.
  • the application examples are not limited.
  • the network device may also be a device in a RAN (Radio Access Network, radio access network), or in other words, a RAN node that accesses the terminal device to the wireless network.
  • RAN Radio Access Network, radio access network
  • gNB transmission reception point
  • TRP transmission reception point
  • eNB evolved Node B
  • RNC radio network controller
  • Node B Node B
  • BSC base station controller
  • base transceiver station base transceiver station
  • BTS home base station
  • home base station for example, home evolved NodeB, or home Node B, HNB
  • Baseband unit base band unit, BBU
  • wireless fidelity wireless fidelity, Wifi
  • FIG. 1 shows a schematic diagram of a scenario applied to an embodiment of the present application.
  • a terminal device a network device A1 and a network device A2 are included.
  • the terminal device can access the network device A1 and the network device A2 at the same time, and this access mode is called dual-connectivity (DC).
  • DC dual-connectivity
  • the one responsible for exchanging radio resource control messages with the terminal device and the one responsible for interacting with the core network control plane entity may be called the primary network device, and the other network device is the secondary network device.
  • Network equipment Similarly, a terminal device can also have communication connections with multiple network devices at the same time and can send and receive data, which can be called multi-connectivity (MC).
  • MC multi-connectivity
  • one network device can be responsible for communicating with The terminal device exchanges radio resource control messages and is responsible for interacting with the core network control plane entity. Then, the network device may be referred to as a primary network device, and the rest of the network devices may be referred to as secondary network devices. In the following embodiments of the present application, dual connections are used as an example for detailed description.
  • the network device A1 and the network device A2 may be network devices of the same wireless access type.
  • the network device A1 and the network device A2 may be network devices of the LTE system, or may be network devices of the NR system.
  • the network device A1 and the network device A2 may also be network devices of different wireless access types.
  • the network device A1 may be a network device of the LTE system
  • the network device A2 may be a network device of the NR system.
  • both the network device A1 and the network device A2 can be used as the main network device.
  • the network device A1 and the network device A2 can respectively serve the terminal device with different radio frequency bands.
  • a communication device may be provided in the terminal device, and the terminal device may send data to the network device A1 and the network device A2 through the communication device, or receive data from the network device A1 and the network device A2 through the communication device.
  • the communication equipment usually includes a power amplifier (Power Amplifier, PA), a power supply device for providing power to the power amplifier, and an RFIC (Radio Frequency Integrated Circuit, radio frequency integrated circuit) for providing radio frequency signals to the PA, etc. Including modems and antennas, etc.
  • two or more sets of power amplifiers need to be set up for multi-channel data transmission; for example, when dual connection is used, two sets of power amplifiers are set so that the terminal device can The network equipment A1 and the network equipment A2 perform data transmission; when three connections are adopted, three sets of power amplifiers are set to enable the terminal equipment to perform data transmission with the corresponding network equipment.
  • the communication equipment in order to improve the working performance of the power amplifier corresponding to each connection channel in the communication device, it is usually necessary to set up multiple independent power modules to supply power independently for each set of power amplifiers. As a result, the communication equipment usually occupies too much layout area in the terminal equipment. It is not conducive to the realization of highly integrated terminal equipment.
  • the following describes the structure of the communication device in the terminal device in detail through the embodiments shown in FIG. 2 to FIG. 8 to solve the technical problem of reducing the layout area.
  • the communication device may include one or more power amplifier chips. At least two power amplifiers may be integrated into each power amplifier chip. That is to say, one power amplifier chip may integrate two power amplifiers, three power amplifiers, or four power amplifiers, etc., which is not limited in this embodiment of the present application. Taking a power amplifier chip including two power amplifiers as an example, the internal structure of the power amplifier chip will be described in detail with reference to FIG. 2 .
  • the power amplifier chip 11 may include a PA1 bare chip and a PA2 bare chip.
  • a bare chip may also be called a Die, that is, an integrated circuit formed on a semiconductor by processes such as growth, doping, etching, or development, and the integrated circuit has the function of power amplification.
  • the PA1 bare chip and the PA2 bare chip may be disposed together in the packaging material by a process such as pasting or sintering, and the packaging material is used to form a packaging shell.
  • the terminals of the PA1 bare chip and the PA2 bare chip are connected to the pins of the package shell and used for connecting with external devices through jumper wires or buried wires, so as to realize the PA1 bare chip and the PA2 bare chip and the external devices. or signal exchange between devices.
  • the packaging case is used to package internal devices, for example, it can be implemented by using a standard packaging process.
  • the packaged internal devices include, but are not limited to, multiple bare chips as described above, and other necessary devices, such as switches, switch groups, capacitors, or controllers mentioned in the following embodiments, for details, please refer to the introduction in the following embodiments. .
  • the power amplifiers PA1 integrated in the PA1 bare chip and the power amplifier PA2 integrated in the PA2 bare chip can be used to support power amplification of signals in different frequency bands.
  • PA1 can support power amplification of N41 frequency band (2496MHz-2690MHz);
  • PA2 can support power amplification of B39 frequency band (1880MHz-1920MHz), B3 frequency band (1710MHz-1785MHz) or B1 frequency band (1920MHz-1980MHz).
  • the power amplifier chip 11 includes a plurality of pins, which are: the signal input terminal N1 of PA1, the signal input terminal N2 of PA2, the power supply terminal V1 of PA1, and the power supply terminal of PA2 V2, the common ground terminal G of PA1 and PA2, the output port Po1 of PA1 and the output port Po2 of PA2.
  • the plurality of pins are respectively connected to external devices or devices such as power supply equipment, RFIC, or antenna equipment, so as to realize the power amplification of the multi-channel uplink communication signal as shown in FIG. 1 .
  • the layout area of the terminal equipment occupied by the power amplifier can be reduced, which is beneficial to the realization of highly integrated terminal equipment.
  • an embodiment of the present application provides a communication device 100 as shown in FIG. 3 , where the communication device 100 includes an RFIC, a power supply device 12 and a power amplifier chip 11 .
  • the power supply device 12 may include two output terminals and a common ground terminal, one of which is connected to the power supply terminal V1 of the power amplifier chip for supplying power to the PA1 in the power amplifier chip 11; the other output terminal is connected to the power supply terminal V1 of the power amplifier chip 11.
  • the power supply terminal V2 of the amplifier chip 11 is connected to supply power to the power amplifier PA2 in the power amplifier chip, and the common ground terminal is connected to the common ground terminal G of the power amplifier chip 11 .
  • the power supply device 12 may include a first power supply chip 121 and a second power supply chip 122 , as shown in FIG. 4 .
  • the first power chip 121 and the second power chip 122 may be independent bare chips, which are packaged in the power supply device 12 .
  • the first power chip 121 supplies power to PA1, and the second power chip 122 supplies power to PA2.
  • the first RF signal output terminal F1 of the RFIC is connected to the signal input terminal N1 of the power amplifier chip 11
  • the second RF signal output terminal F2 of the RFIC is connected to the signal input terminal N2 of the power amplifier chip 11 .
  • the first radio frequency signal output end F1 and the second radio frequency signal output end F2 of the RFIC are respectively used to provide a signal of the first frequency band and a signal of the second frequency band.
  • the signal of the first frequency band may be the signal of the above-mentioned N41 frequency band
  • the signal of the second frequency band may be the signal of the above-mentioned B39 frequency band, the above-mentioned B1 frequency band, or the above-mentioned B3 frequency band.
  • each power amplifier bare chip may further integrate multiple cascaded PAs.
  • the multiple cascaded PAs may be integrated in the same bare chip by processes such as growth, ion doping, etching, and development on the same silicon substrate.
  • the PA used to receive the signal input by the external device is called the previous stage PA
  • the PA used to output the signal to the external device is called the latter stage PA.
  • one or more intermediate-level PAs may also be set between the previous-level PA and the subsequent-level PA. Each level of PA needs power supply when working.
  • the power supply voltage of the former stage PA can be a DC constant voltage; the latter stage PA can support multiple power supply modes.
  • the multiple power supply modes may, for example, include but are not limited to: APT (Average Power Tracker, average power tracking) mode and ET (Envelope Tracker, envelope tracking) mode.
  • the power supply mode of the intermediate-level PA can be selected from DC constant voltage mode, APT mode or ET mode according to the needs of the scene.
  • APT mode in order to improve the linearity of the large-bandwidth download wave, a capacitor is also set between the power supply terminal of the power amplifier and the common ground; while in the ET mode, due to the rapid change of the power supply voltage, the capacitor will affect the envelope tracking. In this case, the capacitor does not need to be set in the ET mode.
  • the power amplifier chip will be described in detail with reference to FIG. 5 , taking the example that each power amplifier bare chip integrates two-stage cascaded PAs.
  • the power amplifier chip 11 includes two PA bare chips, namely the PA1 bare chip and the PA2 bare chip, wherein the PA1 bare chip integrates two cascaded PAs, and the PA2 bare chip also integrates two stages Associated PA.
  • the pins of the power amplifier chip 11 include: a first power supply terminal V1, a second power supply terminal V2, a third power supply terminal V3, a fourth power supply terminal V4, and a signal input terminal N1 , signal input terminal N2, output port Po1, output port Po2 and common ground terminal G.
  • the signal input terminal N1 is used to provide the first frequency band signal input by the RFIC to the previous stage PA in the PA1; the output port Po1 is used to provide the signal output by the latter stage PA in the PA1 to the antenna; the signal input terminal N2 is used for The second frequency band signal input by the RFIC is provided to the previous stage PA in the PA2; the output port Po2 is used to provide the signal output by the latter stage PA in the PA2 to the antenna.
  • the first power supply terminal V1 is used to provide the externally input DC constant voltage to the previous stage PA in the PA1; the second power supply terminal V2 is used to provide the externally inputted PAT mode voltage or ET mode voltage to the latter stage in the PA1.
  • the third power supply terminal V3 is used to provide the externally input DC constant voltage to the previous stage PA in the PA2; the fourth power supply terminal V4 is used to provide the externally inputted PAT mode voltage or ET mode voltage to the latter stage in the PA2 PA.
  • the common ground terminal G is used to provide the externally provided common reference voltage signal to each level of PA in PA1 and each level of PA in PA2.
  • capacitor C1 , capacitor C2 , switch K1 and switch K2 are packaged inside the power amplifier chip 11 ; the external pins of the power amplifier chip 11 also include a control terminal CL1 and a control terminal CL2 .
  • the first pole of the capacitor C1 is connected to the second power supply terminal V2, and the second pole of the capacitor C1 is connected to one end of the switch K1.
  • the other end of the switch K1 is connected to the common ground G, and the control end of the switch K1 is connected to the control end CL1.
  • the first pole of the capacitor C2 is connected to the fourth power supply terminal V4, and the second pole of the capacitor C2 is connected to one end of the switch K2.
  • the other end of the switch K2 is connected to the common ground G, and the control end of the switch K2 is connected to the control end CL2.
  • the positions of the capacitor C1 and the switch K1 can be interchanged. Specifically, one end of the switch K1 is connected to the second power supply terminal V2, the other end of the switch K1 is connected to the first pole of the capacitor C1, and the second pole of the capacitor C1 is connected to the common ground G.
  • the positions of the capacitor C2 and the switch K2 can also be interchanged. For the specific interchange method, reference may be made to the relevant description of the position interchange between the capacitor C1 and the switch K1, which is not repeated here.
  • the control terminal CL1 is used for receiving a control signal sent from outside, so as to control the switch K1 to be turned on or off.
  • the external control signal controls the switch K1 to be turned on through the control terminal CL1, and the capacitor C1 is connected to the common ground G; when the second power terminal V2 is connected to the PA1
  • the external control signal controls the switch K1 to be turned off through the control terminal CL1, and the capacitor C1 and the common ground G are disconnected.
  • the on and off principle of the switch K2 is the same as that of the switch K1 , and details are not repeated here.
  • the switch K1 and the switch K2 may include, but are not limited to, triodes, or MOS transistors.
  • the control terminals of the switch K1 and the switch K2 are the gates, and the other two poles of the switch K1 and the switch K2 are the source and the drain respectively.
  • the selected is determined by PMOS tube or NMOS tube.
  • the capacitor C1, capacitor C2, switch K1 and switch K2 packaged inside the power amplifier chip 11 are also bare chips, for example, these devices may be located in one or more bare chips; The device may also be implemented as a discrete device, which is not limited in this embodiment.
  • the terminal equipment occupied by the communication equipment can be further reduced. layout area.
  • an embodiment of the present application provides a communication device 100 as shown in FIG. 6 , the communication device 100 includes an RFIC, a first power supply chip 121 , a second power supply chip 122 , and a power amplifier chip 11. Antenna device T1 and antenna device T2.
  • the RFIC includes a first radio frequency signal output end F1, a second radio frequency signal output end F2, a first control signal output end Cr1, a second control signal output end Cr2, a third control signal output end Cr3 and a fourth control signal output end Cr4.
  • the first RF signal output end F1 of the RFIC is connected to the signal input end N1 of the power amplifier chip 11
  • the second RF signal output end F2 of the RFIC is connected to the signal input end N2 of the power amplifier chip 11
  • the first control signal of the RFIC The output terminal Cr1 is connected to the control terminal CL1 of the power amplifier chip 11
  • the second control signal output terminal Cr2 of the RFIC is connected to the control terminal CL2 of the power amplifier chip 11
  • the third control signal output terminal Cr3 of the RFIC is connected to the first power supply chip 121 .
  • the control terminal Cr3 is connected, and the fourth control signal output terminal Cr4 of the RFIC is connected to the control terminal Cr4 of the second power chip 122 .
  • the output terminal Vcc1 of the first power chip 121 is connected to the first power terminal V1 of the power amplifier chip 11 , and the output terminal Vcc2 of the first power chip 121 is connected to the second power terminal V2 of the power amplifier chip 11 .
  • the output terminal Vcc3 of the second power chip 122 is connected to the third power terminal V3 of the power amplifier chip 11 , and the output terminal Vcc4 of the second power chip 122 is connected to the fourth power terminal V4 of the power amplifier chip 11 .
  • the first power supply chip 121 and the second power supply chip 122 can be packaged in the same power supply device 12, which are respectively connected to external chips or devices through exposed pins or ports for signal exchange, as shown in FIG. 7 . shown.
  • the communication device in order to improve the performance of the power amplifier for supporting the above-mentioned B41 frequency band in the APT power supply mode, it is usually necessary to connect the second output terminal Vcc2 of the first power chip 121 and the common ground G A capacitor C3 and a switch K3 are connected in series between them, the first pole of the capacitor C3 is connected to the second output terminal Vcc2, the second pole of the capacitor C3 is connected to one end of the switch K3, the other end of the switch K3 is connected to the common ground G, and the other , the positions of the capacitor C3 and the switch K3 can also be interchanged.
  • the RFIC further includes a fifth control signal output terminal Cr5, and the control terminal of the switch K3 is connected to the fifth control signal output terminal Cr5 of the RFIC.
  • the switch K3 may also be arranged inside the power amplifier chip 11 , as shown in FIG. 8 .
  • the pin of the power amplifier chip 11 further includes a control terminal CL3, so as to connect the control terminal of the switch K3 to the fifth control signal output terminal Cr5 of the RFIC through the control terminal CL3.
  • the control terminal CL1 , the control terminal CL2 , the control terminal CL3 and the first control signal output terminal Cr1 , the second control signal output terminal Cr2 , and the third control signal output terminal Cr3 are not shown in FIG. 8 , respectively. connection situation.
  • first power supply chip 121 the second power supply chip 122 , the power amplifier chip 11 and the RFIC all include common ground terminals, and all of their common ground terminals can be connected together. Except for the power amplifier chip 11 in FIGS. 6 and 8 , the common ground terminals of other chips or devices are not shown.
  • the output terminal Vcc1 of the first power supply chip 121 provides a constant DC voltage to the previous stage PA in the PA1, and the second power supply
  • the output terminal Vcc3 of the chip 122 provides a constant DC voltage to the previous stage PA in the PA2.
  • the RFIC can control the output terminal Vcc2 of the first power chip 121 to supply power to the subsequent stage PA of the PA1 through the APT mode or the ET mode, or control the output terminal Vcc4 of the second power chip 122 to pass APT mode or through ET mode to supply power to the next stage PA of PA2.
  • the RFIC when the RFIC detects that the radio frequency signal to be transmitted is a high-power signal, the RFIC can control the first power chip 121 and the second power chip 122 to supply power in the APT mode respectively. At this time, the RFIC can control the switch K1, the switch K2, and the switch K3 to close, the capacitor C1 is connected between the output terminal Vcc2 of the first power chip 121 and the common ground G, and the capacitor C2 is connected between the output terminal Vcc4 and the output terminal of the second power chip 122. Between the common ground G, the capacitor C3 is connected between the output terminal Vcc2 of the first power chip 121 and the common ground G.
  • the RFIC When the RFIC detects that the radio frequency signal to be transmitted is a medium and small power signal, the RFIC can control the first power chip and the second power chip to supply power in the ET mode respectively. At this time, the RFIC can control the switch K1, the switch K2 and the switch K3 to be disconnected respectively, and the capacitor C1, the capacitor C2 and the capacitor C3 are not connected to the circuit at this time.
  • the independent power supply of each PA can be ensured, and the layout area occupied by the communication equipment can also be reduced, which is conducive to the realization of highly integrated terminal equipment.
  • FIG. 9 shows another schematic structural diagram of the electronic device 100 provided by the embodiment of the present application.
  • the electronic device 100 includes a first power supply chip 121 , a second power supply chip 122 , an RFIC and a power amplifier chip 11 .
  • the connection relationship between the RFIC and the first power supply chip 121 and the signal interaction between the two, the connection relationship between the RFIC and the second power supply chip 122 and the signal interaction between the two can be referred to as shown in FIG. 6 .
  • the relevant descriptions in the embodiments are not repeated here.
  • the power amplifier chip 11 includes four PA bare chips, which are PA1 bare chip, PA2 bare chip, PA3 bare chip and PA4 bare chip, wherein, PA1 bare chip, PA2 bare chip, PA3 bare chip and PA4 bare chip can be respectively integrated with Two cascaded PAs. Corresponding ends of the PA1 bare chip, the PA2 bare chip, the PA3 bare chip and the PA4 bare chip are respectively connected to the pins of the power amplifier chip 11 by means of jumpers, buried wires or switches.
  • the power amplifier chip 11 further includes a capacitor C1, a capacitor C2, a switch K1, a switch K2 and a switch K3. Different from the power amplifier chip 11 shown in FIG. 2 to FIG.
  • the power amplifier chip 11 shown in the embodiment of the present application further includes a controller CR.
  • the control terminals of the switch K1, the switch K2 and the switch K3 are controlled to be turned on or off by the controller CR.
  • the functions, beneficial effects, and connection relationships with other components of the capacitor C1, capacitor C2, switch K1, switch K2, and switch K3 are the same as those in the power amplifier chip 11 shown in FIG. 5 to FIG. 8 .
  • the role of the controller CR and the connection relationship with other components are described below.
  • the PA1 bare chip is used to amplify the radio frequency signal of the first frequency band (for example, the 5G frequency band).
  • the previous stage PA in the PA1 bare chip can be connected to the first power supply through the first power supply terminal V1.
  • the output terminal Vcc1 of the chip, the latter stage PA in the PA1 bare chip can be connected to the output terminal Vcc2 of the first power supply chip through the second power terminal V2, and the PA1 bare chip is connected to the first RF signal output terminal of the RFIC through the signal input terminal N1 F1 connection.
  • the PA2 bare chip is used to amplify the radio frequency signal of the second frequency band (such as the low frequency frequency band in 4G)
  • the PA3 bare chip is used to amplify the radio frequency signal of the third frequency band (such as the intermediate frequency frequency band in 4G)
  • the PA4 bare chip is used to amplify the first frequency band.
  • Radio frequency signals in four frequency bands (such as the high frequency bands in 4G).
  • the previous stage PA in the PA2 bare chip, the PA3 bare chip and the PA4 bare chip can be connected to the output terminal Vcc3 of the second power supply chip through the third power supply terminal V3, and the PA2 bare chip, the PA3 bare chip and the PA4 bare chip
  • the latter stage PA can be connected to the output terminal Vcc4 of the second power supply chip through the fourth power terminal V4, the PA2 bare chip is connected to the second RF signal output terminal F2 of the RFIC through the signal input terminal N2, and the PA3 bare chip is connected through the signal input terminal F2.
  • the terminal N3 is connected to the third radio frequency signal output terminal F3 of the RFIC, and the PA4 bare chip is connected to the fourth radio frequency signal output terminal F4 of the RFIC through the signal input terminal N4.
  • the specific working mode of the PA1 bare chip refers to the related description of PA1 shown in FIG. 5
  • the specific working mode of the PA2 bare chip, the PA3 bare chip and the PA4 bare chip refers to the related description of the PA2 shown in FIG. 5 , which will not be repeated here.
  • the switch group also includes nodes that are connected to the output ports in a one-to-one correspondence, and each node is connected to each of the output ports through a different radio frequency signal line.
  • the radio frequency signal line used to connect each node and each output port is determined based on the radio frequency frequency band provided by the output port. Specifically, as shown in FIG.
  • the output end of the PA of the subsequent stage of the PA1 bare chip is connected to the output port Po1 or the output port Po2 through the switch group 1, wherein a node for connecting a node of the switch group 1 to the output port Po1
  • the RF signal line can be the RF signal line suitable for the standard 38101-3-g21 intermediate frequency band number N40, and the RF signal line used to connect another node of the switch group 1 and the output port Po2 can be suitable for the standard 38101-3-
  • the RF signal line with the intermediate frequency band number of g21 is N41; the output end of the PA3 after the bare chip is connected to the output port Po4, the output port Po5 or the output port Po6 through the switch group 2.
  • the RF signal line between the node and the output port Po4 can be the RF signal line suitable for the standard 38101-3-g21 intermediate frequency band number MB39, and the RF signal line used to connect the second node of the switch group 2 and the output port Po5 can be In order to be suitable for the RF signal line with the standard 38101-3-g21 mid-band number MB3, the RF signal line used to connect the third node of the switch group 2 and the output port Po6 can be suitable for the standard 38101-3-g21 mid-band
  • the RF signal line numbered MB1; the output end of the PA of the back stage of the PA4 bare chip is connected to the output port Po7, the output port Po8 or the output port Po9 through the switch group 3, wherein the first node used to connect the switch group 3 and
  • the RF signal line of the output port Po7 can be the RF signal line suitable for the standard 38101-3-g21 intermediate frequency band number LB8, and the RF signal line used to connect the second node of the switch group
  • the number of output terminals corresponding to PA1, PA3 and PA4 is only schematic. It can be understood that PA1, PA3 and PA4 may respectively correspond to more or less output terminals. Correspondingly, each switch More or fewer switches can be included in a group.
  • the power amplifier chip 11 shown in FIG. 9 also includes an output port Po3. The output end of the latter stage PA of the PA2 bare chip is connected to the output port Po3 through a radio frequency signal line. The output port Po3 can support the RF signal with the standard 38101-3-g21 intermediate frequency band number MHB3.
  • the controller CR is connected to the data output terminal SD of the RFIC through the data input terminal SDATA, the controller CR is connected to the clock output terminal SC of the RFIC through the clock signal terminal SCLK, and the controller CR is connected through the battery.
  • the terminal VBAT is connected to the external battery.
  • the control terminal A1 of the controller CR is connected to the gain adjustment terminal A1 of the PA1, the control terminal A11 of the controller CR is connected to the enabling terminal A11 of the PA1; the control terminal A2 of the controller CR is connected to the gain of PA2
  • the adjustment terminal A2 is connected, the control terminal A12 of the controller CR is connected with the enable terminal A12 of PA2; the control terminal A3 of the controller CR is connected with the gain adjustment terminal A3 of PA3, and the control terminal A13 of the controller CR is connected with the enable terminal of PA3.
  • A13 is connected; the control end A4 of the controller CR is connected with the gain adjustment end A4 of the PA4, the control end A14 of the controller CR is connected with the enabling end A14 of the PA4; the control end A5 of the controller CR is connected with the control of the first switch group 1 terminal A5 is connected; the control terminal A6 of the controller CR is connected with the control terminal A6 of the second switch group 2; the control terminal A7 of the controller CR is connected with the control terminal A3 of the third switch group 3; the control terminal A8 of the controller CR is connected to The control end of the switch K1 is connected; the control end A9 of the controller CR is connected with the control end of the switch K2; the control end A10 of the controller CR is connected with the control end of the switch K3.
  • the controller CR may work based on the clock cycle provided by the clock signal terminal SCLK. Based on the clock period provided by the clock signal terminal SCLK, the controller CR may receive data from the data input terminal SDATA. The data is sent to the controller CR by the RFIC through the bus to realize the control of the working mode.
  • the controller CR can analyze the received data, and based on the analysis results, determine the power amplifier used for transmitting the signal, the gain of the selected power amplifier, the selected communication frequency band, and the power supply mode (PAT) of each power amplifier. Power supply mode or ET power supply mode) and other information.
  • the enabling of one or more of PA1, PA2, PA3 or PA4 is controlled, the gain of one or more of PA1, PA2, PA3 or PA4 is adjusted, and the switch group K1, the switch group are controlled The channel of K3 or switch group K4. So that one or more PAs transmit the signal output from the output terminal to the network device through the antenna.
  • PA1 is used to transmit the first radio frequency signal
  • PA3 is used to transmit the second radio frequency signal.
  • the PA of the latter stage of PA1 is powered by APT mode
  • the PA of the latter stage of PA3 is powered by APT mode
  • PA1 is powered by the N41 frequency band in the communication protocol.
  • PA3 transmits signals through the MB39 frequency band in the communication protocol.
  • the RFIC can transmit the configuration information of PA1 and PA3 to the data input terminal SDATA of the power amplifier chip 11 through the bus connected to the data output terminal SD, and then provide the controller CR through the data input terminal SDATA.
  • the controller CR controls the enabling of PA1 and PA3, adjusts the gain of PA1 and PA3, connects the output of PA1 to the output port Po1 (assuming that the output port Po1 supports the N41 frequency band), and connects the output of PA3 To output port Po4 (assuming output port Po4 supports MB39 band).
  • the controller CR can also control the switch K1, the switch K2 and the switch K3 to be turned on.
  • the above configuration information may be carried in a frame format for transmission.
  • the frame format may include a field for indicating a power amplifier, a field for indicating an adopted radio frequency band, a field for indicating an adopted power supply mode, and the like. In a specific scene, it may also include more or less fields than those included in the above frame format, which can be set according to the needs of the scene.
  • Each field can be indicated by multiple bits. For example, taking the field indicating the PA as an example, four bits may be used, and each bit represents one PA. For example, when using PA1 and PA3 to transmit radio frequency signals, the corresponding bit in this field can be set to "1010".
  • the controller CR can also control the switch K1, the switch K3 and the switch K3 to be turned on.
  • the terminal device may multiplex the output end of the power amplifier chip 11 to receive the downlink signal, and then transmit it to the RFIC through the output end of the power amplifier chip 11 .
  • the power amplifier chip 11 further includes a signal receiving end RX1 and a signal receiving end RX2.
  • the signal receiving end RX1 and the signal receiving end RX2 are respectively used for receiving radio frequency signals of different frequencies.
  • the output port Po1 and the output port Po2 of the power amplifier chip 11 are respectively connected to the signal receiving end RN1 and the signal receiving end RN2 of the RFIC; the switch group 1 inside the power amplifier chip 11 also includes an output port for connecting the output ports Po1 and PA1.
  • the switch group 1 also includes a switch for connecting the output port Po2 with the output terminal of PA1 or with the signal receiving terminal RX2.
  • the control terminal A5 of the controller CR is also used to control the switches in the switch group 1, so that the output port Po2 is connected to the output terminal of PA1 or to the signal receiving terminal RX2.
  • the RFIC sends the indication information for indicating the transmitted signal or the received signal to the controller CR through the data input terminal SDATA, and the controller CR controls each switch in the switch group 1 based on the analysis result.
  • the power amplifier chip 11 shown in FIG. 9 and FIG. 10 also includes a common ground terminal G, and all the terminals inside the power amplifier chip 11 can be connected to the common ground terminal G, and the common ground terminal G can be connected with the first terminal G.
  • a power chip, a second power chip and the common ground terminal of the RFIC are connected, so that the power amplifier chip 11, the first power chip, the second power chip and the RFIC can have a common common voltage reference signal.
  • the PAs shown in the embodiments of the present application are applicable to various physical channels of communication systems, that is to say, power amplification can be performed on signals transmitted by various channels.
  • the channels may include but are not limited to: PUCCH channel, PUSCH channel, PRACH channel and SRS channel.
  • the gains adopted by different channels may be different.
  • the PA Before the terminal device needs to transmit signals (the PA is turned off from the off state to the enabled state), or from using the first type channel (such as PUCCH channel) to transmit signals to using the second type channel (such as PUSCH channel) to transmit signals (At this time, the PA is converted from using the first gain to transmit the signal to using the second gain to transmit the signal), the PA needs to be configured (including controlling the PA enable or changing the PA gain, etc.).
  • the RFIC can configure the power of the PA based on the information carried in the frame format sent by the network device, and then transmit the configuration information of the PA to the controller CR, so that the controller CR controls the PA enablement and adjusts the gain of the PA , so that the PA works properly.
  • the communication device in the terminal device (for example, including the baseband processor, the RFIC, and the antenna) can monitor the measurement information sent by the network device, and then analyze the received measurement information, and based on the analysis result, determine whether to communicate with the network device.
  • the frame format used to carry the data the time for each type of data to be transmitted, the channel used for data transmission, and other information. Please refer to FIG.
  • each frame of data may include two time slots, and each time slot may include 14 symbols.
  • the information carried in the frame format shown in FIG. 11 also includes the start symbol of signal transmission, and which symbols use which channel for signal transmission.
  • symbol 12 in time slot 8 is schematically shown to start signaling. Among them, the symbols 12 and 13 in the time slot 8 use the PUCCH channel for signal transmission; the symbols 0 to 11 in the time slot 9 use the PUSCH channel for signal transmission; the symbols 12 to 13 in the time slot 9 use the SRS channel for signal transmission Signal transmission.
  • the PA configuration information transmitted by the RFIC to the controller CR also includes the time for controlling the enabling of the PA and the time for adjusting the gain of the PA.
  • the PA enablement is controlled, or the PA gain is adjusted, for a first preset time period before the distance signal starts to transmit or for a second preset time period before the distance channel switching. For example, in the sequence shown in Fig.
  • the PA uses the first gain for signal transmission, which corresponds to the starting time of the symbol 12 in the time slot 8 shown in Fig. 11, and it is assumed that the time T3 starts, the PA adopts The second gain performs signal transmission, which corresponds to the start time of symbol 0 in time slot 9 shown in FIG. 11 .
  • the PA gain is adjusted and the PA enable is controlled, and at time T2, the PA gain is adjusted, so that the PA uses the second signal for signal transmission.
  • the time period t1 of T2 minus T1 is the same as the time period t2 of T3 minus T2 or has a small difference. It is usually around 2us.
  • the time period t1 and the time period t2 are set to different time periods, wherein the length of the time period t1 is set to be greater than the length of the time period t2, that is, the PA is started in advance.
  • the PA gain can be adjusted and the PA enable can be controlled at time T1 , and the other time points are the same as those shown in FIG. 12 .
  • the PA can have enough time to enter a stable working state, thereby reducing the bit error rate.
  • the error vector magnitude (EVM) of the first symbol can be improved.

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Abstract

本申请实施例提供了一种功率放大器芯片和通信设备，该功率放大器芯片包括：封装壳；多个功率放大器裸芯片，该多个功率放大器裸芯片合封于封装壳中；其中，该多个功率放大器裸芯片中的每一个功率放大器裸芯片包括至少一级功率放大器，从而可以降低功率放大器所占用的终端设备的版图面积，进而降低通信设备所占用的终端设备的版图面积，有利于高度集成化的终端设备的实现。

Description

功率放大器芯片以及通信设备 技术领域
本申请实施例涉及通信领域，尤其涉及一种功率放大器芯片以及通信设备。
背景技术
伴随着科学技术的发展，通信技术得以突飞猛进的提升。无线通信技术经过长期的演化发展，当前无线通信技术中，为了提高信息传输速率，终端设备通常支持双连接的方式同时接入4G网络和5G网络。4G网络或5G网络中基站可以分别采用4G频段或5G频段与终端设备进行数据传输。
相关通信技术中，通常需要在终端设备中设置两套独立的射频单元，以分别支持4G网络和5G网络的数据传输，每一套射频单元包括诸如功率放大器模块和电源模块等。该两套独立的射频单元通常占用终端设备较高的版图面积，不利于终端设备向体积小、集成度高的方向发展。在其他可能的双连接的通信场景，如多卡多待或多模同时传输等场景下，多个独立的射频单元也会造成类似问题。由此，如何在支持双连接数据传输方式的终端设备中、降低射频单元所占用的版图面积成为需要解决的问题。
发明内容
本申请提供的功率放大器芯片和通信设备，有利于降低通信设备所占用的电子设备的版图面积。为达到上述目的，本申请采用如下技术方案。
第一方面，本申请实施例提供一种功率放大器芯片，包括：封装壳；多个功率放大器裸芯片，所述多个功率放大器裸芯片合封于所述封装壳中；其中，所述多个功率放大器裸芯片中的每一个功率放大器裸芯片包括至少一级功率放大器。
本申请实施例通过将多个功率放大器裸芯片封装于同一封装壳中，可以降低功率放大器所占用的终端设备的版图的面积，有利于高度集成化的终端设备的实现。
基于第一方面，在一种可能的实现方式中，所述多个功率放大器裸芯片分别支持不同的射频频段。
该不同的射频频段可以包括但不限于：N41频段(2496MHz–2690MHz)、B39频段(1880MHz–1920MHz)或者B1频段(1920MHz–1980MHz)。
基于第一方面，在一种可能的实现方式中，所述功率放大器芯片还包括：第一开关，位于所述封装壳中，用于将第一电容连接在公共地与所述多个功率放大器裸芯片中的第一功率放大器裸芯片的电源端之间或者断开所述连接。
基于第一方面，在一种可能的实现方式中，所述功率放大器芯片还包括第二电容和第二开关，位于所述封装壳中；所述第二开关用于将所述第二电容连接在公共地与所述多个功率放大器裸芯片中的第二功率放大器裸芯片的电源端之间或者断开所述连接。
可选地，第二功率放大器裸芯片可以是所述第一功率放大器裸芯片，此外，第二功率 放大器裸芯片还可以是与所述第一功率放大器裸芯片不同的功率放大器裸芯片。
通过将第一开关、第二电容和第二开关封装于功率放大器芯片内部，可以使得在具有多种供电模式的功率放大器的场景中，进一步降低通信设备所占用的终端设备的版图面积。
基于第一方面，在一种可能的实现方式中，所述功率放大器芯片还包括：控制器，位于所述封装壳中，所述控制器用于从无线射频集成电路接收用于指示功率放大器配置的指示信息，基于所述指示信息，控制所述多个功率放大器裸芯片中至少一个功率放大器裸芯片内的至少一级功率放大器使能，以及调节所使能的至少一级功率放大器的增益；其中，所述指示信息包括以下至少一项：所使能的至少一级功率放大器、功率放大器的增益、功率放大器的供电模式、控制功率放大器启动的时刻、调节功率放大器的增益的时刻或者所采用的所述功率放大器芯片的输出端口。
基于第一方面，在一种可能的实现方式中，所述功率放大器芯片还包括：多个开关组，位于所述封装壳中，所述多个开关组中的第一开关组包括第一输入端和多个输出端；所述多个功率放大器裸芯片中的第三功率放大器裸芯片的输出端与所述多个第一开关组中的至少一个第一开关组的第一输入端连接，所述至少一个第一开关组中的每个第一开关组的多个输出端与所述功率放大器芯片的多个输出端口中的至少部分输出端口对应连接。
可选地，第三功率放大器裸芯片可以是所述第一功率放大器裸芯片，也可以是所述第二功率放大器裸芯片。
基于第一方面，在一种可能的实现方式中，所述至少一个第一开关组中的第二开关组包括第二输入端；所述第二输入端与所述功率放大器芯片的射频信号接收端连接；所述第二开关组中的开关基于控制信号，将所述射频信号接收端与所述第二开关组中多个输出端的其中一个输出端连接。
基于第一方面，在一种可能的实现方式中，所述多个功率放大器裸芯片中的第二功率放大器裸芯片集成的第一功率放大器，包括第一增益和第二增益；其中，所述第一功率放大器启动的时刻与所述第一功率放大器开始传输信号的时刻之间的第一时间段，大于将所述第一功率放大器开始由所述第一增益调节至所述第二增益的时刻与所述第一功率放大器采用所述第二增益开始传输信号的时刻之间的第二时间段。
第二方面，本申请实施例提供一种通信设备，该通信设备可以包括电源设备以及如第一方面所述的功率放大器芯片；其中，所述电源设备中的第一电源设备用于向所述功率放大器芯片中的第一功率放大器裸芯片供电；所述电源设备中的第二电源设备用于向所述功率放大器芯片中的其余功率放大器裸芯片供电。
基于第二方面，在一种可能的实现方式中，所述通信设备还包括：无线射频集成电路，用于向多个功率放大器裸芯片中的至少一个功率放大器裸芯片集成的功率放大器传输射频信号。
基于第二方面，在一种可能的实现方式中，所述电源设备还用于：从所述无线射频集成电路接收指示信号，基于所示指示信号，采用所述指示信号所指示的供电模式向所述功率放大器供电；所述供电模式包括平均功率追踪模式或者包络追踪模式。
基于第二方面，在一种可能的实现方式中，所述通信设备还包括第一电容；所述第一电容基于第一开关的控制，连接在公共地与所述第一功率放大器裸芯片的电源端之间或者断开所述连接。
基于第二方面，在一种可能的实现方式中，所述无线射频集成电路还用于：向所述功率放大器芯片中的控制器传输指示信息。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例的描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例的提供的一个应用场景示意图；
图2是本申请实施例提供的功率放大器芯片的一个结构示意图；
图3是本申请实施例提供的通信设备的一个结构示意图；
图4是本申请实施例提供的电源设备的内部结构示意图；
图5是本申请实施例提供的功率放大器芯片的又一个结构示意图；
图6是本申请实施例提供的通信设备的又一个结构示意图；
图7是本申请实施例提供的电源设备的又一个结构示意图；
图8是本申请实施例提供的通信设备的又一个结构示意图；
图9是本申请实施例提供的通信设备的又一个结构示意图；
图10是本申请实施例提供的通信设备的又一个结构示意图；
图11是本申请实施例提供的网络设备下发的帧格式的一个示意图；
图12是现有技术中调节功率放大器的增益的时间的一个时序图；
图13是本申请实施例提供的调节功率放大器的增益的时间的一个时序图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的术语“第一”、“第二”等仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元。方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。在本申请实施例的描述中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
本申请实施例中的终端设备也可以称为：用户设备(user equipment，UE)、移动台(mobile station，MS)、移动终端(mobile terminal，MT)、接入终端、用户单元、用户站、移动站、移动台、远方站、远程终端、移动设备、用户终端、终端、无线通信设备、用户代理或用户装置等。终端设备可以是一种向用户提供语音/数据连通性的设备，例如， 具有无线连接功能的手持式设备、车载设备等。目前，一些终端的举例为：手机(mobile phone)、平板电脑、笔记本电脑、掌上电脑、移动互联网设备(mobile internet device，MID)、可穿戴设备，虚拟现实(virtual reality，VR)设备、增强现实(augmented reality，AR)设备、工业控制(industrial control)中的无线终端、无人驾驶(self driving)中的无线终端、远程手术(remote medical surgery)中的无线终端、智能电网(smart grid)中的无线终端、运输安全(transportation safety)中的无线终端、智慧城市(smart city)中的无线终端、智慧家庭(smart home)中的无线终端、蜂窝电话、无绳电话、会话启动协议(session initiation protocol，SIP)电话、无线本地环路(wireless local loop，WLL)站、个人数字助理(personal digital assistant，PDA)、具有无线通信功能的手持设备、计算设备或连接到无线调制解调器的其它处理设备、车载设备、可穿戴设备，未来5G网络中的终端设备或者未来演进的公用陆地移动通信网络(public land mobile network，PLMN)中的终端设备等，本申请实施例对此并不限定。
本申请实施例中的网络设备可以是用于与终端设备通信的设备，该网络设备也可以称为接入网设备或无线接入网设备，可以是LTE系统中的演进型基站(evolved NodeB，eNB或eNodeB)，还可以是云无线接入网络(cloud radio access network，CRAN)场景下的无线控制器，或者该接入设备可以为中继站、接入点、车载设备、可穿戴设备以及未来5G网络中的接入设备或者未来演进的PLMN网络中的接入设备等，可以是WLAN中的接入点(access point，AP),可以是新型无线系统(new radio，NR)系统中的gNB本申请实施例并不限定。另外，在本申请实施例中，网络设备还可以是RAN(Radio Access Network，无线接入网)中的设备，或者说，是将终端设备接入到无线网络的RAN节点。例如，作为示例而非限定，作为网络设备，可以列举：gNB、传输接收点(transmission reception point，TRP)、演进型节点B(evolved Node B，eNB)、无线网络控制器(radio network controller，RNC)、节点B(Node B，NB)、基站控制器(base station controller，BSC)、基站收发台(base transceiver station，BTS)、家庭基站(例如，home evolved NodeB，或home Node B，HNB)、基带单元(base band unit，BBU)，或无线保真(wireless fidelity，Wifi)接入点(access point，AP)等。
请参考图1，其示出了应用于本申请实施例的一个场景示意图。在图1所示的场景中，包括终端设备、网络设备A1和网络设备A2。其中，终端设备可以同时接入到网络设备A1和网络设备A2中，该接入方式称为双连接(dual-connectivity，DC)。在一个示例性场景下，该两个网络设备之中，负责与终端设备交互无线资源控制消息，并负责和核心网控制平面实体交互的为可以称之为主网络设备，另一个网络设备为辅网络设备。类似的，终端设备也可以同时与多个网络设备存在通信连接并可收发数据，可以称之为多连接(multi-connectivity，MC)，该多个网络设备之中，可以有一个网络设备负责与该终端设备交互无线资源控制消息，并负责和核心网控制平面实体交互，那么，该网络设备可以称之为主网络设备，则其余的网络设备可以称之为辅网络设备。本申请以下各实施例中以双连接为例进行详细阐述。
在如图1所示的场景中，网络设备A1和网络设备A2可以为相同无线接入类型的网络设备。例如，网络设备A1和网络设备A2可以为LTE系统的网络设备，或者可以为NR系统的网络设备。网络设备A1和网络设备A2还可以是不同无线接入类型的网络设备。 具体实现中，网络设备A1可以为LTE系统的网络设备，网络设备A2可以为NR系统的网络设备。其中，网络设备A1和网络设备A2均可以作为主网络设备。进一步的，网络设备A1和网络设备A2可以分别以不同的射频频段为终端设备服务。
终端设备中可以设置有通信设备，该终端设备可以通过通信设备向网络设备A1和网络设备A2发送数据，或者通过通信设备从网络设备A1和网络设备A2接收数据。该通信设备通常包括功率放大器(Power Amplifier，PA)、为功率放大器提供电能的电源设备、和用于向PA提供射频信号的RFIC(Radio Frequency Integrated Circuit，无线射频集成电路)等，也可选择性包括调制解调器和天线等。
当终端设备采用双连接或多连接与网络设备进行数据传输时，需要设置两套或多套功率放大器以进行多通道数据传输；例如采用双连接时，设置两套功率放大器以使终端设备分别与网络设备A1和网络设备A2进行数据传输；采用三连接时，设置三套功率放大器以使终端设备与相应的网络设备进行数据传输。此外，为了提高通信设备中各连接通道对应的功率放大器的工作性能，通常需要设置多个独立的电源模块，以为每一套功率放大器进行独立供电。这样一来，通常导致通信设备在终端设备中占用过多的版图面积。不利于高度集成化的终端设备的实现。
基于图1所示的应用场景，下面通过图2-图8所示的实施例，对终端设备中的通信设备的结构进行详细描述，以解决降低版图面积的技术问题。
通信设备可以包括一个或多个功率放大器芯片。每个功率放大器芯片中可以集成有至少两个功率放大器。也即是说，一个功率放大器芯片可以集成有两个功率放大器、三个功率放大器、或四个功率放大器等等，本申请实施例对此不做限定。以一个功率放大器芯片包括两个功率放大器为例，结合图2，对功率放大器芯片的内部结构进行详细描述。
在图2中，功率放大器芯片11可以包括PA1裸芯片和PA2裸芯片。这里裸芯片也可以称为Die，也即在半导体上通过生长、掺杂、刻蚀、或显影等工艺形成的集成电路，该集成电路具有功率放大的功能。具体实践中，PA1裸芯片和PA2裸芯片可以通过粘贴、或烧结等工艺一起设置于封装材料内部，该封装材料用于形成一个封装壳。然后，通过跳线或埋线等工艺将PA1裸芯片和PA2裸芯片的引出端连接至封装壳、用于与外部器件连接的各引脚上，从而实现PA1裸芯片和PA2裸芯片与外部器件或设备之间的信号交流。
在所述功率放大器芯片11中，封装壳用于封装内部器件，例如可采用标准封装工艺实现。被封装的内部器件包括但不限于如前所述的多个裸芯片、以及其他必要器件，如后续实施例提到的开关、开关组、电容或控制器等，具体可参照后续实施例的介绍。
上述PA1裸芯片所集成的功率放大器PA1和PA2裸芯片所集成的功率放大器PA2可以用于支持不同频段信号的功率放大。具体的，PA1可以支持N41频段(2496MHz–2690MHz)的功率放大；PA2可以支持B39频段(1880MHz–1920MHz)、B3频段(1710MHz–1785MHz)或者B1频段(1920MHz–1980MHz)的功率放大。
从图2中可以看出，功率放大器芯片11包括多个引脚，该多个引脚分别为：PA1的信号输入端N1，PA2的信号输入端N2，PA1的电源端V1，PA2的电源端V2，PA1和PA2的公共地端G，PA1的输出端口Po1和PA2的输出端口Po2。该多个引脚分别与外部诸如电源设备、RFIC、或天线设备等设备或器件连接，实现如图1所示的多路上行通信信号的功率放大。
本申请实施例通过将多个功率放大器裸芯片封装于同一功率放大器芯片中，可以降低功率放大器所占用的终端设备的版图的面积，有利于高度集成化的终端设备的实现。
基于图2所示的功率放大器芯片11，本申请实施例提供一种如图3所示的通信设备100，该通信设备100包括RFIC、电源设备12和功率放大器芯片11。
其中，电源设备12可以包括两个输出端和一个公共地端，其中一个输出端与功率放大器芯片的电源端V1连接，以用于向功率放大器芯片11中的PA1供电；另外一个输出端与功率放大器芯片11的电源端V2连接，以用于向功率放大器芯片中的功率放大器PA2供电，公共地端与功率放大器芯片11的公共地端G连接。
在一种可能的实现方式中，电源设备12可以包括第一电源芯片121和第二电源芯片122，如图4所示。第一电源芯片121和第二电源芯片122可以为独立的裸芯片，其封装于电源设备12中。第一电源芯片121为PA1供电，第二电源芯片122为PA2供电。
RFIC的第一射频信号输出端F1与功率放大器芯片11的信号输入端N1连接，RFIC的第二射频信号输出端F2与功率放大器芯片11的信号输入端N2连接。RFIC的第一射频信号输出端F1和第二射频信号输出端F2分别用于提供第一频段的信号和第二频段的信号。该第一频段的信号可以为上述N41频段信号，该第二频段的信号可以为上述B39频段、上述B1频段或者上述B3频段的信号。
在本申请实施例中，功率放大器芯片所包括的多个功率放大器裸芯片中，每一个功率放大器裸芯片还可以集成有多个级联的PA。该多个级联的PA可以是通过在同一个硅衬底生长、离子掺杂、刻蚀、和显影等工艺集成在同一裸芯片中的。其中，用于接收外部设备(例如RFIC)输入的信号的PA称为前一级PA，用于向外部设备(例如天线)输出信号的PA称为后一级PA。此外，在某些场景中，在前一级PA和后一级PA之间还可以设置有一级或多级中间级PA。其中每一级PA在工作时均需要电源供电。其中，前一级PA的供电电压可以为直流恒定电压；后一级PA可以支持多种供电模式。该多种供电模式例如可以包括但不限于：APT(Average Power Tracker，平均功率追踪)模式和ET(Envelope Tracker，包络追踪)模式。中间级PA的供电方式可以根据场景的需要选择直流恒压模式、APT模式或者ET模式。在APT模式下，为了改善大带宽下载波的线性度，在功率放大器的电源端与公共地之间还设置有电容；而在ET模式下，由于供电电压变化较快，电容会影响包络追踪特性，此时ET模式下不需要设置电容。下面，以每一个功率放大器裸芯片集成有两级级联的PA为例，结合图5，对该功率放大器芯片进行详细描述。
请继续参考图5，其示出了本申请实施例提供的功率放大器芯片的又一个结构示意图。在图5中，功率放大器芯片11包括两个PA裸芯片，分别为PA1裸芯片和PA2裸芯片，其中，PA1裸芯片集成有两个级联的PA，PA2裸芯片同样也集成有两个级联的PA。当功率放大器芯片11封装完毕后，从外部看，功率放大器芯片11的引脚包括：第一电源端V1、第二电源端V2、第三电源端V3、第四电源端V4、信号输入端N1、信号输入端N2、输出端口Po1、输出端口Po2和公共地端G。与图2所示的功率放大器芯片11类似，PA1裸芯片和PA2裸芯片的相应端通过跳线或埋线的方式分别连接至功率放大器芯片11的各引脚，在此不再赘述连接关系。信号输入端N1用于将RFIC输入的第一频段信号提供至PA1中的前一级PA；输出端口Po1用于将PA1中的后一级PA输出的信号提供给天线；信号输入端N2用于将RFIC输入的第二频段信号提供至PA2中的前一级PA；输出端口 Po2用于将PA2中的后一级PA输出的信号提供给天线。第一电源端V1用于将外部输入的直流恒定电压提供至PA1中的前一级PA；第二电源端V2用于将外部输入的PAT模式电压或者ET模式电压提供至PA1中的后一级PA。第三电源端V3用于将外部输入的直流恒定电压提供至PA2中的前一级PA；第四电源端V4用于将外部输入的PAT模式电压或者ET模式电压提供至PA2中的后一级PA。公共地端G用于将外部提供的公共参考电压信号提供至PA1中的各级PA以及PA2中的各级PA。
继续参考图5，在图5中，功率放大器芯片11内部还封装有电容C1、电容C2、开关K1和开关K2；功率放大器芯片11的外部引脚还包括控制端CL1和控制端CL2。其中，电容C1的第一极连接至第二电源端V2，电容C1的第二极连接至开关K1的其中一端。开关K1的另外一端连接至公共地G，开关K1的控制端连接至控制端CL1。电容C2的第一极连接至第四电源端V4，电容C2的第二极连接至开关K2的其中一端。开关K2的另外一端连接至公共地G，开关K2的控制端连接至控制端CL2。需要说明的是，实际产品中，电容C1与开关K1的位置可以互换。具体的，开关K1的一端连接至第二电源端V2，开关K1的另外一端连接至电容C1的第一极，电容C1的第二极连接至公共地G。此外，电容C2和开关K2的位置也可以互换，具体互换的方式可以参考电容C1和开关K1之间位置互换的相关描述，在此不在赘述。控制端CL1用于接收外部发送的控制信号，以控制开关K1导通或关断。当第二电源端V2向PA1中的后一级PA输入APT模式的电压时，外部控制信号通过控制端CL1控制开关K1导通，电容C1连接至公共地G；当第二电源端V2向PA1中的后一级PA输入ET模式的电压时，外部控制信号通过控制端CL1控制开关K1关断，电容C1与公共地G之间断开。开关K2的导通和关断的原理与开关K1相同，在此不再赘述。开关K1和开关K2可以包括但不限于三极管、或MOS管等。当开关K1和开关K2为MOS管时，开关K1和开关K2的控制端为栅极，开关K1和开关K2的另外两极分别为源极和漏极，具体哪一端为源极或漏极，根据所选用的为PMOS管或者NMOS管确定。需要说明的是，功率放大器芯片11内部所封装的电容C1、电容C2、开关K1和开关K2也均为裸芯片，例如这几个器件可以位于一个或多个裸芯片中；或者，这几个器件也可以分立器件实现，本实施例对此不限定。
本申请实施例通过将电容C1、电容C2、开关K1和开关K2封装于功率放大器芯片11内部，可以使得在具有多种供电模式的功率放大器的场景中，进一步降低通信设备所占用的终端设备的版图面积。
基于图5所示的功率放大器芯片11，本申请实施例提供一种如图6所示的通信设备100，该通信设备100包括RFIC、第一电源芯片121、第二电源芯片122、功率放大器芯片11、天线设备T1和天线设备T2。
RFIC包括第一射频信号输出端F1、第二射频信号输出端F2、第一控制信号输出端Cr1、第二控制信号输出端Cr2、第三控制信号输出端Cr3和第四控制信号输出端Cr4。其中，RFIC的第一射频信号输出端F1与功率放大器芯片11的信号输入端N1连接，RFIC的第二射频信号输出端F2与功率放大器芯片11的信号输入端N2连接，RFIC的第一控制信号输出端Cr1与功率放大器芯片11的控制端CL1连接，RFIC的第二控制信号输出端Cr2与功率放大器芯片11的控制端CL2连接，RFIC的第三控制信号输出端Cr3与第一电源芯片121的控制端Cr3连接，RFIC的第四控制信号输出端Cr4与第二电源芯片122 的控制端Cr4连接。
第一电源芯片121的输出端Vcc1与功率放大器芯片11的第一电源端V1连接，第一电源芯片121的输出端Vcc2与功率放大器芯片11的第二电源端V2连接。第二电源芯片122的输出端Vcc3与功率放大器芯片11的第三电源端V3连接，第二电源芯片的输出端Vcc4与功率放大器芯片11的第四电源端V4连接。具体实现中，第一电源芯片121和第二电源芯片122可以封装于同一个电源设备12中，其分别通过裸露在外部的引脚或端口与外部芯片或设备连接以进行信号交流，如图7所示。
此外，在如图6所述的通信设备中，为了提高用于支持诸如上述B41频段的功率放大器在APT供电模式的性能，通常需要在第一电源芯片121的第二输出端Vcc2和公共地G之间串联有电容C3和开关K3，电容C3的第一极连接至第二输出端Vcc2，电容C3的第二极连接至开关K3的其中一端，开关K3的另一端连接至公共地G，另外，电容C3和开关K3的位置也可以互换，具体互换的方式可以参考电容C1和开关K1之间位置互换的相关描述，在此不在赘述。此外，RFIC还包括第五控制信号输出端Cr5，开关K3的控制端连接至RFIC的第五控制信号输出端Cr5。
为了进一步降低通信设备所占用的终端设备的版图面积，在一种可能的实现方式中，开关K3还可以设置于功率放大器芯片11内部，如图8所示。此时，功率放大器芯片11的引脚还包括控制端CL3，以通过控制端CL3将开关K3的控制端与RFIC的第五控制信号输出端Cr5连接。为了图8的可视性，图8中未示出控制端CL1、控制端CL2、控制端CL3分别与第一控制信号输出端Cr1、第二控制信号输出端Cr2、第三控制信号输出端Cr3连接的情况。
此外，需要说明的是，第一电源芯片121、第二电源芯片122、功率放大器芯片11和RFIC均包括公共地端，其所有的公共地端均可以连接在一起。图6和图8中除了功率放大器芯片11外，未示出其余芯片或设备的公共地端。
在如图6所示的通信设备中，在采用双连接的方式进行信号发送的场景中，第一电源芯片121的输出端Vcc1向PA1中的前一级PA提供恒定的直流电压，第二电源芯片122的输出端Vcc3向PA2中的前一级PA提供恒定的直流电压。RFIC可以基于所要发射的射频信号的功率大小，控制第一电源芯片121的输出端Vcc2通过APT模式或者通过ET模式向PA1的后一级PA供电，或者控制第二电源芯片122的输出端Vcc4通过APT模式或者通过ET模式向PA2的后一级PA供电。具体的，当RFIC检测到待发射的射频信号为大功率信号时，RFIC可以控制第一电源芯片121和第二电源芯片122分别采用APT模式供电。此时，RFIC可以控制开关K1、开关K2、开关K3闭合，电容C1连接在第一电源芯片121的输出端Vcc2与公共地G之间，电容C2连接在第二电源芯片122的输出端Vcc4与公共地G之间，电容C3连接在第一电源芯片121的输出端Vcc2与公共地G之间。当RFIC检测到待发射的射频信号为中小功率信号时，RFIC可以控制第一电源芯片和第二电源芯片分别采用ET模式供电。此时，RFIC可以分别控制开关K1、开关K2和开关K3断开，电容C1、电容C2和电容C3此时均未接入电路中。
通过采用如图6或图8所示的通信设备，可以在保障各PA独立供电的同时，还可以降低通信设备所占用的版图面积，有利于实现高度集成化的终端设备。
请继续参考图9，其示出了本申请实施例提供的电子设备100的又一个结构示意图。 在图9中，电子设备100包括第一供电芯片121、第二供电芯片122、RFIC和功率放大器芯片11。其中，RFIC与第一供电芯片121之间的连接关系以及二者之间的信号交互、RFIC与第二供电芯片122之间的连接关系以及二者之间的信号交互可以参考图6所示的实施例中的相关描述，在此不再赘述。
功率放大器芯片11包括四个PA裸芯片，分别为PA1裸芯片、PA2裸芯片、PA3裸芯片和PA4裸芯片，其中，PA1裸芯片、PA2裸芯片、PA3裸芯片和PA4裸芯片可以分别集成有两个级联的PA。PA1裸芯片、PA2裸芯片、PA3裸芯片和PA4裸芯片的相应端通过跳线、埋线或者开关的方式分别连接至功率放大器芯片11的各引脚。功率放大器芯片11还包括电容C1、电容C2、开关K1、开关K2和开关K3。与图2-图8所示的功率放大器芯片11不同的是，本申请实施例所示的功率放大器芯片11还包括控制器CR。开关K1、开关K2和开关K3的控制端通过控制器CR控制导通或关断。除此之外，电容C1、电容C2、开关K1、开关K2和开关K3的作用、有益效果以及与其他部件之间的连接关系，与图5-图8所示的功率放大器芯片11中的相同，具体可以参考图5-图8所示的功率放大器芯片11的相关描述，在此不再赘述。控制器CR的作用以及与其他各部件之间的连接关系参见下文描述。
与图5所示的PA1裸芯片相同，PA1裸芯片用于放大第一频段(例如5G频段)的射频信号，PA1裸芯片中的前一级PA可以通过第一电源端V1连接至第一供电芯片的输出端Vcc1，PA1裸芯片中的后一级PA可以通过第二电源端V2连接至第一供电芯片的输出端Vcc2，PA1裸芯片通过信号输入端N1与RFIC的第一射频信号输出端F1连接。PA2裸芯片用于放大第二频段(例如4G中的低频频段)的射频信号，PA3裸芯片用于放大第三频段(例如4G中的中频频段)的射频信号，PA4裸芯片用于放大第四频段(例如4G中的高频频段)的射频信号。其中，PA2裸芯片、PA3裸芯片和PA4裸芯片中的前一级PA可以通过第三电源端V3均连接至第二供电芯片的输出端Vcc3，PA2裸芯片、PA3裸芯片和PA4裸芯片中的后一级PA可以通过第四电源端V4均连接至第二供电芯片的输出端Vcc4，PA2裸芯片通过信号输入端N2与RFIC的第二射频信号输出端F2连接，PA3裸芯片通过信号输入端N3与RFIC的第三射频信号输出端F3连接，PA4裸芯片通过信号输入端N4与RFIC的第四射频信号输出端F4连接。PA1裸芯片的具体工作方式参考图5所示的PA1的相关描述，PA2裸芯片、PA3裸芯片和PA4裸芯片的具体工作方式参考图5所示的PA2的相关描述，在此不再赘述。
通常，针对同一频段的信号，不同国家或地区所采用的通信频段存在细微差别。例如，针对低频频段的信号，一些地区可能采用标准38101-3-g21中频段号为LB1的频段，一些地区可能采用标准38101-3-g21中频段号为LB2的频段。基于此，为了适用多种通信频段，对于用于放大同一频段范围的信号的功率放大器(例如PA1)，可以提供多个输出端口，每一个输出端口适用一种射频频段，PA裸芯片的输出端通过开关组中的开关与其中一个输出端口连接。此外，开关组还包括与输出端口一一对应连接的结点，各结点通过不同的射频信号线与各输出端口一一对应连接。其中，用于连接各结点与各输出端口的射频信号线，是基于输出端口所提供的射频频段决定的。具体的，如图9所示，PA1裸芯片后一级PA的输出端通过开关组1连接至输出端口Po1或者输出端口Po2，其中，用于连接开关组1的一个结点与输出端口Po1的射频信号线可以为适用于标准38101-3-g21中频段号为 N40的射频信号线，用于连接开关组1的另外一个节点与输出端口Po2的射频信号线可以为适用于标准38101-3-g21中频段号为N41的射频信号线；PA3裸芯片后一级PA的输出端通过开关组2连接至输出端口Po4、输出端口Po5或者输出端口Po6，其中，用于连接开关组2的第一结点与输出端口Po4的射频信号线可以为适用于标准38101-3-g21中频段号为MB39的射频信号线，用于连接开关组2的第二结点与输出端口Po5的射频信号线可以为适用于标准38101-3-g21中频段号为MB3的射频信号线，用于连接开关组2的第三结点与输出端口Po6的射频信号线可以为适用于标准38101-3-g21中频段号为MB1的射频信号线；PA4裸芯片后一级PA的输出端通过开关组3连接至输出端口Po7、输出端口Po8或者输出端口Po9，其中，用于连接开关组3的第一结点与输出端口Po7的射频信号线可以为适用于标准38101-3-g21中频段号为LB8的射频信号线，用于连接开关组3的第二结点与输出端口Po8的射频信号线可以为适用于标准38101-3-g21中频段号为LB28的射频信号线，用于连接开关组3的第三结点与输出端口Po9的射频信号线可以为适用于标准38101-3-g21中频段号为LB20的射频信号线。需要说明的是，PA1、PA3和PA4所对应的输出端的数目仅是示意性的，可以理解的是，PA1、PA3和PA4可以分别对应更多或更少的输出端，相应的，每一个开关组中可以包括更多或更少的开关。此外，如图9所示的功率放大器芯片11还包括输出端口Po3。PA2裸芯片的后一级PA的输出端通过射频信号线与输出端口Po3连接。输出端口Po3可以支持标准38101-3-g21中频段号为MHB3的射频信号。
请继续参看图9，在图9中，控制器CR通过数据输入端SDATA与RFIC的数据输出端SD连接，控制器CR通过时钟信号端SCLK与RFIC的时钟输出端SC连接，控制器CR通过电池端VBAT与外部电池连接。在功率放大器芯片11内部，控制器CR的控制端A1与PA1的增益调节端A1连接，控制器CR的控制端A11与PA1的使能端A11连接；控制器CR的控制端A2与PA2的增益调节端A2连接，控制器CR的控制端A12与PA2的使能端A12连接；控制器CR的控制端A3与PA3的增益调节端A3连接，控制器CR的控制端A13与PA3的使能端A13连接；控制器CR的控制端A4与PA4的增益调节端A4连接，控制器CR的控制端A14与PA4的使能端A14连接；控制器CR的控制端A5与第一开关组1的控制端A5连接；控制器CR的控制端A6与第二开关组2的控制端A6连接；控制器CR的控制端A7与第三开关组3的控制端A3连接；控制器CR的控制端A8与开关K1的控制端连接；控制器CR的控制端A9与开关K2的控制端连接；控制器CR的控制端A10与开关K3的控制端连接。
具体的，控制器CR可以基于时钟信号端SCLK提供的时钟周期工作。基于时钟信号端SCLK提供的时钟周期，控制器CR可以从数据输入端SDATA接收数据。该数据是RFIC通过总线发送给控制器CR的，实现工作方式控制。控制器CR可以对所接收到的数据进行解析，基于解析结果，确定出用于发射信号的功率放大器、所选用的功率放大器的增益、所选用的通信频段、和各功率放大器的供电模式(PAT供电模式或者ET供电模式)等信息。然后，基于所确定出的信息控制PA1、PA2、PA3或者PA4中的一个或多个使能，调节PA1、PA2、PA3或者PA4中的一个或多个的增益，以及控制开关组K1、开关组K3或者开关组K4的通路。以使一个或多个PA将输出端输出的信号通过天线传输至网络设备。
作为示例，假设采用PA1发射第一射频信号、采用PA3发射第二射频信号，PA1的后一级PA采用APT模式供电，PA3的后一级PA采用APT模式供电，PA1通过通信协议中的N41频段发射信号，PA3通过通信协议中的MB39频段发射信号。RFIC可以将PA1的配置信息和PA3的配置信息，通过与数据输出端SD连接的总线传输至功率放大器芯片11的数据输入端SDATA，然后通过数据输入端SDATA提供给控制器CR。控制器CR基于所接收到的数据，控制PA1和PA3使能，调节PA1和PA3的增益，将PA1的输出端连接至输出端口Po1(假设输出端口Po1支持N41频段)，将PA3的输出端连接至输出端口Po4(假设输出端口Po4支持MB39频段)。此外，控制器CR还可以控制开关K1、开关K2和开关K3均导通。
上述配置信息可以承载于帧格式中传输。该帧格式可以包括用于指示功率放大器的字段、用于指示所采用的射频频段的字段和用于指示所采用的供电模式的字段等。具体场景中，还可以包括比上述帧格式所包括的字段更多或者更少的字段，根据场景的需要设置。各个字段可以通过多位比特位指示。例如，以指示PA的字段为例，可以采用四位比特位，每一位代表一个PA。例如，当采用PA1和PA3发射射频信号时，则该字段相应的比特位可以设置为“1010”。此外，控制器CR还可以控制开关K1、开关K3和开关K3均导通。
在本实施例一种可能的实现方式中，终端设备可以复用功率放大器芯片11的输出端接收下行信号，然后通过功率放大器芯片11的输出端传输至RFIC。具体的，如图10所示。在图10中，功率放大器芯片11还包括信号接收端RX1和信号接收端RX2。其中，信号接收端RX1和信号接收端RX2分别用于接收不同频率的射频信号。此外，功率放大器芯片11的输出端口Po1和输出端口Po2分别连接至RFIC的信号接收端RN1和信号接收端RN2；功率放大器芯片11内部的开关组1还包括用于将输出端口Po1与PA1的输出端连接或者与信号接收端RX1连接的开关，开关组1还包括用于将输出端口Po2与PA1的输出端连接或者与信号接收端RX2连接的开关。控制器CR的控制端A5还用于控制开关组1中的开关，使得输出端口Po2与PA1的输出端连接或者与信号接收端RX2连接。具体的，RFIC将用于指示发射信号或者接收信号的指示信息通过数据输入端SDATA发送给控制器CR，控制器CR基于解析结果控制开关组1中的各开关。
需要说明的是，如图9和图10所示的功率放大器芯片11还包括公共地端G，功率放大器芯片11内部的各地端均可以连接至公共地端G，该公共地端G可以与第一电源芯片、第二电源芯片和RFIC的公共地端连接，从而功率放大器芯片11、第一电源芯片、第二电源芯片和RFIC可以具有共同的公共电压参考信号。
本申请各实施例所示的PA适用于通信制式各种物理信道，也即是说可以对各种信道传输的信号进行功率放大。该信道可以包括但不限于：PUCCH信道、PUSCH信道、PRACH信道和SRS信道。其中，不同的信道所采用的增益可以不同。当终端设备需要发射信号(此时PA由关断状态转为使能状态)之前，或者由采用第一类型信道(如PUCCH信道)发射信号转为采用第二类型信道(如PUSCH信道)发射信号(此时PA由采用第一增益发送信号转换为采用第二增益发送信号)之前，均需要对PA进行配置(包括控制PA使能或者改变PA增益等)。其中，RFIC可以基于网络设备下发的帧格式承载的信息对PA的功率进行配置，然后将PA的配置信息传输至控制器CR，以使得控制器CR控制PA使能，以及对PA进行增益调节，以使得PA正常工作。具体场景中，终端设备中的通信装 置(例如包括基带处理器、RFIC和天线)可以监听网络设备发送的测量信息，然后对所接收到的测量信息进行解析，基于解析结果确定出与网络设备进行数据传输时用于承载数据的帧格式、各类型的数据进行传输的时间、用于进行数据传输的信道等信息。请参考图11，其示意性的示出了网络设备下发的帧格式的一个示意图。在图11中可以看出，每一帧数据可以包括两个时隙，每个时隙又可以包括14个符号。此外，承载于图11所示的帧格式中的信息还包括信号传输的起始符号，以及哪几个符号采用哪种信道进行信号传输。在图11中，示意性的示出了时隙8中的符号12开始进行信号传输。其中，时隙8中的符号12和符号13采用PUCCH信道进行信号传输；时隙9中的符号0至符号11采用PUSCH信道进行信号传输；时隙9中的符号12至符号13采用SRS信道进行信号传输。也即，时隙8中的符号12起始前，PA处于关断状态，在时隙8中的符号12开始，PA由关断状态转为使能状态。时隙9中的符号0之前，PA采用第一增益进行信号传输，时隙9中的符号0开始，PA采用第二增益进行信号传输。RFIC向控制器CR传输的PA配置信息中，还包括控制PA使能的时间以及调节PA增益的时间。通常，在距离信号开始传输之前的第一预设时间段或者在距离信道转换之前的第二预设时间段控制PA使能，或者调节PA增益。例如，在图12所示的时序中，假设T2时刻开始，PA采用第一增益进行信号传输，其对应图11所示的时隙8中的符号12起始时刻，假设T3时刻开始，PA采用第二增益进行信号传输，其对应图11所示的时隙9中的符号0起始时刻。那么，传统技术中，在T1时刻，调节PA增益以及控制PA使能，在T2时刻，调节PA增益，以使得PA采用第二进行信号传输。其中，T2减去T1的时间段t1与T3减去T2的时间段t2相同或者具有较小的差异。其通常为2us左右。由于PA由关断状态转为使能状态的过程中，具有较大的时延，且在启动过程中由于外部因素等影响，通常导致输出的信号不稳定，进而导致所传输的信号具有较高的误码率。基于此，本申请实施例中，将时间段t1与时间段t2设置不同的时间段，其中，将时间段t1的长度设置为大于时间段t2的长度，也即提前启动PA。具体的，如图13所示时序，可以在T1时刻，调节PA增益以及控制PA使能，其余各时刻与图12所示的各时刻相同。这样一来，可以使得PA具有足够的时间进入稳定的工作状态，从而可以降低误码率。此外，还可以提高首符号的误差向量幅度(EVM)。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (12)

  1. 一种功率放大器芯片，其特征在于，包括：
    封装壳；
    多个功率放大器裸芯片，所述多个功率放大器裸芯片合封于所述封装壳中；其中，
    所述多个功率放大器裸芯片中的每一个功率放大器裸芯片包括至少一级功率放大器。
  2. 根据权利要求1所述的功率放大器芯片，其特征在于，所述多个功率放大器裸芯片分别支持不同的射频频段。
  3. 根据权利要求1或2所述的功率放大器芯片，其特征在于，所述功率放大器芯片还包括：
    第一开关，位于所述封装壳中，用于将第一电容连接在公共地与所述多个功率放大器裸芯片中的第一功率放大器裸芯片的电源端之间或者断开所述连接。
  4. 根据权利要求1-3任一项所述的功率放大器芯片，其特征在于，所述功率放大器芯片还包括第二电容和第二开关，位于所述封装壳中；
    所述第二开关用于将所述第二电容连接在公共地与所述多个功率放大器裸芯片中的第二功率放大器裸芯片的电源端之间或者断开所述连接。
  5. 根据权利要求1-4任一项所述的功率放大器芯片，其特征在于，所述功率放大器芯片还包括：
    控制器，位于所述封装壳中，所述控制器用于从无线射频集成电路接收用于指示功率放大器配置的指示信息，基于所述指示信息，控制所述多个功率放大器裸芯片中至少一个功率放大器裸芯片内的至少一级功率放大器使能，以及调节所使能的所述至少一级功率放大器的增益；
    其中，所述指示信息包括以下至少一项：所使能的所述至少一级功率放大器、功率放大器的增益、功率放大器的供电模式、功率放大器的启动时刻、调节功率放大器的增益的时刻或者所采用的所述功率放大器芯片的输出端口。
  6. 根据权利要求1-5任一项所述的功率放大器芯片，其特征在于，所述功率放大器芯片还包括：
    多个开关组，位于所述封装壳中，所述多个开关组中的第一开关组包括第一输入端和多个输出端；
    所述多个功率放大器裸芯片中的第三功率放大器裸芯片的输出端与所述多个开关组中至少一个第一开关组的第一输入端连接，所述至少一个第一开关组中的每个第一开关组的多个输出端与所述功率放大器芯片的多个输出端口中的至少部分输出端口连接。
  7. 根据权利要求6所述的功率放大器芯片，其特征在于，所述至少一个第一开关组中的第二开关组包括第二输入端；
    所述第二输入端与所述功率放大器芯片的射频信号接收端连接；
    所述第二开关组中的开关基于控制信号，将所述射频信号接收端与所述第二开关组中多个输出端的其中一个输出端连接。
  8. 根据权利要求1-7任一项所述的功率放大器芯片，其特征在于，所述每一个功率放大器裸芯片中所述至少一级功率放大器的第一功率放大器，包括第一增益和第二增益；其 中，
    所述第一功率放大器启动的时刻与所述第一功率放大器开始传输信号的时刻之间的第一时间段，大于将所述第一功率放大器开始由所述第一增益调节至所述第二增益的时刻与所述第一功率放大器采用所述第二增益开始传输信号的时刻之间的第二时间段。
  9. 一种通信设备，其特征在于，所述通信设备包括电源设备以及如权利要求1-8任一项所述的功率放大器芯片；其中，
    所述电源设备中的第一电源设备用于向所述功率放大器芯片中的第一功率放大器裸芯片供电；
    所述电源设备中的第二电源设备用于向所述功率放大器芯片中的其余功率放大器裸芯片供电。
  10. 根据权利要求9所述的通信设备，其特征在于，所述通信设备还包括：
    无线射频集成电路，用于向多个功率放大器裸芯片中的至少一个功率放大器裸芯片集成的功率放大器传输射频信号。
  11. 根据权利要求10所述的通信设备，其特征在于，所述电源设备还用于：
    从所述无线射频集成电路接收指示信号，基于所示指示信号，采用所述指示信号所指示的供电模式向所述功率放大器供电，所述供电模式包括平均功率追踪模式或者包络追踪模式。
  12. 根据权利要求9-11任一项所述的通信设备，其特征在于，所述通信设备还包括第一电容；
    所述第一电容基于第一开关的控制，连接在公共地与所述第一功率放大器裸芯片的电源端之间或者断开所述连接。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115395965A (zh) * 2022-09-01 2022-11-25 深圳市创凌智联科技有限公司 三频智能Mesh路由器

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100148357A1 (en) * 2008-12-16 2010-06-17 Freescale Semiconductor, Inc. Method of packaging integrated circuit dies with thermal dissipation capability
US20150145737A1 (en) * 2012-11-19 2015-05-28 Broadcom Corporation Reflective Beamforming For Performing Chip-to-Chip And Other Communications
CN205319143U (zh) * 2015-12-31 2016-06-15 无锡华润矽科微电子有限公司 一种封装有多个音频功率放大芯片的电路结构
CN107819441A (zh) * 2017-12-08 2018-03-20 成都聚利中宇科技有限公司 高频功率放大器封装模块
CN210403716U (zh) * 2019-11-08 2020-04-24 嘉盛半导体(苏州)有限公司 射频功放模组封装结构及通信基站

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2879882B1 (fr) * 2004-12-22 2007-05-18 Sagem Procede et systeme d'autocalibration d'une chaine d'emission d'un terminal mobile par l'utilisation d'un recepteur umts ou gsm embarque
US7676239B1 (en) * 2005-02-24 2010-03-09 National Semiconductor Corporation System and method for providing a power controller with flat amplitude and phase response
JP2007312031A (ja) * 2006-05-17 2007-11-29 Matsushita Electric Ind Co Ltd 電子デバイス
US8255009B2 (en) * 2008-04-25 2012-08-28 Apple Inc. Radio frequency communications circuitry with power supply voltage and gain control
US8598950B2 (en) * 2010-12-14 2013-12-03 Skyworks Solutions, Inc. Apparatus and methods for capacitive load reduction
JP2015529408A (ja) * 2012-08-17 2015-10-05 ▲華▼▲為▼▲終▼端有限公司 電力消費を低減する無線端末および無線端末の電力消費を低減するための方法
CN104158505A (zh) * 2013-05-14 2014-11-19 中兴通讯股份有限公司 一种射频功放电路、控制方法及终端
CN104753476B (zh) * 2013-12-30 2018-05-18 国民技术股份有限公司 多模多频功率放大器
CN106561009B (zh) * 2015-09-30 2020-07-31 展讯通信（上海）有限公司 无线通信系统中的信号中继放大系统和方法
CN106330247B (zh) * 2016-08-31 2019-11-08 成都大奇鹰科技有限公司 一种功率放大电路及功率放大盒
CN107707251B (zh) * 2017-06-20 2021-05-14 深圳市锐能微科技有限公司 一种信号发射功率控制方法及装置
CN109787569B (zh) * 2017-11-14 2023-08-01 锐迪科微电子科技（上海）有限公司 一种多模多频射频功率放大器
CN108601078A (zh) * 2018-03-19 2018-09-28 四川斐讯信息技术有限公司 一种路由器和路由器发射功率的调节方法
CN108683435A (zh) * 2018-04-13 2018-10-19 维沃移动通信有限公司 一种终端设备及其控制方法
CN111277296B (zh) * 2020-02-25 2021-07-02 Oppo广东移动通信有限公司 射频电路、射频芯片和电子设备
CN111313854B (zh) * 2020-02-25 2022-10-14 广州慧智微电子股份有限公司 一种射频功率放大器电路及增益控制方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100148357A1 (en) * 2008-12-16 2010-06-17 Freescale Semiconductor, Inc. Method of packaging integrated circuit dies with thermal dissipation capability
US20150145737A1 (en) * 2012-11-19 2015-05-28 Broadcom Corporation Reflective Beamforming For Performing Chip-to-Chip And Other Communications
CN205319143U (zh) * 2015-12-31 2016-06-15 无锡华润矽科微电子有限公司 一种封装有多个音频功率放大芯片的电路结构
CN107819441A (zh) * 2017-12-08 2018-03-20 成都聚利中宇科技有限公司 高频功率放大器封装模块
CN210403716U (zh) * 2019-11-08 2020-04-24 嘉盛半导体(苏州)有限公司 射频功放模组封装结构及通信基站

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4184575A4 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115395965A (zh) * 2022-09-01 2022-11-25 深圳市创凌智联科技有限公司 三频智能Mesh路由器
CN115395965B (zh) * 2022-09-01 2023-05-09 深圳市创凌智联科技有限公司 三频智能Mesh路由器

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