WO2022033466A1 - 一种电容测量电路 - Google Patents

一种电容测量电路 Download PDF

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Publication number
WO2022033466A1
WO2022033466A1 PCT/CN2021/111758 CN2021111758W WO2022033466A1 WO 2022033466 A1 WO2022033466 A1 WO 2022033466A1 CN 2021111758 W CN2021111758 W CN 2021111758W WO 2022033466 A1 WO2022033466 A1 WO 2022033466A1
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capacitance
value
stage circuit
digital signal
capacitor
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PCT/CN2021/111758
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English (en)
French (fr)
Inventor
曾衍瀚
植浩昌
陈涌楠
陈俊凯
杨敬慈
吴添贤
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广州大学
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Application filed by 广州大学 filed Critical 广州大学
Publication of WO2022033466A1 publication Critical patent/WO2022033466A1/zh
Priority to US18/299,088 priority Critical patent/US20230314495A1/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
    • G01R27/2605—Measuring capacitance

Definitions

  • the present invention relates to the technical field of integrated circuits, in particular to a capacitance measurement circuit.
  • Capacitance measurement is a conventional technology in the field of integrated circuits, and with the development of science and technology, the accuracy requirements for capacitance measurement are getting higher and higher, especially when the capacitance value is small (below 200f).
  • the capacitance value of the capacitance to be measured is calculated by comparing and calculating the capacitance value of the capacitance to be measured by applying a current or voltage to the capacitance to be measured after designing a detection circuit.
  • the prior art is limited by the accuracy requirements of each device in a real circuit, and its error margin is relatively high, so it is practically impossible to achieve the same or similar data as theoretically. If the components with higher precision are replaced, the circuit cost will be greatly increased, which is not conducive to expansion and application.
  • Embodiments of the present invention provide a capacitance measurement circuit, which can detect a small capacitance value in a wide range through two measurements, reduce measurement errors, and improve measurement accuracy.
  • the invention provides a capacitance measurement circuit, comprising: an analog pre-stage circuit, a parasitic capacitance, an ADC module, an output shift register and a controller;
  • the input end of the ADC module is connected with the output end of the analog pre-stage circuit, and the output end of the ADC module is connected with the output shift register;
  • the controller is used to control the analog pre-stage circuit, the parasitic capacitance, the ADC module and the output shift register to perform capacitance measurement on the capacitance to be measured, specifically:
  • the first digital signal is used as the capacitance measurement value of the capacitance to be measured.
  • connection number m of the current mirror circuit is determined, specifically:
  • D max is the maximum output value of the ADC module
  • the value of the first digital signal is less than D max /2 but greater than D max /8, the value of the connection number m is 2;
  • the value of the connection number m is 2 i-1 , where i is a positive integer greater than or equal to 3.
  • the output shift register is controlled to shift the second digital signal to obtain the capacitance measurement value of the capacitance to be measured, specifically:
  • connection number m If the value of the connection number m is 1, the output shift register is controlled not to shift the second digital signal, and the capacitance measurement value of the capacitance to be measured is obtained;
  • the output shift register is controlled to move the second digital signal to the right by 1 bit to obtain the capacitance measurement value of the capacitance to be measured;
  • the output shift register is controlled to shift the second digital signal by i-1 bits to the right, to obtain the capacitance measurement value of the capacitance to be measured.
  • the analog pre-stage circuit includes: an operational amplifier module, a first capacitor, a second capacitor, a voltage follower, and the M parallel current mirror circuits;
  • a current mirror circuit includes two current mirror circuits with a width to length ratio of 1:1, and an inverter between the two current mirror circuits;
  • the forward input terminal of the operational amplifier module is connected to the input terminal of the analog pre-stage circuit, the reverse input terminal of the operational amplifier module is connected to the first terminal of the first capacitor, and the output end is connected to the M parallel current mirror circuits;
  • the input end of the voltage follower is respectively connected with the first end of the second capacitor and the M parallel current mirror circuits, and the output end of the voltage follower is connected with the output end of the analog pre-stage circuit ;
  • the second end of the first capacitor and the second end of the second capacitor are respectively connected to the signal ground.
  • analog pre-stage circuit also includes several control switches and several MOS tubes;
  • the controller controls the analog pre-stage circuit by controlling the plurality of control switches and MOS transistors.
  • the input end of the analog pre-stage circuit is connected to the capacitor to be measured, specifically:
  • the input end of the analog pre-stage circuit is connected to the capacitor to be measured through the control switch S3;
  • the controller is also used to control the on-off of the control switch S3 to control the connection or disconnection of the capacitor to be measured.
  • the input end of the ADC module is connected with the output end of the analog pre-stage circuit, specifically:
  • the reverse input end of the ADC module is connected to the output end of the analog pre-stage circuit through the control switch S4, and the non-inverting input end of the ADC module is connected to the output end of the analog pre-stage circuit;
  • the controller is also used to control the on-off of the control switch S4 to control the connection or disconnection of the reverse input end of the ADC module.
  • the capacitance measurement circuit includes an analog pre-stage circuit, a parasitic capacitance, an ADC module, an output shift register and a controller; wherein, M parallel current mirror circuits are arranged in the analog pre-stage circuit.
  • the controller first disconnects the access of the capacitor to be measured, only connects one current mirror circuit, charges the parasitic capacitor and simulates the output of the previous stage circuit, records the AFE output voltage V N collected by the reverse input end of the ADC module, and then connects After the analog front-end circuit is stabilized, the AFE output voltage V P of the non-inverting input end of the ADC module is collected, and the value of (V P - V N ) is converted into a first digital signal; according to the first digital signal , determine the connection number m of the current mirror circuit, control the analog front-stage circuit to connect m current mirror circuits, and repeat the above steps to obtain the second digital signal; finally, the second digital signal is shifted according to the connection number m, Obtain a capacitance measurement for the capacitance to be measured.
  • the present invention firstly obtains the interval where the capacitance to be measured is located through the first rough measurement, and then uses m current mirror circuits to connect and then perform the fine side measurement. , to obtain the capacitance measurement of the capacitance to be measured.
  • the invention realizes the detection of the smaller capacitance value in a wide range through two measurements, reduces the measurement error and improves the measurement accuracy.
  • FIG. 1 is a schematic structural diagram of an embodiment of a capacitance measurement circuit provided by the present invention.
  • FIG. 2 is a schematic flowchart of an embodiment of a capacitance measurement method provided by the present invention
  • FIG. 3 is a schematic structural diagram of another embodiment of the capacitance measurement circuit provided by the present invention.
  • FIG. 5 is a corresponding diagram of a capacitance-voltage conversion relationship of a circuit according to an embodiment of the present invention.
  • FIG. 1 it is a schematic structural diagram of an embodiment of a capacitance measurement circuit provided by the present invention.
  • the circuit includes an analog pre-stage circuit 101 , an ADC module 102 , an output shift register 103 , a parasitic capacitor 104 and a controller 105 .
  • the input end of the ADC module 102 is connected to the output end of the analog pre-stage circuit 101 , and the output end of the ADC module 102 is connected to the output shift register 101 .
  • the input terminals of the analog pre-stage circuit 101 are respectively connected to the parasitic capacitance 104 and the capacitance to be measured; wherein, the analog pre-stage circuit 101 is provided with M parallel current mirror circuits 1011 .
  • M 2 N-1 , where N is a positive integer.
  • FIG. 2 is a schematic flowchart of an embodiment of a capacitance measurement method provided by the present invention. As shown in FIG. 2, the process includes steps S1 to S6, and each step is as follows:
  • step S4 the controller controls the analog front-end circuit to connect only one current mirror circuit, and the ADC module separately collects the AFE output voltage before and after the capacitor to be measured is connected (before the analog circuit is connected) stage circuit, referred to as AFE), to complete the first rough measurement of capacitance.
  • Step S5 is to determine the interval where the capacitance to be measured is located according to the result of the rough measurement, so as to determine the connection number m of the current mirror circuit.
  • Step S6 is to perform fine measurement on the capacitance to be measured after the m current mirror circuits are turned on, and perform a shift process on the fine measurement result to obtain a final measured capacitance value.
  • the first digital signal can be used as the capacitance measurement value of the capacitance to be measured to improve the measurement efficiency .
  • connection number m of the current mirror circuit is determined, specifically:
  • D max is the maximum output value of the ADC module
  • the value of the first digital signal is less than D max /2 but greater than D max /8, the value of the connection number m is 2;
  • the value of the connection number m is 2 i-1 ; where i is a positive integer greater than or equal to 3.
  • the maximum output value of the ADC module is used as a judgment parameter to confirm the number of connections m required for the capacitor to be measured, and since the number of connections of the current mirror circuit M is 2 N-1 , when the number of connections m is When it is 1, the interval corresponding to the first digital signal is (D max /2, D max ); when the number of connections m is 2, the interval corresponding to the first digital signal is (D max /8, D max /2); When the number m is 4, the interval corresponding to the first digital signal is (D max /16, D max /8); when the number m of connections is i, the interval corresponding to the first digital signal is (D max /2 i+1 , D max /2 i ), where i is a positive integer greater than or equal to 3.
  • the output shift register is controlled to shift the second digital signal to obtain the capacitance measurement value of the capacitance to be measured, specifically:
  • the output shift register is controlled not to shift the second digital signal, and the capacitance measurement value of the capacitance to be measured is obtained;
  • the output shift register is controlled to move the second digital signal to the right by 1 bit to obtain the capacitance measurement value of the capacitance to be measured;
  • the output shift register is controlled to move the second digital signal to the right by i-1 bits to obtain the capacitance measurement value of the capacitance to be measured.
  • the digital signal is shifted to the right by 1 bit; 4 current mirror circuits are connected, the digital signal is shifted to the right by 2 bits; 8 current mirror circuits are connected , the digital signal is shifted to the right by 3 bits.
  • FIG. 3 is a schematic structural diagram of another embodiment of the capacitance measurement circuit provided by the present invention.
  • the analog pre-stage circuit includes: an operational amplifier module 1013 , a first capacitor C offset , a second capacitor C y , a voltage follower 1014 and M parallel current mirror circuits 1011 .
  • one current mirror circuit includes two current mirror circuits with a width to length ratio of 1:1, and an inverter 1012 disposed between the two current mirror circuits.
  • the forward input terminal of the operational amplifier module 1013 is connected to the input terminal of the analog pre-stage circuit, the reverse input terminal of the operational amplifier module 1013 is connected to the first terminal of the first capacitor C offset , and the output terminal of the operational amplifier module 1013 is connected to M
  • the parallel current mirror circuits 1011 are connected.
  • the input end of the voltage follower 1014 is connected to the first end of the second capacitor Cy and the M parallel current mirror circuits 1011 respectively, and the output end of the voltage follower 1014 is connected to the output end of the analog pre-stage circuit.
  • the second end of the first capacitor C offset and the second end of the second capacitor C y are respectively connected to the signal ground.
  • the analog pre-stage circuit further includes several control switches and several MOS transistors.
  • the controller 105 controls the analog pre-stage circuit by controlling several control switches (S1, S2) and MOS transistors.
  • the input end of the analog pre-stage circuit is connected to the capacitor C x to be measured, specifically: the input end of the analog pre-stage circuit is connected to the capacitor C x to be measured through the control switch S3.
  • the controller 105 is also used to control the on-off of the control switch S3 to control the connection or disconnection of the capacitor to be measured.
  • the input end of the ADC module 102 is connected to the output end of the analog pre-stage circuit 101, specifically: the reverse input end of the ADC module 102 is connected to the output end of the analog pre-stage circuit 101 through the control switch S4, and the same-direction input of the ADC module 102
  • the terminal is connected to the output terminal of the analog pre-stage circuit 102 .
  • the controller 105 is also used to control the on-off of the control switch S4, so as to control the connection or disconnection of the reverse input end of the ADC module.
  • the analog pre-stage circuit 101 is used to linearly and correspondingly convert the input capacitance value of the capacitance to be measured into a voltage value that can be measured by the ADC module 102 .
  • Its internal operational amplifier module 1013 is a first-stage operational amplifier with low offset voltage.
  • C offset is a picofarad capacitor used to store the output offset voltage of the op amp during calibration.
  • Vref is the first reference voltage introduced externally, and Cy is the capacitor for collecting the charge.
  • the voltage follower 1014 adopts a one-stage or two-stage structure to isolate the ADC module 102 and the analog pre-stage circuit 101 and provide impedance matching.
  • the current mirror circuit in the center of the analog pre-stage circuit 101 includes two current mirror circuits with a width to length ratio of 1:1.
  • the aspect ratio is the ratio of the length and width of the conductive channel of the MOS tube, which determines the multiple of the source and drain currents flowing into and out of the MOS tube under the same four port voltages.
  • the parallel circuit differs in that the inputs to the inverters are A[0] to A[M-1].
  • A[M-1:0] is generated by the controller 105 and is used to control the gain multiplier of the charge flowing into Cy , and is a digital signal of M.
  • the whole circuit uses 8 switches, among which, S3 controls any form of off-chip switches, and the remaining 7 switches are on-chip MOS transistor switches.
  • S3 controls any form of off-chip switches
  • the remaining 7 switches are on-chip MOS transistor switches.
  • the function of each switch is briefly described as follows:
  • Control switch S1 control the initialization of the analog front-end circuit
  • Control switch S2 a control signal connecting the off-chip and on-chip circuits
  • Control switch S3 control whether the off-chip capacitor C x to be measured is connected
  • Control switch S4 the input terminal switching signal of the ADC module.
  • the ADC module 102 has differential input and parallel output, and is used to convert the voltage value output by the analog pre-stage circuit 101 into a digital quantity.
  • the controller 105 is used to generate the control sequence logic for controlling the switches S1 to S4 to control the switches in the analog pre-stage circuit 101 to close, to provide the ADC module 102 with clock signals and sampling control signals, and to provide shift control for the output shift register 103 signal, and the signal for controlling A[M-1:0] according to the first digital signal output by the ADC module 102 .
  • the output shift register 103 is a shift register with the same width as the output bit width of the ADC module 102 , and is used to perform a shift operation on the output digital quantity of the ADC module 102 .
  • the parasitic capacitance C para is the capacitance of the pad inside and outside the chip. After the chip is packaged, it needs to lead out the pins to the outside, so that it can be used.
  • Pad is the metal that connects the inside and outside of the chip, and this layer of metal will have parasitic capacitance with the inside and outside.
  • T0 Set A to (0001) 2 to start capacitance measurement.
  • T1 The switches S1 and S4 are closed, the circuit is initialized, the feedback loop of the non-inverting input terminal of the operational amplifier module 1013 is disconnected, the feedback loop of the inverting input terminal is turned on, the offset voltage V offset of the operational amplifier is saved to C offset , C y is The initial value is Vref, and the inverting input terminal of the ADC module 102 continuously collects the AFE output voltage before the capacitor Cx to be measured is connected.
  • T2 The switch S1 is turned off, S2 and S4 are turned on, the measurement pin of the chip is turned on, and the switch for initialization is turned off.
  • the inverting input voltage of the op amp module 1013 is V offset , which offsets the op amp module 1013 the offset voltage.
  • the equivalent parasitic capacitance 104 parasitic on the Pad and the external wiring is charged to Vref.
  • T3 The switch S4 is turned off, S2 is turned on, and the inverting input terminal of the ADC module 102 is disconnected. At this time, the AFE output voltage before being connected to the capacitor C x to be measured has been saved to the inverting input terminal of the ADC module 102, which is denoted as V N .
  • T4 The switches S2 and S3 are closed, the capacitor C x to be measured is connected, the non-inverting input terminal of the operational amplifier module 1013 is pulled down, and the push-pull stage is controlled to supplement the charge.
  • the current mirror circuit 1011 injects M times the charge into Cy , and after the circuit is stabilized, the upper plate voltage VP of Cy is saved to the non-inverting input terminal of the ADC module 102, and the ADC module 102 starts to convert VP -V value of N.
  • T5 The first acquisition is completed, all switches are turned off, the output value of the ADC module 102 is D1, assuming that the maximum output value of the ADC module 102 is D max , if D1 is greater than D max /2, then A remains unchanged. If D1 is less than D max /2 but greater than D max /8, set A to (0011) 2 . If D1 is less than D max /8, A is set to (1111) 2 , and so on.
  • T6 According to the obtained number of accesses of the current mirror circuit, perform T1 to T4 again to obtain the second output D2 of the ADC module 102, send D2 to the output shift register, and perform D2 according to the number of accesses Right-shift 1-bit operation, repeat the right-shift not more than M/2 integer times to obtain the actual measurement value.
  • FIG. 5 shows the corresponding diagram of the capacitance-voltage conversion relationship of the circuit.
  • the connected capacitance of the capacitance value to be measured is converted into a voltage value linearly corresponding to a certain capacitance value. Since the rough side has been passed first, a fine measurement can be performed again with different M values according to the first measurement value, so Figure 5 is a segmented linear waveform.
  • C x,max is the maximum capacitance value that the circuit can measure
  • V max is the maximum voltage value output by the analog pre-stage circuit
  • its units are fF and V respectively.
  • M is the number of parallel connections
  • ⁇ is the amount of change in the AFE output voltage after the 1fF capacitor is connected when A is (0001) 2 , that is
  • the measured capacitance is less than At this time, the charge transfer caused by the access to the capacitor to be measured is less, so the signal input to the AFE is weak. At this time, the signal-to-noise ratio of the input signal is too low to limit the measurement accuracy, so the power of the effective signal should be increased to improve the signal-to-noise ratio. .
  • the capacitance value read by the sub-sampling ADC is M times the actual value.
  • Vref is set as a higher voltage, and a Vref of 2V is used in the circuit implemented in this paper; capacitance is greater than When the power supply voltage of the output stage is 3.3V, the effective upper swing is less than 1.3V, and the connection of a capacitor larger than that will cause the voltage to be unable to be maintained because the swing of the output stage is insufficient, so it should be considered to reduce the power of the effective signal and Guaranteed biasing of the output stage.
  • Figure 5 shows the case where M is set to 4.
  • the capacitance of 1C corresponds to the change of the AFE output voltage when A is (0001) 2 , and the corresponding value of V after being measured by the ADC The number is 1 LSB.
  • the capacitance of 1C corresponds to 1 LSB of the ADC output digital quantity, and judge the access to be measured according to the digital quantity obtained by the "coarse measurement” What range is the capacitor in?
  • the capacitance of 1C corresponds to 4 LSBs of the ADC output digital quantity, so the ADC output digital quantity needs to be shifted to the left by 2 bits. if in In this interval, set A as (0011) 2 , and perform another measurement. At this time, the capacitance of 1C corresponds to 2 LSBs of the ADC output digital quantity, and then the result is shifted to the left by 1 bit.
  • the measuring circuit of the present invention realizes the function of detecting and outputting small capacitances in a large range, and has the characteristics of high precision.
  • the invention provides an approximation type AFE based on the charge transfer type, which performs two measurements of coarse side and fine measurement for capacitors of different sizes under a wide range of capacitance to be measured, so as to obtain the best measurement value.
  • the present invention designs a simple and effective control sequence and a corresponding logic circuit, and designs a SAR ADC comparator with an offset voltage calibration technology, thereby improving the accuracy of the ADC.
  • the present invention proposes a matching intermediate structure (high-precision follower) of the AFE and the ADC, which isolates the AFE and the ADC, uses a sleeve-type folded common-gate op amp as the first stage to improve the gain, and uses a push-pull structure for the second stage. So that the follower can drive a large capacitance, and at the same time, it has the characteristics of high precision and will not cause errors.
  • the device embodiments described above are only schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physically separated unit, that is, it can be located in one place, or it can be distributed over multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution in this embodiment.
  • the connection relationship between the modules indicates that there is a communication connection between them, which may be specifically implemented as one or more communication buses or signal lines. Those of ordinary skill in the art can understand and implement it without creative effort.

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Abstract

本发明公开了一种电容测量电路，包括模拟前级电路、寄生电容、ADC模块、输出移位寄存器和控制器；模拟前级电路内设置有M个并联的电流镜电路。控制器先断开待测电容的接入，只连通一个电流镜电路，通过寄生电容充电和模拟前级电路的输出，记录ADC模块的反向输入端采集的AFE输出电压V N，然后再接入待测电容，采集ADC模块的同向输入端的AFE输出电压V P，并将(V P-V N)的值转换为第一数字信号；根据第一数字信号的值，确定电流镜电路的连通数量m，控制模拟前级电路连通m个电流镜电路，再重复上述步骤后获得第二数字信号；最后根据连通数量m对第二数字信号进行移位处理，获得待测电容的电容测量值。采用本发明技术方案能够降低测量误差，提高测量精度。

Description

一种电容测量电路 技术领域
本发明涉及集成电路技术领域，尤其涉及一种电容测量电路。
背景技术
电容测量是在集成电路领域中的常规技术，而随着科技的发展，对于电容测量的精度要求也越来越高，特别是电容值较小的情况(200f以下)。现有技术对于电容测量主要是通过设计检测电路后对待测电容施加电流或电压，通过比较计算出待测电容的电容值。但是针对微弱电容值的电容，现有技术会受限于真实电路中各器件的精度要求，其误差幅度较高，实际上无法达到与理论上相同或相似的数据。若更换精度更高的元器件，则会大大增加电路成本，不利于扩展和应用。
发明内容
本发明实施例提供一种电容测量电路，通过两次测量实现在大范围内对较小的电容值进行检测，降低测量误差，提高测量精度。
本发明提供了一种电容测量电路，包括：模拟前级电路、寄生电容、ADC模块、输出移位寄存器和控制器；
其中，所述ADC模块的输入端与所述模拟前级电路的输出端连接，所述ADC模块的输出端与所述输出移位寄存器连接；
所述模拟前级电路的输入端分别连接所述寄生电容和待测电容；其中，所述模拟前级电路内设置有M个并联的电流镜电路；M＝2 N-1，N为正整数；
所述控制器用于控制所述模拟前级电路、所述寄生电容、所述ADC模块和所述输出移位寄存器对所述待测电容进行电容测量，具体为：
S1、控制所述模拟前级电路只连通一个所述电流镜电路；
S2、断开所述待测电容的接入，并控制所述ADC模块的反向输入端持续采集所述模拟前级电路在接入所述待测电容前的AFE输出电压；
S3、控制所述模拟前级电路，以使所述寄生电容充电至第一参考电压，并记录所述ADC模块的反向输入端当前采集的AFE输出电压V N；
S4、接入所述待测电容，待所述模拟前级电路稳定后，控制所述ADC模块的同向输入端采集所述模拟前级电路的AFE输出电压V P，并控制所述ADC模块将(V P-V N)的值转换为第一数字信号；
S5、根据所述第一数字信号的值，确定所述电流镜电路的连通数量m，并控制所述模拟前级电路连通m个所述电流镜电路；其中，m＝2 n-1，且n为小于等于N的正整数；
S6、重复步骤S2至S4，获得第二数字信号，并根据所述连通数量m，控制所述输出移位寄存器对所述第二数字信号进行移位，获得所述待测电容的电容测量值。
进一步的，在所述S5之后，若所述连通数量m的值为1，则将所述第一数字信号作为所述待测电容的电容测量值。
进一步的，在所述S5中，根据所述第一数字信号的值，确定所述电流镜电路的连通数量m，具体为：
若所述第一数字信号的值大于D max/2，则所述连通数量m的值为1；D max为所述ADC模块的最大输出值；
若所述第一数字信号的值小于D max/2但大于D max/8，则所述连通数量m的值为2；
若所述第一数字信号的值小于D max/2 i但大于D max/2 i+1，则所述连通数量m的值 为2 i-1；其中，i为大于等于3的正整数。
进一步的，在所述S6中，根据所述连通数量m，控制所述输出移位寄存器对所述第二数字信号进行移位，获得所述待测电容的电容测量值，具体为：
若所述连通数量m的值为1，则控制所述输出移位寄存器对所述第二数字信号不进行移位，获得所述待测电容的电容测量值；
若所述连通数量m的值为2，则控制所述输出移位寄存器对所述第二数字信号向右移动1位，获得所述待测电容的电容测量值；
若所述连通数量m的值为2 i-1，则控制所述输出移位寄存器对所述第二数字信号向右移动i-1位，获得所述待测电容的电容测量值。
进一步的，所述模拟前级电路包括：运放模块、第一电容、第二电容、电压跟随器和所述M个并联的电流镜电路；
其中，一个电流镜电路包括两个宽长比为1:1的电流镜子电路、以及设置两个电流镜子电路之间的反向器；
所述运放模块的正向输入端与所述模拟前级电路的输入端连接，所述运放模块的反向输入端与所述第一电容的第一端连接，所述运放模块的输出端与所述M个并联的电流镜电路连接；
所述电压跟随器的输入端分别与所述第二电容的第一端、所述M个并联的电流镜电路连接，所述电压跟随器的输出端与所述模拟前级电路的输出端连接；
所述第一电容的第二端、所述第二电容的第二端分别与信号地连接。
进一步的，所述模拟前级电路还包括若干个控制开关和若干个MOS管；
所述控制器通过控制所述若干个控制开关和MOS管，以控制所述模拟前级电路。
进一步的，所述模拟前级电路的输入端连接所述待测电容，具体为：
所述模拟前级电路的输入端通过控制开关S3连接所述待测电容；
所述控制器还用于控制所述控制开关S3的通断，以控制所述待测电容的接入或断开。
进一步的，所述ADC模块的输入端与所述模拟前级电路的输出端连接，具体为：
所述ADC模块的反向输入端通过控制开关S4与所述模拟前级电路的输出端连接，所述ADC模块的同向输入端与所述模拟前级电路的输出端连接；
所述控制器还用于控制所述控制开关S4的通断，以控制所述ADC模块的反向输入端的接入或断开。
由上可见，本发明提供的电容测量电路，包括模拟前级电路、寄生电容、ADC模块、输出移位寄存器和控制器；其中，模拟前级电路内设置有M个并联的电流镜电路。控制器先断开待测电容的接入，只连通一个电流镜电路，通过寄生电容充电和模拟前级电路的输出，记录ADC模块的反向输入端采集的AFE输出电压V N，然后再接入待测电容，待模拟前级电路稳定后，采集ADC模块的同向输入端的AFE输出电压V P，并将(V P-V N)的值转换为第一数字信号；根据第一数字信号的值，确定电流镜电路的连通数量m，控制模拟前级电路连通m个电流镜电路，再重复上述步骤后获得第二数字信号；最后根据连通数量m对第二数字信号进行移位处理，获得待测电容的电容测量值。相比于现有技术在测量微弱电容时需依赖测量电路的元器件精度，本发明先通过第一粗测得知待测电容所在的区间，再用m个电流镜电路接入后进行细侧，获得待测电容的电容测量值。本发明通过两次测量实现在大范围内对较小的电容值进行检测，降低测量误差，提高测量精度。
附图说明
图1是本发明提供的电容测量电路的一种实施例的结构示意图；
图2是本发明提供的电容测量方法的一种实施例的流程示意图；
图3是本发明提供的电容测量电路的另一种实施例的结构示意图；
图4是本发明提供的一种实施例的电路开关时序图；
图5是本发明提供的一种实施例的电路的电容-电压转换关系对应图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
参见图1，是本发明提供的电容测量电路的一种实施例的结构示意图。如图1所示，该电路包括模拟前级电路101、ADC模块102、输出移位寄存器103、寄生电容104和控制器105。
其中，ADC模块102的输入端与模拟前级电路101的输出端连接，ADC模块102的输出端与输出移位寄存器101连接。模拟前级电路101的输入端分别连接寄生电容104和待测电容；其中，模拟前级电路101内设置有M个并联的电流镜电路1011。M＝2 N-1，N为正整数。
控制器105用于控制模拟前级电路101、寄生电容104、ADC模块102和输出移位寄存器103对待测电容进行电容测量。参见图2，图2是本发明提供的电容测量方法的一种实施例的流程示意图。如图2所示，该流程包括步骤S1至步骤S6，各步骤具体如下：
S1、控制模拟前级电路只连通一个电流镜电路。
S2、断开待测电容的接入，并控制ADC模块的反向输入端持续采集模拟前级电路在接入待测电容前的AFE输出电压。
S3、控制模拟前级电路，以使寄生电容充电至第一参考电压，并记录ADC模 块的反向输入端当前采集的AFE输出电压V N。
S4、接入待测电容，待模拟前级电路稳定后，控制ADC模块的同向输入端采集模拟前级电路的AFE输出电压V P，并控制ADC模块将(V P-V N)的值转换为第一数字信号。
S5、根据第一数字信号的值，确定电流镜电路的连通数量m，并控制模拟前级电路连通m个所述电流镜电路；其中，m＝2 n-1，且n为小于等于N的正整数。
S6、重复步骤S2至S4，获得第二数字信号，并根据连通数量m，控制输出移位寄存器对第二数字信号进行移位，获得待测电容的电容测量值。
在本实施例中，步骤S1至步骤S4是控制器通过控制模拟前级电路只连通一个电流镜电路，并由ADC模块分别采集待测电容接入前和接入后的AFE输出电压(模拟前级电路，简称AFE)，完成第一次电容的粗测。步骤S5是根据粗测的结果，确定待测电容所在的区间，从而确定电流镜电路的连通数量m。步骤S6是在接通m个电流镜电路后，对待测电容进行细测，并对细测结果进行移位处理后获得最终的电容测量值。
作为本实施例的一种举例，如果在第一次粗测时，确定的连通数量m＝1，则为了节省重复测量，可以将第一数字信号作为待测电容的电容测量值，提高测量效率。
在本实施例中，在S5中，根据第一数字信号的值，确定电流镜电路的连通数量m，具体为：
若第一数字信号的值大于D max/2，则连通数量m的值为1；D max为ADC模块的最大输出值；
若第一数字信号的值小于D max/2但大于D max/8，则连通数量m的值为2；
若第一数字信号的值小于D max/2 i但大于D max/2 i+1，则连通数量m的值为2 i-1； 其中，i为大于等于3的正整数。
在本实施例中，通过ADC模块的最大输出值作为判断参数，确认待测电容所需的连通数量m，而由于电流镜电路M的接入个数为2 N-1，则当连通数量m为1时，第一数字信号对应的区间为(D max/2，D max)；连通数量m为2时，第一数字信号对应的区间为(D max/8，D max/2)；连通数量m为4时，第一数字信号对应的区间为(D max/16，D max/8)；连通数量m为i时，第一数字信号对应的区间为(D max/2 i+1，D max/2 i)，i为大于等于3的正整数。
在本实施例中，在S6中，根据连通数量m，控制输出移位寄存器对第二数字信号进行移位，获得待测电容的电容测量值，具体为：
若连通数量m的值为1，则控制输出移位寄存器对第二数字信号不进行移位，获得待测电容的电容测量值；
若连通数量m的值为2，则控制输出移位寄存器对第二数字信号向右移动1位，获得待测电容的电容测量值；
若连通数量m的值为2 i-1，则控制所述输出移位寄存器对所述第二数字信号向右移动i-1位，获得待测电容的电容测量值。
在本实施例中，若接入了2个电流镜电路，则对数字信号进行右移1位；接入4个电流镜电路，则对数字信号右移2位；接入8个电流镜电路，则对数字信号右移3位。
为了更好的说明本发明的电路结构和工作原理，参见图3，图3是本发明提供的电容测量电路的另一种实施例的结构示意图。如图3所示，模拟前级电路包括：运放模块1013、第一电容C offset、第二电容C y、电压跟随器1014和M个并联的电流镜电路1011。其中，一个电流镜电路包括两个宽长比为1:1的电流镜子电路、以及设置两个电流镜子电路之间的反向器1012。
运放模块1013的正向输入端与模拟前级电路的输入端连接，运放模块1013 的反向输入端与第一电容C offset的第一端连接，运放模块1013的输出端与M个并联的电流镜电路1011连接。电压跟随器1014的输入端分别与第二电容C y的第一端、M个并联的电流镜电路1011连接，电压跟随器1014的输出端与模拟前级电路的输出端连接。第一电容C offset的第二端、第二电容C y的第二端分别与信号地连接。
在图3的实施例中，模拟前级电路还包括若干个控制开关和若干个MOS管。控制器105通过控制若干个控制开关(S1、S2)和MOS管，以控制模拟前级电路。
模拟前级电路的输入端连接待测电容C x，具体为：模拟前级电路的输入端通过控制开关S3连接待测电容C x。控制器105还用于控制所述控制开关S3的通断，以控制待测电容的接入或断开。
ADC模块102的输入端与模拟前级电路101的输出端连接，具体为：ADC模块102的反向输入端通过控制开关S4与模拟前级电路101的输出端连接，ADC模块102的同向输入端与模拟前级电路102的输出端连接。控制器105还用于控制所述控制开关S4的通断，以控制ADC模块的反向输入端的接入或断开。
如图3所示，模拟前级电路101用于将输入的待测电容的电容值线性对应地转换成一个可供ADC模块102测量的电压值。其内部的运放模块1013是一个低失调电压的一级运放。C offset是一个用于在校正过程中存储运放的输出失调电压的皮法电容。Vref是外部引入的第一参考电压，C y是用于收集电荷的电容。电压跟随器1014采用一级或二级结构，用于隔离ADC模块102和模拟前级电路101，并提供阻抗匹配。
模拟前级电路101中心的电流镜电路包括两个宽长比为1:1的电流镜子电路。该长宽比为MOS管导电沟道的长和宽之比，其决定了MOS管在相同的四个端口电压下，流入流出源极和漏极电流的倍数，假设在某个电路中，某个PMOS管在M＝1时，流入源极和漏极的电流为x，则把M增加到2时，该电流也会相应的变成2x。电流镜电路用于将流过左端补给C x的电荷复制到右端的C y，电流镜右端为M个相同结构的电路并联，M＝(1、2、4、8……2 N-1)。并联电路的不同之处在于反相器的输入为A[0]至A[M-1]。A[M-1:0]是有控制器105产生的，用于控制流入到C y的电荷增益倍数，是一个M为的数字信号。
整个电路一个用到8个开关，其中，S3控制的是片外的任意形式开关，剩余7个开关为片内的MOS管开关。各开关的作用简述如下：
控制开关S1：控制模拟前级电路电路初始化；
控制开关S2：连通片外与片内电路的控制信号；
控制开关S3：控制片外待测电容C x是否接入；
控制开关S4：ADC模块的输入端切换信号。
在本实施例中，ADC模块102是差分输入、并行输出的，用于将模拟前级电路101输出的电压值转换为数字量。控制器105用于产生控制开关S1至S4的控制时序逻辑，以控制模拟前级电路101中的开关闭合，为ADC模块102提供时钟信号和采样控制信号，为输出移位寄存器103提供移位控制信号，以及根据ADC 模块102输出的第一数字信号控制A[M-1:0]的信号。输出移位寄存器103是一个和ADC模块102输出位宽相同的移位寄存器，用于对ADC模块102的输出数字量进行移位运算。寄生电容C para是片内外pad的电容，芯片被封装后需要引出引脚到外部，这样才能被使用。Pad就是连接芯片内和芯片外的金属，而这层金属与内部和外部都会有寄生电容。
为了更好的说明本发明的工作原理，参见图4的电路开关时序图，以下参照时序图和图3给出各个时间点电路进行的动作。
T0：将A设为(0001) 2，开始进行电容值测量。
T1：开关S1、S4闭合，电路初始化，运放模块1013同相输入端的反馈环路断开、反相输入端的反馈环路接通，运放的失调电压V offset被保存至C offset，C y被初始为Vref，ADC模块102的反相输入端持续采集接入待测电容C x之前的AFE输出电压。
T2：开关S1断开，S2、S4闭合，将芯片的测量引脚导通，断开用于初始化的开关，此时运放模块1013的反相输入电压为V offset，抵消了运放模块1013的失调电压。同时将寄生在Pad和外部连线的等效寄生电容104充电至Vref。
T3:开关S4断开，S2闭合，断开ADC模块102的反相输入端，此时已经将接入待测电容C x前的AFE输出电压保存到ADC模块102的反相输入端，记为V N。
T4：开关S2、S3闭合，接入待测电容C x，运放模块1013的同相输入端被拉低，控制推挽级补充电荷。同时，电流镜电路1011将M倍的电荷注入到C y，等待电路稳定后，C y的上极板电压V P被保存到ADC模块102的同相输入端，ADC模块102开始转换V P-V N的值。
T5：第一次采集完成，断开所有开关，ADC模块102的输出值为D1，假设ADC模块102的最大输出值为D max，如果D1大于D max/2，则A不变。如果D1小于D max/2但大于D max/8，则将A设为(0011) 2。如果D1小于D max/8，则将A设为(1111) 2，以 此类推。
T6：根据得到的A控制电流镜电路的接入数量，再进行一次T1至T4，获得ADC模块102第二次的输出D2，将D2送入输出移位寄存器，并根据接入数量将D2进行右移1位运算，重复右移不大于M/2的整数次，获得实际的测量值。
参见图5，图5给出了电路的电容-电压转换关系对应图，通过两次测量将电容值的接入待测电容转换成某个电容值线性对应的电压值。由于先通过了一次粗侧，可以根据第一次测量值，用不同的M值再进行一次细测，故图5是一个分段的线性波形。
其中，C x,max是电路能测量的最大电容值，V max为模拟前级电路输出的最大电压值，其单位分别是fF和V。M是并联个数，θ是A取(0001) 2时，1fF电容接入后AFE输出电压的改变量，即
Figure PCTCN2021111758-appb-000001
在测量电容小于
Figure PCTCN2021111758-appb-000002
的时候，接入待测电容造成的电荷转移较少，故而输入AFE的信号微弱，此时限制测量精度的是输入信号的信噪比过低，所以应该增加有效信号的功率进而提高信噪比。将并联数设为M，根据电荷守恒的原理，由于M倍于将待测电容充电至Vref的电荷M*C x*V ref进入C y，有效信号的功率也为原本的M倍，同时本次采样ADC读出的电容值为实际的M倍。
由于需要在接入相同的待测电容时获得更多的电荷转移以获得较高的输入信噪比，所以将Vref定为较高的电压，本文实现电路中使用了2V的Vref；而在测量电容大于
Figure PCTCN2021111758-appb-000003
的时候，因为输出级的电源电压为3.3V，有效的上摆幅小于1.3V，而大于的电容接入会因为输出级的摆幅不足进而无法保持电压，所以应该考虑降低有效信号的功率而保证输出级的偏置。
如图5是将M设为4的情况，假设测量的最小电容精度为C，1C的电容在A为(0001) 2时对应AFE输出电压的改变量为V，而V被ADC测量后对应的数字量是1个LSB。在测量的时候，先进行一次”粗测”，将A设为(0001) 2，此时1C的 电容对应ADC输出数字量1个LSB，根据“粗测”得到的数字量判断接入待测电容在哪个区间。
如果大于
Figure PCTCN2021111758-appb-000004
保持A不变，再测一次，然后计算两次AD的平均值作为输出或者直接将第一次测量作为电容测量值。如果小于
Figure PCTCN2021111758-appb-000005
将A设为(1111) 2，再进行一次测量，此时1C的电容对应ADC输出数字量4个LSB，所以要对ADC输出数字量左移2位。如果是在
Figure PCTCN2021111758-appb-000006
这个区间，将A设为(0011) 2，再进行一次测量，此时1C的电容对应ADC输出数字量2个LSB，然后把结果左移1位。
假设移位后的结果为D，则这个结果表示接入待测电容的值为D*C。通过灵活调整模拟前级电路中的Cy和各个参数，或者对移位后的结果再进行数字信号处理，可以获得各种场景需要的数字量结果。
由上可见，本发明的测量电路实现了在较大范围内对较小的电容进行检测并且输出的功能，具有高精度的特性。本发明给出了一种基于电荷转移型AFE，在宽待测电容范围下针对不同大小的电容进行粗侧和细测两次测量，以获得最佳测量值的粗细测逼近型AFE，实现了在2pF测量范围内1fF的分辨率，同时1pF测量范围内误差最大不超过3LSB的精度(1LSB＝0.5mV)。
此外，本发明设计了一种结构简单有效的控制时序以及对应的逻辑电路，同时设计了具有失调电压校准技术的SAR ADC比较器，改善了ADC的精度。而且本发明提出了AFE和ADC的匹配中间结构(高精度跟随器)，将AFE和ADC隔离开，使用套筒型折叠共栅运放作为第一级来提高增益，第二用推挽结构来做，从而使得该跟随器能驱动大电容的同时，具有高精度的特征，不会造成误差。
需说明的是，以上所描述的装置实施例仅仅是示意性的，其中所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案 的目的。另外，本发明提供的装置实施例附图中，模块之间的连接关系表示它们之间具有通信连接，具体可以实现为一条或多条通信总线或信号线。本领域普通技术人员在不付出创造性劳动的情况下，即可以理解并实施。
以上所述是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本发明的保护范围。

Claims (8)

  1. 一种电容测量电路，其特征在于，包括：模拟前级电路、寄生电容、ADC模块、输出移位寄存器和控制器；
    其中，所述ADC模块的输入端与所述模拟前级电路的输出端连接，所述ADC模块的输出端与所述输出移位寄存器连接；
    所述模拟前级电路的输入端分别连接所述寄生电容和待测电容；其中，所述模拟前级电路内设置有M个并联的电流镜电路；M＝2 N-1，N为正整数；
    所述控制器用于控制所述模拟前级电路、所述寄生电容、所述ADC模块和所述输出移位寄存器对所述待测电容进行电容测量，具体为：
    S1、控制所述模拟前级电路只连通一个所述电流镜电路；
    S2、断开所述待测电容的接入，并控制所述ADC模块的反向输入端持续采集所述模拟前级电路在接入所述待测电容前的AFE输出电压；
    S3、控制所述模拟前级电路，以使所述寄生电容充电至第一参考电压，并记录所述ADC模块的反向输入端当前采集的AFE输出电压V N；
    S4、接入所述待测电容，待所述模拟前级电路稳定后，控制所述ADC模块的同向输入端采集所述模拟前级电路的AFE输出电压V P，并控制所述ADC模块将(V P-V N)的值转换为第一数字信号；
    S5、根据所述第一数字信号的值，确定所述电流镜电路的连通数量m，并控制所述模拟前级电路连通m个所述电流镜电路；其中，m＝2 n-1，且n为小于等于N的正整数；
    S6、重复步骤S2至S4，获得第二数字信号，并根据所述连通数量m，控制所述输出移位寄存器对所述第二数字信号进行移位，获得所述待测电容的电容测量值。
  2. 根据权利要求1所述的电容测量电路，其特征在于，在所述S5之后，若所述连通数量m的值为1，则将所述第一数字信号作为所述待测电容的电容测量值。
  3. 根据权利要求1所述的电容测量电路，其特征在于，在所述S5中，根据所述第一数字信号的值，确定所述电流镜电路的连通数量m，具体为：
    若所述第一数字信号的值大于D max/2，则所述连通数量m的值为1；D max为所述ADC模块的最大输出值；
    若所述第一数字信号的值小于D max/2但大于D max/8，则所述连通数量m的值为2；
    若所述第一数字信号的值小于D max/2 i但大于D max/2 i+1，则所述连通数量m的值为2 i-1；其中，i为大于等于3的正整数。
  4. 根据权利要求3所述的电容测量电路，其特征在于，在所述S6中，根据所述连通数量m，控制所述输出移位寄存器对所述第二数字信号进行移位，获得所述待测电容的电容测量值，具体为：
    若所述连通数量m的值为1，则控制所述输出移位寄存器对所述第二数字信号不进行移位，获得所述待测电容的电容测量值；
    若所述连通数量m的值为2，则控制所述输出移位寄存器对所述第二数字信号向右移动1位，获得所述待测电容的电容测量值；
    若所述连通数量m的值为2 i-1，则控制所述输出移位寄存器对所述第二数字信号向右移动i-1位，获得所述待测电容的电容测量值。
  5. 根据权要求1所述的电容测量电路，其特征在于，所述模拟前级电路包括：运放模块、第一电容、第二电容、电压跟随器和所述M个并联的电流镜电路；
    其中，一个电流镜电路包括两个宽长比为1:1的电流镜子电路、以及设置两 个电流镜子电路之间的反向器；
    所述运放模块的正向输入端与所述模拟前级电路的输入端连接，所述运放模块的反向输入端与所述第一电容的第一端连接，所述运放模块的输出端与所述M个并联的电流镜电路连接；
    所述电压跟随器的输入端分别与所述第二电容的第一端、所述M个并联的电流镜电路连接，所述电压跟随器的输出端与所述模拟前级电路的输出端连接；
    所述第一电容的第二端、所述第二电容的第二端分别与信号地连接。
  6. 根据权利要求5所述的电容测量电路，其特征在于，所述模拟前级电路还包括若干个控制开关和若干个MOS管；
    所述控制器通过控制所述若干个控制开关和MOS管，以控制所述模拟前级电路。
  7. 根据权利要求6所述的电容测量电路，其特征在于，所述模拟前级电路的输入端连接所述待测电容，具体为：
    所述模拟前级电路的输入端通过控制开关S3连接所述待测电容；
    所述控制器还用于控制所述控制开关S3的通断，以控制所述待测电容的接入或断开。
  8. 根据权利要求6所述的电容测量电路，其特征在于，所述ADC模块的输入端与所述模拟前级电路的输出端连接，具体为：
    所述ADC模块的反向输入端通过控制开关S4与所述模拟前级电路的输出端连接，所述ADC模块的同向输入端与所述模拟前级电路的输出端连接；
    所述控制器还用于控制所述控制开关S4的通断，以控制所述ADC模块的反向输入端的接入或断开。
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