WO2022032579A1 - 发射机系统及电子设备 - Google Patents

发射机系统及电子设备 Download PDF

Info

Publication number
WO2022032579A1
WO2022032579A1 PCT/CN2020/108946 CN2020108946W WO2022032579A1 WO 2022032579 A1 WO2022032579 A1 WO 2022032579A1 CN 2020108946 W CN2020108946 W CN 2020108946W WO 2022032579 A1 WO2022032579 A1 WO 2022032579A1
Authority
WO
WIPO (PCT)
Prior art keywords
output terminal
common mode
coupled
reverse
feedback
Prior art date
Application number
PCT/CN2020/108946
Other languages
English (en)
French (fr)
Inventor
覃林
龚涛
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2020/108946 priority Critical patent/WO2022032579A1/zh
Priority to CN202080103989.2A priority patent/CN116114224A/zh
Publication of WO2022032579A1 publication Critical patent/WO2022032579A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems

Definitions

  • the present application relates to the field of transmitters, and in particular, to a transmitter system and electronic equipment.
  • the main task of the transmitter system is to complete the modulation of the high-frequency carrier by the useful intermediate frequency signal (including zero intermediate frequency signal and low intermediate frequency signal), and turn it into a certain center frequency.
  • Bandwidth suitable for electromagnetic waves emitted through an antenna.
  • the transmitter system includes a transmit channel and a feedback channel; the feedback channel is provided with a feedback mixer and a local oscillator (local oscillator), and the feedback mixer and the local oscillator are connected through a local oscillator path (ie, an LO path).
  • a local oscillator path ie, an LO path
  • Embodiments of the present application provide a transmitter system and an electronic device, which can improve the problem of performance degradation of the transmitter system caused by leakage of radio frequency feedback signals.
  • An embodiment of the present application provides a transmitter system, including a feedback channel and a first transmit channel; the first transmit channel includes a first transmit mixer, and the first transmit mixer is used to convert a received baseband transmit signal into a radio frequency transmit signal
  • the radio frequency transmission signal is amplified by the first power amplifier and then output to the first coupler for coupling and then transmitted through the antenna;
  • the feedback channel is used to receive the radio frequency feedback signal coupled from the first coupler;
  • the feedback channel includes a feedback mixer, The feedback mixer is used for converting the radio frequency feedback signal into a baseband feedback signal;
  • the feedback mixer is coupled with the first local oscillator through the first local oscillator path; the first local oscillator path is used for receiving the differential local oscillator of the first local oscillator
  • the oscillator signal is converted into a local oscillator in-phase quadrature signal with common mode rejection characteristics and then output to the feedback mixer.
  • the leakage of the RF feedback signal received by the feedback channel is easy to cause leakage and lead to common mode interference.
  • the transmitter system of the present application will The differential local oscillator signal of the local oscillator is converted into an in-phase quadrature signal with common mode rejection characteristics and output to the feedback mixer, thereby reducing the common mode interference problem caused by the leakage of the RF feedback signal, that is, improving the RF feedback signal.
  • the problem of performance degradation of the transmitter system caused by leakage improves the performance of the transmitter system.
  • the first local oscillator path includes an in-phase quadrature signal generator (ie an IQ signal generator) and a common mode rejection circuit; the common mode rejection circuit is coupled between the first local oscillator and the in-phase quadrature signal between the generators; or, the common mode rejection circuit is coupled between the in-phase quadrature signal generator and the feedback mixer.
  • the common mode suppression circuit is used to suppress the transmission signal on the first local oscillator path.
  • the in-phase quadrature signal generator includes a first forward input terminal, a second reverse input terminal, an in-phase forward output terminal (ie, the I+ output terminal), and an in-phase and reverse output terminal (ie I- output end), quadrature forward output end (ie Q+ output end), quadrature reverse output end (ie Q- output end);
  • the common mode rejection circuit includes a first forward input end, a second reverse a forward input terminal, a first forward output terminal, and a second reverse output terminal; the first forward input terminal and the second reverse input terminal of the common mode rejection circuit are respectively coupled with the two differential output terminals of the first local oscillator connected, the first forward output terminal and the second reverse output terminal of the common mode rejection circuit are respectively coupled with the first forward input terminal and the second reverse input terminal of the in-phase quadrature signal generator; the in-phase quadrature signal generator The in-phase forward output terminal, the non-inverted reverse output terminal, the quadrature forward output terminal and the quadrature reverse output terminal of the device are coupled
  • the common-mode rejection circuit performs common-mode cancellation and differential-mode amplification (that is, common-mode rejection) of the differential local oscillator signal received from the first local oscillator, and outputs it to the first signal generator of the in-phase quadrature signal generator.
  • a forward input terminal and a second reverse input terminal, the in-phase quadrature signal generator is uniformly decomposed into four groups of signals according to the phase and output to the feedback mixer.
  • the IQ signal generator uses a divide-by-2 circuit to generate the IQ signal; in this case, the IQ signal generator may include a first latch and a second latch.
  • the D input end of the first latch is connected to the Q- output end, the C input end of the first latch is connected to the first forward input end of the IQ signal generator, and the Q output end of the first latch It is connected with the I+ output end, the QB output end of the first latch is connected with the I- output end; the D input end of the second latch is connected with the I+ output end, and the C input end of the second latch is generated with the IQ signal
  • the second reverse input terminal of the second latch is connected to the Q output terminal of the second latch, the Q output terminal of the second latch is connected to the Q+ output terminal, and the QB output terminal of the second latch is connected to the Q- output terminal.
  • the IQ signal generator uses a polyphase filter (polyphase filter, PPF) to generate the IQ signal; in this case, the IQ signal generator may include a first resistor, a first capacitor, a first Two resistors, a second capacitor, a third resistor, a third capacitor, a fourth resistor, and a fourth capacitor.
  • PPF polyphase filter
  • both ends of the first resistor are respectively connected to the first forward input end and the I+ output end of the IQ signal generator; both ends of the first capacitor are respectively connected to the first forward input end and the Q+ output end of the IQ signal generator;
  • the two ends of the second resistor are connected to the ground terminal and the Q+ output terminal respectively;
  • the two ends of the second capacitor are respectively connected to the ground terminal and the I- output terminal;
  • the two ends of the third resistor are respectively connected to the second reverse input terminal of the IQ signal generator and I-output terminal;
  • two ends of the third capacitor are respectively connected to the second reverse input terminal and Q-output terminal of the IQ signal generator;
  • two ends of the fourth resistor are respectively connected to the ground terminal and the Q-output terminal;
  • the fourth capacitor The two ends are connected to the ground terminal and the I+ output terminal respectively.
  • the first local oscillator path includes two common mode rejection circuits; the two common mode rejection circuits are the first common mode rejection circuit and the second common mode rejection circuit respectively;
  • the in-phase quadrature signal generator includes a first forward input terminal, a second reverse input terminal, a non-inverting forward output terminal, a non-inverting reverse output terminal, a quadrature forward output terminal, and a quadrature reverse output terminal;
  • the common mode suppression circuit includes a first forward input terminal terminal, the second reverse input terminal, the first forward output terminal, the second reverse output terminal; the first forward input terminal and the second reverse input terminal of the in-phase quadrature signal generator are respectively connected with the first local oscillator
  • the two differential output terminals of the in-phase quadrature signal generator are respectively coupled to the first forward input terminal and the second reverse input terminal of the first common mode suppression circuit.
  • the quadrature forward output terminal and the quadrature reverse output terminal of the in-phase quadrature signal generator are respectively coupled with the first forward input terminal and the second reverse input terminal of the second common mode suppression circuit;
  • the first forward output terminal and the second reverse output terminal of the mode rejection circuit and the first forward output terminal and the second reverse output terminal of the second common mode rejection circuit are coupled to the feedback mixer.
  • the in-phase quadrature signal generator uniformly decomposes the differential local oscillator signal received from the first local oscillator into four groups of signals according to the phases, and two groups of differential signals in the four groups of signals are respectively passed through the first common mode suppression circuit. It performs common mode cancellation and differential mode amplification (that is, common mode rejection) with the second common mode rejection circuit, and outputs the result to the feedback mixer.
  • the in-phase forward output terminal, the in-phase reverse output terminal, the quadrature forward output terminal, and the forward and reverse output terminals of the in-phase quadrature signal generator are respectively coupled to the feedback through different driving circuits Mixer.
  • the signal output by the in-phase quadrature signal generator is adjusted to a standard voltage by setting the driving circuit and output to the feedback mixer.
  • the in-phase forward output terminal and the non-inverted reverse output terminal of the in-phase quadrature signal generator are respectively connected to the first forward input terminal and the second inversion terminal of the first common mode rejection circuit through different driving circuits.
  • coupled to the input end, the first forward output end and the second reverse output end of the first common mode rejection circuit are respectively coupled to the feedback mixer through the driving circuit;
  • the quadrature forward output of the in-phase quadrature signal generator The terminal and the quadrature reverse output terminal are respectively coupled to the first forward input terminal and the second reverse input terminal of the second common mode suppression circuit through different driving circuits, and the first forward output of the second common mode suppression circuit
  • the terminal and the second inverting output terminal are respectively coupled with the feedback mixer through the driving circuit.
  • driving circuits By arranging driving circuits on the paths of the input and output ends of the first common mode rejection circuit and the second common mode rejection circuit, respectively, that is, the input terminals of the first common mode rejection circuit and the second common mode rejection circuit receive through the driving circuit
  • the adjusted standard voltage, and the signals output by the output terminals of the first common mode rejection circuit and the second common mode rejection circuit are adjusted to the standard voltage by the driving circuit, and then output to the feedback mixer.
  • the common mode suppression circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; the gate of the first NMOS transistor and the first forward input of the common mode suppression circuit terminal is coupled, the drain of the first NMOS tube is coupled to the first voltage terminal, the source of the first NMOS tube is coupled to the first forward output terminal of the common mode rejection circuit; the gate of the second NMOS tube is coupled to the common mode rejection circuit The second reverse input terminal of the circuit is coupled, the drain of the second NMOS transistor is coupled to the first forward output terminal of the common mode rejection circuit, the source of the second NMOS transistor is coupled to the second voltage terminal; the third NMOS transistor The gate of the transistor is coupled to the second reverse input terminal of the common mode suppression circuit, the drain of the third NMOS transistor is coupled to the first voltage terminal, and the source of the third NMOS transistor is connected to the second reverse output of the common mode suppression circuit The gate of the fourth NMOS transistor is
  • the input signal can be divided into two kinds of signals: common-mode and differential-mode.
  • common-mode signal the input signals of the first NMOS transistor and the second NMOS transistor are the same, and the output signals have opposite polarities. Therefore, the common mode signal is cancelled at the first forward output terminal;
  • differential mode signal the input signals of the first NMOS tube and the second NMOS tube are opposite, and the output polarities are the same, so that the differential mode signal phase is realized at the output end. add.
  • the third NMOS transistor and the fourth NMOS transistor realize the cancellation of common mode signals and the addition of differential mode signals.
  • the common mode suppression circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor; the gate of the first PMOS transistor and the first forward input of the common mode suppression circuit terminal is coupled, the source of the first PMOS tube is coupled to the first voltage terminal, the drain of the first PMOS tube is coupled to the first forward output terminal of the common mode rejection circuit; the gate of the second PMOS tube is coupled to the common mode rejection circuit The second reverse input terminal of the circuit is coupled, the source of the second PMOS transistor is coupled to the first forward output terminal of the common mode rejection circuit, the drain of the second PMOS transistor is coupled to the second voltage terminal; the third PMOS transistor The gate of the transistor is coupled to the second reverse input terminal of the common mode suppression circuit, the source of the third PMOS transistor is coupled to the first voltage terminal, and the drain of the third PMOS transistor is connected to the second reverse output of the common mode suppression circuit; The gate of the fourth PMOS tube is coupled to the first forward input terminal of the common mode rejection circuit,
  • the common mode rejection circuit includes a first differential input transistor, a second differential input transistor, a current source (also referred to as a tail current source), a first resistor, and a second resistor; one end of the first resistor is connected to the first voltage terminal, the other end of the first resistor is connected to the second reverse output terminal of the common mode rejection circuit; the gate of the first differential input tube is connected to the first forward input terminal of the common mode rejection circuit, and the first differential input tube is connected to the first forward input terminal of the common mode rejection circuit.
  • the drain of the input transistor is connected to the second reverse output terminal of the common mode rejection circuit, and the source of the first differential input transistor is connected to the second voltage terminal (eg ground terminal) through a current source.
  • One end of the second resistor is connected to the first voltage end, and the other end of the second resistor is connected to the first forward output end of the common mode rejection circuit; the gate of the second differential input tube is connected to the second reverse input end of the common mode rejection circuit connection, the drain of the second differential input tube is connected to the first forward output terminal of the common-mode rejection circuit, and the source of the second differential input tube is connected to the second voltage terminal (such as the ground terminal) through the current source; that is, the first The differential input transistor and the second differential input transistor are common-mode current sources; wherein, the first differential input transistor and the second differential input transistor are both NMOS transistors.
  • the transmitter system further includes a second transmit channel, the second transmit channel includes a second transmit mixer, and the second transmit mixer is configured to convert the received baseband transmit signal into a second radio frequency transmit signal
  • the second radio frequency transmit signal is amplified by the second power amplifier and then output to the second coupler for coupling and then transmitted through the antenna; the first local oscillator is used for the first transmit mixer and/or the second transmit mixer
  • the device provides the local oscillator signal.
  • the first local oscillator can provide a local oscillator signal to one or both of the first transmit mixer and the second transmit mixer; that is, the first transmit mixer and the second transmit mixer
  • the oscillator can multiplex the first local oscillator.
  • the second coupler and the first coupler are coupled to the feedback mixer through a selector; so as to transmit the radio frequency feedback signal coupled by the second coupler or the first coupler to the feedback mixer through the selector control. Feedback mixer.
  • the first local oscillator further includes a phase-locked loop, a first frequency divider, a second frequency divider, and a selector; the input ends of the first frequency divider and the second frequency divider are the same as the The phase-locked loop is coupled, and the output ends of the first frequency divider and the second frequency divider are coupled to the first local oscillator channel through a selector.
  • the first local oscillator can select one of the first frequency divider and the second frequency divider to communicate with the first local oscillator channel through the selector, so as to provide the feedback mixer through the first local oscillator channel In-phase quadrature signals.
  • the in-phase quadrature signal generator is a polyphase filter.
  • the driving circuit includes an inverter, so that the phase of the received signal at the input end is inverted by 180° through the inverter, and adjusted to a standard voltage and output through the output end.
  • the feedback channel further includes an attenuator coupled between the first coupler and the feedback mixer, so as to attenuate the coupled high-energy RF feedback signal through the attenuator to prevent the feedback channel from entering saturated state.
  • the first transmit channel further includes an amplifier coupled between the first transmit mixer and the first power amplifier, so as to further increase the amplification factor of the radio frequency transmit signal.
  • the first transmit channel further includes a filter coupled to the output end of the amplifier, and a filter coupled to the output end of the first power amplifier; to filter the amplified radio frequency transmit signal through the filter .
  • the first transmit channel further includes a duplexer coupled to the first power amplifier and the antenna, so as to realize the separation of the transmit channel and the receive channel through the duplexer, and when transmitting a part of the signal to the antenna At the same time, a part of the signal can be coupled from the antenna to the receiving channel.
  • the duplexer is a frequency division duplexer, so as to implement frequency division duplexing on filters of different frequency bands.
  • the duplexer is a time division duplexer to implement time division duplexing through switches.
  • Embodiments of the present application further provide an electronic device, including the transmitter system in any of the foregoing possible implementation manners.
  • FIG. 1 is a schematic structural diagram of a transmitter system according to an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a transmitter system according to an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a local oscillator according to an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a local oscillator path provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a local oscillator path provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of an IQ signal generator provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of an IQ signal generator provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a common mode suppression circuit provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a common mode suppression circuit provided by an embodiment of the present application.
  • FIG. 10 is a schematic diagram of a common mode signal principle of a common mode suppression circuit provided by an embodiment of the present application.
  • FIG. 11 is a schematic diagram of a differential mode signal principle of a common mode suppression circuit provided by an embodiment of the present application.
  • FIG. 12 is a schematic diagram of a connection relationship in a local oscillator path according to an embodiment of the present application.
  • FIG. 13 is a schematic diagram of a connection relationship in a local oscillator path according to an embodiment of the present application.
  • FIG. 14 is a schematic diagram of a connection relationship in a local oscillator path provided by an embodiment of the application.
  • FIG. 15 is a schematic structural diagram of a driving circuit provided by an embodiment of the present application.
  • a method, system, product or device is not necessarily limited to those steps or units expressly listed, but may include other steps or units not expressly listed or inherent to the process, method, product or device.
  • Connected “Connected” and similar words are used to express the intercommunication or interaction between different components, and may include direct connection or indirect connection through other components.
  • the embodiment of the present application provides an electronic device, and the electronic device is provided with a transmitter system; the specific form of the electronic device is not limited in the present application, and the electronic device may be a wireless communication device, such as a mobile phone, a computer, and the like.
  • the transmitter system adopted by the electronic device can improve the problem of system performance degradation caused by the leakage of the radio frequency feedback signal, thereby improving the stability of the electronic device.
  • the transmitter system provided by the embodiment of the present application will be specifically described below.
  • the transmitter system includes a feedback channel f1 and a first transmission channel t1.
  • the first transmit channel t1 includes a first transmit mixer 1.1
  • the first transmit mixer 1.1 is used to convert the received baseband transmit signal into a radio frequency transmit signal
  • the radio frequency transmit signal passes through the first power amplifier a1 ( power amplifier, PA) is amplified and output to the first coupler 2.1, and is coupled through the first coupler 2.1 and then transmitted through the antenna 3.
  • the radio frequency transmit signal output by the first transmit mixer 1.1 can be amplified and filtered in turn by an amplifier (amplifier, AMP) and a filter at the previous stage,
  • the output to the first power amplifier a1 and the filter of the latter stage are amplified and filtered in turn, and then coupled through the first coupler 2.1 and then transmitted through the antenna 3 .
  • the first transmit channel t1 may also be provided with a duplexer; wherein, the duplexer may be coupled between the antenna and the first power amplifier a1 to pass the duplexer
  • the multiplexer realizes the separation of the transmit channel and the receive channel (that is, the RX channel). While transmitting a part of the signal to the antenna, it can couple a part of the signal from the antenna to the receive channel.
  • the duplexer may adopt a frequency division duplexer, and the frequency division duplexer can be realized by filtering signals in different frequency bands; for another example, in some possible implementation manners, the duplexer can also use a time division duplexer, so as to realize time division duplexing through a single-pole multi-throw switch or a plurality of switches in parallel.
  • the feedback channel f1 is used to receive the RF feedback signal coupled from the first coupler 2.1; the feedback channel f1 includes a feedback mixer 4, and the feedback mixing frequency
  • the device 4 is used to convert the radio frequency feedback signal into a baseband feedback signal.
  • an attenuator 6 may also be set in the feedback channel f1, and the attenuator 6 is coupled between the first coupler 2.1 and the feedback mixer 4 to pass the attenuator 6. Attenuate the coupled RF feedback signal to prevent the feedback channel from entering a saturated state.
  • the feedback mixer 4 is coupled to the first local oscillator 5 through a first local oscillator path (ie, a first LO path) LO1; the first local oscillator path LO1 is used to receive the first local oscillator path LO1.
  • a differential local oscillator signal of the local oscillator 5 is converted into an in-phase quadrature signal (abbreviated as IQ signal) with common-mode rejection characteristics, and then output to the feedback mixer 4; wherein, I is in-phase (in-phase) , Q is quadrature; for illustration, in some possible implementations, the IQ signal may be an IQ clock signal.
  • the leakage of the RF feedback signal received by the feedback channel is easy to cause leakage and lead to common mode interference.
  • the transmitter system of the present application will The differential local oscillator signal of the local oscillator is converted into an in-phase quadrature signal with common mode rejection characteristics and output to the feedback mixer, thereby reducing the common mode interference problem caused by the leakage of the RF feedback signal, that is, improving the RF feedback signal.
  • the problem of performance degradation of the transmitter system caused by leakage improves the performance of the transmitter system.
  • FIG. 1 is only a schematic illustration of the transmitter system provided with one transmission channel (ie, the first transmission channel t1 ) as an example, but the present application is not limited to this, in some possible implementations , a plurality of transmission channels can be set in the transmitter system; schematically, as shown in FIG.
  • the transmitter system can also include a second transmission channel t2 on the basis of the aforementioned first transmission channel t1; the second transmission channel t2
  • the transmit channel t2 includes a second transmit mixer 1.2, which is used to convert the received baseband transmit signal into a second radio frequency transmit signal; the second radio frequency transmit signal is amplified by the second power amplifier a2
  • the output is sent to the second coupler 2.2, and is coupled through the second coupler 2.2 and then transmitted through the antenna 3.
  • the second coupler 2.2 and the first coupler 2.1 can be coupled to the feedback mixer 4 through a selector (MUX), so as to control the second coupler or the first coupler through the selector
  • the coupled radio frequency feedback signal is passed to the feedback mixer 4 .
  • the first coupler 2.1 and the second coupler 2.2 can be coupled to the same antenna, or can be coupled to different antennas. This application There is no specific restriction on this, and the setting can be selected according to actual needs.
  • the first local oscillator 5 is coupled to one or both of the first transmit mixer 1.1 and the second transmit mixer 1.2 to provide the first transmit mixer 1.1 and one or both of the second transmit mixers 1.2 provide the local oscillator signal.
  • the first local oscillator 5 is coupled to the first transmit mixer 1.1 to provide a local oscillator signal to the first transmit mixer 1.1; for example, in some possible implementations , the first local oscillator 5 is coupled to the second transmit mixer 1.2 to provide a local oscillator signal to the second transmit mixer 1.2; for another example, in some possible implementations, the first local oscillator 5 It is coupled to both the first transmit mixer 1.1 and the second transmit mixer 1.2 to provide a local oscillator signal to both the first transmit mixer 1.1 and the second transmit mixer 1.2, that is, the first transmit mixer The first local oscillator 5 is multiplexed with the second transmit mixer 1.1 and the second transmit mixer 1.2.
  • the above-mentioned first local oscillator 5 may include a phase-locked loop 50 , a first frequency divider 51 , a second frequency divider 52 , and a selector 53.
  • the first frequency divider 51 and the second frequency divider 51 have different frequency division ratios, and the input ends of the first frequency divider 51 and the second frequency divider 52 are coupled to the phase-locked loop 50, and the first frequency divider
  • the output terminals of the frequency divider 51 and the second frequency divider 52 are coupled to the first local oscillator path LO1 through the selector 53 .
  • the first local oscillator 5 can select one of the first frequency divider 51 and the second frequency divider 52 to communicate with the first local oscillator path LO1 through the selector 53, so as to pass the first local oscillator path LO1 provides the IQ signal to feedback mixer 4 .
  • the phase-locked loop 50 may include a phase detector 501, Charge pump 502, loop filter 503, voltage-controlled oscillator 504, frequency divider 505; in addition, the phase detector 501 in the phase-locked loop 50 can be connected with the crystal oscillator module ( 3 ) connection, the phase-locked loop 50 is coupled to the first frequency divider 51 and the second frequency divider 52 through a voltage controlled oscillator 504 .
  • the transmitter system of the present application converts the differential local oscillator signal output by the first local oscillator 5 into an IQ signal with common mode rejection characteristics through the first local oscillator path LO1 and outputs it to the feedback mixer 4 to
  • the problem of performance degradation of the transmitter system caused by the leakage of the radio frequency feedback signal is improved; the following further detailed description will be given on the related setting of the first local oscillator channel LO1 to realize the IQ signal conversion with the common mode rejection characteristic.
  • the first local oscillator path LO1 may include an in-phase quadrature signal generator (hereinafter referred to as an IQ signal generator for short) 100 and a common mode rejection circuit 200; Common mode suppression is performed on the transmission signal on the first local oscillator path LO1 by the common mode suppression circuit 200 .
  • an IQ signal generator hereinafter referred to as an IQ signal generator for short
  • common mode rejection circuit 200 Common mode suppression is performed on the transmission signal on the first local oscillator path LO1 by the common mode suppression circuit 200 .
  • the common mode rejection circuit 200 may be coupled between the first local oscillator 5 and the IQ signal generator 100 , that is, the common mode rejection circuit 200 may be provided in the IQ signal generator 100 the input side of the .
  • the common mode rejection circuit 200 may be coupled between the IQ signal generator 100 and the feedback mixer 4 ; output side.
  • the IQ signal generator 100 includes a first forward input terminal Vin+, a second reverse input terminal Vin-, a non-inverting forward output terminal I+ (hereinafter referred to as the I+ output terminal), and a non-inverting input terminal.
  • the IQ signal generator 100 is used to decompose a group of differential signals input by the first forward input terminal Vin+ and the second reverse input terminal Vin- into four groups of signals (I+ signal, Q+ signal, I- signal according to the phase uniformity , Q-signal), output through I+ output terminal, Q+ output terminal, I- output terminal and Q- output terminal respectively; that is to say, the vector direction of the output signal of I+ output terminal and the input signal of the first forward input terminal Vin+
  • the output signal of the I- output terminal is opposite to the vector direction of the input signal of the first forward input terminal Vin+ (ie, the difference is 180°), and the output signal of the Q+ output terminal is intersected with the vector direction of the input signal of the first forward input terminal Vin+.
  • the IQ signal generator 100 may use a polyphase filter (polyphase filter, PPF) to generate the IQ signal; as shown in FIG. 6 , the IQ signal generator 100 (ie, the polyphase filter, PPF)
  • the filter may include a first resistor R1, a first capacitor C1, a second resistor R2, a second capacitor C2, a third resistor R3, a third capacitor C3, a fourth resistor R4, and a fourth capacitor C4.
  • the two ends of the first resistor R1 are respectively connected to the first forward input terminal Vin+ and the I+ output terminal; the two ends of the first capacitor C1 are respectively connected to the first forward input terminal Vin+ and the Q+ output terminal; The terminals are respectively connected to the ground terminal and the Q+ output terminal; the two ends of the second capacitor C2 are respectively connected to the ground terminal and the I- output terminal; the two ends of the third resistor R3 are respectively connected to the second reverse input terminal Vin- and the I- output terminal; The two ends of the third capacitor C3 are respectively connected to the second reverse input terminal Vin- and the Q- output terminal; the two ends of the fourth resistor R4 are respectively connected to the ground terminal and the Q- output terminal; the two ends of the fourth capacitor C4 are respectively connected to the ground terminal and I+ output terminal.
  • the IQ signal generator 100 may use a divide-by-2 circuit to generate the IQ signal; as shown in FIG. 7 , the IQ signal generator 100 (ie, the divide-by-2 circuit) may include the first a latch and a second latch.
  • the D input terminal of the first latch is connected to the Q- output terminal
  • the C input terminal of the first latch is connected to the first forward input terminal Vin+
  • the Q output terminal of the first latch is connected to the I+ output terminal.
  • the QB output end of the first latch is connected with the I- output end;
  • the D input end of the second latch is connected with the I+ output end, and the C input end of the second latch is connected with the second reverse input end Vin - connection,
  • the Q output terminal of the second latch is connected to the Q+ output terminal, and the QB output terminal of the second latch is connected to the Q- output terminal.
  • the common mode rejection circuit 200 includes a first forward input terminal in1, a second reverse input terminal in2, a first forward output terminal out1, a second reverse output terminal out2, and a first voltage terminal VDD and the second voltage terminal (such as the ground terminal); the input signal of the first forward input terminal in1 is in phase with the output signal of the first forward output terminal out1, and the input signal of the second reverse input terminal in2 is in phase with the second reverse The output signal to the output terminal out2 is in phase.
  • the common mode suppression circuit 200 can suppress the common mode voltage of a group of differential signals input by the first forward input terminal in1 and the second reverse input terminal in2, generate a new set of differential signals with common mode rejection characteristics, and Output is performed through the first forward output terminal out1 and the second reverse output terminal out2.
  • the common mode rejection circuit 200 may use a cross-coupled buffer circuit; as shown in FIG. 8 , the common mode rejection circuit 200 (ie, the cross-coupled buffer circuit) may include The first MOS transistor T1, the second MOS transistor T2, the third MOS transistor T3, and the fourth MOS transistor T4.
  • the first MOS transistor T1, the second MOS transistor T2, the third MOS transistor T3, and the fourth MOS transistor T4 may be NMOS transistors or PMOS transistors, which are not limited in this application.
  • the common mode rejection circuit 200 will be described by taking a low level voltage (eg, ground voltage) as an example.
  • the gate of the first MOS transistor T1 is connected to the first forward input terminal in1 of the common mode suppression circuit 200 , and the drain of the first MOS transistor T1 is connected to the first voltage
  • the terminal VDD is connected, and the source of the first MOS transistor T1 is connected to the first forward output terminal out1 of the common mode rejection circuit 200 .
  • the gate of the second MOS transistor T2 is connected to the second reverse input terminal in2 of the common mode rejection circuit 200
  • the drain of the second MOS transistor T2 is connected to the first forward output terminal out1 of the common mode rejection circuit 200
  • the second MOS transistor T2 is connected to the first forward output terminal out1 of the common mode rejection circuit 200 .
  • the source of T2 is connected to the second voltage terminal (eg, the ground terminal).
  • the gate of the third MOS transistor T3 is connected to the second reverse input terminal in2 of the common mode rejection circuit 200, the drain of the third MOS transistor T3 is connected to the first voltage terminal VDD, and the source of the third MOS transistor T3 is connected to the common mode rejection terminal
  • the second inverting output terminal out2 of the circuit 200 is connected.
  • the gate of the fourth MOS transistor T4 is connected to the first forward input terminal in1 of the common mode suppression circuit 200 , the drain of the fourth MOS transistor T4 is connected to the second reverse output terminal out2 of the common mode suppression circuit 200 , and the fourth MOS transistor
  • the source of T4 is connected to the second voltage terminal (eg, the ground terminal).
  • the connection relationship between the source and the drain of the aforementioned NMOS transistors is interchanged, namely Can.
  • the common mode rejection circuit 200 may include a resistor Ra, a resistor Rb, a differential input transistor Ta, a differential input transistor Tb, a current source (also referred to as a tail current) source) S.
  • the differential input transistor Ta and the differential input transistor Tb may be NMOS transistors or PMOS transistors, which are not limited in this application.
  • the common mode rejection circuit 200 will be described.
  • one end of the resistor Ra is connected to the first voltage terminal VDD, and the other end of the resistor Ra is connected to the second reverse output terminal out2; the gate of the differential input transistor Ta is connected to the The first forward input terminal in1 is connected, the drain of the differential input transistor Ta is connected to the second reverse output terminal out2, and the source of the differential input transistor Ta is connected to the second voltage terminal (eg ground terminal) through the current source S.
  • One end of the resistor Rb is connected to the first voltage terminal VDD, and the other end of the resistor Rb is connected to the first forward output terminal out1; the gate of the differential input transistor Tb is connected to the second reverse input terminal in2, and the drain of the differential input transistor Tb
  • the pole is connected to the first forward output terminal out1
  • the source of the differential input tube Tb is connected to the second voltage terminal (such as the ground terminal) through the current source S; that is, the differential input tube Ta, the differential input tube Tb common mode current source S .
  • the differential input transistor Ta and the differential input transistor Tb are both PMOS transistors, the connection relationship between the source and drain of the differential input transistor Ta and differential input transistor Tb of the NMOS transistors can be interchanged.
  • differential input transistors (Ta, Tb) are used to suppress the common-mode signal of the differential input signal at the input terminals (in1, in2), when the output of the tail current source S
  • the common node of the differential input transistors (Ta, Tb) is virtually connected to the ground, so it can be equivalent to a common source amplifier.
  • the common node of the differential input transistors (Ta, Tb) goes from the output impedance of the tail current source S to ground, which is equivalent to a source-stage negative feedback amplifier.
  • the gain approaches 0.
  • the output impedance of the tail current source S is limited, so that the common mode rejection capability of the common mode rejection circuit 200 is limited.
  • the existence of the tail current source will occupy a certain voltage domain, resulting in differential input.
  • the effective amplitude of the signal is limited.
  • the common mode rejection circuit 200 shown in FIG. 8 it adopts a fully differential circuit. Since the common mode rejection circuit 200 adopts a left-right symmetrical circuit structure, the following takes the half circuit on the left as an example to suppress the common mode rejection circuit.
  • the common mode rejection capability of the circuit 200 is described in detail.
  • the input signal can be divided into two types of signals: common mode and differential mode.
  • common mode signal as shown in FIG. 10, the input of the first NMOS transistor T1 and the second NMOS transistor T2 The signals are the same, and the polarity of the output signal is opposite, so that the common mode signal is cancelled at the first forward output terminal out1; for the differential mode signal, referring to FIG.
  • the input signals of the first NMOS transistor T1 and the second NMOS transistor T2 instead, the outputs have the same polarity, enabling differential mode signal summation at the output.
  • the third NMOS transistor T3 and the fourth NMOS transistor T4 in the right-half circuit realize the cancellation of common mode signals and the addition of differential mode signals.
  • the common mode rejection circuit 200 shown in FIG. 8 Compared with the common mode rejection circuit in FIG. 7, it mainly relies on the negative feedback at the source stage, which is limited by the output impedance of the tail current source; the common mode rejection circuit 200 shown in FIG. 8 has no tail current source. Therefore, the maximum swing value of the input signal is relatively larger, and through the superposition of signals of opposite polarities, the common mode signal can be eliminated under the condition that the gains of the two channels are consistent, so that the common mode suppression of the common mode suppression circuit is improved. more capable.
  • the first forward input terminal in1 of the common mode rejection circuit 200 and the second The reverse input terminal in2 is respectively coupled to the two differential output terminals of the first local oscillator 5 , and the first forward output terminal out1 of the common mode rejection circuit 200 is coupled to the first forward input terminal Vin+ of the IQ signal generator 100 connected, the second reverse output terminal out2 of the common mode rejection circuit 200 is coupled to the second reverse input terminal Vin- of the IQ signal generator 100; the I+ output terminal, the Q+ output terminal, and the I- output terminal of the IQ signal generator 100 The terminal and the Q-output terminal are coupled to the feedback mixer 4 .
  • the IQ signal generator 100 For the I+ output, Q+ output, I- output, and Q- output of the IQ signal generator 100 to be connected to the feedback mixer 4, in some possible implementations, as shown in FIG. 12 , the IQ The I+ output terminal, Q+ output terminal, I- output terminal and Q- output terminal of the signal generator 100 can be respectively coupled to the feedback mixer 4 through different driving circuits (300.1, 300.2, 300.3, 300.4).
  • the common-mode rejection circuit 200 performs common-mode cancellation and differential-mode amplification (ie, common-mode rejection) of the differential local oscillator signal received from the first local oscillator 5 , and outputs it to the IQ signal generator 100 .
  • a standard voltage for example, IQ clock signal with full swing
  • the first local oscillator path LO1 includes two common mode rejection circuits: the first A common mode rejection circuit 200.1 and a second common mode rejection circuit 200.2.
  • the first forward input terminal Vin+ and the second reverse input terminal Vin+ of the IQ signal generator 100 are respectively coupled to the two differential output terminals of the first local oscillator 5; the I+ output terminal of the IQ signal generator 100, The I- output terminal is respectively coupled to the first forward input terminal in1 and the second reverse input terminal in2 of the first common mode rejection circuit 200.1, and the Q+ output terminal and the Q- output terminal of the IQ signal generator 100 are respectively connected to the second reverse input terminal in1.
  • the first forward input terminal in1 and the second reverse input terminal in2 of the common mode rejection circuit 200.2 are coupled; the first forward output terminal out1, the second reverse output terminal out2, and the second The first forward output terminal out1 and the second reverse output terminal out2 of the common mode rejection circuit 200 . 2 are coupled to the feedback mixer 4 .
  • the first forward output terminal out1 and the second reverse output terminal out2 of the first common mode rejection circuit 200.1 and the first forward output terminal out1 and the second reverse output terminal out2 of the second common mode rejection circuit 200.2 are coupled to In terms of being connected to the feedback mixer 4, in some possible implementations, as shown in FIG. 13, the first forward output terminal out1, the second reverse output terminal out2 and the second forward output terminal of the first common mode rejection circuit 200.1
  • the first forward output terminal out1 and the second reverse output terminal out2 of the common mode rejection circuit 200.2 can be respectively coupled to the feedback mixer 4 through different driving circuits (300.1, 300.2, 300.3, 300.4).
  • the I+ output terminal and the I- output terminal of the IQ signal generator 100 may pass through different driving circuits (300.5, 300.6) and the first common mode rejection circuit 200.1 respectively through different driving circuits (300.5, 300.6).
  • a forward input terminal in1 and a second reverse input terminal in2 are coupled, and the Q+ output terminal and the Q- output terminal of the IQ signal generator 100 can pass through different driving circuits (300.7, 300.8) and the second common mode rejection circuit respectively.
  • the first forward input terminal in1 and the second reverse input terminal in2 of 200.2 are coupled; the first forward output terminal out1, the second reverse output terminal out2 and the second common mode rejection circuit of the first common mode rejection circuit 200.1
  • the first forward output terminal out1 and the second reverse output terminal out2 of 200.2 are respectively coupled to the feedback mixer 4 through different driving circuits (300.1, 300.2, 300.3, 300.4). That is to say, driving circuits are respectively provided on the paths of the input end and the output end of the first common mode rejection circuit 200.1 and the second common mode rejection circuit 200.2.
  • the IQ signal generator 100 evenly decomposes the differential local oscillator signal received from the first local oscillator 5 into four groups of signals (I+ signal, Q+ signal , I-signal, Q-signal); the I+ signal at the I+ output end and the I- signal at the I- output end are respectively adjusted to the standard voltage by the driving circuits (300.5, 300.6), and then the common mode is eliminated by the first common mode suppression circuit 200.1.
  • differential mode amplification that is, common mode rejection
  • the second common-mode suppression circuit 200.2 performs common-mode elimination and differential-mode amplification (that is, common-mode suppression), and then passes through the driving circuits (300.3, 300.4) respectively. Adjust to standard voltage and output to feedback mixer 4.
  • the driving circuit may adopt one-stage or multi-stage cascaded inversion device.
  • the circuit diagram of the inverter can be referred to as shown in FIG. 15, including two transistors (M1, M2).
  • the transistor M1 is an N-type transistor (ie, an NMOS transistor), which is called a drive transistor;
  • the transistor M2 is a P-type transistor (ie, a PMOS transistor). ), called the load tube; the inverter can reverse the phase of the received signal at the input end by 180°, and adjust it to the standard voltage and output it through the output end.

Landscapes

  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Transmitters (AREA)

Abstract

本申请提供了一种发射机系统及电子设备，涉及发射机领域，能够改善因射频反馈信号泄露发射机系统的性能下降的问题。该发射机系统包括：反馈通道和第一发射通道；第一发射通道包括第一发射混频器，第一发射混频器用于将接收的基带发射信号转换为射频发射信号；射频发射信号在经过第一功率放大器放大后输出至第一耦合器进行耦合后通过天线发射出去；反馈通道接收从第一耦合器耦合的射频反馈信号；反馈通道包括反馈混频器，反馈混频器将射频反馈信号转换为基带反馈信号；反馈混频器通过第一本振通路与第一本地振荡器耦接；第一本振通路用于接收第一本地振荡器的差分本地振荡器信号，并转换为具有共模抑制特性的同相正交信号后输出给反馈混频器。

Description

发射机系统及电子设备 技术领域
本申请涉及发射机领域，尤其涉及一种发射机系统及电子设备。
背景技术
发射机系统作为电子设备中的重要组成部分，其主要任务是完成有用的中频信号(包括零中频信号、低中频信号)对高频载波的调制，将其变为在某一中心频率上具有一定带宽、适合通过天线发射的电磁波。
发射机系统中包括发射通道和反馈通道；其中，反馈通道中设置有反馈混频器和本地振荡器(local oscillator)，且反馈混频器和本地振荡器通过本振通路(即LO通路)连接，通常，由于反馈通道接收的射频反馈信号的能量较大容易产生泄露，造成发射机系统的性能下降。
发明内容
本申请实施例提供一种发射机系统及电子设备，能够改善因射频反馈信号泄露导致的发射机系统性能下降的问题。
本申请实施例提供一种发射机系统，包括反馈通道和第一发射通道；第一发射通道包括第一发射混频器，第一发射混频器用于将接收的基带发射信号转换为射频发射信号；射频发射信号在经过第一功率放大器放大后输出至第一耦合器进行耦合后通过天线发射出去；反馈通道用于接收从第一耦合器耦合的射频反馈信号；反馈通道包括反馈混频器，反馈混频器用于将射频反馈信号转换为基带反馈信号；反馈混频器通过第一本振通路与第一本地振荡器耦接；第一本振通路用于接收第一本地振荡器的差分本地振荡器信号，并转换为具有共模抑制特性的本地振荡器同相正交信号后输出给反馈混频器。
相比相关技术的发射机系统中，容易因反馈通道接收的射频反馈信号的能量较大产生泄露导致共模干扰而言，本申请的发射机系统通过设置第一本振通路将接收的第一本地振荡器的差分本地振荡器信号转换为共模抑制特性的同相正交信号输出给反馈混频器，从而降低了因射频反馈信号泄露导致的共模干扰问题，也即改善了因射频反馈信号泄露导致的发射机系统性能下降的问题，提高了发射机系统的性能。
在一些可能实现的方式中，第一本振通路包括同相正交信号产生器(即IQ信号产生器)、共模抑制电路；共模抑制电路耦接在第一本地振荡器与同相正交信号产生器之间；或者，共模抑制电路耦接在同相正交信号产生器和反馈混频器之间。以通过共模抑制电路对第一本振通路上的传输信号进行共模抑制。
在一些可能实现的方式中，同相正交信号产生器包括第一正向输入端、第二反向输入端、同相正向输出端(也即I+输出端)、同相反向输出端(也即I-输出端)、正交正向输出端(也即Q+输出端)、正交反向输出端(也即Q-输出端)；共模抑制电路包括第一正向输入端、第二反向输入端、第一正向输出端、第二反向输出端；共模抑制电路的第一正 向输入端和第二反向输入端分别与第一本地振荡器的两个差分输出端耦接，共模抑制电路的第一正向输出端、第二反向输出端分别与同相正交信号产生器的第一正向输入端、第二反向输入端耦接；同相正交信号产生器的同相正向输出端、同相反向输出端、正交正向输出端、正交反向输出端与反馈混频器耦接。
在此情况下，共模抑制电路将从第一本地振荡器接收的差分本地振荡器信号进行共模消除、差模放大(即进行共模抑制)后，输出至同相正交信号产生器的第一正向输入端和第二反向输入端，同相正交信号产生器按照相位均匀分解为四组信号输出至反馈混频器。
在一些可能实现的方式中，IQ信号产生器采用2分频电路实现IQ信号的生成；在此情况下，IQ信号产生器可以包括第一锁存器和第二锁存器。其中，第一锁存器的D输入端与Q-输出端连接，第一锁存器的C输入端与IQ信号产生器的第一正向输入端连接，第一锁存器的Q输出端与I+输出端连接，第一锁存器的QB输出端与I-输出端连接；第二锁存器的D输入端与I+输出端连接，第二锁存器的C输入端与IQ信号产生器的第二反向输入端连接，第二锁存器的Q输出端与Q+输出端连接，第二锁存器的QB输出端与Q-输出端连接。
在一些可能实现的方式中，IQ信号产生器采用多相滤波器(poly phase filter，PPF)实现IQ信号的生成；在此情况下，IQ信号产生器可以包括第一电阻、第一电容、第二电阻、第二电容、第三电阻、第三电容、第四电阻、第四电容。其中，第一电阻的两端分别连接IQ信号产生器的第一正向输入端和I+输出端；第一电容的两端分别连接IQ信号产生器的第一正向输入端和Q+输出端；第二电阻的两端分别连接接地端和Q+输出端；第二电容的两端分别连接接地端和I-输出端；第三电阻的两端分别连接IQ信号产生器的第二反向输入端和I-输出端；第三电容的两端分别连接IQ信号产生器的第二反向输入端和Q-输出端；第四电阻的两端分别连接接地端和Q-输出端；第四电容的两端分别连接接地端和I+输出端。
在一些可能实现的方式中，第一本振通路包括两个共模抑制电路；两个共模抑制电路分别为第一共模抑制电路和第二共模抑制电路；同相正交信号产生器包括第一正向输入端、第二反向输入端、同相正向输出端、同相反向输出端、正交正向输出端、正交反向输出端；共模抑制电路包括第一正向输入端、第二反向输入端、第一正向输出端、第二反向输出端；同相正交信号产生器的第一正向输入端、第二反向输入端分别与第一本地振荡器的两个差分输出端耦接；同相正交信号产生器的同相正向输出端、同相反向输出端分别与第一共模抑制电路的第一正向输入端和第二反向输入端耦接，同相正交信号产生器的正交正向输出端、正交反向输出端分别与第二共模抑制电路的第一正向输入端和第二反向输入端耦接；第一共模抑制电路的第一正向输出端、第二反向输出端以及第二共模抑制电路的第一正向输出端、第二反向输出端与反馈混频器耦接。
在此情况下，同相正交信号产生器将从第一本地振荡器接收的差分本地振荡器信号按照相位均匀分解为四组信号，四组信号中两组差分信号分别经第一共模抑制电路和第二共模抑制电路进行共模消除、差模放大(即进行共模抑制)后输出至反馈混频器。
在一些可能实现的方式中，同相正交信号产生器的同相正向输出端、同相反向输出端、正交正向输出端、正向反向输出端分别通过不同的驱动电路耦接到反馈混频器。通过设置驱动电路将同相正交信号产生器输出的信号调整至标准电压，输出至反馈混频器。
在一些可能实现的方式中，同相正交信号产生器的同相正向输出端、同相反向输出端分别通过不同的驱动电路与第一共模抑制电路的第一正向输入端和第二反向输入端耦接，第一共模抑制电路的第一正向输出端和第二反向输出端分别通过驱动电路与反馈混频器耦接；同相正交信号产生器的正交正向输出端、正交反向输出端分别通过不同的驱动电路与第二共模抑制电路的第一正向输入端和第二反向输入端耦接，第二共模抑制电路的第一正向输出端和第二反向输出端分别通过驱动电路与反馈混频器耦接。通过在第一共模抑制电路和第二共模抑制电路的输入端和输出端的通路上分别设置驱动电路，也即第一共模抑制电路和第二共模抑制电路的输入端接收通过驱动电路调整后的标准电压，并且第一共模抑制电路和第二共模抑制电路的输出端输出的信号经驱动电路调整至标准电压后，输出至反馈混频器。
在一些可能实现的方式中，共模抑制电路包括第一NMOS管、第二NMOS管、第三NMOS管、第四NMOS管；第一NMOS管的栅极与共模抑制电路的第一正向输入端耦接，第一NMOS管的漏极与第一电压端耦接，第一NMOS管的源极与共模抑制电路的第一正向输出端耦接；第二NMOS管的栅极与共模抑制电路的第二反向输入端耦接，第二NMOS管的漏极与共模抑制电路的第一正向输出端耦接，第二NMOS管的源极与第二电压端耦接；第三NMOS管的栅极与共模抑制电路的第二反向输入端耦接，第三NMOS管的漏极与第一电压端耦接，第三NMOS管的源极与共模抑制电路的第二反向输出端耦接；第四NMOS管的栅极与共模抑制电路的第一正向输入端耦接，第四NMOS管的漏极与共模抑制电路的第二反向输出端耦接，第四NMOS管的源极与第二电压端耦接。
在该共模抑制电路中，输入信号可以拆分为共模和差模两种信号，对于共模信号而言，第一NMOS管和第二NMOS管的输入信号相同，输出信号极性相反，从而在第一正向输出端实现共模信号相抵消；对于差模信号而言，第一NMOS管和第二NMOS管的输入信号相反，输出极性相同，从而在输出端实现差模信号相加。同理如第三NMOS管和第四NMOS管实现共模信号相抵消以及差模信号相加。
在一些可能实现的方式中，共模抑制电路包括第一PMOS管、第二PMOS管、第三PMOS管、第四PMOS管；第一PMOS管的栅极与共模抑制电路的第一正向输入端耦接，第一PMOS管的源极与第一电压端耦接，第一PMOS管的漏极与共模抑制电路的第一正向输出端耦接；第二PMOS管的栅极与共模抑制电路的第二反向输入端耦接，第二PMOS管的源极与共模抑制电路的第一正向输出端耦接，第二PMOS管的漏极与第二电压端耦接；第三PMOS管的栅极与共模抑制电路的第二反向输入端耦接，第三PMOS管的源极与第一电压端耦接，第三PMOS管的漏极与共模抑制电路的第二反向输出端耦接；第四PMOS管的栅极与共模抑制电路的第一正向输入端耦接，第四PMOS管的源极与共模抑制电路的第二反向输出端耦接，第四PMOS管的漏极与第二电压端耦接。
在一些可能实现的方式中，共模抑制电路包括第一差分输入管、第二差分输入管、电流源(也可以称为尾电流源)、第一电阻、第二电阻；第一电阻的一端与第一电压端连接，第一电阻的另一端与共模抑制电路的第二反向输出端连接；第一差分输入管的栅极与共模抑制电路的第一正向输入端连接，第一差分输入管的漏极与共模抑制电路的第二反向输出端连接，第一差分输入管的源极通过电流源与第二电压端(如接地端)连接。第二电阻的一端与第一电压端连接，第二电阻的另一端与共模抑制电路的第一正向输出端连接；第二 差分输入管的栅极与共模抑制电路的第二反向输入端连接，第二差分输入管的漏极与共模抑制电路的第一正向输出端连接，第二差分输入管的源极通过电流源与第二电压端(如接地端)连接；也即第一差分输入管、第二差分输入管共模电流源；其中，第一差分输入管、第二差分输入管均为NMOS管。
在一些可能实现的方式中，发射机系统还包括第二发射通道，第二发射通道包括第二发射混频器，第二发射混频器用于将接收的基带发射信号转换为第二射频发射信号；第二射频发射信号在经过第二功率放大器放大后输出至第二耦合器进行耦合后通过天线发射出去；第一本地振荡器用于为第一发射混频器和/或第二发射混频器提供本振信号。在此情况下，第一本地振荡器能够向第一发射混频器和第二发射混频器中的一个或两个提供本振信号；也即第一发射混频器和第二发射混频器可以复用第一本地振荡器。
在一些可能实现的方式中，第二耦合器与第一耦合器通过选择器耦接到反馈混频器；以通过选择器控制将第二耦合器或第一耦合器耦合的射频反馈信号传输至反馈混频器。
在一些可能实现的方式中，第一本地振荡器中还包括锁相环、第一分频器、第二分频器、选择器；第一分频器、第二分频器的输入端与锁相环耦接，第一分频器、第二分频器的输出端通过选择器与第一本振通路耦接。在此情况下，第一本地振荡器通过选择器可以选择第一分频器和第二分频器中的一个与第一本振通路连通，以通过第一本振通路向反馈混频器提供同相正交信号。
在一些可能实现的方式中，同相正交信号产生器为多相滤波器。
在一些可能实现的方式中，驱动电路包括反相器，以通过反相器将输入端的接收信号的相位反转180°，并调整至标准电压通过输出端输出。
在一些可能实现的方式中，反馈通道还包括耦接在第一耦合器与反馈混频器之间的衰减器，以通过衰减器对耦合的大能量的射频反馈信号进行衰减，避免反馈通道进入饱和状态。
在一些可能实现的方式中，第一发射通道还包括耦接在第一发射混频器和第一功率放大器之间的放大器，以进一步的增加对射频发射信号的放大倍数。
在一些可能实现的方式中，第一发射通道还包括耦接在放大器输出端的滤波器，以及耦接在第一功率放大器输出端的滤波器；以通过滤波器对放大后的射频发射信号进行滤波处理。
在一些可能实现的方式中，第一发射通道还包括耦接在第一功率放大器与天线的双工器，以通过双工器实现发射通道和接收通道的分离，在将一部分信号发射给天线的同时，能够从天线耦合一部分信号到接收通道。
在一些可能实现的方式中，双工器为频分双工器，以对不同频段的滤波器以实现频分双工。
在一些可能实现的方式中，双工器为时分双工器，以通过开关以实现时分双工。
本申请实施例还提供一种电子设备，包括前述任一种可能实现的方式中的发射机系统。
附图说明
图1为本申请实施例提供的一种发射机系统的结构示意图；
图2为本申请实施例提供的一种发射机系统的结构示意图；
图3为本申请实施例提供的一种本地振荡器的结构示意图；
图4为本申请实施例提供的一种本振通路的结构示意图；
图5为本申请实施例提供的一种本振通路的结构示意图；
图6为本申请实施例提供的一种IQ信号产生器的结构示意图；
图7为本申请实施例提供的一种IQ信号产生器的结构示意图；
图8为本申请实施例提供的一种共模抑制电路的结构示意图；
图9为本申请实施例提供的一种共模抑制电路的结构示意图；
图10为本申请实施例提供的一种共模抑制电路的共模信号原理示意图；
图11为本申请实施例提供的一种共模抑制电路的差模信号原理示意图；
图12为本申请实施例提供的一种本振通路中的连接关系示意图；
图13为本申请实施例提供的一种本振通路中的连接关系示意图；
图14为本申请实施例提供的一种本振通路中的连接关系示意图；
图15为本申请实施例提供的一种驱动电路的结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合本申请中的附图，对本申请中的技术方案进行清楚地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书实施例和权利要求书及附图中的术语“第一”、“第二”等仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序；各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元。方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。“连接”、“耦接”等类似的词语，用于表达不同组件之间的互通或互相作用，可以包括直接相连或通过其他组件间接相连。
本申请实施例提供一种电子设备，该电子设备中设置有发射机系统；本申请对该电子设备的具体形式不做限制，该电子设备可以为无线通信设备；例如手机、电脑等。
该电子设备采用的发射机系统能够改善因射频反馈信号泄露导致的系统性能下降的问题，进而能够提高电子设备的稳定性。
以下对本申请实施例提供的发射机系统进行具体说明。
本申请实施例提供一种发射机系统，如图1所示，该发射机系统包括反馈通道f1和第一发射通道t1。其中，第一发射通道t1包括第一发射混频器1.1，该第一发射混频器1.1用于将接收的基带发射信号转换为射频发射信号，该射频发射信号在经过第一功率放大器a1(power amplifier，PA)放大后输出至第一耦合器2.1，并经第一耦合器2.1进行耦合后通过天线3发射出去。
当然，在一些具体的实施例中，如图1所示，第一发射混频器1.1输出的射频发射信号，可以通过前级的放大器(amplifier，AMP)和滤波器依次进行放大和滤波后，输出给 第一功率放大器a1和后级的滤波器依次进行放大和滤波，然后再经过第一耦合器2.1进行耦合后通过天线3发射出去。
此外，在一些可能实现的方式中，如图1所示，第一发射通道t1还可以设置双工器；其中，双工器可以耦接在天线与第一功率放大器a1之间，以通过双工器实现发射通道和接收通道(也即RX通道)的分离，将一部分信号发射给天线的同时，能够从天线耦合一部分信号到接收通道。当然，本申请对于双工器不作具体限制；例如，在一些可能实现的方式中，双工器可以采用频分双工器，通过对不同频段的信号滤波以实现频分双工；又例如，在一些可能实现的方式中，双工器也可以采用时分双工器，以通过单刀多掷开关或者多个并列的开关以实现时分双工。
在此基础上，在该发射机系统中，参考图1所示，反馈通道f1用于接收从第一耦合器2.1耦合的射频反馈信号；反馈通道f1中包括反馈混频器4，反馈混频器4用于将射频反馈信号转换为基带反馈信号。
在一些可能实现的方式中，如图1所示，反馈通道f1中还可以设置衰减器6，该衰减器6耦接在第一耦合器2.1与反馈混频器4之间，以通过衰减器6对耦合的过大的射频反馈信号进行衰减，避免反馈通道进入饱和状态。
另外，参考图1所示，该反馈混频器4通过第一本振通路(也即第一LO通路)LO1与第一本地振荡器5耦接；该第一本振通路LO1用于接收第一本地振荡器5的差分本地振荡器信号，并转换为具有共模抑制特性的同相正交信号(简称为IQ信号)后输出给反馈混频器4；其中，I为同相(in-phase)，Q为正交(quadrature)；示意的，在一些可能实现的方式中，IQ信号可以为IQ时钟信号。
需要说明的是，作为发射机系统，其内部还设置有其他的模块、器件等，例如图1中与第一发射混频器1.1连接的发射基带滤波器，与反馈混频器4连接的反馈基带滤波器，连接在衰减器6以及反馈混频器4之间的放大器(AMP)等等，具体可以参考相关技术，此处不再一一说明。
相比相关技术的发射机系统中，容易因反馈通道接收的射频反馈信号的能量较大产生泄露导致共模干扰而言，本申请的发射机系统通过设置第一本振通路将接收的第一本地振荡器的差分本地振荡器信号转换为共模抑制特性的同相正交信号输出给反馈混频器，从而降低了因射频反馈信号泄露导致的共模干扰问题，也即改善了因射频反馈信号泄露导致的发射机系统性能下降的问题，提高了发射机系统的性能。
此外，图1中仅是示意的以该发射机系统中设置有一个发射通道(即第一发射通道t1)为例进行说明的，但本申请并不限制于此，在一些可能实现的方式中，该发射机系统中可以设置多个发射通道；示意的，如图2所示，该发射机系统在包括前述第一发射通道t1的基础上，还可以包括第二发射通道t2；该第二发射通道t2包括第二发射混频器1.2，第二发射混频器1.2用于将接收的基带发射信号转换为第二射频发射信号；该第二射频发射信号在经过第二功率放大器a2放大后输出至第二耦合器2.2，并经第二耦合器2.2进行耦合后通过天线3发射出去。
另外，如图2所示，第二耦合器2.2与第一耦合器2.1可以通过选择器(MUX)耦接到反馈混频器4，以通过选择器控制将第二耦合器或第一耦合器耦合的射频反馈信号传输至反馈混频器4。并且发射机系统在采用第一耦合器2.1和第二耦合器2.2的情况下，第 一耦合器2.1和第二耦合器2.2可以耦接至同一天线，也可以耦接至不同的天线，本申请对此不作具体限制，实际中可以根据需要选择设置即可。
关于第二发射通道t2中的其他相关设置(例如放大器、双工器、滤波器、发射基带滤波器等)可以参考前述关于第一发射通道t1的描述，此处不再赘述。
在此基础上，如图2所示，第一本地振荡器5与第一发射混频器1.1和第二发射混频器1.2中一个或者两个耦接，以向第一发射混频器1.1和第二发射混频器1.2中的一个或者两个提供本振信号。例如，在一些可能实现的方式中，第一本地振荡器5与第一发射混频器1.1耦接，以向第一发射混频器1.1提供本振信号；又例如，在一些可能实现的方式中，第一本地振荡器5与第二发射混频器1.2耦接，以向第二发射混频器1.2提供本振信号；再例如，在一些可能实现的方式中，第一本地振荡器5与第一发射混频器1.1和第二发射混频器1.2均耦接，以向第一发射混频器1.1和第二发射混频器1.2均提供本振信号，也即第一发射混频器1.1和第二发射混频器1.2复用第一本地振荡器5。
另外，参考图1和图3所示，在一些可能实现的方式中，上述第一本地振荡器5中可以包括锁相环50、第一分频器51、第二分频器52、选择器53。其中，第一分频器51和第二分频器51具有不同的分频比，且第一分频器51和第二分频器52的输入端与锁相环50耦接，第一分频器51和第二分频器52的输出端通过选择器53与第一本振通路LO1耦接。在此情况下，该第一本地振荡器5通过选择器53可以选择第一分频器51和第二分频器52中的一个与第一本振通路LO1连通，以通过第一本振通路LO1向反馈混频器4提供IQ信号。
需要说明的是，本申请对于前述锁相环50的具体设置形式不做限制；示意的，在一些可能实现的方式中，锁相环50可以包括如图3中示出的相位检测器501、电荷泵502、环路滤波器503、压控振荡器504、分频器505；另外，该锁相环50中的相位检测器501可以与位于第一本地振荡器5中的晶体振荡器模块(图3中未示出)连接，该锁相环50通过压控振荡器504与第一分频器51、第二分频器52耦接。
如前述可知，本申请的发射机系统通过第一本振通路LO1将第一本地振荡器5输出的差分本地振荡器信号转换为具有共模抑制特性的IQ信号输出给反馈混频器4，以改善因射频反馈信号泄露导致的发射机系统性能下降的问题；以下对该第一本振通路LO1实现具有共模抑制特性的IQ信号转换的相关设置情况做进一步的具体说明。
在一些可能实现的方式中，参考图4和图5所示，第一本振通路LO1中可以包括同相正交信号产生器(下文简称为IQ信号产生器)100和共模抑制电路200；以通过共模抑制电路200对第一本振通路LO1上的传输信号进行共模抑制。
示意的，如图4所示，共模抑制电路200可以耦接在第一本地振荡器5与IQ信号产生器100之间，也就是说，共模抑制电路200可以设置在IQ信号产生器100的输入端一侧。
示意的，如图5所示，共模抑制电路200可以耦接在IQ信号产生器100和反馈混频器4之间；也就是说，共模抑制电路200可以设置在IQ信号产生器100的输出端一侧。
以下对IQ信号产生器100和共模抑制电路200的具体设置情况做进一步的说明。
参考图6和图7所示，IQ信号产生器100包括第一正向输入端Vin+、第二反向输入端Vin-、同相正向输出端I+(以下均简称为I+输出端)、同相反向输出端I-(以下均简 称为I-输出端)、正交正向输出端Q+(以下均简称为Q+输出端)、正交反向输出端Q-(以下均简称为Q-输出端)；IQ信号产生器100用于将第一正向输入端Vin+和第二反向输入端Vin-输入的一组差分信号按照相位均匀分解为四组信号(I+信号、Q+信号、I-信号、Q-信号)，分别通过I+输出端、Q+输出端、I-输出端、Q-输出端输出；也就是说，I+输出端的输出信号与第一正向输入端Vin+的输入信号的矢量方向相同，I-输出端的输出信号与第一正向输入端Vin+的输入信号的矢量方向相反(即相差180°)，Q+输出端的输出信号与第一正向输入端Vin+的输入信号的矢量方向相交(即相差90°)，Q-输出端的输出信号与第一正向输入端Vin+的输入信号的矢量方向相差270°。
示意的，在一些可能实现的方式中，IQ信号产生器100可以采用多相滤波器(poly phase filter，PPF)实现IQ信号的生成；如图6所示，IQ信号产生器100(即多相滤波器)可以包括第一电阻R1、第一电容C1、第二电阻R2、第二电容C2、第三电阻R3、第三电容C3、第四电阻R4、第四电容C4。其中，第一电阻R1的两端分别连接第一正向输入端Vin+和I+输出端；第一电容C1的两端分别连接第一正向输入端Vin+和Q+输出端；第二电阻R2的两端分别连接接地端和Q+输出端；第二电容C2的两端分别连接接地端和I-输出端；第三电阻R3的两端分别连接第二反向输入端Vin-和I-输出端；第三电容C3的两端分别连接第二反向输入端Vin-和Q-输出端；第四电阻R4的两端分别连接接地端和Q-输出端；第四电容C4的两端分别连接接地端和I+输出端。
示意的，在另一些可能实现的方式中，IQ信号产生器100可以采用2分频电路实现IQ信号的生成；如图7所示，IQ信号产生器100(即2分频电路)可以包括第一锁存器和第二锁存器。其中，第一锁存器的D输入端与Q-输出端连接，第一锁存器的C输入端与第一正向输入端Vin+连接，第一锁存器的Q输出端与I+输出端连接，第一锁存器的QB输出端与I-输出端连接；第二锁存器的D输入端与I+输出端连接，第二锁存器的C输入端与第二反向输入端Vin-连接，第二锁存器的Q输出端与Q+输出端连接，第二锁存器的QB输出端与Q-输出端连接。
参考图8和图9所示，共模抑制电路200包括第一正向输入端in1、第二反向输入端in2、第一正向输出端out1、第二反向输出端out2、第一电压端VDD和第二电压端(如接地端)；第一正向输入端in1的输入信号与第一正向输出端out1的输出信号同相，第二反向输入端in2的输入信号与第二反向输出端out2的输出信号同相。该共模抑制电路200能够对第一正向输入端in1和第二反向输入端in2输入的一组差分信号的共模电压进行抑制，生成一组新的具有共模抑制特性的差分信号并通过第一正向输出端out1、第二反向输出端out2进行输出。
示意的，在一些可能实现的方式中，该共模抑制电路200可以采用交叉耦合缓冲电路(cross couple buffer)；如图8所示，该共模抑制电路200(即交叉耦合缓冲电路)可以包括第一MOS管T1、第二MOS管T2、第三MOS管T3、第四MOS管T4。其中，第一MOS管T1、第二MOS管T2、第三MOS管T3、第四MOS管T4可以采用NMOS管，也可以采用PMOS管；本申请对此不作限制。以下均是以第一MOS管T1、第二MOS管T2、第三MOS管T3、第四MOS管T4均采用NMOS管，第一电压端VDD的电压为高电平电压，第二电压端的电压为低电平电压(例如接地电压)为例，对该共模抑制电路200进行说明的。
如图8所示，在该共模抑制电路200中，第一MOS管T1的栅极与共模抑制电路200的第一正向输入端in1连接，第一MOS管T1的漏极与第一电压端VDD连接，第一MOS管T1的源极与共模抑制电路200的第一正向输出端out1连接。第二MOS管T2的栅极与共模抑制电路200的第二反向输入端in2连接，第二MOS管T2的漏极与共模抑制电路200的第一正向输出端out1连接，第二MOS管T2的源极与第二电压端(如接地端)连接。第三MOS管T3的栅极与共模抑制电路200的第二反向输入端in2连接，第三MOS管T3的漏极与第一电压端VDD连接，第三MOS管T3的源极与共模抑制电路200的第二反向输出端out2连接。第四MOS管T4的栅极与共模抑制电路200的第一正向输入端in1连接，第四MOS管T4的漏极与共模抑制电路200的第二反向输出端out2连接，第四MOS管T4的源极与第二电压端(如接地端)连接。当然，在第一MOS管T1、第二MOS管T2、第三MOS管T3、第四MOS管T4均采用PMOS管的情况下，将前述NMOS管的源极和漏极的连接关系互换即可。
示意的，在一些可能实现的方式中，如图9所示，该共模抑制电路200可以包括电阻Ra、电阻Rb、差分输入管Ta、差分输入管Tb、电流源(也可以称为尾电流源)S。其中，差分输入管Ta和差分输入管Tb可以采用NMOS管，也可以采用PMOS管，本申请对此不作限制。以下均是以差分输入管(Ta、Tb)可以采用NMOS管，第一电压端VDD的电压为高电平电压，第二电压端的电压为低电平电压(例如接地电压)为例，对该共模抑制电路200进行说明。
如图9所示，在该共模抑制电路200中，电阻Ra的一端与第一电压端VDD连接，电阻Ra的另一端与第二反向输出端out2连接；差分输入管Ta的栅极与第一正向输入端in1连接，差分输入管Ta的漏极与第二反向输出端out2连接，差分输入管Ta的源极通过电流源S与第二电压端(如接地端)连接。电阻Rb的一端与第一电压端VDD连接，电阻Rb的另一端与第一正向输出端out1连接；差分输入管Tb的栅极与第二反向输入端in2连接，差分输入管Tb的漏极与第一正向输出端out1连接，差分输入管Tb的源极通过电流源S与第二电压端(如接地端)连接；也即差分输入管Ta、差分输入管Tb共模电流源S。当然，在差分输入管Ta、差分输入管Tb均采用PMOS管的情况下，将前述NMOS管的差分输入管Ta、差分输入管Tb的源极和漏极的连接关系互换即可。
对于图9中示出的共模抑制电路200而言，其采用差分输入管(Ta、Tb)来抑制输入端(in1、in2)的差分输入信号的共模信号，当尾电流源S的输出阻抗无穷大时，对于差分输入信号而言，差分输入管(Ta、Tb)的公共节点虚连到地，故可以等效为共源放大器。而对于共模信号而言，差分输入管(Ta、Tb)的公共节点由尾电流源S的输出阻抗到地，等效为源级负反馈放大器，当尾电流源S的输出阻抗为无穷大时，增益趋近为0。但是实际电路中，尾电流源S的输出阻抗是有限的，从而使得该共模抑制电路200的共模抑制能力有限，同时由于有尾电流源的存在会占用一定的电压域度，导致差分输入信号的有效幅度受限。
对于图8中示出的共模抑制电路200而言，其采用全差分电路，由于该共模抑制电路200采用左右对称的电路结构，以下以左侧的半电路为例，对该共模抑制电路200的共模抑制能力进行具体说明。在该共模抑制电路200中，输入信号可以拆分为共模和差模两种信号，对于共模信号而言，参考图10所示，第一NMOS管T1和第二NMOS管T2的输 入信号相同，输出信号极性相反，从而在第一正向输出端out1实现共模信号相抵消；对于差模信号而言，参考图11，第一NMOS管T1和第二NMOS管T2的输入信号相反，输出极性相同，从而在输出端实现差模信号相加。同理如右半侧电路中第三NMOS管T3和第四NMOS管T4实现共模信号相抵消以及差模信号相加。
相比于图7中的共模抑制电路主要依赖于源级负反馈，受限于尾电流源的输出阻抗值大小；图8中示出的共模抑制电路200由于没有尾电流源的存在，所以输入信号的摆幅最大值相对更大，并且通过相反极性信号的叠加，在保证两个通路的增益一致的情况下即可消除共模信号，从而使得该共模抑制电路的共模抑制能力更强。
以下以采用图8中示出的共模抑制电路200为例，对图4和图5中位于第一本振通路LO1中的IQ信号产生器100和共模抑制电路200的具体连接方式做进一步的说明。
参考图4所示，在共模抑制电路200设置在IQ信号产生器100的输入端一侧的情况下，如图12所示，共模抑制电路200的第一正向输入端in1和第二反向输入端in2分别与第一本地振荡器5的两个差分输出端耦接，共模抑制电路200的第一正向输出端out1与IQ信号产生器100的第一正向输入端Vin+耦接，共模抑制电路200的第二反向输出端out2与IQ信号产生器100的第二反向输入端Vin-耦接；IQ信号产生器100的I+输出端、Q+输出端、I-输出端、Q-输出端与反馈混频器4耦接。
对于上述IQ信号产生器100的I+输出端、Q+输出端、I-输出端、Q-输出端与反馈混频器4连接而言，在一些可能实现的方中，如图12所示，IQ信号产生器100的I+输出端、Q+输出端、I-输出端、Q-输出端可以分别通过不同的驱动电路(300.1、300.2、300.3、300.4)与反馈混频器4耦接。
在此情况下，共模抑制电路200将从第一本地振荡器5接收的差分本地振荡器信号进行共模消除、差模放大(即进行共模抑制)后，输出至IQ信号产生器100的第一正向输入端Vin+和第二反向输入端Vin-；IQ信号产生器100将第一正向输入端Vin+和第二反向输入端Vin-输入的一组差分信号按照相位均匀分解为四组信号(I+信号、Q+信号、I-信号、Q-信号)，分别通过I+输出端、Q+输出端、I-输出端、Q-输出端输出；然后通过驱动电路(300.1、300.2、300.3、300.4)分别将四组信号(I+信号、Q+信号、I-信号、Q-信号)调整至标准电压(例如满摆幅的IQ时钟信号)输出至反馈混频器4。
参考图5所示，在共模抑制电路200设置在IQ信号产生器100的输出端一侧的情况下，如图13所示，第一本振通路LO1包括两个共模抑制电路：第一共模抑制电路200.1和第二共模抑制电路200.2。其中，IQ信号产生器100的第一正向输入端Vin+和第二反向输入端Vin+分别与第一本地振荡器5的两个差分输出端耦接；IQ信号产生器100的I+输出端、I-输出端分别与第一共模抑制电路200.1的第一正向输入端in1和第二反向输入端in2耦接，IQ信号产生器100的Q+输出端、Q-输出端分别与第二共模抑制电路200.2的第一正向输入端in1和第二反向输入端in2耦接；第一共模抑制电路200.1的第一正向输出端out1、第二反向输出端out2以及第二共模抑制电路200.2的第一正向输出端out1、第二反向输出端out2耦接到反馈混频器4。
对于上述第一共模抑制电路200.1的第一正向输出端out1、第二反向输出端out2以及第二共模抑制电路200.2的第一正向输出端out1、第二反向输出端out2耦接到反馈混频器4而言，在一些可能实现的方式中，如图13所示，第一共模抑制电路200.1的第一正向输 出端out1、第二反向输出端out2以及第二共模抑制电路200.2的第一正向输出端out1、第二反向输出端out2可以分别通过不同的驱动电路(300.1、300.2、300.3、300.4)耦接到反馈混频器4。
在一些可能实现的方式中，如图14所示，IQ信号产生器100的I+输出端、I-输出端可以分别通过不同的驱动电路(300.5、300.6)与第一共模抑制电路200.1的第一正向输入端in1和第二反向输入端in2耦接，IQ信号产生器100的Q+输出端、Q-输出端可以分别通过不同的驱动电路(300.7、300.8)与第二共模抑制电路200.2的第一正向输入端in1和第二反向输入端in2耦接；第一共模抑制电路200.1的第一正向输出端out1、第二反向输出端out2以及第二共模抑制电路200.2的第一正向输出端out1、第二反向输出端out2分别通过不同的驱动电路(300.1、300.2、300.3、300.4)与反馈混频器4耦接。也就是说，在第一共模抑制电路200.1和第二共模抑制电路200.2的输入端和输出端的通路上分别设置驱动电路。
以图14中示出的第一本振通路LO1为例，IQ信号产生器100将从第一本地振荡器5接收的差分本地振荡器信号按照相位均匀分解为四组信号(I+信号、Q+信号、I-信号、Q-信号)；I+输出端的I+信号以及I-输出端的I-信号通过驱动电路(300.5、300.6)分别调整至标准电压后，经第一共模抑制电路200.1进行共模消除、差模放大(即进行共模抑制)，再次经过通过驱动电路(300.1、300.2)分别调整至标准电压，并输出至反馈混频器4；Q+输出端的Q+信号以及Q-输出端的Q-信号通过驱动电路(300.7、300.8)分别调整至标准电压后，经第二共模抑制电路200.2进行共模消除、差模放大(即进行共模抑制)，再次经过通过驱动电路(300.3、300.4)分别调整至标准电压，并输出至反馈混频器4。
对于前述的任一驱动电路(300.1、300.2、300.3、300.4、300.5、300.6、300.7、300.8)而言，在一些可能实现的方式中，该驱动电路可以采用一级或者多级级联的反相器。其中，反相器的电路图可以参考图15所示，包括两个晶体管(M1、M2)，晶体管M1为N型晶体管(即NMOS管)，称驱动管；晶体管M2为P型晶体管(即PMOS管)，称负载管；反相器能够将输入端的接收信号的相位反转180°，并调整至标准电压通过输出端输出。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (13)

  1. 一种发射机系统，其特征在于，包括反馈通道和第一发射通道；
    所述第一发射通道包括第一发射混频器，所述第一发射混频器用于将接收的基带发射信号转换为射频发射信号；
    所述射频发射信号在经过第一功率放大器放大后输出至第一耦合器进行耦合后通过天线发射出去；
    所述反馈通道用于接收从所述第一耦合器耦合的射频反馈信号；
    所述反馈通道包括反馈混频器，所述反馈混频器用于将所述射频反馈信号转换为基带反馈信号；
    所述反馈混频器通过第一本振通路与第一本地振荡器耦接；
    所述第一本振通路用于接收所述第一本地振荡器的差分本地振荡器信号，并转换为具有共模抑制特性的同相正交信号后输出给所述反馈混频器。
  2. 根据权利要求1所述的发射机系统，其特征在于，
    所述第一本振通路包括同相正交信号产生器、共模抑制电路；
    所述共模抑制电路耦接在所述第一本地振荡器与所述同相正交信号产生器之间；或者，所述共模抑制电路耦接在所述同相正交信号产生器和所述反馈混频器之间。
  3. 根据权利要求2所述的发射机系统，其特征在于，
    所述同相正交信号产生器包括第一正向输入端、第二反向输入端、同相正向输出端、同相反向输出端、正交正向输出端、正交反向输出端；
    所述共模抑制电路包括第一正向输入端、第二反向输入端、第一正向输出端、第二反向输出端；
    所述共模抑制电路的第一正向输入端和第二反向输入端分别与所述第一本地振荡器的两个差分输出端耦接，所述共模抑制电路的第一正向输出端、第二反向输出端分别与所述同相正交信号产生器的第一正向输入端、第二反向输入端耦接；
    所述同相正交信号产生器的同相正向输出端、同相反向输出端、正交正向输出端、正交反向输出端与所述反馈混频器耦接。
  4. 根据权利要求2所述的发射机系统，其特征在于，所述第一本振通路包括两个共模抑制电路；两个所述共模抑制电路分别为第一共模抑制电路和第二共模抑制电路；
    所述同相正交信号产生器包括第一正向输入端、第二反向输入端、同相正向输出端、同相反向输出端、正交正向输出端、正交反向输出端；所述共模抑制电路包括第一正向输入端、第二反向输入端、第一正向输出端、第二反向输出端；
    所述同相正交信号产生器的第一正向输入端、第二反向输入端分别与所述第一本地振荡器的两个差分输出端耦接；
    所述同相正交信号产生器的同相正向输出端、同相反向输出端分别与所述第一共模抑制电路的第一正向输入端和第二反向输入端耦接，所述同相正交信号产生器的正交正向输出端、所述正交反向输出端分别与所述第二共模抑制电路的第一正向输入端和第二反向输入端耦接；
    所述第一共模抑制电路的第一正向输出端、第二反向输出端以及所述第二共模抑制电 路的第一正向输出端、第二反向输出端与所述反馈混频器耦接。
  5. 根据权利要求3或4所述的发射机系统，其特征在于，
    所述同相正交信号产生器的同相正向输出端、同相反向输出端、正交正向输出端、正向反向输出端分别通过不同的驱动电路耦接到所述反馈混频器。
  6. 根据权利要求4所述的发射机系统，其特征在于，
    所述同相正交信号产生器的同相正向输出端、同相反向输出端分别通过不同的驱动电路与所述第一共模抑制电路的第一正向输入端和第二反向输入端耦接，所述第一共模抑制电路的第一正向输出端和第二反向输出端分别通过驱动电路与所述反馈混频器耦接；
    所述同相正交信号产生器的正交正向输出端、所述正交反向输出端分别通过不同的驱动电路与所述第二共模抑制电路的第一正向输入端和第二反向输入端耦接，所述第二共模抑制电路的第一正向输出端和第二反向输出端分别通过驱动电路与所述反馈混频器耦接。
  7. 根据权利要求2-6任一项所述的发射机系统，其特征在于，
    所述共模抑制电路包括第一NMOS管、第二NMOS管、第三NMOS管、第四NMOS管；
    所述第一NMOS管的栅极与所述共模抑制电路的第一正向输入端耦接，所述第一NMOS管的漏极与所述第一电压端耦接，所述第一NMOS管的源极与所述共模抑制电路的第一正向输出端耦接；
    所述第二NMOS管的栅极与所述共模抑制电路的第二反向输入端耦接，所述第二NMOS管的漏极与所述共模抑制电路的第一正向输出端耦接，所述第二NMOS管的源极与所述第二电压端耦接；
    所述第三NMOS管的栅极与所述共模抑制电路的第二反向输入端耦接，所述第三NMOS管的漏极与所述第一电压端耦接，所述第三NMOS管的源极与所述共模抑制电路的第二反向输出端耦接；
    所述第四NMOS管的栅极与所述共模抑制电路的第一正向输入端耦接，所述第四NMOS管的漏极与所述共模抑制电路的第二反向输出端耦接，所述第四NMOS管的源极与所述第二电压端耦接。
  8. 根据权利要求1-7任一项所述的发射机系统，其特征在于，
    所述发射机系统还包括第二发射通道，所述第二发射通道包括第二发射混频器，所述第二发射混频器用于将接收的基带发射信号转换为第二射频发射信号；
    所述第二射频发射信号在经过第二功率放大器放大后输出至第二耦合器进行耦合后通过天线发射出去；
    所述第一本地振荡器用于为所述第一发射混频器和/或所述第二发射混频器提供本振信号。
  9. 根据权利要求1-8任一项所述的发射机系统，其特征在于，
    所述第一本地振荡器中还包括锁相环、第一分频器、第二分频器、选择器；
    所述第一分频器、所述第二分频器的输入端与所述锁相环耦接，所述第一分频器、所述第二分频器的输出端通过所述选择器与所述第一本振通路耦接。
  10. 根据权利要求1-9任一项所述的发射机系统，其特征在于，
    所述同相正交信号产生器为多相滤波器。
  11. 根据权利要求5-10任一项所述的发射机系统，其特征在于，
    所述驱动电路包括反相器。
  12. 根据权利要求1-11任一项所述的发射机系统，其特征在于，
    所述反馈通道还包括耦接在所述第一耦合器与所述反馈混频器之间的衰减器。
  13. 一种电子设备，其特征在于，包括如权利要求1-12任一项所述的发射机系统。
PCT/CN2020/108946 2020-08-13 2020-08-13 发射机系统及电子设备 WO2022032579A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2020/108946 WO2022032579A1 (zh) 2020-08-13 2020-08-13 发射机系统及电子设备
CN202080103989.2A CN116114224A (zh) 2020-08-13 2020-08-13 发射机系统及电子设备

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/108946 WO2022032579A1 (zh) 2020-08-13 2020-08-13 发射机系统及电子设备

Publications (1)

Publication Number Publication Date
WO2022032579A1 true WO2022032579A1 (zh) 2022-02-17

Family

ID=80246804

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/108946 WO2022032579A1 (zh) 2020-08-13 2020-08-13 发射机系统及电子设备

Country Status (2)

Country Link
CN (1) CN116114224A (zh)
WO (1) WO2022032579A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115296689A (zh) * 2022-08-08 2022-11-04 慷智集成电路(上海)有限公司 全双工发射接收电路、串行电路芯片、电子设备及车辆

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080051055A1 (en) * 2006-07-20 2008-02-28 Samsung Electro-Mechanics Co., Ltd. Frequency conversion circuit
CN102291347A (zh) * 2011-09-02 2011-12-21 大唐移动通信设备有限公司 一种基于多频段频谱的dpd处理方法和设备
CN202261371U (zh) * 2011-08-15 2012-05-30 京信通信系统（中国）有限公司 一种混模射频拉远系统
CN102710268A (zh) * 2012-05-31 2012-10-03 澜起科技（上海）有限公司 低中频接收机
CN102739265A (zh) * 2011-04-07 2012-10-17 英特尔移动通信有限公司 用于改进的天线匹配的天线调谐器与改动的反馈接收器的组合
CN104052507A (zh) * 2013-03-14 2014-09-17 美国亚德诺半导体公司 使用回送电路的发射器lo泄漏校准方案
CN107093983A (zh) * 2011-11-25 2017-08-25 英特尔移动通信有限责任公司 共模抑制电路
US20180006855A1 (en) * 2016-06-29 2018-01-04 International Business Machines Corporation Using common mode local oscillator termination in single-ended commutating circuits for conversion gain improvement

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080051055A1 (en) * 2006-07-20 2008-02-28 Samsung Electro-Mechanics Co., Ltd. Frequency conversion circuit
CN102739265A (zh) * 2011-04-07 2012-10-17 英特尔移动通信有限公司 用于改进的天线匹配的天线调谐器与改动的反馈接收器的组合
CN202261371U (zh) * 2011-08-15 2012-05-30 京信通信系统（中国）有限公司 一种混模射频拉远系统
CN102291347A (zh) * 2011-09-02 2011-12-21 大唐移动通信设备有限公司 一种基于多频段频谱的dpd处理方法和设备
CN107093983A (zh) * 2011-11-25 2017-08-25 英特尔移动通信有限责任公司 共模抑制电路
CN102710268A (zh) * 2012-05-31 2012-10-03 澜起科技（上海）有限公司 低中频接收机
CN104052507A (zh) * 2013-03-14 2014-09-17 美国亚德诺半导体公司 使用回送电路的发射器lo泄漏校准方案
US20180006855A1 (en) * 2016-06-29 2018-01-04 International Business Machines Corporation Using common mode local oscillator termination in single-ended commutating circuits for conversion gain improvement

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115296689A (zh) * 2022-08-08 2022-11-04 慷智集成电路(上海)有限公司 全双工发射接收电路、串行电路芯片、电子设备及车辆
CN115296689B (zh) * 2022-08-08 2023-11-03 慷智集成电路(上海)有限公司 全双工发射接收电路、串行电路芯片、电子设备及车辆

Also Published As

Publication number Publication date
CN116114224A (zh) 2023-05-12

Similar Documents

Publication Publication Date Title
ES2409266T3 (es) Convertidor elevador y convertidor reductor con una transconductancia conmutada y una máscara de oscilador local
KR101066054B1 (ko) 주파수 변환을 위한 시스템, 방법 및 장치
CN111384902B (zh) 一种阻抗匹配频率可调的宽带接收机电路
US9037095B2 (en) Radio frequency tracking filter
JP5436455B2 (ja) ハーモニックリジェクションミキサ
GB2349021A (en) Switching down conversion mixer for use in multi-stage receiver architectures
US8299865B2 (en) Quadrature modulator and semiconductor integrated circuit with it built-in
US20200028534A1 (en) Radio receivers
Syu et al. Large improvement in image rejection of double-quadrature dual-conversion low-IF architectures
US20130130632A1 (en) Signal generator circuit and radio transmission and reception device including the same
US8433277B2 (en) Passive mixer and four-phase clocking method and apparatus
WO2022032579A1 (zh) 发射机系统及电子设备
JP2017508325A (ja) 局部発振器信号生成
GB2438082A (en) Active and passive dual local oscillator mixers comprising triple gate mixer circuits or exclusive NOR switch (XNOR-SW) circuits.
CN104796088A (zh) 用于混频器的系统和方法
US8818318B2 (en) Frequency up and down converter
US8180313B2 (en) Mixer and transceiver having the mixer
US9479132B2 (en) Signal conversion with gain in the forward path
TWI806749B (zh) 差分式毫米波通訊架構及電子設備
WO2019128974A1 (zh) 信号接收电路、信号处理芯片、通信设备及信号接收方法
KR20180102640A (ko) 무선 센서 디바이스에서 로컬 발진기 신호들 생성
WO2013093616A2 (en) Output stage for wireless transmitter
WO2003007471A2 (en) Mixer
US20240120959A1 (en) Multiband radio receivers
JP2013123213A (ja) 増幅器中での高調波および混変調の除去による広帯域線形化

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20949078

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20949078

Country of ref document: EP

Kind code of ref document: A1