WO2022021047A1 - 驱动装置、芯片、拍摄装置和无人机 - Google Patents

驱动装置、芯片、拍摄装置和无人机 Download PDF

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Publication number
WO2022021047A1
WO2022021047A1 PCT/CN2020/105057 CN2020105057W WO2022021047A1 WO 2022021047 A1 WO2022021047 A1 WO 2022021047A1 CN 2020105057 W CN2020105057 W CN 2020105057W WO 2022021047 A1 WO2022021047 A1 WO 2022021047A1
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Prior art keywords
unit
capacitor
voltage
field effect
terminal
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PCT/CN2020/105057
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English (en)
French (fr)
Inventor
黄睿
陈龙
蔡畅
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深圳市大疆创新科技有限公司
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Priority to CN202080033628.5A priority Critical patent/CN113796006A/zh
Priority to PCT/CN2020/105057 priority patent/WO2022021047A1/zh
Publication of WO2022021047A1 publication Critical patent/WO2022021047A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M11/00—Power conversion systems not covered by the preceding groups
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00—Circuit arrangements for ac mains or ac distribution networks
    • H02J3/28—Arrangements for balancing of the load in a network by storage of energy
    • H02J3/32—Arrangements for balancing of the load in a network by storage of energy using batteries with converting means
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0068—Battery or charger load switching, e.g. concurrent charging and load supply
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/34—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering
    • H02J7/345—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering using capacitors as storage or buffering devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/53—Generators characterised by the type of circuit or by the means used for producing pulses by the use of an energy-accumulating element discharged through the load by a switching device controlled by an external signal and not incorporating positive feedback
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J2207/00—Indexing scheme relating to details of circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J2207/50—Charging of capacitors, supercapacitors, ultra-capacitors or double layer capacitors

Definitions

  • the embodiments of the present application relate to the field of electronic technology, and in particular, to a driving device, a chip, a photographing device, and an unmanned aerial vehicle.
  • energy storage capacitor components are usually used to realize the drive higher than the power supply voltage.
  • the drive device needs to manage the charge and discharge of the energy storage capacitor components while avoiding the problem of high current surge caused by the unconstant discharge power during the drive process.
  • a controller is usually used to control the operations of the charge management unit and the discharge drive unit respectively.
  • the present application provides a driving device, a chip, a photographing device and an unmanned aerial vehicle.
  • a driving device By multiplexing the structure of the charging circuit and the discharging circuit, the volume of the driving device is reduced, the control circuit is simplified, the circuit loss is reduced, and the power consumption is reduced.
  • a driving device including: a controller, an energy storage capacitor unit, and a multiplexing circuit;
  • the controller is connected to the multiplexing circuit, and is used for sending a control signal to the multiplexing circuit;
  • the multiplexing circuit is connected to the energy storage capacitor unit, and is used for charging or discharging the energy storage capacitor unit in response to a control signal of the controller, and outputting a drive signal to the target load;
  • the multiplexing circuit includes a filter circuit unit, and the filter circuit unit is electrically connected between the controller and the target load, and between the energy storage capacitor unit and the target load;
  • the filter circuit unit When the energy storage capacitor unit is charged, the filter circuit unit is used as a passive network of a charging loop, and when the energy storage capacitor unit is discharged, the filter circuit unit is used as an EMI filter.
  • a chip including the driving device described in the first aspect of the present application.
  • a photographing device including a target load, and the chip according to the second aspect of the present application or the driving device according to the first aspect of the present application.
  • an unmanned aerial vehicle comprising a main body and a photographing device according to the first aspect of the present application mounted on the main body.
  • the application provides a driving device, a chip, a photographing device and an unmanned aerial vehicle.
  • the driving device is connected to a multiplexing circuit through a controller, and sends a control signal to the multiplexing circuit; the multiplexing circuit is connected to an energy storage capacitor unit, and responds to the The control of the controller is to charge or discharge the energy storage capacitor unit, and output a drive signal to the target load, wherein the multiplexing circuit includes a filter circuit unit, and the filter circuit unit is electrically connected between the controller and the controller. Between the target loads, and between the energy storage capacitor unit and the target load; when charging the energy storage capacitor unit, the filter circuit unit is used as a passive network of the charging loop.
  • the filter circuit unit When the energy storage capacitor unit is discharged, the filter circuit unit is used as an EMI filter, thereby realizing the structural reuse of the charging circuit and the discharging circuit, reducing the volume of the driving device, simplifying the control circuit, reducing the circuit loss and reducing the power consumption. Small power consumption.
  • FIG. 1 is a schematic structural diagram of a driving device provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of another driving device provided by an embodiment of the present application.
  • FIG. 2A-2C are schematic diagrams of charging and discharging stages based on the structure of FIG. 2 provided by an embodiment of the present application;
  • FIG. 3 is a schematic structural diagram of yet another driving device provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of another driving device provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a capacitor voltage balancing unit provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of another capacitor voltage equalizing unit provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of yet another capacitor voltage equalizing unit provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a tree-connected capacitor voltage equalizing unit provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a driving device for pre-boosting provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a pre-boost unit provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of another pre-boost unit provided by an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of yet another pre-boost unit provided by an embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of another pre-boost unit provided by an embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of another pre-boost unit provided by an embodiment of the present application.
  • 15 is a schematic structural diagram of an adder unit provided by an embodiment of the present application.
  • 16 is a schematic diagram of a chip structure provided by an embodiment of the present application.
  • FIG. 17 is a schematic structural diagram of a photographing device provided by an embodiment of the present application.
  • FIG. 18 is a schematic structural diagram of an unmanned aerial vehicle provided by an embodiment of the present application.
  • Q1 the first switch unit Q1; Q2: the second switch unit; Q3: the third switch unit; Q4: the fourth switch unit; L1: the first inductance unit; L2: the second inductance unit; D1: the first resistance circulating diode ;D2: the second blocking diode;
  • Vcap voltage node
  • Vs power supply terminal
  • C1 first filter capacitor unit
  • C2 second filter capacitor unit
  • 131 main gate drive unit
  • g1 first output terminal
  • g2 second output terminal
  • g3 The third output terminal
  • g4 the fourth output terminal
  • capacitor sub-unit 14: capacitor voltage equalizing unit;
  • Rp1 first reference voltage dividing unit;
  • Rp2 second reference voltage dividing unit;
  • U1 comparator;
  • RF+ positive feedback impedance unit;
  • RF- negative feedback impedance unit ;
  • Cosc oscillating capacitor unit;
  • Lo filter inductor unit;
  • 141 buffer unit; 14a: first capacitor voltage equalization unit; 14b: second capacitor voltage equalization unit; 14c: third capacitor voltage equalization unit; CL1: first storage capacitor; CL2: second storage capacitor; CL3: third capacitor Storage capacitor; CL4: fourth storage capacitor;
  • 15 pre-boost unit; 151: first half-bridge control unit; 152: second half-bridge energy storage unit; 1511: first gate driver; G1: first field effect transistor; G2: second field effect transistor; Cfly1: The first flying capacitor; Cout1: The first output capacitor; 1521: The second gate driver; Rd: Coupling resistor; Cd: Coupling capacitor; G3: The third field effect transistor; G4: The fourth field effect transistor; Db1: the first bootstrap diode; Cb1: the first isolation capacitor; Db2: the second bootstrap diode; Cb2: the second isolation capacitor;
  • G5 fifth field effect transistor
  • G6 sixth field effect transistor
  • G7 seventh field effect transistor
  • G8 eighth field effect transistor
  • R1 first filter resistor
  • R2 The second filter resistor
  • R3 the third filter resistor
  • R4 the fourth filter resistor
  • C31 the first filter capacitor
  • C32 the second filter capacitor
  • C33 the third filter capacitor
  • C34 the fourth filter capacitor
  • Cout2 the second output capacitor
  • Cfly2 the second flying capacitor
  • the drive device and energy storage capacitor components are usually used to realize the target load. drive.
  • the charging management and discharge driving of the energy storage capacitor components are realized by two independent circuits, and the circuit volume is relatively large; and the controller needs to use two independent control lines to control the charging management module. It is controlled separately from the discharge drive module, and the control circuit is complicated.
  • the present application provides a driving device, which uses a multiplexing circuit to realize the structure multiplexing of charge management and discharge drive, while reducing the circuit volume, simplifying the control circuit and reducing the circuit size. energy consumption on.
  • FIG. 1 is a schematic structural diagram of a driving device provided by an embodiment of the present application.
  • the driving device 10 shown in FIG. 1 includes a controller 11 , an energy storage capacitor unit 12 and a multiplexing circuit 13 .
  • the controller 11 is connected to the multiplexing circuit 13 for sending control signals to the multiplexing circuit 13 .
  • the multiplexing circuit 13 is connected to the energy storage capacitor unit 12, and is used for charging or discharging the energy storage capacitor unit 12 in response to the control signal of the controller 11, and outputting a drive signal to the target load.
  • the multiplexing circuit 13 includes a filter circuit unit, and the filter circuit unit is electrically connected between the controller 11 and the target load, and between the energy storage capacitor unit 12 and the target load; when the energy storage capacitor unit 12 is charged, the filter The circuit unit is used as a passive network of the charging loop. When the energy storage capacitor unit 12 is discharged, the filter circuit unit is used as an electromagnetic interference (Electromagnetic Interference, EMI for short) filter.
  • electromagnetic interference Electromagnetic Interference, EMI for short
  • the communication between the controller 11 and the multiplexing circuit 13 is the connection communication of the multiplexed signal lines.
  • the alternate control of charging and discharging can be realized through the control of the timing sequence, so as to realize the multiplexing and simplification of the control circuit.
  • the driving device is connected to the multiplexing circuit through the controller, and sends a control signal to the multiplexing circuit; the multiplexing circuit is connected to the energy storage capacitor unit, and charges the energy storage capacitor unit in response to the control of the controller Or discharge, and output a drive signal to the target load, wherein the multiplexing circuit includes a filter circuit unit, and the filter circuit unit is electrically connected between the controller and the target load, and between the energy storage capacitor unit and the target load; When the energy capacitor unit is charged, the filter circuit unit is used as a passive network of the charging circuit. When the energy storage capacitor unit is discharged, the filter circuit unit is used as an EMI filter.
  • the drive unit is reduced. The volume occupied by the device is conducive to miniaturization applications, and by controlling the multiplexing of signal lines, the signal lines are simplified and the circuit reliability is improved.
  • control signal output by the above-mentioned controller to the multiplexing circuit may be a multiplexed control signal, that is, the controller sends a control signal while controlling the multiplexing circuit to charge or discharge the energy storage capacitor unit. After that, the multiplexing circuit outputs the driving signal to the target load.
  • control signal output by the above-mentioned controller to the multiplexing circuit can also be an independent control signal, that is, the controller sends a control signal to control the multiplexing circuit to charge or discharge the energy storage capacitor unit, and sends another control signal to control the multiplexing.
  • the circuit outputs the drive signal to the target load.
  • the multiplexing circuit may further include a switch circuit unit, which is electrically connected between the controller and the filter circuit unit, and between the energy storage capacitor unit and the filter circuit unit, for controlling the energy storage capacitor unit to charge or discharge . It can be understood that there are other control signal sending manners in the specific implementation process, which are not limited in this application.
  • the multiplexing circuit may further include a blocking circuit unit, and the blocking circuit unit is electrically connected between the filtering circuit unit and the target load. When the energy storage capacitor unit supplies power to the target load through the filter circuit unit, the blocking circuit unit plays a blocking role to avoid circulating current.
  • FIG. 2 is a schematic structural diagram of another driving device provided by an embodiment of the present application.
  • the controller 11 is not shown, the energy storage capacitor unit 12 is represented by a single capacitor, and the multiplexing circuit 13 may specifically include a first switch unit Q1 (in the figure, a field effect transistor is used as an example) ), the second switching unit Q2 (the FET is used as an example in the figure), the third switching unit Q3 (the FET is used as an example in the figure), the fourth switching unit Q4 (the FET is used as an example in the figure), A first inductance unit L1 (in the figure, a single inductance is used as an example), a second inductance unit L2 (in the figure, a single inductance is used as an example), a first choke diode D1, and a second choke diode D2.
  • a first switch unit Q1 in the figure, a field effect transistor is used as an example
  • the second switching unit Q2 the FET is used as an example in the figure
  • the multiplexing circuit 13 can be understood as an H-bridge circuit with charge and discharge multiplexing, and the circuits connected on both sides of the target load are basically symmetrical and consistent.
  • One end of the storage capacitor unit 12 is connected to the voltage node Vcap, and the other end is grounded.
  • one end of the first switch unit Q1 is connected to the ground terminal through the second switch unit Q2 , and the other end is connected to the high voltage terminal of the energy storage capacitor unit.
  • One end of the first inductance unit L1 is connected to the target load, and the other end is connected between the first switch unit Q1 and the second switch unit Q2.
  • the anode of the first choke diode D1 is connected to the power supply terminal Vs, and the cathode is connected between the first inductance unit L1 and the target load.
  • One end of the fourth switch unit Q4 is connected to the ground end through the third switch unit Q3, and the other end is connected to the high voltage end of the energy storage capacitor unit.
  • the second inductance unit L2 is connected to the target load, and the other end is connected between the fourth switch unit Q4 and the third switch unit Q3.
  • the anode of the second choke diode D2 is connected to the power supply terminal Vs, and the cathode is connected between the second inductance unit L2 and the target load.
  • the low voltage end of the energy storage capacitor unit is connected to the ground end.
  • the first switch unit Q1, the second switch unit Q2, the third switch unit Q3, and the fourth switch unit Q4 are all N-type field effect transistors as examples, but may also be transistors, relays, etc. with switching functions components.
  • the first switch unit Q1, the second switch unit Q2, the third switch unit Q3, and the fourth switch unit Q4 are all connected in the forward direction.
  • the forward connection is that the source of each switch unit shown in FIG. 2 is connected to a low potential, the drain is connected to a high potential, and each switch tube is forward biased.
  • the control terminal of the first switch unit Q1, the control terminal of the second switch unit Q2, the control terminal of the third switch unit Q3, and the control terminal of the fourth switch unit Q4 are all connected to the controller connect.
  • the gate of the first switch unit Q1, the gate of the second switch unit Q2, the gate of the third switch unit Q3, and the gate of the fourth switch unit Q4 in FIG. 2 are all connected to the controller for responding to the controller turn on or off each switch tube under the control of .
  • the controller is specifically configured to issue a control signal for controlling the turn-on sequence of the first switch unit Q1 , the second switch unit Q2 , the third switch unit Q3 and the fourth switch unit Q4 .
  • the right half bridge formed by the inductor unit L2 and the second blocking diode D2 is symmetrical in structure, and the charging and discharging principles are similar.
  • the charging and discharging process of the left half bridge is used as an example for illustration.
  • the turn-on and turn-off of the first switch unit Q1 and the second switch unit Q2 are controlled by a control signal sent by the controller.
  • FIG. 2A-2C are schematic diagrams of charging and discharging stages based on the structure of FIG. 2 provided by an embodiment of the present application.
  • the realization of a complete charging and discharging process in FIG. 2 may include three stages in sequence: in the first stage, as shown in FIG. 2A , the controller controls the first switching unit Q1 to be turned off and the second switching unit Q2 to be turned on, and the first resistance
  • the circulating diode D1 is forward biased to provide a charging current path, and the power supply terminal Vs directly charges the first inductance unit L1 to realize the charging of the first inductance unit L1; in the second stage, as shown in FIG. 2B, the controller controls the first inductance unit L1.
  • a switch unit Q1 is turned on and the second switch unit Q2 is turned off.
  • the first inductance unit L1 is equivalent to a current source discharging to the energy storage capacitor unit, and the current on the first inductance unit L1 is gradually reduced to 0.
  • the inductor unit L1 discharges the target load to drive the target load, and at this stage, the first blocking loop diode D1 is reverse biased to block the discharge current path from the power supply terminal Vs to avoid circulating current.
  • the charging stage can be understood as the process in which the power supply terminal Vs transfers energy to the energy storage capacitor unit through the first inductance unit L1 in the first and second stages. Since the energy transfer process has nothing to do with the voltage of the capacitor, the current The charging power in the charging phase is constant in the embodiment.
  • the discharge stage can be understood as being in the third stage, the energy storage capacitor unit discharges to the target load through the first switch unit Q1 and the first inductance unit L1. In the structure shown in FIG.
  • the first blocking current diode D1 and the second blocking current diode D2 isolate the charging process and the discharging process of the half bridge on both sides, so as to avoid the high-voltage reverse feeding power supply terminal Vs during the discharging process, thus realizing the
  • the structures of the charging path and the discharging path are multiplexed, which reduces the volume of the charging circuit and the discharging circuit.
  • the energy storage capacitor unit can also be connected with the controller to realize feedback and monitoring of the charging condition, so that the controller can further control the working state of each switch unit according to the charging condition of the energy storage capacitor unit, so that the energy storage capacitor unit is always in the pre-set state. fluctuates around the set voltage value.
  • FIGS 2A-2C show the charging and discharging process of the left half bridge in Figure 2, and the charging and discharging sequence of the left half bridge and the right half bridge in Figure 2 discharging the target load can be performed alternately, or it can be synchronously.
  • the discharge timings of the left half-bridge and the right half-bridge may be reversed.
  • the left half-bridge is in the first stage and the second stage in the T1 period, that is, first the first switch unit Q1 is turned off, the second switch unit Q2 is turned on to charge the first inductance unit L1, and then The first switch unit Q1 is turned on and the second switch unit Q2 is turned off to charge the energy storage capacitor unit; while the right half bridge is in the third stage during the T1 period, that is, the third switch unit Q3 is kept off and the fourth switch is kept off.
  • the unit Q4 is turned on to form a discharge path for the energy storage capacitor unit to the target load.
  • the left half bridge enters the third stage in the T2 period after T1, that is, keeping the first switch unit Q1 on and the second switch unit Q2 off to form a discharge path for the energy storage capacitor unit to the target load; and the right half bridge
  • the bridge enters the first stage and the second stage, that is, first the fourth switch unit Q4 is turned off, the third switch unit Q3 is turned on to charge the second inductance unit L2, and then the fourth switch unit Q4 is turned on, The third switch unit Q3 is turned off to charge the energy storage capacitor unit.
  • This cycle T1-T2 realizes the alternate charging and discharging of the left half bridge and the right half bridge to the target load.
  • the left half bridge and the right half bridge alternately discharge the target load, which reduces the output current of the power supply terminal Vs, reduces the loss of the transmission line, and reduces the impact on the power supply terminal Vs.
  • the discharge sequence of the left half-bridge and the right half-bridge may be the same.
  • the left half bridge and the right half bridge are in the first stage and the second stage at the same time at T1, that is, the first switch unit Q1 is turned off first, the second switch unit Q2 is turned on, and the first inductance unit L1 is turned on.
  • the fourth switch unit Q4 is turned off, the third switch unit Q3 is turned on to charge the second inductor unit L2, and then the first switch unit Q1 is turned on and the second switch unit Q2 is turned off to charge the energy storage capacitor unit, At the same time, the fourth switch unit Q4 is turned on, and the third switch unit Q3 is turned off to charge the energy storage capacitor unit.
  • both the left half bridge and the right half bridge enter the third stage during the T2 period, that is, keeping the first switch unit Q1 on and the second switch unit Q2 off to form a discharge path for the energy storage capacitor unit to the target load, while maintaining The third switch unit Q3 is turned off and the fourth switch unit Q4 is turned on to form a discharge path for the energy storage capacitor unit to the target load.
  • This cycle of T1-T2 realizes the synchronous charge and discharge of the left half bridge and the right half bridge to the target load. Targeted load synchronous discharge simplifies timing control.
  • the first inductance unit L1 and the second inductance unit L2 may both be a single inductance as shown in FIG. 2 , or may be a component composed of multiple inductances, which is not limited herein.
  • the above-mentioned first switch unit Q1, second switch unit Q2, third switch unit Q3, and fourth switch unit Q4 may be N-type field effect transistors as shown in FIG. 2, transistors, relays, etc. The realization principle and technical effect of the device with switch control are similar to those of the field effect transistor shown in FIG. 2 , which will not be repeated here.
  • FIG. 3 is a schematic structural diagram of another driving device provided by an embodiment of the present application.
  • the filter circuit unit in the multiplexing circuit shown in FIG. 3 may specifically include a first filter capacitor unit C1 and a second filter capacitor unit C2, which are respectively connected with the first inductance unit L1 and the second inductance unit L2.
  • the LC low-pass filter is formed to realize the filtering during the discharge process of the energy storage capacitor unit.
  • one end of the first filter capacitor unit C1 is connected between the first inductance unit L1 and the target load, and the other end is connected to the ground.
  • the first inductance unit L1 and the second inductance unit L2 are both used as charging inductances in the first stage shown in FIG. 2A and the second stage shown in FIG. 2B, but in the third stage shown in FIG. 2C, they are the same as the charging inductance.
  • the first filter capacitor unit C1 and the second filter capacitor unit C2 form a second-order low-pass filter, which reduces the high-order harmonics input to the target load and reduces the electromagnetic interference radiated by the target load to the outside.
  • the first filter capacitor unit C1 and the second filter capacitor unit C2 in this embodiment the energy recovery of the bulk capacitance in the switch unit can be realized. Specifically, during the dead time of the third stage of the embodiment shown in FIG. 2C, the bulk capacitance of the second switching unit Q2 can discharge the first filter capacitance unit C1 through the first inductance unit L1, and the energy of the bulk capacitance is transferred. stored in the first filter capacitor unit C1. In the first stage of the embodiment shown in FIG.
  • this part of the energy stored by the first filter capacitor unit C1 also participates in the charging of the first inductor unit L1, so that the first filter capacitor unit C1 realizes the The energy recovery of the bulk capacitance of the two switching units Q2.
  • the second filter capacitor unit C2 realizes the recovery of the bulk capacitance energy of the third switch unit Q3 based on the same principle.
  • FIG. 4 is a schematic structural diagram of another driving device provided by the embodiment of the present application.
  • the multiplexing circuit shown in FIG. 4 also includes a main gate driving unit 131, which is used to convert the control signal from the controller into a signal for driving the gate of the switch tube.
  • the gate driving signal, the main gate driving unit may be the main gate driver.
  • the main gate driving unit 131 has one input terminal for accessing the multiplexed signal and four output terminals (g1, g2, g3, g4).
  • the input terminal of the main gate driving unit 131 is connected to the controller, the first output terminal g1 is connected to the control terminal of the first switching unit Q1, the second output terminal g2 is connected to the control terminal of the second switching unit Q2, and the first output terminal g1 is connected to the control terminal of the second switching unit Q2.
  • the three output terminals g3 are connected to the control terminal of the third switch unit Q3, and the fourth output terminal g4 is connected to the control terminal of the fourth switch unit Q4.
  • the main gate driving unit 131 converts the control signal from the controller into a switch driving signal that can directly drive each switch unit. In FIG.
  • the first switch unit Q1 , the second switch unit Q2 , the third switch unit Q3 , and the fourth switch unit Q4 are field effect transistors, and their respective control terminals are the gates of the field effect transistors. If the first switch unit Q1, the second switch unit Q2, the third switch unit Q3, and the fourth switch unit Q4 are transistors, the control terminal is the base of the transistors. If the first switch unit Q1, the second switch unit Q2, the third switch unit Q3, and the fourth switch unit Q4 are relays, the control terminal is a switching control port of the relay.
  • the energy storage capacitor unit may be a capacitor or an assembly composed of multiple capacitors, which is not limited herein.
  • a capacitor voltage equalizing unit can be added to perform voltage equalization.
  • the capacitor included in the energy storage capacitor unit may be a Farad capacitor.
  • FIG. 5 is a schematic structural diagram of a capacitor voltage balancing unit provided by an embodiment of the present application.
  • the energy storage capacitor unit may specifically include two capacitor sub-units 121 .
  • the driving device may further include a capacitor voltage equalizing unit 14 as shown in FIG. 5 .
  • the capacitor voltage equalizing unit 14 is connected between the two capacitor subunits 121 shown in FIG. 5 , and is used for equalizing the voltage of the two capacitor subunits 121 .
  • the capacitor subunit 121 is exemplified by a single capacitor, but each capacitor subunit 121 may specifically be a component including multiple capacitors, or a capacitor-type component composed of capacitors and other electronic devices.
  • the structures of the capacitor subunits 121 on both sides of the access position of the capacitor voltage equalizing unit 14 should be consistent to realize a symmetrical structure in which two capacitor subunits 121 are connected in series.
  • the specific structure of a single capacitor subunit 121 is not limited in this embodiment.
  • the capacitor subunit 121 in the storage capacitor unit may be a Farad capacitor.
  • the capacitor voltage equalizing unit 14 in FIG. 5 may include: a first reference voltage dividing unit Rp1, a second reference voltage dividing unit Rp2, a comparator U1, a positive feedback impedance unit RF+, a negative feedback impedance unit RF-, an oscillating capacitor unit Cosc, and a filter Inductance unit Lo.
  • the first reference voltage dividing unit Rp1 and the second reference voltage dividing unit Rp2 are connected in series between the high voltage end and the ground end of the energy storage capacitor unit.
  • the high voltage terminal of the energy storage capacitor unit in FIG. 5 is the voltage node Vcap connected to the energy storage capacitor unit shown in FIG.
  • the reference voltage of , and the voltage value is half of the voltage of the voltage node Vcap.
  • the first reference voltage dividing unit Rp1 and the second reference voltage dividing unit Rp2 may be, for example, the resistors shown in FIG. 5 or other impedance-type components, which are not limited herein.
  • the non-inverting input terminal of the comparator U1 (indicated by the symbol +) is connected between the first reference voltage dividing unit Rp1 and the second reference voltage dividing unit Rp2, thereby accessing the reference voltage.
  • the inverting input terminal of the comparator U1 (marked with a symbol -) is connected to the ground terminal through the oscillation capacitor unit Cosc.
  • the first end of the filter inductor unit Lo is connected to the output end of the comparator U1 , and the second end is connected between the two capacitor subunits 121 .
  • One end of the positive feedback impedance unit RF+ is connected to the non-inverting input end of the comparator U1, and the other end is connected to the output end of the comparator U1.
  • One end of the negative feedback impedance unit RF- is connected to the inverting input end of the comparator U1, and the other end is connected to the second end of the filter inductance unit Lo.
  • the capacitor voltage equalization unit 14 does not need to communicate with the controller, so that the capacitor voltage equalization with high dynamic response accuracy can be realized.
  • the capacitor voltage equalizing unit 14 After the capacitor voltage equalizing unit 14 is powered on, it can enter into a very high frequency oscillation state, so that the comparator U1 outputs a pulse width modulation (PWM) wave whose duty cycle and frequency are changed.
  • the voltage value of the voltage node Vcap is U Cap
  • the resistance values of the first reference voltage dividing unit Rp1 and the second reference voltage dividing unit Rp2 are both R P
  • the resistance values of the positive feedback impedance unit RF+ and the negative feedback impedance unit RF- All are RF .
  • the voltage of one of the capacitor sub-units 121 is slightly higher, its energy will be absorbed by the filter inductance unit Lo and transferred to the other capacitor sub-unit 121 with a lower voltage to achieve energy transfer and voltage balance.
  • the first reference voltage dividing unit Rp1, the second reference voltage dividing unit Rp2, the positive feedback impedance unit RF+, and the negative feedback impedance unit RF- may be a single resistor as shown in FIG. 5, or may be composed of multiple resistors.
  • the oscillating capacitor unit Cosc can be a single capacitor as shown in Figure 5, or it can be a component composed of multiple capacitors;
  • the filter inductance unit Lo can be a single inductor as shown in Figure 5, or it can be composed of multiple inductors components, which are not limited in this embodiment.
  • FIG. 6 is a schematic structural diagram of another capacitor voltage equalizing unit provided by the embodiments of the present application.
  • FIG. 7 is a schematic structural diagram of still another capacitor voltage equalizing unit provided by an embodiment of the present application.
  • the capacitor voltage equalization unit 14 shown in FIG. 6 and FIG. 7 may further include a buffer unit 141 .
  • the output end of the comparator U1 is connected to the first end of the filter inductance unit Lo through the buffer unit 141 .
  • the buffer unit 141 may be a Complementary Metal Oxide Semiconductor (Complementary Metal Oxide Semiconductor, CMOS) buffer circuit composed of two field effect transistors as shown in FIG. 6 , or may be two transistors as shown in FIG. 7 . composed of bipolar transistor buffer circuit.
  • CMOS Complementary Metal Oxide Semiconductor
  • the CMOS buffer circuit shown in Figure 6 can achieve smaller losses; while in the capacitor bank voltage equalization scenario with higher voltage, the use of the CMOS buffer circuit shown in Figure 7
  • the bipolar transistor snubber circuit shown can achieve smaller losses.
  • each capacitor subunit 121 in the energy storage capacitor unit may specifically include: 2 n capacitor cells, and 2 n ⁇ 1 There are capacitor voltage equalization units 14 connected in a tree shape, and n is an integer greater than 0.
  • FIG. 8 is a schematic structural diagram of a capacitor voltage balancing unit connected in a tree shape provided by an embodiment of the present application. In the tree-shaped connection structure shown in FIG.
  • the first capacitor voltage equalization unit 14a, the second capacitor voltage equalization unit 14b, and the third capacitor voltage equalization unit 14c are three capacitor voltage equalization circuits with the same structure, and the first storage capacitor CL1 and the second storage capacitor CL2 are connected in series to form one capacitor sub-unit 121 , and the third storage capacitor CL3 and the fourth storage capacitor CL4 are connected in series to form another capacitor sub-unit 121 .
  • the first storage capacitor CL1, the second storage capacitor CL2, the third storage capacitor CL3 and the fourth storage capacitor CL4 are connected in series between the voltage node Vcap and the ground terminal in sequence.
  • the first capacitor voltage equalizing unit 14a is connected between the second storage capacitor CL2 and the third storage capacitor CL3
  • the second capacitor voltage equalizing unit 14b is connected between the first storage capacitor CL1 and the second storage capacitor CL2
  • the third capacitors are both
  • the voltage unit 14c is connected between the third storage capacitor CL3 and the fourth storage capacitor CL4.
  • the voltage node Vcap is used as the high voltage terminal of the second capacitor voltage equalizing unit 14b
  • the second storage capacitor CL2 and the third storage capacitor CL3 are used as the ground terminal of the second capacitor voltage equalizing unit 14b
  • the second storage capacitor CL2 and the third storage capacitor CL2 The high voltage terminal of the third storage capacitor CL3 is used between the storage capacitors CL3, and the third storage capacitor CL3 is directly connected to the ground terminal.
  • FIG. 9 is a schematic structural diagram of a driving device for pre-boosting provided by an embodiment of the present application.
  • the driving device shown in FIG. 9 may further include a pre-boosting unit 15 .
  • the multiplexing circuit is connected to the power supply terminal Vs through the pre-boost unit 15 .
  • the pre-boosting unit 15 is used to boost the voltage of the power supply terminal Vs and transmit it to the multiplexing circuit.
  • the current will be reduced to 1/2-1/4 of the original current.
  • the reduction of the current in the circuit can realize the reduction of heat generation and the reduction of the inductance size of the energy storage capacitor unit, and further reduce the energy consumption of the circuit.
  • the pre-boost unit 15 shown in FIG. 9 may be a conventional DC/DC circuit, such as a boost circuit, but the power inductor will occupy a larger size, resulting in a larger overall circuit size.
  • the pre-boost unit 15 can also be implemented using a switched capacitor converter (SCC).
  • SCC switched capacitor converter
  • the existing diode switched capacitor converter has low efficiency due to the existence of diodes, and needs to be used with an AC power supply.
  • the AC power itself belongs to the inverter circuit, which needs to occupy a certain size. It is difficult to realize the miniaturization of the circuit when it is used together with the bulky diode array and capacitor array.
  • the diodes and capacitors in the existing diode switched capacitor converter need to withstand twice the power supply voltage, and the voltage stress is relatively high, which is not conducive to optimizing the cost. Moreover, the output impedance in the equivalent model of the diode switched capacitor converter is relatively high, which is not conducive to high-power scenarios.
  • FIG. 10 is a schematic structural diagram of a pre-boost unit provided by an embodiment of the present application. As shown in FIG. 10 , the pre-boost unit 15 specifically includes a first half-bridge control unit 151 and a second half-bridge energy storage unit 152 .
  • the first half-bridge control unit 151 is connected to the controller, the second half-bridge energy storage unit 152, the power supply terminal Vs and the ground terminal, and is used for responding to the control of the controller to convert the power supply voltage signal of the power supply terminal Vs or the ground voltage signal of the ground terminal It is transmitted to the second half-bridge energy storage unit 152 .
  • the second half-bridge energy storage unit 152 is also connected to the controller, the multiplexing circuit, the DC terminal and the ground terminal, and is used for turning on the DC terminal in response to the control of the controller when the first half-bridge control unit 151 transmits the ground voltage signal. Charging and storing energy, and when the first half-bridge control unit 151 transmits the power supply voltage signal, the ground terminal is turned on in response to the control of the controller to boost and discharge the output to the multiplexing circuit.
  • the number of the second half-bridge energy storage unit 152 may be one or more. If the pre-boost unit 15 includes only one second half-bridge energy storage unit 152 , the DC terminal corresponding to the second half-bridge energy storage unit 152 is directly the power terminal Vs. For example, in FIG. 10 , a first half-bridge control unit 151 and a second half-bridge energy storage unit 152 realize a boost output that increases the voltage of the power supply terminal Vs to 2 times. If the number of the second half-bridge energy storage units 152 included in the pre-boost unit 15 is M greater than 1, FIG. 11 is a schematic structural diagram of another pre-boost unit provided by the embodiment of the present application. As shown in FIG.
  • the M second half-bridge energy storage units 152 are connected in sequence, each second half-bridge energy storage unit 152 is connected to the first half-bridge control unit 151, and the first and second half-bridge energy storage units
  • the DC terminal corresponding to the bridge energy storage unit 152 is the output terminal of the power supply unit, and the DC terminals corresponding to the remaining M-1 second half-bridge energy storage units 152 are the output terminals of the second half-bridge energy storage unit 152 in the sequence.
  • the last second half-bridge energy storage unit 152 is connected to the multiplexing circuit. As shown in FIG. 11 , the second second half-bridge memory cell in sequence is the last second half-bridge memory cell connected in sequence, and the output voltage thereof is three times the voltage of the power supply terminal Vs.
  • a second half-bridge storage unit Each time a second half-bridge storage unit is added, the output voltage of the previous second half-bridge storage unit is added with 1 times the voltage of the power supply terminal. Therefore, by increasing the number of the second half-bridge memory cells connected in sequence, a pre-boost in which the output voltages are superimposed one by one by 1 times the voltage of the power supply terminals can be realized.
  • a single second half-bridge storage unit may be equivalent to one voltage adder unit 153 .
  • the first half-bridge control unit 151 includes: a first gate driver 1511 , a first field effect transistor G1 and a second field effect transistor G2 .
  • the first field effect transistor G1 and the second field effect transistor G2 are connected in series between the power supply terminal Vs and the ground terminal.
  • the forward series connection can be understood that the first field effect transistor G1 and the second field effect transistor G2 are connected in series, and both are connected positively.
  • the first field effect transistor G1 and the second field effect transistor G2 are both N-type field effect transistors.
  • the first gate driver 1511 is used to convert the control signal output by the controller into a gate driving signal for the first field effect transistor G1 and the second field effect transistor G2.
  • the high-side driving signal output terminal (Vho) of the first gate driver 1511 is connected to the gate of the first field effect transistor G1
  • the half-bridge module output terminal (VS) of the first gate driver 1511 is connected to the first gate driver 1511.
  • the low-side driving signal output terminal (Vlo) of the first gate driver 1511 is connected to the gate of the second field effect transistor G2
  • the high side of the first gate driver 1511 is connected to the gate of the second field effect transistor G2.
  • the side input terminal (Hin) and the low side input terminal (Lin) are connected with the controller.
  • the second half-bridge energy storage unit 152 includes: a first flying capacitor Cfly1Cfly1, a first output capacitor Cout1Cout1, a second gate driver 1521, a coupling resistor Rd, a coupling capacitor Cd, a third field effect transistor G3 and a fourth field effect transistor Tube G4.
  • the third field effect transistor G3 and the fourth field effect transistor G4 are connected in reverse series, the drain of the third field effect transistor G3 is connected to the ground terminal through the first output capacitor Cout1, and the source of the fourth field effect transistor G4 is connected to the ground terminal. DC terminal connection. As shown in FIG. 10 and FIG.
  • the reversed series connection can be understood that the third field effect transistor G3 and the fourth field effect transistor G4 are connected in series, and both are reversely connected.
  • the third field effect transistor G3 and the fourth field effect transistor G4 are also N-type field effect transistors.
  • the second gate driver 1521 is used to convert the control signal output by the controller into a gate driving signal for the third field effect transistor G3 and the fourth field effect transistor G4.
  • the high-side driving signal output terminal (Vho) of the second gate driver 1521 is connected to the gate of the third field effect transistor G3, and the low-side driving signal output terminal (Vlo) of the second gate driver 1521 is connected to the third FET G3 through the coupling capacitor Cd.
  • the gates of the four field effect transistors G4 are connected, one end of the coupling resistor Rd is connected to the DC terminal, the other end is connected between the fourth field effect transistor G4 and the coupling capacitor Cd, and the high-side input terminal of the second gate driver 1521 ( Hin) and the low-side input (Lin) are connected to the controller.
  • One end of the first flying capacitor Cfly1 is connected to the output end (VS) of the half-bridge module of the second gate driver 1521 , and the other end is connected between the first field effect transistor G1 and the second field effect transistor G2 .
  • the control signals input by the high-side input terminals (Hin) of each gate driver are synchronized with each other, and the low-side input terminals of each gate driver are synchronized with each other.
  • the control signals input to the side input terminal (Lin) are also synchronized with each other, but the control signals input to the high-side input terminal (Hin) and the low-side input terminal (Lin) are opposite. Therefore, the control of each FET in the pre-boost unit 15 realizes the pre-boost of the voltage of the power supply terminal.
  • the power supply terminal Vs is connected to the second half-bridge energy storage unit 152.
  • the first flying capacitor Cfly1 is charged so that its voltage polarity is left negative and right positive.
  • the first field effect transistor G1 and the third field effect transistor G3 are controlled to be turned on, and the second field effect transistor G2 and the fourth field effect transistor G4 are controlled to be turned off, the power supply terminal Vs and the first flying capacitor Cfly1 whose voltage is Vs Connected in series, the first output capacitor Cout1 is charged by the third field effect transistor G3 outputting a voltage of 2Vs to achieve the 2Vs output shown in FIG. 10 or the 3Vs output shown in FIG. 11 .
  • the "inverted half bridge" formed by the reverse connection of the third field effect transistor G3 and the fourth field effect transistor G4 shown in FIG. 10 and FIG. 11 realizes a special synchronous rectification network.
  • the FET works in a synchronous rectification state, that is, the conduction of the fourth FET G4 will shield its body diode, and the conduction of the third FET G3 will shield its body diode.
  • the gate needs a higher driving voltage than Vs.
  • the high-side driving signal output terminal (Vho) of the second gate driver 1521 is already occupied by the third field effect transistor G3, so in the above embodiment, the AC coupling network composed of the coupling resistor Rd and the coupling capacitor Cd, the second gate
  • the AC driving component provided by the low-side driving signal output terminal (Vlo) of the pole driver 1521 provides the driving voltage for the fourth field effect transistor G4.
  • the coupling capacitor Cd isolates the DC component output by the low-side driving signal output terminal (Vlo), and finally couples a driving voltage with an amplitude of Vd/2 on the gate of the fourth field effect transistor G4 to realize the driving of the fourth field effect transistor G4 .
  • the output voltage of the low-side driving signal output terminal (Vlo) of the second gate driver 1521 is Vd
  • the high-side driving signal output terminal (Vho) of the second gate driver 1521 is relative to the output terminal of the half-bridge module (VS ) output Vd voltage.
  • Vd is 12V
  • the gate voltage through capacitive coupling is 6V.
  • both the first gate driver 1511 and the second gate driver 1521 may be bootstrap gate drivers, thereby reducing hardware cost.
  • the first half-bridge control unit 151 further includes a first bootstrap diode Db1 and a first isolation capacitor Cb1. As shown in FIG. 10 and FIG. 11 , the anode of the first bootstrap diode Db1 is connected to the chip power supply terminal (Vd) of the first gate driver 1511 , and the cathode is connected to the floating power supply terminal (Vb) of the first gate driver 1511 .
  • the second half-bridge control unit may further include a second bootstrap diode Db2 and a second isolation capacitor Cb2 .
  • the anode of the second bootstrap diode Db2 is connected to the second power supply terminal (the second power supply terminal and its voltage value are indicated by Vd+Vs in the figure), and the cathode is connected to the floating power supply terminal (Vb) of the second gate driver 1521 .
  • One end of the second isolation capacitor Cb2 is connected to the floating power supply terminal (Vb) of the second gate driver 1521, and the other end is connected to the output terminal (VS) of the half-bridge module of the second gate driver 1521; wherein, the second gate driver 1521
  • the power supply terminal (Vb) of the chip is also connected to the first power supply terminal, and the voltage of the second power supply terminal is the sum of the voltage of the power supply terminal and the voltage of the first power supply terminal.
  • the voltage required for the bootstrap diode of the bootstrap driver to drive the third field effect transistor G3 is Vd+Vs, where Vd can be a fully conductive field The voltage required by the effect tube.
  • Vd is also a voltage value provided by the first power supply terminal.
  • the gate driving of the field effect transistor is realized by a combination of AC coupling and bootstrapping.
  • each field effect transistor may be a silicon field effect transistor, or may be a new type of wide bandgap semiconductor device such as gallium nitride and silicon carbide, which is not limited herein.
  • the first gate driver 1511 and the second gate driver 1521 may be connected in series with additional damping resistors or fast discharge diodes, or may also be connected in parallel with components such as Zener diodes, which are not limited herein.
  • FIG. 12 is a schematic structural diagram of still another pre-boost unit provided by an embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of another pre-boost unit provided by an embodiment of the present application.
  • the pre-boost unit 15 may specifically include a single or multiple basic double voltage units 153 .
  • the multiplexing circuit is connected to the power supply terminal Vs through a single basic double voltage unit 153, and the power supply terminal Vs is a single basic double voltage unit 153.
  • the power supply terminal before the voltage doubling of the voltage doubling unit 153 is used to boost the voltage of the power supply terminal by 2 times and then transmit it to the multiplexing circuit.
  • the pre-boost unit 15 specifically includes K basic double voltage units 153 connected in sequence, and K is greater than or equal to An integer of 1.
  • the structure shown in FIG. 13 can be understood as an extension of the structure shown in FIG. 12 .
  • the specific way of connecting in sequence can be shown in Figure 13.
  • Each basic double voltage unit 153 is connected to the controller, and the power supply terminal before the voltage doubler connected to the first basic double voltage unit 153 is the power supply terminal Vs.
  • the pre-voltage power supply terminal connected to the two basic double voltage units 153 is the output terminal of the first basic double voltage unit 153, and so on.
  • the multiplexing circuit is connected to the power supply terminal Vs through K basic double voltage units 153 connected in sequence.
  • the K basic double voltage units 153 connected in sequence are used to boost the voltage of the power supply terminal by 2K times and then transmit it to the multiplexing circuit.
  • K are sequentially connected to the basic double voltage unit 153 in sequence, and the first basic double voltage unit 153 in sequence is connected to the power terminal Vs and the ground terminal, and is used to boost the power terminal voltage by 2 times and then output.
  • the remaining K-1 basic doubling units 153 are connected to the ground terminal and the voltage doubling output terminal of the previous basic doubling unit 153 in order to superimpose the output voltage of the previous basic doubling unit 153 in the sequence by 2 times the power supply. output after the terminal voltage.
  • the power supply terminal Vs is the power supply terminal before the voltage doubling of the first basic double voltage unit 153 in the sequence, and the voltage double output terminal of the first basic double voltage unit 153 in the sequence is the remaining K-1 basic double voltage units. 153 voltage doubler front power supply terminal.
  • the basic double voltage unit 153 specifically includes: a fifth field effect transistor G5, a sixth field effect transistor G6, a seventh field effect transistor G7, an eighth field effect transistor G8, a first filter resistor R1, The second filter resistor R2, the third filter resistor R3, the fourth filter resistor R4, the first filter capacitor C31, the second filter capacitor C32, the third filter capacitor C33, the fourth filter capacitor C34, and the second output capacitor Cout2 and the second flying capacitor Cfly2.
  • the fifth field effect transistor G5 and the sixth field effect transistor G6 are connected in series between the power supply terminal and the ground terminal before the voltage doubler, and the seventh field effect transistor G7 and the eighth field effect transistor G8 are connected in reverse series in the doubler between the power supply terminal and the ground terminal before voltage, and the eighth field effect transistor G8 is connected to the ground terminal through the second output capacitor Cout2.
  • the forward series connection means that the fifth field effect transistor G5 and the sixth field effect transistor G6 are connected in series with each other, and they are all connected directly;
  • the reverse series connection means that the seventh field effect transistor G7 and the eighth field effect transistor G8 are connected in series with each other, and they are all connected in reverse. .
  • the fifth field effect transistor G5 and the eighth field effect transistor G8 are P-type field effect transistors; the sixth field effect transistor G6 and the seventh field effect transistor G7 are N-type field effect transistors.
  • One end of the first filter resistor R1 is connected to the power supply terminal before the voltage doubling, the other end is connected to the controller through the first filter capacitor C31, and the gate of the fifth field effect transistor G5 is connected to the first filter resistor R1 and the first filter between capacitor C31.
  • One end of the second filter resistor R2 is connected to the ground terminal, the other end is connected to the controller through the second filter capacitor C32, and the gate of the sixth field effect transistor G6 is connected to between the second filter resistor R2 and the second filter capacitor C32 between.
  • One end of the third filter resistor R3 is connected to the power supply terminal before the voltage doubling, the other end is connected to the controller through the third filter capacitor C33, and the gate of the seventh field effect transistor G7 is connected to the third filter resistor R3 and the third filter between capacitor C33.
  • One end of the fourth filter resistor R4 is connected to the ground terminal through the second output capacitor Cout2, the other end is connected to the controller through the fourth filter capacitor C34, and the gate of the eighth field effect transistor G8 is connected to the fourth filter resistor R4 and between the fourth filter capacitor C34.
  • the first end of the second flying capacitor Cfly2 is connected between the fifth field effect transistor G5 and the sixth field effect transistor G6, and the second end of the second flying capacitor Cfly2 is connected to the seventh field effect transistor G7 and the eighth field effect transistor between effect transistors G8.
  • the fifth field effect transistor G5 , the sixth field effect transistor G6 , the seventh field effect transistor G7 and the eighth field effect transistor G8 are all MOS transistors.
  • the effect transistor G5 and the eighth field effect transistor G8 are PMOS, and the sixth field effect transistor G6 and the seventh field effect transistor G7 are NMOS.
  • the first filter resistor R1, the second filter resistor R2, the third filter resistor R3, the fourth filter resistor R4, the first filter capacitor C31, the second filter capacitor C32, the third filter capacitor C33, the fourth filter capacitor C34 constitutes an RC high-pass filter in pairs.
  • the power supply terminal before the voltage doubling in Figure 12 is the power supply terminal Vs, and the control signal sent from the controller is connected between the first filter capacitor C31 and the second filter capacitor C32, as well as the third filter capacitor C33 and the fourth filter capacitor C34 between, in order to realize the synchronous control of the fifth field effect transistor G5, the sixth field effect transistor G6, the seventh field effect transistor G7 and the eighth field effect transistor G8.
  • the voltage of the output value multiplexing unit after the basic double voltage unit is doubled by 153 is 2Vs.
  • the controller sends a control signal to drive the fifth field effect transistor G5, the sixth field effect transistor G6, the seventh field effect transistor G7 and the eighth field effect transistor G8 through the high-pass filter, the first filter capacitor C31, the second filter capacitor C32, the third filter capacitor C33, and the fourth filter capacitor C34 are responsible for the voltage difference between the control signal and the voltage rail. Due to the opposite turn-on conditions of NMOS and PMOS, when the sixth field effect transistor G6 and the seventh field effect transistor G7 are turned on at the same time, the fifth field effect transistor G5 and the eighth field effect transistor G8 are turned off, and the power supply terminal Vs passes through the sixth field effect transistor.
  • the transistor G6 and the seventh field effect transistor G7 charge the second flying capacitor Cfly2, and the voltage polarity of the second flying capacitor Cfly2 is left negative and right positive.
  • the fifth field effect transistor G5 and the eighth field effect transistor G8 are turned on, the sixth field effect transistor G6 and the seventh field effect transistor G7 are turned off, and the power supply terminal Vs is connected in series with the left negative and right positive second flying capacitor Cfly2
  • the second output capacitor Cout2 is charged, and the output voltage on the second output capacitor Cout2 is 2Vs, which is twice the input voltage.
  • the first terminal of the second flying capacitor Cfly2 also forms a reverse pulse output terminal, which is used for the output voltage value that is the same as the voltage of the power supply terminal, and the phase is twice the voltage of the controller input.
  • the signal of the unit is the opposite of the pulse signal.
  • a pulse signal whose amplitude is Vs and whose phase is opposite to that of the control signal can be drawn from the basic double voltage unit 153 .
  • the basic double voltage unit 153 shown in FIG. 12 and FIG. 13 only one control signal needs to be input to the basic double voltage unit 153 , which reduces the complexity of the control circuit.
  • FIG. 14 is a schematic structural diagram of another pre-boost unit provided by the embodiment of the present application.
  • the pre-boost unit 15 shown in FIG. 14 may further include: adder units corresponding to the basic double voltage unit 153 one-to-one, and T+1 switch selectors, where T is the number of adder units.
  • the T adder units are connected in sequence, and each adder unit is connected to the reverse pulse output terminal of a basic double voltage unit 153 through a switch selector.
  • the last adder unit in the sequence is also connected to the voltage multiplier output terminal of the last basic double voltage unit 153 in the sequence through a switch selector, and the addition output terminals of the remaining T-1 adder units are connected to the previous adder unit in the sequence.
  • the input end of the sequence is connected, and the addition output end of the first adder unit is connected to the multiplexing circuit.
  • T+1 switch selectors are used to control the voltage output to the multiplexing circuit by the addition output end of the first adder unit in the sequence.
  • the number of adder units is also multiple.
  • T basic double voltage units 153 with reverse pulse output terminals are connected in sequence, they have T+1 DC voltage outputs, the sizes of which are 2 T , 2 T-1 , 2 T-2 Vietnamese times of Vs, with T-channel inverted pulse signal output, the peak size of which is 2 T-1 ?? 2 2,2,1 times of Vs, with the above T above adder units , the T+1-bit digital voltage doubler can be obtained.
  • the pre-boost unit 15 includes 4 basic double voltage units 153, 4 adder units, and 5 switch selectors (D00, D01, D02, D03, D04). Voltage 0 to 63 times any integer multiple of the voltage. Assuming that the voltage of three times the power supply terminal is to be output to the multiplexing circuit, that is, 3Vs, D00 and D01 in the control diagram are connected to their corresponding reverse pulse output terminals, and other switch selectors are grounded. In this way, the configuration of the pre-boost output can be realized by configuring the switch selector. By analogy, digital voltage multipliers of eight, ten, twelve and even higher digits can be realized.
  • the wiring of the control signal line is simple, the anti-interference capability of the line is improved, and the circuit volume is reduced.
  • FIG. 15 is a schematic structural diagram of an adder unit provided by an embodiment of the present application.
  • the adder unit 153 shown in FIG. 15 specifically includes: a third flying capacitor Cfly3, a ninth field effect transistor G9, a tenth field effect transistor G10, a fifth filter resistor R5, a sixth filter resistor R6, and a fifth The filter capacitor C35, the sixth filter capacitor C36 and the addition capacitor C+.
  • the ninth field effect transistor G9 and the tenth field effect transistor G10 are connected in reverse series between the addition input terminal and the ground terminal, and the tenth field effect transistor G10 is connected to the ground terminal through the addition capacitor C+.
  • the reverse series connection here is that the ninth field effect transistor G9 and the tenth field effect transistor G10 are connected in series with each other, and both are reversely connected.
  • One end of the fifth filter resistor R5 is connected to the addition input terminal (the voltage of the addition input terminal is indicated by V1 in the figure), the other end is connected to the controller through the fifth filter capacitor C35, and the gate of the ninth field effect transistor G9 is connected to the first Between the fifth filter resistor R5 and the fifth filter capacitor C35.
  • One end of the sixth filter resistor R6 is connected to the ground terminal through the addition capacitor C+, the other end is connected to the controller through the sixth filter capacitor C36, and the gate of the tenth FET G10 is connected to the sixth filter resistor R6 and the sixth filter resistor R6.
  • the ninth field effect transistor G9 is an N-type field effect transistor
  • the tenth field effect transistor G10 is a P-type field effect transistor.
  • One end of the adding capacitor C+ connected to the tenth field effect transistor G10 is the adding output end of the adder unit 153 (the voltage of the adding output end is represented by V1+V2 in the figure).
  • the fifth filter resistor R5 , the sixth filter resistor R6 , the fifth filter capacitor C35 , and the sixth filter capacitor C36 constitute a high-pass filter.
  • the inverting pulse output terminal of the basic double voltage unit 153 provides a pulse signal with a peak value V2 at a low level.
  • the ninth field effect transistor G9 is turned on, and the addition
  • the input terminal charges the third flying capacitor Cfly3 through the ninth field effect transistor G9, and the polarity is left negative and right positive; when the control signal is low level, the tenth field effect transistor G10 is turned on, and the voltage of the basic double voltage unit 153 is turned on.
  • the pulse signal of the peak value V2 provided by the inverting pulse output terminal is a high level.
  • V2 is connected in series with the third flying capacitor Cfly3 with the left negative and right positive and the voltage at both ends is V1 and then output to the addition capacitor C+.
  • the voltage on the addition capacitor C+ is V1+V2, realizes the addition of voltage.
  • the above-mentioned adder unit 153 needs a direct current voltage V1 and a pulse signal with a peak value of V2, and V2 is required to be inverse to the control signal received by the adder from the controller, so that the voltage of V1+V2 can be finally output to realize pre-boosting. Voltage addition in unit 15.
  • the ninth field effect transistor G9 and the tenth field effect transistor G10 may be silicon field effect transistors, or may be new wide bandgap semiconductor devices such as gallium nitride and silicon carbide, which are not limited herein.
  • FIG. 16 is a schematic diagram of a chip structure provided by an embodiment of the present application.
  • the present application further provides a chip 20 as shown in FIG. 16 , including the driving device 10 described in any of the foregoing embodiments.
  • the chip may be a driver chip for the target load.
  • the chip 20 may be, for example, a flash chip, a shutter chip, a magnetron chip, etc., which is not limited herein.
  • FIG. 17 is a schematic structural diagram of a photographing apparatus provided by an embodiment of the present application.
  • the photographing device 30 shown in FIG. 17 includes a target load, and the chip 20 or the driving device 10 described in any of the above embodiments.
  • the photographing device 30 includes the chip 20 as an example.
  • the present application can be applied to various application scenarios driven by instantaneous high pulse power, the photographing device is only an example of one application scenario, and the present application is not limited thereto.
  • FIG. 18 is a schematic structural diagram of an unmanned aerial vehicle provided by an embodiment of the present application.
  • the drone shown in FIG. 18 includes a main body 40 and the photographing device 30 mounted on the main body 40 .

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Abstract

本申请提供一种驱动装置、芯片、拍摄装置和无人机，驱动装置中通过控制器与复用电路连接，向复用电路发送控制信号；复用电路与储能电容单元连接，响应所述控制器的控制，对所述储能电容单元进行充电或放电，以及向目标负载输出驱动信号，其中，复用电路包括滤波电路单元，所述滤波电路单元电连接在所述控制器与所述目标负载之间，以及所述储能电容单元与所述目标负载之间；当对所述储能电容单元进行充电时，所述滤波电路单元作为充电回路的无源网络使用，当所述储能电容单元进行放电时，所述滤波电路单元作为EMI滤波器使用，从而实现了对充电回路和放电回路的结构复用，降低了驱动装置的体积，精简了控制线路，降低线路损耗减小功耗。

Description

驱动装置、芯片、拍摄装置和无人机 技术领域
本申请实施例涉及电子技术领域，尤其涉及一种驱动装置、芯片、拍摄装置和无人机。
背景技术
在各类终端设备的驱动设计中，通常利用储能电容组件来实现高于电源电压的驱动。而驱动装置需要在对储能电容组件进行充放电管理的同时，避免驱动过程中放电功率不恒定导致高电流浪涌问题。
相关技术中，通常利用控制器分别对充电管理单元和放电驱动单元的工作进行控制。
然而，控制器复杂的控制线路、相互独立模块化的充电管理和放电驱动，都导致了产品体积和功耗的上升，难以满足终端设备小型化、低功耗的需求。
发明内容
本申请提供一种驱动装置、芯片、拍摄装置和无人机，通过对充电回路和放电回路的结构复用，降低了驱动装置的体积，精简了控制线路，降低线路损耗减小功耗。
根据本申请的第一方面，提供了一种驱动装置，包括：控制器、储能电容单元以及复用电路；
所述控制器与所述复用电路连接，用于向所述复用电路发送控制信号；
所述复用电路与所述储能电容单元连接，用于响应所述控制器的控制信号，对所述储能电容单元进行充电或放电，以及向目标负载输出驱动信号；
其中，所述复用电路包括滤波电路单元，所述滤波电路单元电连接在所述控制器与所述目标负载之间，以及所述储能电容单元与所述目标负载之间；
当对所述储能电容单元进行充电时，所述滤波电路单元作为充电回路的无源网络使用，当所述储能电容单元进行放电时，所述滤波电路单元作为EMI滤波器使用。
根据本申请的第二方面，提供了一种芯片，包括本申请第一方面所述的驱动装置。
根据本申请的第三方面，提供了一种拍摄装置，包括目标负载，以及如本申请的 第二方面所述的芯片或本申请的第一方面所述的驱动装置。
根据本申请的第四方面，提供了一种无人机，包括主体机身和安装于所述主体机身上的如本申请的第一方面所述的拍摄装置。
本申请提供一种驱动装置、芯片、拍摄装置和无人机，驱动装置中通过控制器与复用电路连接，向复用电路发送控制信号；复用电路与储能电容单元连接，响应所述控制器的控制，对所述储能电容单元进行充电或放电，以及向目标负载输出驱动信号，其中，所述复用电路包括滤波电路单元，所述滤波电路单元电连接在所述控制器与所述目标负载之间，以及所述储能电容单元与所述目标负载之间；当对所述储能电容单元进行充电时，所述滤波电路单元作为充电回路的无源网络使用，当所述储能电容单元进行放电时，所述滤波电路单元作为EMI滤波器使用，从而实现了对充电回路和放电回路的结构复用，降低了驱动装置的体积，精简了控制线路，降低线路损耗减小功耗。
附图说明
图1是本申请实施例提供的一种驱动装置结构示意图；
图2是本申请实施例提供的另一种驱动装置结构示意图；
图2A-2C是本申请实施例提供的在图2结构基础上的充放电阶段示意图；
图3是本申请实施例提供的再一种驱动装置结构示意图；
图4是本申请实施例提供的又一种驱动装置结构示意图；
图5是本申请实施例提供的一种电容均压单元结构示意图；
图6是本申请实施例提供的另一种电容均压单元结构示意图；
图7是本申请实施例提供的再一种电容均压单元结构示意图；
图8是本申请实施例提供的一种树形连接的电容均压单元结构示意图；
图9是本申请实施例提供的一种预升压的驱动装置结构示意图；
图10是本申请实施例提供的一种预升压单元结构示意图；
图11是本申请实施例提供的另一种预升压单元结构示意图；
图12是本申请实施例提供的再一种预升压单元结构示意图；
图13是本申请实施例提供的又一种预升压单元结构示意图；
图14是本申请实施例提供的又一种预升压单元结构示意图；
图15是本申请实施例提供的一种加法器单元的结构示意图；
图16是本申请实施例提供的一种芯片结构示意图；
图17是本申请实施例提供的一种拍摄装置结构示意图；
图18是本申请实施例提供的一种无人机结构示意图。
附图标记：
10：驱动装置；11：控制器；12：储能电容单元；13：复用电路；
Q1：第一开关单元Q1；Q2：第二开关单元；Q3：第三开关单元；Q4：第四开关单元；L1：第一电感单元；L2：第二电感单元；D1：第一阻环流二极管；D2：第二阻环流二极管；
Vcap：电压节点；Vs：电源端；C1：第一滤波电容单元；C2：第二滤波电容单元；131：主栅极驱动单元；g1：第一输出端；g2：第二输出端；g3：第三输出端；g4：第四输出端；
121：电容子单元；14：电容均压单元；Rp1：第一基准分压单元；Rp2：第二基准分压单元；U1：比较器；RF+：正反馈阻抗单元；RF-：负反馈阻抗单元；Cosc：振荡电容单元；Lo：滤波电感单元；
141：缓冲单元；14a：第一电容均压单元；14b：第二电容均压单元；14c：第三电容均压单元；CL1：第一存储电容；CL2：第二存储电容；CL3：第三存储电容；CL4：第四存储电容；
15：预升压单元；151：第一半桥控制单元；152：第二半桥储能单元；1511：第一栅极驱动器；G1：第一场效应管；G2：第二场效应管；Cfly1：第一飞跨电容；Cout1：第一输出电容；1521：第二栅极驱动器；Rd：耦合阻抗器；Cd：耦合电容；G3：第三场效应管；G4：第四场效应管；Db1：第一自举二极管；Cb1：第一隔离电容；Db2：第二自举二极管；Cb2：第二隔离电容；
153：基本二倍压单元；G5：第五场效应管；G6：第六场效应管；G7：第七场效应管；G8：第八场效应管；R1：第一滤波阻抗器；R2：第二滤波阻抗器；R3：第三滤波阻抗器；R4：第四滤波阻抗器；C31：第一滤波电容；C32：第二滤波电容；C33：第三滤波电容；C34：第四滤波电容；Cout2：第二输出电容；Cfly2：第二飞跨电容；
153：加法器单元；Cfly3：第三飞跨电容；G9：第九场效应管；G10：第十场效应管；R5：第五滤波阻抗器；R6：第六滤波阻抗器；C35：第五滤波电容；C36：第六滤波电容以及C+：加法电容。
具体实施方式
下面以具体地实施例对本申请的技术方案进行详细说明。下面这几个具体的实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例不再赘述。
在例如相机快门驱动、电磁铁充磁驱动、补光灯(闪光灯)驱动或者测距系统供电等需要提供瞬时高脉冲功率驱动的应用场景中，通常利用驱动装置和储能电容组件实现对目标负载的驱动。而在相关技术中，对储能电容组件实现充电管理和放电驱动是分别以两个相互独立的电路来实现的，电路体积较大；并且控制器需要以两条独立的控制线路对充电管理模块和放电驱动模块进行分别控制，控制线路复杂。
为了解决相关技术中存在的问题，本申请提供了一种驱动装置，以复用电路实现充电管理和放电驱动的结构复用，在减小电路体积的同时，精简了控制线路，也降低了电路上的能耗。
图1是本申请实施例提供的一种驱动装置结构示意图。如图1所示的驱动装置10包括：控制器11、储能电容单元12以及复用电路13。其中，控制器11与复用电路13连接，用于向复用电路13发送控制信号。复用电路13与储能电容单元12连接，用于响应控制器11的控制信号，对储能电容单元12进行充电或放电，向目标负载输出驱动信号。图1所示的复用电路13具有对储能电容单元12进行充电管理的功能和控制储能电容单元12放电实现对目标负载驱动的功能，是相关技术中充电管理模块和放电驱动模块的电路结构复用。其中，复用电路13包括滤波电路单元，滤波电路单元电连接在控制器11与目标负载之间，以及储能电容单元12与目标负载之间；当对储能电容单元12进行充电时，滤波电路单元作为充电回路的无源网络使用，当储能电容单元12进行放电时，滤波电路单元作为电磁干扰(Electromagnetic Interference，简称：EMI)滤波器使用。控制器11与复用电路13的通信是复用信号线的连接通信，例如可以通过时序的控制实现充电和放电的交替控制，实现了控制线路的复用和精简。
本实施例中驱动装置通过控制器与复用电路连接，向复用电路发送控制信号；复用电路与储能电容单元连接，响应所述控制器的控制，对所述储能电容单元进行充电或放电，向目标负载输出驱动信号，其中，复用电路包括滤波电路单元，滤波电路单元电连接在控制器与所述目标负载之间，以及储能电容单元与目标负载之间；当对储能电容单元进行充电时，滤波电路单元作为充电回路的无源网络使用，当储能电容单元进行放电时，滤波电路单元作为EMI滤波器使用，通过电路复用结构的精简设计，减小驱动单元的体积占用，利于小型化应用，并通过控制信号线的复用，精简了信号线路，提高了电路可靠性。
示例性的，上述控制器向复用电路输出的控制信号可以是复用的控制信号，即控制器发送一个控制信号同时控制复用电路对储能电容单元进行充电或放电，当充电或放电结束后，复用电路向目标负载输出驱动信号。另外，上述控制器向复用电路输出的控制信号也可以是独立的控制信号，即控制器发送一个控制信号控制复用电路对储能电容单元进行充电或放电，发送另一个控制信号控制复用电路向目标负载输出驱动信号。其中，复用电路还可以包括开关电路单元，开关电路单元电连接在控制器与滤波电路单元之间，以及储能电容单元与滤波电路单元之间，用于控制储能电容单元进行充电或放电。可以理解的是，在具体实现过程中还有其它控制信号发送方式，本申请对此不做限制。在图1所示结构的基础上，下面对图1中复用电路13的可选电路结构进行举例说明。进一步地，复用电路还可以包括阻断电路单元，该阻断电路单元电 连接在滤波电路单元与目标负载之间。当储能电容单元通过滤波电路单元对目标负载进行供电时，阻断电路单元起到阻断作用，避免出现环流。图2是本申请实施例提供的另一种驱动装置结构示意图。在图2所示的驱动装置10中，控制器11未示出，储能电容单元12以单个电容作为示意，复用电路13具体可以包括第一开关单元Q1(图中以场效应管为示例)、第二开关单元Q2(图中以场效应管为示例)、第三开关单元Q3(图中以场效应管为示例)、第四开关单元Q4(图中以场效应管为示例)、第一电感单元L1(图中以单个电感为示例)、第二电感单元L2(图中以单个电感为示例)、第一阻环流二极管D1以及第二阻环流二极管D2。如图2所示，复用电路13可以理解为是一种充放电复用的H桥电路，目标负载两侧所连电路基本对称一致。储能电容单元12的一端连接至电压节点Vcap，另一端接地。
具体结构如图2所示，第一开关单元Q1的一端通过第二开关单元Q2连接接地端，另一端与储能电容单元的高压端连接。第一电感单元L1的一端与目标负载连接，另一端连接至第一开关单元Q1与第二开关单元Q2之间。第一阻环流二极管D1的正极与电源端Vs连接，负极连接至第一电感单元L1与目标负载之间。第四开关单元Q4的一端通过第三开关单元Q3连接接地端，另一端与储能电容单元的高压端连接。第二电感单元L2的一端与目标负载连接，另一端连接至第四开关单元Q4与第三开关单元Q3之间。第二阻环流二极管D2的正极与电源端Vs连接，负极连接至第二电感单元L2与目标负载之间。储能电容单元的低压端与接地端连接。如图2所示，第一开关单元Q1、第二开关单元Q2、第三开关单元Q3、第四开关单元Q4都以N型场效应管作为示例，但也可以是晶体管、继电器等具有开关功能的元器件。本实施例中第一开关单元Q1、第二开关单元Q2、第三开关单元Q3、第四开关单元Q4都是正向连接。正向连接例如是图2所示各开关单元的源极接低电位，漏极接高电位，各开关管正向偏置。
在图2所示的示例中，其中，第一开关单元Q1的控制端、第二开关单元Q2的控制端、第三开关单元Q3的控制端、第四开关单元Q4的控制端都与控制器连接。例如图2中第一开关单元Q1的栅极、第二开关单元Q2的栅极、第三开关单元Q3的栅极、第四开关单元Q4的栅极都与控制器连接，用于响应控制器的控制而导通或截止各开关管。控制器具体用于发出控制第一开关单元Q1、第二开关单元Q2、第三开关单元Q3和第四开关单元Q4的导通时序的控制信号。
由于图2中第一开关单元Q1、第二开关单元Q2、第一电感单元L1以及第一阻环流二极管D1构成的左侧半桥，与第三开关单元Q3、第四开关单元Q4、第二电感单元 L2以及第二阻环流二极管D2构成的右侧半桥在结构上相互对称，其充放电原理类似，本实施例以左侧半桥进行充放电过程举例说明。第一开关单元Q1、第二开关单元Q2的导通和截止由控制器发出的控制信号实现控制。
图2A-2C是本申请实施例提供的在图2结构基础上的充放电阶段示意图。图2中实现一个完整充放电过程具体可以顺序地包含三个阶段：在第一阶段，如图2A所示，控制器控制第一开关单元Q1截止且第二开关单元Q2导通，第一阻环流二极管D1正向偏置提供充电电流路径，电源端Vs直接对第一电感单元L1充电，实现对第一电感单元L1的充能；在第二阶段，如图2B所示，控制器控制第一开关单元Q1导通且第二开关单元Q2截止，第一电感单元L1在此阶段中相当于一个电流源放电至储能电容单元，第一电感单元L1上电流逐渐减小到0，实现对储能电容单元的充能；在第三阶段，如图2C所示，控制器保持第一开关单元Q1导通且第二开关单元Q2截止，储能电容单元通过第一开关单元Q1、第一电感单元L1向目标负载放电，实现对目标负载的驱动，并且在此阶段中第一阻环流二极管D1反向偏置，将放电电流路径与电源端Vs阻断，避免出现环流。循环执行图2A-2C所示的三个阶段，就能实现对储能电容单元的循环充放电控制。
其中，充电阶段可以理解为是在第一阶段和第二阶段中，电源端Vs通过第一电感单元L1将能量转移至储能电容单元的过程，由于能量转移过程与电容器的电压无关，因此本实施例中充电阶段的充电功率恒定。而放电阶段可以理解为是在第三阶段，储能电容单元经过第一开关单元Q1、第一电感单元L1向目标负载放电。在图2所示的结构中，第一阻环流二极管D1和第二阻环流二极管D2对两侧半桥的充电过程和放电过程进行隔离，避免放电过程高压反灌电源端Vs，由此实现了充电路径和放电路径的结构复用，减少了充电电路和放电电路的体积。可选地，储能电容单元还可以与控制器连接实现充电情况的反馈和监控，以便控制器进一步根据储能电容单元的充电情况控制各开关单元的工作状态，使得储能电容单元始终在预设的电压值附近波动。
图2A-2C示出了图2中左侧半桥的充放电过程，而图2中左侧半桥和右侧半桥对目标负载放电的充放电时序，可以是交替进行的，也可以是同步进行的。
作为一种对目标负载交替放电的实施例，可以是左侧半桥和右侧半桥的放电时序相反。在图2中，例如，左侧半桥在T1时段中处于第一阶段和第二阶段，即先第一开关单元Q1截止、第二开关单元Q2导通对第一电感单元L1充能，然后第一开关单元Q1导通、第二开关单元Q2截止对储能电容单元充能；而右侧半桥在该T1时段内则处 于第三阶段，即保持第三开关单元Q3截止、第四开关单元Q4导通形成储能电容单元对目标负载的放电路径。接着，左侧半桥在T1之后的T2时段中进入第三阶段，即保持第一开关单元Q1导通、第二开关单元Q2截止形成储能电容单元对目标负载的放电路径；而右侧半桥在该T2时段内则进入第一阶段和第二阶段，即先第四开关单元Q4截止、第三开关单元Q3导通对第二电感单元L2充能，然后第四开关单元Q4导通、第三开关单元Q3截止对储能电容单元充能。如此循环T1-T2实现左侧半桥和右侧半桥对目标负载的交替充放电。左侧半桥和右侧半桥交替对目标负载放电，降低了电源端Vs输出电流，减小传输路线的损耗，也减小了对电源端Vs的冲击。
作为一种对目标负载同步放电的实施例，可以是左侧半桥和右侧半桥的放电时序相同。在图2中，例如，左侧半桥和右侧半桥在T1同时处于第一阶段和第二阶段，即先第一开关单元Q1截止、第二开关单元Q2导通对第一电感单元L1充能，同时第四开关单元Q4截止、第三开关单元Q3导通对第二电感单元L2充能，然后第一开关单元Q1导通、第二开关单元Q2截止对储能电容单元充能，同时第四开关单元Q4导通、第三开关单元Q3截止对储能电容单元充能。接着，左侧半桥和右侧半桥在T2时段都进入第三阶段，即保持第一开关单元Q1导通、第二开关单元Q2截止形成储能电容单元对目标负载的放电路径，同时保持第三开关单元Q3截止、第四开关单元Q4导通形成储能电容单元对目标负载的放电路径。如此循环T1-T2实现左侧半桥和右侧半桥对目标负载的同步充放电。目标负载同步放电简化了时序控制。
上述对储能电容单元充电的过程中，由于电源端Vs和相当于电流源的电感单元串联对储能电容单元充电，能够在储能电容单元上加载高于电源端Vs电压的电压值。上述实施例中第一电感单元L1、第二电感单元L2都可以如图2所示的单个电感，也可以是多个电感构成的组件，在此不做限定。上述的第一开关单元Q1、第二开关单元Q2、第三开关单元Q3、第四开关单元Q4具体可以是如图2所示的N型场效应管，也可以是晶体管，还可以是继电器等具有开关控制的器件，其实现原理和技术效果与图2所示场效应管类似，在此不做赘述。
在图2所示结构的基础上，图3是本申请实施例提供的再一种驱动装置结构示意图。与图2相比，如图3所示的复用电路中的滤波电路单元具体可以包括第一滤波电容单元C1和第二滤波电容单元C2，分别与第一电感单元L1和第二电感单元L2构成LC低通滤波，以实现储能电容单元放电过程中的滤波。具体地，如图3所示，第一滤波电容单元C1的一端连接至第一电感单元L1和目标负载之间，另一端与接地端连接。 第二滤波电容单元C2的一端连接至第二电感单元L2和目标负载之间，另一端与接地端连接。第一电感单元L1和第二电感单元L2在上述图2A所示的第一阶段和图2B所示的第二阶段，都作为充电电感，但在上述图2C所示的第三阶段，则与第一滤波电容单元C1和第二滤波电容单元C2构成二阶低通滤波器，降低输入目标负载的高次谐波，减小目标负载对外辐射的电磁干扰。并且，由于电子元器件通常都存在因自身的体电容(开关管的Coss电容与Crss电容)导致能量流失的问题，而本实施例中的第一滤波电容单元C1和第二滤波电容单元C2，能够实现对开关单元中体电容能量的回收。具体地，在上述图2C所示实施例的第三阶段的死区时间内，第二开关单元Q2的体电容可以通过第一电感单元L1对第一滤波电容单元C1放电，体电容的能量转移到第一滤波电容单元C1中存储。而在图2A所示实施例的第一阶段中，第一滤波电容单元C1存储的这部分能量也参与给第一电感单元L1的充能，由此通过第一滤波电容单元C1实现了对第二开关单元Q2的体电容能量的回收。第二滤波电容单元C2基于同样的原理实现了对第三开关单元Q3的体电容能量的回收。
在图2或图3所示实施例中，图4是本申请实施例提供的又一种驱动装置结构示意图。与图2或图3所示相比，图4所示复用电路还包括主栅极驱动单元131,主栅极驱动单元131用于将来自控制器的控制信号转换为驱动开关管栅极的栅极驱动信号，主栅极驱动单元可以是主栅极驱动器。主栅极驱动单元131具有一个接入复用信号的输入端和四个输出端(g1、g2、g3、g4)。具体地，主栅极驱动单元131的输入端与控制器连接，第一输出端g1与第一开关单元Q1的控制端连接，第二输出端g2与第二开关单元Q2的控制端连接，第三输出端g3与第三开关单元Q3的控制端连接，第四输出端g4与第四开关单元Q4的控制端连接。主栅极驱动单元131将来自控制器的控制信号转变为可以直接驱动各开关单元的开关驱动信号。图4中第一开关单元Q1、第二开关单元Q2、第三开关单元Q3、第四开关单元Q4为场效应管，则其各自的控制端是各场效应管的栅极。假如第一开关单元Q1、第二开关单元Q2、第三开关单元Q3、第四开关单元Q4是晶体管，则控制端是晶体管的基极。假如第一开关单元Q1、第二开关单元Q2、第三开关单元Q3、第四开关单元Q4是继电器，则控制端是继电器的切换控制端口。
在上述各种实施例中，储能电容单元可以是一个电容器也可以是多个电容器构成的组件，在此不做限定。但对于储能电容单元包含两个串联电容器的结构，可以增加电容均压单元进行均压。其中，储能电容单元包含的电容器可以是法拉电容器。
图5是本申请实施例提供的一种电容均压单元结构示意图。在图2、图3或者图4所示实施例基础上，储能电容单元具体可以包括2个电容子单元121。为了在储能电容单元充放电过程中，降低2个电容子单元121之间因元器件个体差异导致的电压不均衡，驱动装置还可以包括如图5所示的电容均压单元14。该电容均压单元14连接至图5所示2个电容子单元121之间，用于对该2个电容子单元121均衡电压。图5中电容子单元121以单个电容进行示例，但每个电容子单元121具体还可以是包含多个电容的组件，或者是电容和其他电子器件构成的电容型组件。电容均压单元14接入位置两侧的电容子单元121结构应一致，实现2个电容子单元121的相互串联的对称结构，本实施例对单个电容子单元121的具体结构不做限定。储能电容单元中的电容子单元121可以是法拉电容器。
图5中电容均压单元14可以包括：第一基准分压单元Rp1、第二基准分压单元Rp2、比较器U1、正反馈阻抗单元RF+、负反馈阻抗单元RF-、振荡电容单元Cosc以及滤波电感单元Lo。具体地，如图5所示，第一基准分压单元Rp1和第二基准分压单元Rp2串联在储能电容单元的高压端和接地端之间。图5中储能电容单元的高压端为图2所示储能电容单元所连的电压节点Vcap，由此在第一基准分压单元Rp1和第二基准分压单元Rp2之间的节点提供稳定的基准电压，且电压值为电压节点Vcap电压的一半。第一基准分压单元Rp1和第二基准分压单元Rp2例如可以是图5所示的电阻或其他阻抗型元器件，在此不做限定。比较器U1的正相输入端(以符号+标识)连接至第一基准分压单元Rp1和第二基准分压单元Rp2之间，由此接入较为基准电压。比较器U1的反相输入端(以符号-标识)通过振荡电容单元Cosc与接地端连接。滤波电感单元Lo的第一端与比较器U1的输出端连接，第二端连接至2个电容子单元121之间。正反馈阻抗单元RF+的一端与比较器U1的正相输入端连接，另一端与比较器U1的输出端连接。负反馈阻抗单元RF-的一端与比较器U1的反相输入端连接，另一端与滤波电感单元Lo的第二端连接。如图5所示的电容均压单元14不需要与控制器通讯，即可实现电容高动态响应稿精度均压。
电容均压单元14上电后即可进入极高频率的震荡状态，使得比较器U1输出占空比和频率都变化的脉冲宽度调制(Pulse width modulation，PWM)波。其中，电压节点Vcap的电压值是U Cap，第一基准分压单元Rp1和第二基准分压单元Rp2的电阻值都是R P，正反馈阻抗单元RF+和负反馈阻抗单元RF-的电阻值都是R F。当储能电容单元中的2个电容子单元121存在电压不均衡，比较器U1输出占空比和频率会随之改变, 电容子单元121的电压在如下设定误差区间内上下波动：
Figure PCTCN2020105057-appb-000001
若其中一个电容子单元121的电压稍高，它的能量会被滤波电感单元Lo吸收并转移到电压低的另一个电容子单元121上，实现能量转移和电压均衡。
图5中第一基准分压单元Rp1和第二基准分压单元Rp2、正反馈阻抗单元RF+、负反馈阻抗单元RF-分别可以是如图5所示的单个电阻，也可以是多个电阻构成的组件；振荡电容单元Cosc可以是如图5所示的单个电容，也可以是多个电容构成的组件；滤波电感单元Lo可以是如图5所示的单个电感，也可以是多个电感构成的组件，本实施例在此都不做限定。
在一些实施例中，图6是本申请实施例提供的另一种电容均压单元结构示意图。图7是本申请实施例提供的再一种电容均压单元结构示意图。在图5所示实施例中，要对电容容量较大的储能电容单元进行均压，电容均压单元14需要较高的均压能力。为了提高对储能电容单元的均压效果，图6和图7所示电容均压单元14还可以包括缓冲单元141。比较器U1的输出端通过缓冲单元141与滤波电感单元Lo的第一端连接。如图6和图7所示，缓冲单元141的输入端连接比较器U1的输出端，输出端连接滤波电感单元Lo的第一端，缓冲单元141的加入，减少了振荡、提高了电容均压单元14矫正电流输出能力，使得电容均压单元14能够实现较大容量电容组的均压。其中，缓冲单元141可以是如图6所示的两个场效应管组成的互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，简称：CMOS)缓冲电路，也可以是如图7所示的两个晶体管组成的双极性晶体管缓冲电路。相比较而言，在电压较低的电容组均压场景中，采用图6所示的CMOS缓冲电路可以实现更小的损耗；而在电压较高的电容组均压场景中，采用图7所示的双极性晶体管缓冲电路可以实现更小的损耗。
以法拉电容作为电容子单元121为例，由于法拉电容单体耐压为2.5V，两个法拉电容进行均压获得的电容组耐压为5V。若需要获得更高耐压的电容组，那么就需要对更多数目的电容进行串联和均压。在上述加缓冲单元141或不加缓冲单元141的各种电压均压单元实施例中，储能电容单元中每个电容子单元121可以具体包括：2 n个电容单体，以及2 n-1个树形连接的电容均压单元14，n为大于0的整数。可以理解为，本实施例中可以对均压单元进行树形连接，实现均压结构的扩展组合和浮地工作，由此实现对2个以上电容的均压。以未加缓冲单元141的均压单元为例，图8是本申请实施例提供的一种树形连接的电容均压单元结构示意图。在图8所示的树形连接结构 中，第一电容均压单元14a、第二电容均压单元14b、第三电容均压单元14c是三个结构相同的电容均压电路，第一存储电容CL1和第二存储电容CL2串联构成一个电容子单元121，第三存储电容CL3和第四存储电容CL4串联构成另一个电容子单元121。第一存储电容CL1、第二存储电容CL2、第三存储电容CL3和第四存储电容CL4依次串联在电压节点Vcap和接地端之间。第一电容均压单元14a连接至第二存储电容CL2与第三存储电容CL3之间，第二电容均压单元14b连接至第一存储电容CL1与第二存储电容CL2之间，第三电容均压单元14c连接至第三存储电容CL3与第四存储电容CL4之间。其中，电压节点Vcap作为第二电容均压单元14b的高压端，第二存储电容CL2与第三存储电容CL3之间作为第二电容均压单元14b的接地端；第二存储电容CL2与第三存储电容CL3之间作为第三存储电容CL3的高压端，第三存储电容CL3直接连接至接地端。在图8所示的结构中，每个电容子单元121包括2个电容单体和1个电容均压单元14。假如电容子单元121中有4个电容单体，则设置3个树形连接的电容均压单元14。每个电容子单元121中，对于2 n个电容单体的均压任务，需要电容均压单元14的数目是1+2+4+…2^(n-1),这是一个以2为公比的等比数列求和，也就是2 n-1个。例如，对于4个电容单体的均压任务，n＝2，电容子单元121包含的电容均压单元14的数目也就是4-1＝3个；对于8个电容单体均压，n＝3,电容子单元121包含电容均压单元14的数目也就是8-1＝7个。本实施例中电容均压单元14对电容单体两两均压。
在上述各种实施例中，在目标负载所需驱动电压较高的情况下，驱动装置需要对电源端Vs电压进行更高的升压处理。在利用上述复用电路的充电可以进行升压之外，还可以通过引入预升压单元15来提高升压效果。图9是本申请实施例提供的一种预升压的驱动装置结构示意图。如图9所示的驱动装置，还可以包括预升压单元15。复用电路通过预升压单元15与电源端Vs连接。预升压单元15用于将电源端Vs的电压升压后传输给复用电路。例如，在电源端Vs的电压经过预升压单元15提高2-4倍后再送入复用电路给储能电容单元充能时，与无预升压单元15的结构中原电流相比较，本实施例的复用电路中电流会降低到1/2-1/4的原电流。电路中电流的降低，可以实现发热的降低和储能电容单元的电感尺寸的减小，也进一步降低了电路能耗。
图9所示的预升压单元15可以是传统的DC/DC电路，例如boost电路，但功率电感器会占据较大尺寸，导致整体电路尺寸较大。预升压单元15也可以使用开关电容变换器(SCC)来实现，然而现有的二极管开关电容变换器由于二极管的存在，效率较低，且需要搭配交流电源使用。对于电子线路而言，交流电源本身属于逆变电路，需要占 用一定尺寸，与体积庞大的二极管阵列和电容阵列共同使用，很难实现电路的小型化。现有的二极管开关电容变换器中二极管和电容需要承受二倍电源电压，电压应力较高，不利于优化成本。并且，二极管式开关电容变换器等效模型中的输出阻抗较高，不利于大功率场景。
为了实现结构的小型化，以及对大功率场景的适用，本实施例的预升压单元15引入场效应管桥式电路来实现。图10是本申请实施例提供的一种预升压单元结构示意图。如图10所示，预升压单元15具体包括第一半桥控制单元151和第二半桥储能单元152。第一半桥控制单元151与控制器、第二半桥储能单元152、电源端Vs和接地端连接，用于响应控制器的控制，将电源端Vs的电源电压信号或接地端的接地电压信号传输给第二半桥储能单元152。第二半桥储能单元152还与控制器、复用电路、直流端和接地端连接，用于在第一半桥控制单元151传输接地电压信号时，响应控制器的控制导通直流端进行充电储能，以及，在第一半桥控制单元151传输电源电压信号时，响应控制器的控制导通接地端升压放电输出至复用电路。
其中，第二半桥储能单元152的数量可以是1个也可以是多个。如果预升压单元15中仅包括一个第二半桥储能单元152，那么该第二半桥储能单元152对应的直流端直接为电源端Vs。例如图10中，1个第一半桥控制单元151和1个第二半桥储能单元152实现将电源端Vs的电压提升至2倍的升压输出。如果预升压单元15中包含的第二半桥储能单元152的数量为大于1的M，那么图11是本申请实施例提供的另一种预升压单元结构示意图。如图11所示，该M个第二半桥储能单元152顺序依次连接，每个第二半桥储能单元152都与第一半桥控制单元151连接，且顺序第一个第二半桥储能单元152对应的直流端为电源单元的输出端，其余M-1个第二半桥储能单元152对应的直流端为顺序前一个第二半桥储能单元152的输出端，顺序最后一个第二半桥储能单元152与复用电路连接。如图11所示，顺序第二个第二半桥存储单元是顺序依次连接的最后一个第二半桥存储单元，其输出的电压是电源端Vs的电压的3倍。每增加一个第二半桥存储单元，就是在前一个第二半桥存储单元输出电压的基础上加上1倍电源端电压。由此，通过增加顺序依次连接的第二半桥存储单元的数量，可以实现输出电压以1倍电源端电压逐个叠加的预升压。本实施例中单个第二半桥存储单元可以相当于一个电压加法器单元153。
具体地，如图10或图11所示，第一半桥控制单元151包括：第一栅极驱动器1511、第一场效应管G1和第二场效应管G2。其中，第一场效应管G1和第二场效应管G2正 向串联连接于电源端Vs和接地端之间。如图10和图11所示，正向串联可以理解为第一场效应管G1和第二场效应管G2串联，且都正接。第一场效应管G1和第二场效应管G2都是N型场效应管。第一栅极驱动器1511用于将控制器输出的控制信号转化为对第一场效应管G1和第二场效应管G2的栅极驱动信号。具体地，第一栅极驱动器1511的高侧驱动信号输出端(Vho)与第一场效应管G1的栅极连接，第一栅极驱动器1511的半桥模块输出端(VS)连接至第一场效应管G1和第二场效应管G2之间，第一栅极驱动器1511的低侧驱动信号输出端(Vlo)与第二场效应管G2的栅极连接，第一栅极驱动器1511的高侧输入端(Hin)和低侧输入端(Lin)与控制器连接。
第二半桥储能单元152包括：第一飞跨电容Cfly1Cfly1、第一输出电容Cout1Cout1、第二栅极驱动器1521、耦合阻抗器Rd、耦合电容Cd、第三场效应管G3和第四场效应管G4。第三场效应管G3和第四场效应管G4反向串联连接，第三场效应管G3的漏极通过第一输出电容Cout1与接地端连接，所述第四场效应管G4的源极与直流端连接。如图10和图11所示，反向串联可以理解为第三场效应管G3和第四场效应管G4串联，且都反接。第三场效应管G3和第四场效应管G4也都是N型场效应管。第二栅极驱动器1521用于将控制器输出的控制信号转化为对第三场效应管G3和第四场效应管G4的栅极驱动信号。第二栅极驱动器1521的高侧驱动信号输出端(Vho)与第三场效应管G3的栅极连接,第二栅极驱动器1521的低侧驱动信号输出端(Vlo)通过耦合电容Cd与第四场效应管G4的栅极连接，耦合阻抗器Rd的一端与直流端连接，另一端连接至第四场效应管G4和耦合电容Cd之间，第二栅极驱动器1521的高侧输入端(Hin)和低侧输入端(Lin)与控制器连接。第一飞跨电容Cfly1的一端与第二栅极驱动器1521的半桥模块输出端(VS)连接，另一端连接至第一场效应管G1和第二场效应管G2之间。
在上述图10和图11所示的实施例的第一栅极驱动器1511和第二栅极驱动器1521中，各栅极驱动器的高侧输入端(Hin)输入的控制信号都互相同步，各低侧输入端(Lin)输入的控制信号也互相同步，但且高侧输入端(Hin)与低侧输入端(Lin)输入的控制信号相反。由此对预升压单元15中各场效应管的控制，实现对电源端的电压预升压。具体例如，当控制第二场效应管G2和第四场效应管G4导通、第一场效应管G1和第三场效应管G3截止时，电源端Vs对第二半桥储能单元152中的第一飞跨电容Cfly1充电，使其电压极性为左负右正。当控制第一场效应管G1和第三场效应管G3导通、第二场效应管G2和第四场效应管G4截止时，电源端Vs与两端电压为Vs的第一飞跨电容Cfly1串联，通过第三场效应管G3输出2Vs的电压对第一输出电容Cout1充电，实现 图10所示2Vs输出或图11所示3Vs输出。在上述过程中，图10和图11所示第三场效应管G3和第四场效应管G4反接形成的“颠倒半桥”实现特殊的同步整流网络。场效应管工作在同步整流状态，也就是第四场效应管G4的导通将屏蔽其体二极管，第三场效应管G3的导通将屏蔽其体二极管。
如图10和图11所示，由于第四场效应管G4是源极接正电压的NMOS，要让第四场效应管G4导通，栅极需要比Vs更高的驱动电压。但是第二栅极驱动器1521的高侧驱动信号输出端(Vho)已经被第三场效应管G3占用，所以上述实施例中利用耦合阻抗器Rd和耦合电容Cd构成的交流耦合网络、第二栅极驱动器1521的低侧驱动信号输出端(Vlo)提供的交流驱动分量，为第四场效应管G4提供驱动电压。耦合电容Cd隔离低侧驱动信号输出端(Vlo)输出的直流分量，最终在第四场效应管G4的栅极耦合出幅度为Vd/2的驱动电压，实现对第四场效应管G4的驱动。其中，第二栅极驱动器1521的低侧驱动信号输出端(Vlo)输出电压为Vd，而第二栅极驱动器1521的高侧驱动信号输出端(Vho)是相对于半桥模块输出端(VS)输出Vd电压。例如，Vd为12V，通过电容耦合过去的栅极电压为6V。
在上述实施例中，第一栅极驱动器1511和第二栅极驱动器1521都可以是自举栅极驱动器，从而降低硬件成本。
在一些自举栅极驱动器的实施例中，第一半桥控制单元151还包括第一自举二极管Db1和第一隔离电容Cb1。如图10和图11所示，第一自举二极管Db1的正极连接第一栅极驱动器1511的芯片供电端(Vd)，负极连接第一栅极驱动器1511的浮空供电端(Vb)。第一隔离电容Cb1的一端连接第一栅极驱动器1511的浮空供电端(Vb)，另一端连接第一栅极驱动器1511的半桥模块输出端(VS)，其中，第一栅极驱动器1511的芯片供电端(Vd)还连接至第一供电端(图中还以Vd示意第一供电端及其提供的电压值)。如图10和图11所示，第二半桥控制单元还可以包括第二自举二极管Db2和第二隔离电容Cb2。第二自举二极管Db2的正极连接第二供电端(图中以Vd+Vs示意第二供电端及其提供的电压值)，负极连接第二栅极驱动器1521的浮空供电端(Vb)。第二隔离电容Cb2的一端连接第二栅极驱动器1521的浮空供电端(Vb)，另一端连接第二栅极驱动器1521的半桥模块输出端(VS)；其中，第二栅极驱动器1521的芯片供电端(Vb)还连接至第一供电端，且第二供电端的电压为电源端的电压与第一供电端的电压之和。由于第三场效应管G3的参考最低电压为Vs而不是地，所以驱动第三场效应管G3的自举驱动器的自举二极管需要接的电压是Vd+Vs，其中Vd可以为完全导通 场效应管所需的电压。其中，Vd也是第一供电端提供的电压值。本实施例通过交流耦合和自举结合的方式实现场效应管的栅极驱动。
在图10和图11所示的实施例中，各场效应管可以是硅场效应管，也可以是氮化镓、碳化硅等新型宽禁带半导体器件，在此不做限定。第一栅极驱动器1511、第二栅极驱动器1521根据不同的实际需要，可以串联额外的阻尼电阻或者快速泄放二极管，或者也可以并联稳压二极管等元器件，在此不做限定。
在另一些预升压单元15的实施例中，区别于图10和图11所示的结构，还可以通过引入P型场效应管实现上述预升压单元15，由此可以降低栅极驱动器成本，减小栅极驱动器的尺寸。图12是本申请实施例提供的再一种预升压单元结构示意图。图13是本申请实施例提供的又一种预升压单元结构示意图。预升压单元15具体可以包括单个或多个基本二倍压单元153。
在一些预升压单元15包括单个基本二倍压单元153的实施例中，如图12所示，复用电路通过单个基本二倍压单元153与电源端Vs连接，电源端Vs为单个基本二倍压单元153的倍压前供电端。基本二倍压单元153用于将电源端电压升压2倍后传输给复用电路。
在一些预升压单元15包括多个基本二倍压单元153的实施例中，如图13所示，预升压单元15具体包括K个顺序依次连接的基本二倍压单元153，K为大于1的整数。图13所示结构可以理解为是图12所示结构的扩展。顺序依次连接的具体方式可以如图13示意，每个基本二倍压单元153都连接至控制器，且第一个基本二倍压单元153所连接的倍压前供电端为电源端Vs，第二个基本二倍压单元153所连接的倍压前供电端为第一个基本二倍压单元153的输出端，以此类推，之后每个基本二倍压单元153的倍压前供电端都是顺序前一个基本二倍压单元153的输出，由此实现2K倍电源端电压的升压。具体地，例如复用电路通过K个顺序依次连接的基本二倍压单元153与电源端Vs连接。K个顺序依次连接的基本二倍压单元153用于将电源端电压升压2K倍后传输给复用电路。其中，K个顺序依次连接基本二倍压单元153中，顺序第一个基本二倍压单元153与电源端Vs和接地端连接，用于将电源端电压升压2倍后输出。其余K-1个基本二倍压单元153与接地端和顺序前一个基本二倍压单元153的倍压输出端相连，用于将顺序前一个基本二倍压单元153的输出电压叠加2倍电源端电压后输出。电源端Vs为顺序第一个基本二倍压单元153的倍压前供电端，所述顺序前一个基本二倍压单元153的倍压输出端为所述其余K-1个基本二倍压单元153的倍压前供电 端。
如图12所示，基本二倍压单元153具体包括：第五场效应管G5、第六场效应管G6、第七场效应管G7、第八场效应管G8、第一滤波阻抗器R1、第二滤波阻抗器R2、第三滤波阻抗器R3、第四滤波阻抗器R4、第一滤波电容C31、第二滤波电容C32、第三滤波电容C33、第四滤波电容C34、第二输出电容Cout2以及第二飞跨电容Cfly2。其中，第五场效应管G5和第六场效应管G6正向串联连接于倍压前供电端和接地端之间，第七场效应管G7和第八场效应管G8反向串联连接于倍压前供电端和接地端之间，且第八场效应管G8通过第二输出电容Cout2连接接地端。正向串联是指第五场效应管G5和第六场效应管G6相互串联，且都正接；反向串联是指第七场效应管G7和第八场效应管G8相互串联，且都反接。其中，第五场效应管G5和第八场效应管G8为P型场效应管；第六场效应管G6和第七场效应管G7为N型场效应管。第一滤波阻抗器R1的一端与倍压前供电端连接，另一端通过第一滤波电容C31与控制器连接，第五场效应管G5的栅极连接至第一滤波阻抗器R1和第一滤波电容C31之间。第二滤波阻抗器R2的一端与接地端连接，另一端通过第二滤波电容C32与控制器连接，第六场效应管G6的栅极连接至第二滤波阻抗器R2和第二滤波电容C32之间。第三滤波阻抗器R3的一端与倍压前供电端连接，另一端通过第三滤波电容C33与控制器连接，第七场效应管G7的栅极连接至第三滤波阻抗器R3和第三滤波电容C33之间。第四滤波阻抗器R4的一端通过第二输出电容Cout2与接地端连接，另一端通过第四滤波电容C34与控制器连接，第八场效应管G8的栅极连接至第四滤波阻抗器R4和第四滤波电容C34之间。第二飞跨电容Cfly2的第一端连接至第五场效应管G5和第六场效应管G6之间，第二飞跨电容Cfly2的第二端连接至第七场效应管G7和第八场效应管G8之间。
图12所示的基本二倍压单元153中，第五场效应管G5、第六场效应管G6、第七场效应管G7以及第八场效应管G8都是为MOS管，其中第五场效应管G5和第八场效应管G8为PMOS，第六场效应管G6和第七场效应管G7为NMOS。第一滤波阻抗器R1、第二滤波阻抗器R2、第三滤波阻抗器R3、第四滤波阻抗器R4、第一滤波电容C31、第二滤波电容C32、第三滤波电容C33、第四滤波电容C34两两构成RC高通滤波器。图12中的倍压前供电端就是电源端Vs，从控制器发来的控制信号接入第一滤波电容C31与第二滤波电容C32之间、以及第三滤波电容C33与第四滤波电容C34之间，以实现对第五场效应管G5、第六场效应管G6、第七场效应管G7以及第八场效应管G8的同步控制。基本二倍压单元153倍压后输出值复用单元的电压为2Vs。控制器发出控制信号 通过高通滤波器对第五场效应管G5、第六场效应管G6、第七场效应管G7以及第八场效应管G8进行驱动，第一滤波电容C31、第二滤波电容C32、第三滤波电容C33、第四滤波电容C34承担控制信号与电压轨之间的压差。由于NMOS和PMOS开启条件的相反性，第六场效应管G6和第七场效应管G7同时导通时第五场效应管G5和第八场效应管G8截止，电源端Vs通过第六场效应管G6和第七场效应管G7对第二飞跨电容Cfly2充电，第二飞跨电容Cfly2电压极性左负右正。第五场效应管G5和第八场效应管G8导通时，第六场效应管G6和第七场效应管G7截止，此时电源端Vs与左负右正的第二飞跨电容Cfly2串联对第二输出电容Cout2充电，第二输出电容Cout2上输出电压为2Vs，即是输入电压的2倍。
在上述基本二倍压单元153的实施例中，第二飞跨电容Cfly2的第一端还形成反向脉冲输出端，用于输出电压值与电源端电压相同、相位与控制器输入二倍压单元的信号相反的脉冲信号。由此可以从基本二倍压单元153引出幅度为Vs、相位和控制信号相反的脉冲信号。在如图12和图13所示基本二倍压单元153的实施例中，只需要对基本二倍压单元153输入一路控制信号，减少了控制线路的复杂程度。
在引出反向脉冲输出端的基础上，图14是本申请实施例提供的又一种预升压单元结构示意图。如图14所示的预升压单元15还可以包括：与基本二倍压单元153一一对应的加法器单元，以及T+1个开关选择器，T为加法器单元的数量。T个加法器单元顺序依次连接，每个加法器单元通过一个开关选择器与一个基本二倍压单元153的反向脉冲输出端连接。其中，顺序最后一个加法器单元还通过一个开关选择器与顺序最后一个基本二倍压单元153的倍压输出端连接，其余T-1个加法器单元的加法输出端与顺序前一个加法器单元的输入端连接，顺序第一个加法器单元的加法输出端与复用电路连接。其中，T+1个开关选择器用于控制所述顺序第一个加法器单元的加法输出端向所述复用电路输出的电压。
例如，在图12所示单个基本二倍压单元153的基础上，可以仅加入1个加法器单元和2个开关选择器，由此通过对开关选择器的选通实现0-3倍Vs的预升压。
例如，在图13所示多个基本二倍压单元153的基础上，加法器单元的数量也为多个。T个带反向脉冲输出端的基本二倍压单元153顺序连接时，具有T+1路直流电压输出，其大小分别为2 T,2 T-1,2 T-2.....2 2,2,1倍的Vs，具有T路反相的脉冲信号输出，其峰值大小分别为2 T-1.....2 2,2,1倍的Vs，配合上述T个上述加法器单元，可以得到T+1位数字倍压器。以图14为例，预升压单元15包含4个基本二倍压单元153、4个 加法器单元以及5个开关选择器(D00、D01、D02、D03、D04)，则可以实现对电源端电压的0至63倍任意整数倍数的倍压。假设要向复用电路输出3倍电源端的电压，即3Vs，则控制图中D00和D01接入其对应的反向脉冲输出端，其他开关选择器都接地。如此，可以通过对开关选择器的配置，实现预升压输出的配置。以此类推可以实现八位，十位，十二位甚至更高位数的数字倍压器。
上述图12至14所示的各种预升压的实施例中，控制信号线路布线简单，提高了线路抗干扰能力，减小了电路体积。
图15是本申请实施例提供的一种加法器单元的结构示意图。如图15所示的加法器单元153具体包括：第三飞跨电容Cfly3、第九场效应管G9、第十场效应管G10、第五滤波阻抗器R5、第六滤波阻抗器R6、第五滤波电容C35、第六滤波电容C36以及加法电容C+。其中，第九场效应管G9和第十场效应管G10反向串联连接于加法输入端和接地端之间，且第十场效应管G10通过加法电容C+连接接地端。这里的反向串联是第九场效应管G9和第十场效应管G10相互串联，且都反接。第五滤波阻抗器R5的一端与加法输入端(图中以V1示意加法输入端的电压)连接，另一端通过第五滤波电容C35与控制器连接，第九场效应管G9的栅极连接至第五滤波阻抗器R5和第五滤波电容C35之间。第六滤波阻抗器R6的一端通过加法电容C+与接地端连接，另一端通过第六滤波电容C36与控制器连接，第十场效应管G10的栅极连接至第六滤波阻抗器R6和第六滤波电容C36之间。第三飞跨电容Cfly3的一端连接基本二倍压单元153的反相脉冲输出端(图中以V2示意反相脉冲输出端的电压)，另一端连接至第九场效应管G9和第十场效应管G10之间。其中，第九场效应管G9是N型场效应管，第十场效应管G10是P型场效应管。加法电容C+与第十场效应管G10相连的一端为加法器单元153的加法输出端(图中以V1+V2示意加法输出端的电压)。
图15所示的加法器单元153中，第五滤波阻抗器R5、第六滤波阻抗器R6、第五滤波电容C35、第六滤波电容C36两两构成高通滤波器。例如，当控制器发来的控制信号为高电平时，基本二倍压单元153的反相脉冲输出端提供峰值V2的脉冲信号为低电平,此时第九场效应管G9导通，加法输入端通过第九场效应管G9对第三飞跨电容Cfly3充电，极性为左负右正；当控制信号为低电平时，第十场效应管G10导通，基本二倍压单元153的反相脉冲输出端提供峰值V2的脉冲信号为高电平，V2与左负右正且两端电压为V1的第三飞跨电容Cfly3串联后输出到加法电容C+,加法电容C+上的电压就是V1+V2,实现了电压的相加。上述加法器单元153需要一路直流电压V1和一 路峰值为V2的脉冲信号,V2要求与该加法器从控制器接收的控制信号反相，由此最终可以输出V1+V2的电压，实现预升压单元15中的电压加法。
上述第九场效应管G9和第十场效应管G10可以是硅场效应管，也可以是氮化镓、碳化硅等新型宽禁带半导体器件，在此不做限定。
图16是本申请实施例提供的一种芯片结构示意图。本申请还提供如图16所示的芯片20，包括上述任一实施例所述的驱动装置10。该芯片具体可以是对目标负载的驱动芯片。芯片20例如可以是闪光灯芯片、快门芯片、磁控芯片等，在此不做限定。
图17是本申请实施例提供的一种拍摄装置结构示意图。如图17所示的拍摄装置30，包括目标负载，以及所述芯片20或上述任一实施例所述的驱动装置10。图17中以拍摄装置30包含芯片20作为举例。
应当理解地，本申请可以应用于各种瞬时高脉冲功率驱动的应用场景中，拍摄装置仅为一种应用场景的举例，本申请不限于此。
图18是本申请实施例提供的一种无人机结构示意图。如图18所示的无人机，包括主体机身40和安装于主体机身40上的所述拍摄装置30。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”“第四”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本申请的实施例能够以除了在这里图示或描述的那些以外的顺序实施。
应当理解，在本申请中，“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
应当理解，在本申请中，“多个”是指两个或两个以上。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (25)

  1. 一种驱动装置，用于驱动电机，其特征在于，包括：控制器、储能电容单元以及复用电路；
    所述控制器与所述复用电路连接，用于向所述复用电路发送控制信号；
    所述复用电路与所述储能电容单元连接，用于响应所述控制器的控制信号，对所述储能电容单元进行充电或放电，以及向目标负载输出驱动信号；
    其中，所述复用电路包括滤波电路单元，所述滤波电路单元电连接在所述控制器与所述目标负载之间，以及所述储能电容单元与所述目标负载之间；
    当对所述储能电容单元进行充电时，所述滤波电路单元作为充电回路的无源网络使用，当所述储能电容单元进行放电时，所述滤波电路单元作为EMI滤波器使用。
  2. 根据权利要求1所述的驱动装置，其特征在于，所述复用电路还包括开关电路单元，所述开关电路单元电连接在所述控制器与所述滤波电路单元之间，以及所述储能电容单元与所述滤波电路单元之间，用于控制所述储能电容单元进行充电或放电。
  3. 根据权利要求2所述的驱动装置，其特征在于，所述复用电路还包括阻断电路单元，所述阻断电路单元电连接在所述滤波电路单元与所述目标负载之间；
    当所述储能电容单元通过所述滤波电路单元对所述目标负载进行供电时，所述阻断电路单元起到阻断作用，避免出现环流。
  4. 根据权利要求3所述的驱动装置，其特征在于，所述复用电路具体包括第一开关单元、第二开关单元、第三开关单元、第四开关单元、第一电感单元、第二电感单元、第一阻环流二极管以及第二阻环流二极管；
    所述第一开关单元的一端通过所述第二开关单元连接接地端，另一端与所述储能电容单元的高压端连接；所述第一电感单元的一端与所述目标负载连接，另一端连接至所述第一开关单元与所述第二开关单元之间；所述第一阻环流二极管的正极与电源端连接，负极连接至所述第一电感单元与所述目标负载之间；
    所述第四开关单元的一端通过所述第三开关单元连接接地端，另一端与所述储能电容单元的高压端连接；所述第二电感单元的一端与所述目标负载连接，另一端连接至所述第四开关单元与所述第三开关单元之间；所述第二阻环流二极管的正极与电源端连接，负极连接至所述第二电感单元与所述目标负载之间；所述储能电容单元的低压端与接地端连接；
    其中，所述第一开关单元的控制端、所述第二开关单元的控制端、所述第三开关 单元的控制端、所述第四开关单元的控制端都与所述控制器连接；所述控制器具体用于发出控制所述第一开关单元、第二开关单元、第三开关单元和第四开关单元的导通时序的控制信号。
  5. 根据权利要求4所述的驱动装置，其特征在于，所述滤波电路单元具体包括第一滤波电容单元和第二滤波电容单元；
    所述第一滤波电容单元的一端连接至所述第一电感单元和所述目标负载之间，另一端与接地端连接；
    所述第二滤波电容单元的一端连接至所述第二电感单元和所述目标负载之间，另一端与接地端连接。
  6. 根据权利要求4或5所述的驱动装置，其特征在于，所述复用电路还包括主栅极驱动单元，所述主栅极驱动单元用于将来自控制器的控制信号转换为驱动开关管栅极的栅极驱动信号；
    所述主栅极驱动单元的输入端与所述控制器连接，第一输出端与所述第一开关单元的控制端连接，第二输出端与所述第二开关单元的控制端连接，第三输出端与所述第三开关单元的控制端连接，第四输出端与所述第四开关单元的控制端连接。
  7. 根据权利要求1所述的驱动装置，其特征在于，所述储能电容单元包括2个电容子单元；
    所述驱动装置还包括：电容均压单元，连接至所述2个电容子单元之间，用于对所述2个电容子单元均衡电压。
  8. 根据权利要求7所述的驱动装置，其特征在于，所述电容均压单元包括：第一基准分压单元、第二基准分压单元、比较器、正反馈阻抗单元、负反馈阻抗单元、振荡电容单元以及滤波电感单元；
    所述第一基准分压单元和所述第二基准分压单元串联在所述储能电容单元的高压端和接地端之间；所述比较器的正相输入端连接至所述第一基准分压单元和所述第二基准分压单元之间，所述比较器的反相输入端通过所述振荡电容单元与接地端连接；所述滤波电感单元的第一端与所述比较器的输出端连接，第二端连接至所述2个电容子单元之间；所述正反馈阻抗单元的一端与所述比较器的正相输入端连接，另一端与所述比较器的输出端连接；所述负反馈阻抗单元的一端与所述比较器的反相输入端连接，另一端与所述滤波电感单元的第二端连接。
  9. 根据权利要求8所述的驱动装置，其特征在于，所述电容均压单元还包括缓冲 单元；
    所述比较器的输出端通过所述缓冲单元与所述滤波电感单元的第一端连接。
  10. 根据权利要求8或9所述的驱动装置，其特征在于，所述电容子单元包括2 n个电容单体，以及2 n-1个树形连接的所述电容均压单元，所述n为大于0的整数。
  11. 根据权利要求1所述的驱动装置，其特征在于，还包括预升压单元；
    所述复用电路通过所述预升压单元与电源端连接；所述预升压单元用于将所述电源端的电压升压后传输给所述复用电路。
  12. 根据权利要求11所述的驱动装置，其特征在于，所述预升压单元具体包括第一半桥控制单元和第二半桥储能单元；
    所述第一半桥控制单元与控制器、第二半桥储能单元、电源端和接地端连接，用于响应所述控制器的控制，将所述电源端的电源电压信号或所述接地端的接地电压信号传输给第二半桥储能单元；
    所述第二半桥储能单元还与控制器、复用电路、直流端和接地端连接，用于在所述第一半桥控制单元传输接地电压信号时，响应所述控制器的控制导通所述直流端进行充电储能，以及，在所述第一半桥控制单元传输电源电压信号时，响应所述控制器的控制导通所述接地端升压放电输出至所述复用电路。
  13. 根据权利要求12所述的驱动装置，其特征在于，所述第二半桥储能单元的数量为1；
    所述第二半桥储能单元对应的直流端为电源端。
  14. 根据权利要求12所述的驱动装置，其特征在于，所述第二半桥储能单元的数量为大于1的M；
    M个所述第二半桥储能单元顺序依次连接，每个所述第二半桥储能单元都与所述第一半桥控制单元连接，且顺序第一个第二半桥储能单元对应的直流端为电源单元的输出端，其余M-1个第二半桥储能单元对应的直流端为顺序前一个第二半桥储能单元的输出端，顺序最后一个第二半桥储能单元与所述复用电路连接。
  15. 根据权利要求12至14任一所述的驱动装置，其特征在于，
    所述第一半桥控制单元包括：第一栅极驱动器、第一场效应管和第二场效应管；所述第一场效应管和所述第二场效应管正向串联连接于电源端和接地端之间；所述第一栅极驱动器的高侧驱动信号输出端与所述第一场效应管的栅极连接，所述第一栅极驱动器的半桥模块输出端连接至所述第一场效应管和所述第二场效应管之间，所述第 一栅极驱动器的低侧驱动信号输出端与所述第二场效应管的栅极连接，所述第一栅极驱动器的高侧输入端和低侧输入端与所述控制器连接；
    第二半桥储能单元包括：第一飞跨电容、第一输出电容、第二栅极驱动器、耦合阻抗器、耦合电容、第三场效应管和第四场效应管；所述第三场效应管和所述第四场效应管反向串联连接，所述第三场效应管的漏极通过所述第一输出电容与接地端连接，所述第四场效应管的源极与直流端连接；所述第二栅极驱动器的高侧驱动信号输出端与所述第三场效应管的栅极连接,所述第二栅极驱动器的低侧驱动信号输出端通过所述耦合电容与所述第四场效应管的栅极连接，所述耦合阻抗器的一端与所述直流端连接，另一端连接至所述第四场效应管和所述耦合电容之间，所述第二栅极驱动器的高侧输入端和低侧输入端与所述控制器连接；所述第一飞跨电容的一端与所述第二栅极驱动器的半桥模块输出端连接，另一端连接至所述第一场效应管和所述第二场效应管之间。
  16. 根据权利要求15所述的驱动装置，其特征在于，所述第一半桥控制单元还包括第一自举二极管和第一隔离电容；所述第一自举二极管的正极连接所述第一栅极驱动器的芯片供电端，负极连接所述第一栅极驱动器的浮空供电端；所述第一隔离电容的一端连接所述第一栅极驱动器的浮空供电端，另一端连接所述第一栅极驱动器的半桥模块输出端，其中，所述第一栅极驱动器的芯片供电端还连接至第一供电端；
    所述第二半桥控制单元还包括第二自举二极管和第二隔离电容；所述第二自举二极管的正极连接第二供电端，负极连接所述第二栅极驱动器的浮空供电端；所述第二隔离电容的一端连接所述第二栅极驱动器的浮空供电端，另一端连接所述第二栅极驱动器的半桥模块输出端；其中，所述第二栅极驱动器的芯片供电端还连接至所述第一供电端，且所述第二供电端的电压为所述电源端的电压与所述第一供电端的电压之和。
  17. 根据权利要求11所述的驱动装置，其特征在于，所述预升压单元具体包括单个基本二倍压单元；
    所述复用电路通过所述单个基本二倍压单元与电源端连接，所述电源端为所述单个基本二倍压单元的倍压前供电端；
    所述基本二倍压单元用于将所述电源端电压升压2倍后传输给所述复用电路。
  18. 根据权利要求11所述的驱动装置，其特征在于，所述预升压单元具体包括K个顺序依次连接的基本二倍压单元，所述K为大于1的整数；
    所述复用电路通过所述K个顺序依次连接的基本二倍压单元与电源端连接；所述 K个顺序依次连接的基本二倍压单元用于将所述电源端电压升压2K倍后传输给所述复用电路；
    其中，所述K个顺序依次连接基本二倍压单元中，顺序第一个基本二倍压单元与电源端和接地端连接，用于将电源端电压升压2倍后输出；其余K-1个基本二倍压单元与接地端和顺序前一个基本二倍压单元的倍压输出端相连，用于将顺序前一个基本二倍压单元的输出电压叠加2倍电源端电压后输出；所述电源端为所述顺序第一个基本二倍压单元的倍压前供电端，顺序前一个基本二倍压单元的倍压输出端为所述其余K-1个基本二倍压单元的倍压前供电端。
  19. 根据权利要求17或18所述的驱动装置，其特征在于，所述基本二倍压单元包括：第五场效应管、第六场效应管、第七场效应管、第八场效应管、第一滤波阻抗器、第二滤波阻抗器、第三滤波阻抗器、第四滤波阻抗器、第一滤波电容、第二滤波电容、第三滤波电容、第四滤波电容、第二输出电容以及第二飞跨电容；
    所述第五场效应管和所述第六场效应管正向串联连接于倍压前供电端和接地端之间，所述第七场效应管和所述第八场效应管反向串联连接于倍压前供电端和接地端之间，且所述第八场效应管通过所述第二输出电容连接所述接地端；
    所述第一滤波阻抗器的一端与倍压前供电端连接，另一端通过所述第一滤波电容与所述控制器连接，所述第五场效应管的栅极连接至所述第一滤波阻抗器和所述第一滤波电容之间；
    所述第二滤波阻抗器的一端与接地端连接，另一端通过所述第二滤波电容与所述控制器连接，所述第六场效应管的栅极连接至所述第二滤波阻抗器和所述第二滤波电容之间；
    所述第三滤波阻抗器的一端与倍压前供电端连接，另一端通过所述第三滤波电容与所述控制器连接，所述第七场效应管的栅极连接至所述第三滤波阻抗器和所述第三滤波电容之间；
    所述第四滤波阻抗器的一端通过所述第二输出电容与接地端连接，另一端通过所述第四滤波电容与所述控制器连接，所述第八场效应管的栅极连接至所述第四滤波阻抗器和所述第四滤波电容之间；
    所述第二飞跨电容的第一端连接至所述第五场效应管和所述第六场效应管之间，所述第二飞跨电容的第二端连接至所述第七场效应管和所述第八场效应管之间；
    其中，所述第五场效应管和所述第八场效应管为P型场效应管；所述第六场效应 管和所述第七场效应管为N型场效应管。
  20. 根据权利要求19所述的驱动装置，其特征在于，所述第二飞跨电容的第一端还形成反向脉冲输出端，用于输出电压值与电源端电压相同、相位与所述控制器输入二倍压单元的信号相反的脉冲信号。
  21. 根据权利要求20所述的驱动装置，其特征在于，所述预升压单元还包括：与所述基本二倍压单元一一对应的加法器单元，以及T+1个开关选择器，所述T为所述加法器单元的数量；
    T个所述加法器单元顺序依次连接，每个所述加法器单元通过一个所述开关选择器与一个所述基本二倍压单元的反向脉冲输出端连接；其中，顺序最后一个加法器单元还通过一个开关选择器与顺序最后一个基本二倍压单元的倍压输出端连接，其余T-1个加法器单元的加法输出端与顺序前一个加法器单元的加法输入端连接，顺序第一个加法器单元的加法输出端与所述复用电路连接；
    其中，T+1个开关选择器用于控制所述顺序第一个加法器单元的加法输出端向所述复用电路输出的电压。
  22. 根据权利要求21所述的驱动装置，其特征在于，所述加法器单元具体包括：第三飞跨电容、第九场效应管、第十场效应管、第五滤波阻抗器、第六滤波阻抗器、第五滤波电容、第六滤波电容以及加法电容；
    所述第九场效应管和所述第十场效应管反向串联连接于加法输入端和接地端之间，且所述第十场效应管通过所述加法电容连接所述接地端；
    所述第五滤波阻抗器的一端与加法输入端连接，另一端通过所述第五滤波电容与控制器连接，所述第九场效应管的栅极连接至所述第五滤波阻抗器和所述第五滤波电容之间；
    所述第六滤波阻抗器的一端通过所述加法电容与接地端连接，另一端通过所述第六滤波电容与控制器连接，所述第十场效应管的栅极连接至所述第六滤波阻抗器和所述第六滤波电容之间；
    所述第三飞跨电容的一端连接反相脉冲输出端，另一端连接至所述第九场效应管和所述第十场效应管之间；
    其中，所述第九场效应管是N型场效应管，所述第十场效应管是P型场效应管；
    所述加法电容与所述第十场效应管相连的一端为所述加法器单元的加法输出端。
  23. 一种芯片，其特征在于，包括权利要求1至22任一所述的驱动装置。
  24. 一种拍摄装置，其特征在于，包括目标负载，以及
    如权利要求23所述的芯片或如权利要求1至22任一所述的驱动装置。
  25. 一种无人机，其特征在于，包括主体机身和安装于所述主体机身上的如权利要求24所述的拍摄装置。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024098979A1 (zh) * 2022-11-07 2024-05-16 深圳市汇顶科技股份有限公司 驱动电路、主动笔和触控芯片

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101764352A (zh) * 2009-12-03 2010-06-30 宁波振东光电有限公司 一种半导体激光器脉冲驱动电路
CN101772233A (zh) * 2009-01-05 2010-07-07 台达电子工业股份有限公司 光源驱动电路
CN102523654A (zh) * 2011-12-20 2012-06-27 凹凸电子（武汉）有限公司 Led光源的驱动电路、控制电路及控制方法
US20140117867A1 (en) * 2011-06-10 2014-05-01 Koninklijke Philips N.V. Driver device and driving method for driving a load, in particular an led unit
CN203859679U (zh) * 2014-03-21 2014-10-01 国网电力科学研究院武汉南瑞有限责任公司 一种单线圈永磁机构驱动电路
CN207783204U (zh) * 2017-01-25 2018-08-28 杭州士兰微电子股份有限公司 Led驱动电路
CN208923555U (zh) * 2018-08-22 2019-05-31 西安飞芯电子科技有限公司 一种预充电激光驱动电路
CN110798092A (zh) * 2019-12-03 2020-02-14 中国科学院长春光学精密机械与物理研究所 一种正脉冲电源发生装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007306647A (ja) * 2006-05-09 2007-11-22 Lenovo Singapore Pte Ltd 電源システムおよび電子機器
CN201181853Y (zh) * 2008-04-28 2009-01-14 郑州德朗能电池有限公司 太阳能碱性锌锰干电池充电器及其手机充电器
CN101572427A (zh) * 2009-05-27 2009-11-04 沈建良 基于高效大电流升压器的电池供电系统
CN203645360U (zh) * 2013-11-15 2014-06-11 中科恒源科技股份有限公司 一种充放电复用电路
TWI571029B (zh) * 2015-10-28 2017-02-11 茂達電子股份有限公司 補償電路及使用其的儲能裝置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101772233A (zh) * 2009-01-05 2010-07-07 台达电子工业股份有限公司 光源驱动电路
CN101764352A (zh) * 2009-12-03 2010-06-30 宁波振东光电有限公司 一种半导体激光器脉冲驱动电路
US20140117867A1 (en) * 2011-06-10 2014-05-01 Koninklijke Philips N.V. Driver device and driving method for driving a load, in particular an led unit
CN102523654A (zh) * 2011-12-20 2012-06-27 凹凸电子（武汉）有限公司 Led光源的驱动电路、控制电路及控制方法
CN203859679U (zh) * 2014-03-21 2014-10-01 国网电力科学研究院武汉南瑞有限责任公司 一种单线圈永磁机构驱动电路
CN207783204U (zh) * 2017-01-25 2018-08-28 杭州士兰微电子股份有限公司 Led驱动电路
CN208923555U (zh) * 2018-08-22 2019-05-31 西安飞芯电子科技有限公司 一种预充电激光驱动电路
CN110798092A (zh) * 2019-12-03 2020-02-14 中国科学院长春光学精密机械与物理研究所 一种正脉冲电源发生装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024098979A1 (zh) * 2022-11-07 2024-05-16 深圳市汇顶科技股份有限公司 驱动电路、主动笔和触控芯片

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