WO2021097763A1 - 整流器、逆变器及无线充电设备 - Google Patents

整流器、逆变器及无线充电设备 Download PDF

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Publication number
WO2021097763A1
WO2021097763A1 PCT/CN2019/119991 CN2019119991W WO2021097763A1 WO 2021097763 A1 WO2021097763 A1 WO 2021097763A1 CN 2019119991 W CN2019119991 W CN 2019119991W WO 2021097763 A1 WO2021097763 A1 WO 2021097763A1
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WIPO (PCT)
Prior art keywords
terminal
coupled
tube
capacitor
switch
Prior art date
Application number
PCT/CN2019/119991
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English (en)
French (fr)
Inventor
胡章荣
魏巍
Original Assignee
华为技术有限公司
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Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201980057036.4A priority Critical patent/CN113228488B/zh
Priority to PCT/CN2019/119991 priority patent/WO2021097763A1/zh
Priority to EP19953701.0A priority patent/EP4040664A4/en
Priority to CN202210768497.6A priority patent/CN115296438A/zh
Publication of WO2021097763A1 publication Critical patent/WO2021097763A1/zh
Priority to US17/748,885 priority patent/US20220278558A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/505—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means
    • H02M7/515—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only
    • H02M7/521—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only in a bridge configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M10/00—Secondary cells; Manufacture thereof
    • H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
    • H01M10/44—Methods for charging or discharging
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J50/00—Circuit arrangements or systems for wireless supply or distribution of electric power
    • H02J50/10—Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling
    • H02J50/12—Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling of the resonant type
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/02—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries for charging batteries from ac mains by converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/02—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries for charging batteries from ac mains by converters
    • H02J7/04—Regulation of charging current or voltage
    • H02J7/06—Regulation of charging current or voltage using discharge tubes or semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33573—Full-bridge at primary side of an isolation transformer
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J2207/00—Indexing scheme relating to details of circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J2207/20—Charging or discharging characterised by the power electronics converter
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • This application relates to the field of wireless charging technology, and in particular to a rectifier, an inverter, and a wireless charging device.
  • Wireless charging technology refers to a technology that uses a magnetic field to transfer electric energy between a charger and an electric device, and the two do not need a wire connection to charge the user's device.
  • a wireless charging receiver usually includes: a resonance circuit and a rectifier circuit.
  • the resonant circuit is used to convert the electromagnetic signal obtained from the wireless charging transmitter
  • the rectifier circuit is used to rectify the signal output by the resonant circuit
  • the rectifier circuit operates in the full-bridge rectification mode, that is, the output voltage of the output terminal of the rectifier circuit Approximately equal to the input voltage at its input.
  • a wireless charging transmitter usually includes: a resonance circuit and an inverter circuit.
  • the resonant circuit is used to convert the signal output by the inverter circuit into an electromagnetic signal
  • the inverter circuit is used to perform inversion processing on the input signal for the resonant circuit to emit electromagnetic signals
  • the inverter circuit operates in the full-bridge inverter mode , That is, the output voltage of the output terminal of the inverter circuit is approximately equal to the input voltage of its input terminal.
  • the output voltage of the rectifier circuit in the wireless charging receiver or the inverter circuit in the wireless charging transmitter in the related art is approximately equal to its input voltage, and the variable dynamic range is small.
  • the present application provides a rectifier, an inverter, and a wireless charging device, which solves the problem that the rectifier circuit in the wireless charging receiver in the related art, or the inverter circuit in the wireless charging transmitter has a small dynamic range of variable output voltage.
  • an embodiment of the present application provides a rectifier, including: a signal conversion unit and a switchable capacitor unit; the signal conversion unit includes a first terminal, a second terminal, a third terminal, a fourth terminal, and a first unidirectional A semiconductor tube, a second one-way conduction semiconductor tube, a third one-way conduction semiconductor tube, and a fourth one-way conduction semiconductor tube.
  • the output end of the first one-way conduction semiconductor tube and the input end of the second one-way conduction semiconductor tube are coupled to the first end, and the output end of the second one-way conduction semiconductor tube and the third one-way conduction semiconductor tube
  • the output terminal is coupled to the second terminal, the output terminal of the fourth one-way conducting semiconductor tube and the input terminal of the third one-way conducting semiconductor tube are coupled to the third terminal, and the input terminal of the first one-way conducting semiconductor tube
  • the input end of the fourth unidirectional conducting semiconductor tube is coupled to the fourth end, the first end and the third end are used for coupling to a resonant circuit, and the fourth end is used for coupling to a constant voltage.
  • the switchable capacitor unit is coupled to at least one of the first terminal and the third terminal, the second terminal and the fourth terminal.
  • the first terminal and the third terminal are input terminals of the rectifier
  • the second terminal and the fourth terminal are output terminals of the rectifier
  • the constant voltage may be a ground voltage.
  • the switchable capacitor unit in the embodiment of the present application is used to switch the rectification mode of the above-mentioned rectifier, where the rectification mode may include, but is not limited to: a voltage double rectification mode and a full-bridge rectification mode.
  • the above-mentioned first uni-conducting semiconductor tube, second uni-conducting semiconductor tube, third uni-conducting semiconductor tube, and fourth uni-conducting semiconductor tube may all be diodes.
  • the input of each diode The terminal may be the anode of the diode, and the output terminal of each diode may be the cathode of the diode.
  • first uni-conducting semiconductor tube, second uni-conducting semiconductor tube, third uni-conducting semiconductor tube, and fourth uni-conducting semiconductor tube may all be metal-oxide-semiconductor MOS transistors.
  • connection direction of each MOS tube must satisfy: the anode of the body diode of the MOS tube is used as the input terminal of the MOS tube, and the cathode of the body diode of the MOS tube is used as the output terminal of the MOS tube.
  • any unidirectional conductive semiconductor tube is a PMOS tube
  • the input terminal of the unidirectional conductive tube is the drain of the PMOS tube
  • the output terminal of the unidirectional conductive tube is the source of the PMOS tube.
  • the input terminal of the unidirectional conducting tube is the source of the NMOS tube
  • the output terminal of the unidirectional conducting tube is the drain of the NMOS tube.
  • first uniconducting semiconductor tube, second uniconducting semiconducting tube, third uniconducting semiconducting tube, and fourth uniconducting semiconducting tube may all be PMOS tubes, or all of them may be NMOS transistors. tube.
  • part of the first uni-conducting semiconductor tube, the second uni-conducting semiconductor tube, the third uni-conducting semiconductor tube, and the fourth uni-conducting semiconductor tube may be PMOS tube, another part of unidirectional conduction semiconductor tube can be NMOS tube.
  • connection method in this example needs to meet the following connection rules: 1) When the PMOS tube is coupled to the NMOS tube, the source of the PMOS tube is coupled to the source of the NMOS tube, or the drain of the PMOS tube is coupled to The drain of the NMOS tube; 2) The terminal used for coupling to the second end is the source of the PMOS tube or the drain of the NMOS tube.
  • part of the first uni-conducting semiconductor tube, the second uni-conducting semiconductor tube, the third uni-conducting semiconductor tube, and the fourth uni-conducting semiconductor tube may be diodes.
  • the other part of the uni-conducting semiconductor tube can be a MOS tube.
  • the input terminal of each diode may be the anode of the diode
  • the output terminal of each diode may be the cathode of the diode.
  • the connection direction of each MOS tube must satisfy: the anode of the body diode of the MOS tube is used as the input terminal of the MOS tube, and the cathode of the body diode of the MOS tube is used as the output terminal of the MOS tube.
  • any unidirectional conductive semiconductor tube is a PMOS tube
  • the input terminal of the unidirectional conductive tube is the drain of the PMOS tube
  • the output terminal of the unidirectional conductive tube is the source of the PMOS tube.
  • the input terminal of the unidirectional conducting tube is the source of the NMOS tube
  • the output terminal of the unidirectional conducting tube is the drain of the NMOS tube.
  • each MOS tube can be used as a control terminal to receive a control signal to control the turn-on or turn-off of the MOS tube, thereby controlling the current to enter the output terminal of the MOS tube.
  • the rectifier provided by the embodiment of the present application includes: a signal conversion unit and a switchable capacitor unit that are coupled to each other.
  • the switchable capacitor unit is used to switch the rectification mode of the rectifier. Therefore, the output voltage of the rectifier provided by the embodiment of the present application The variable dynamic range is large.
  • the switchable capacitor unit includes a first switch and a capacitor unit, the first switch is coupled between the third terminal and an intermediate node, and the capacitor unit is coupled to the second terminal and the second terminal. Four ends and the intermediate node.
  • the capacitor unit includes: a first capacitor and a second capacitor, the first capacitor is coupled between the intermediate node and the second terminal, and the second capacitor is coupled between the intermediate node and the second terminal. Between the fourth end.
  • the capacitor unit further includes: a third capacitor, and the third capacitor is coupled between the second terminal and the fourth terminal.
  • the capacitor unit includes: a first capacitor and a second capacitor, the first capacitor is coupled between the intermediate node and a preset position, and the second capacitor is coupled between the second end and the Between the fourth end.
  • the preset position includes any one of the following: the second end, the fourth end, or a preset voltage.
  • the switchable capacitor unit includes a first switch, a first capacitor, and a second capacitor, the first capacitor is coupled between the third terminal and the intermediate node, and the first switch is coupled to the Between the intermediate node and the preset position, the second capacitor is coupled between the second terminal and the fourth terminal.
  • the preset position includes any one of the following: the second end, the fourth end, or a preset voltage.
  • the switchable capacitor unit further includes: a first switching unit and a second switching unit, the first switching unit is coupled between the intermediate node and the first terminal, and the second switching unit It is coupled between the fourth terminal and the resonant circuit.
  • the conduction or disconnection of the first switching unit and the second switching unit in conjunction with the conduction or disconnection of the first switch, can switch the rectification mode of the rectifier.
  • the first switching unit includes: a fifth unidirectional conducting semiconductor tube and a second switch; the second switch is coupled between the intermediate node and the input end of the fifth unidirectional conducting semiconductor tube In between, the output terminal of the fifth uniconducting semiconductor tube is coupled to the first end; or, the input terminal of the fifth uniconducting semiconductor tube is coupled to the intermediate node, and the second switch is coupled to the first end and The fifth one-way conduction between the output ends of the semiconductor tube.
  • the above-mentioned second switch may be a mechanical switch or a MOS tube; and/or, the above-mentioned fifth unidirectional conducting semiconductor tube may be a diode or a MOS tube; wherein, the MOS tube may be a PMOS tube or an NMOS tube .
  • the second switching unit includes: a sixth unidirectional conducting semiconductor tube and a third switch; the third switch is coupled to the fourth terminal and the input end of the sixth unidirectional conducting semiconductor tube In between, the output terminal of the sixth unidirectional conducting semiconductor tube is coupled to the resonant circuit; or, the input terminal of the sixth unidirectional conducting semiconductor tube is coupled to the fourth terminal, and the third switch is coupled to the sixth unit. Conducting between the output end of the semiconductor tube and the resonant circuit.
  • the above-mentioned third switch may be a mechanical switch or a MOS tube; and/or, the above-mentioned sixth unidirectional conducting semiconductor tube may be a diode or a MOS tube; wherein, the MOS tube may be a PMOS tube or an NMOS tube .
  • the rectifier is in the n1 voltage doubler rectification mode, where n1 is a real number greater than zero.
  • the rectifier is in the n2 voltage doubler rectification mode, where n2 is A real number greater than 0, and n2 is greater than n1.
  • the rectifier is in the full-bridge rectification mode.
  • the rectifier provided in the above embodiment can switch more rectification modes of the rectifier through the conduction or disconnection of the first switching unit and the second switching unit in conjunction with the conduction or disconnection of the first switch. It can be seen that the variable dynamic range of the output voltage of the rectifier provided in the embodiment of the present application is further increased.
  • auxiliary boost circuit which is coupled between the first terminal and the second terminal, and is configured to boost the voltage of the first terminal, The boosted voltage meets the starting voltage of the controller, so that the controller can control the switchable capacitor unit to switch the rectification mode of the rectifier.
  • an embodiment of the present application provides a wireless charging device for receiving a wireless charging signal, and the device includes: the rectifier and the resonance circuit described in any implementation manner of the first aspect.
  • the device further includes: a controller for controlling the switchable capacitor unit to switch the rectification mode of the rectifier; wherein, the rectification mode includes: a voltage doubler rectification mode, or a full-bridge rectification mode Mode:
  • the voltage doubler rectification mode includes the above-mentioned n1 voltage doubler rectification mode or n2 voltage doubler rectifier mode.
  • controller is also used to control the turning on or turning off of each unidirectional conductive semiconductor tube in the above-mentioned signal conversion unit.
  • the device provided in this implementation manner can adjust the output voltage of the device by switching the rectification mode of the above-mentioned rectifier to meet the power supply demand.
  • the device further includes: a charge management unit coupled between the second terminal and the fourth terminal, configured to perform voltage conversion on the output voltage of the output terminal of the rectifier to match the electrical energy storage The storage voltage of the cell.
  • an embodiment of the present application provides an inverter, including: a signal conversion unit and a switchable capacitor unit; the signal conversion unit includes a first terminal, a second terminal, a third terminal, a fourth terminal, and a first terminal.
  • the input end of the first one-way conduction semiconductor tube and the output end of the second one-way conduction semiconductor tube are coupled to the first end, and the input end of the second one-way conduction semiconductor tube and the third one-way conduction semiconductor tube
  • the input terminal is coupled to the second terminal, the input terminal of the fourth one-way conducting semiconductor tube and the output terminal of the third one-way conducting semiconductor tube are coupled to the third terminal, and the output terminal of the first one-way conducting semiconductor tube
  • the output end of the fourth unidirectional conducting semiconductor tube is coupled to the fourth end, the first end and the third end are used for coupling to a resonant circuit, and the fourth end is used for coupling to a constant voltage.
  • the switchable capacitor unit is coupled to at least one of the first terminal and the third terminal, the second terminal and the fourth terminal; wherein the first terminal and the third terminal are the output of the inverter Terminal, the second terminal and the fourth terminal are input terminals of the inverter; the constant voltage may be a ground voltage.
  • the switchable capacitor unit in the embodiment of the present application is used to switch the inverter mode of the above-mentioned inverter, where the inverter mode may include, but is not limited to: a voltage division inverter mode and a full-bridge inverter mode.
  • the above-mentioned first unidirectional conducting semiconductor tube, second unidirectional conducting semiconducting tube, third unidirectional conducting semiconducting tube and fourth unidirectional conducting semiconducting tube may all be metal-oxide-semiconductor MOS tubes.
  • the connection direction of each MOS tube should satisfy: the cathode of the body diode of the MOS tube is used as the input terminal of the MOS tube, and the anode of the body diode of the MOS tube is used as the output terminal of the MOS tube.
  • any unidirectional conduction semiconductor tube is a PMOS tube
  • the input terminal of the unidirectional conduction tube is the source of the PMOS tube
  • the output terminal of the unidirectional conduction tube is the drain of the PMOS tube.
  • the input terminal of the unidirectional conducting tube is the drain of the NMOS tube
  • the output terminal of the unidirectional conducting tube is the source of the NMOS tube.
  • first uniconducting semiconductor tube, second uniconducting semiconducting tube, third uniconducting semiconducting tube, and fourth uniconducting semiconducting tube may all be PMOS tubes, or all of them may be NMOS transistors. tube.
  • part of the first uni-conducting semiconductor tube, the second uni-conducting semiconductor tube, the third uni-conducting semiconductor tube, and the fourth uni-conducting semiconductor tube may be PMOS tube, another part of unidirectional conduction semiconductor tube can be NMOS tube.
  • connection method in this example needs to meet the following connection rules: 1) When the PMOS tube is coupled to the NMOS tube, the source of the PMOS tube is coupled to the source of the NMOS tube, or the drain of the PMOS tube is coupled to The drain of the NMOS tube; 2) The terminal used for coupling to the second end is the source of the PMOS tube or the drain of the NMOS tube.
  • each MOS tube can be used as a control terminal to receive a control signal to control the turn-on or turn-off of the MOS tube, thereby controlling the current to enter the output terminal of the MOS tube.
  • the inverter provided by the embodiment of the present application includes: a signal conversion unit and a switchable capacitor unit that are coupled to each other.
  • the switchable capacitor unit is used to switch the inverter mode of the inverter. Therefore, the embodiment of the present application provides The variable dynamic range of the inverter's output voltage is larger.
  • the switchable capacitor unit includes a first switch and a capacitor unit, the first switch is coupled between the third terminal and an intermediate node, and the capacitor unit is coupled to the second terminal and the second terminal. Four ends and the intermediate node.
  • the capacitor unit includes: a first capacitor and a second capacitor, the first capacitor is coupled between the intermediate node and the second terminal, and the second capacitor is coupled between the intermediate node and the second terminal. Between the fourth end.
  • the capacitor unit further includes: a third capacitor, and the third capacitor is coupled between the second terminal and the fourth terminal.
  • the capacitor unit includes: a first capacitor and a second capacitor, the first capacitor is coupled between the intermediate node and a preset position, and the second capacitor is coupled between the second end and the Between the fourth end.
  • the preset position includes any one of the following: the second end, the fourth end, or a preset voltage.
  • the switchable capacitor unit includes a first switch, a first capacitor, and a second capacitor, the first capacitor is coupled between the third terminal and the intermediate node, and the first switch is coupled to the Between the intermediate node and the preset position, the second capacitor is coupled between the second terminal and the fourth terminal.
  • the preset position includes any one of the following: the second end, the fourth end, or a preset voltage.
  • the switchable capacitor unit further includes: a first switching unit and a second switching unit, the first switching unit is coupled between the intermediate node and the first terminal, and the second switching unit It is coupled between the fourth terminal and the resonant circuit.
  • the conduction or disconnection of the first switching unit and the second switching unit in conjunction with the conduction or disconnection of the first switch, can switch the inverter mode of the inverter.
  • the first switching unit includes: a fifth unidirectional conducting semiconductor tube and a second switch; the second switch is coupled between the intermediate node and the input end of the fifth unidirectional conducting semiconductor tube In between, the output terminal of the fifth uniconducting semiconductor tube is coupled to the first end; or, the input terminal of the fifth uniconducting semiconductor tube is coupled to the intermediate node, and the second switch is coupled to the first end and The fifth one-way conduction between the output ends of the semiconductor tube.
  • the above-mentioned second switch may be a mechanical switch or a MOS tube; and/or, the above-mentioned fifth unidirectional conducting semiconductor tube may be a diode or a MOS tube; wherein, the MOS tube may be a PMOS tube or an NMOS tube .
  • the second switching unit includes: a sixth unidirectional conducting semiconductor tube and a third switch; the third switch is coupled to the fourth terminal and the input end of the sixth unidirectional conducting semiconductor tube In between, the output terminal of the sixth unidirectional conducting semiconductor tube is coupled to the resonant circuit; or, the input terminal of the sixth unidirectional conducting semiconductor tube is coupled to the fourth terminal, and the third switch is coupled to the sixth unit. Conducting between the output end of the semiconductor tube and the resonant circuit.
  • the above-mentioned third switch may be a mechanical switch or a MOS tube; and/or, the above-mentioned sixth unidirectional conducting semiconductor tube may be a diode or a MOS tube; wherein, the MOS tube may be a PMOS tube or an NMOS tube .
  • the inverter is in the 1/n1 voltage division inverter mode, where n1 is greater than 0 Real number.
  • the inverter is in a 1/n2 voltage division inverter mode , Where n2 is a real number greater than 0, and n2 is greater than n1.
  • the inverter is in the full-bridge inverter mode.
  • inverter through the on or off of the first switching unit and the second switching unit, in conjunction with the on or off of the first switch, more of the inverter can be switched. Inverter mode. It can be seen that the variable dynamic range of the output voltage of the inverter provided by the embodiment of the present application is further increased.
  • an embodiment of the present application provides a wireless charging device, which is used to send a wireless charging signal.
  • the device includes the inverter and a resonance circuit as described in any implementation manner of the third aspect.
  • the device further includes: a controller for controlling the switchable capacitor unit to switch the inverter mode of the inverter; wherein, the inverter mode includes: a divided voltage inverter mode , Or a full-bridge inverter mode; the voltage-divided inverter mode includes the above-mentioned 1/n1 voltage-divided inverter mode, or a 1/n2 voltage-divided inverter mode.
  • controller is also used to control the turning on or turning off of each unidirectional conductive semiconductor tube in the above-mentioned signal conversion unit.
  • the device provided in this implementation manner can adjust the output voltage of the device by switching the inverter mode of the above-mentioned inverter to meet the voltage required to be coupled to the receiving coil of the receiving end.
  • Figure 1 is a schematic diagram of a system architecture provided by an embodiment of the application.
  • 2A is a first structural diagram of a conversion circuit provided by an embodiment of the application.
  • 2B is a second structural diagram of a conversion circuit provided by an embodiment of this application.
  • 2C is a third structural diagram of a conversion circuit provided by an embodiment of this application.
  • 3A is a fourth structural diagram of a conversion circuit provided by an embodiment of this application.
  • FIG. 3B is a fifth structural schematic diagram of a conversion circuit provided by an embodiment of the application.
  • 3C is a sixth structural diagram of a conversion circuit provided by an embodiment of this application.
  • FIG. 3D is a schematic diagram 7 of the structure of the conversion circuit provided by the embodiment of the application.
  • FIG. 3E is an eighth structural diagram of a conversion circuit provided by an embodiment of this application.
  • 3F is a schematic diagram 9 of the structure of a conversion circuit provided by an embodiment of the application.
  • FIG. 4A is a tenth structural diagram of a conversion circuit provided by an embodiment of this application.
  • FIG. 4B is an eleventh structural diagram of a conversion circuit provided by an embodiment of this application.
  • FIG. 4C is a twelfth structural diagram of a conversion circuit provided by an embodiment of the application.
  • FIG. 4D is a schematic diagram 13 of the structure of a conversion circuit provided by an embodiment of this application.
  • 4E is a fourteenth structural diagram of a conversion circuit provided by an embodiment of this application.
  • Figure 5 is a fifteenth structural schematic diagram of a conversion circuit provided by an embodiment of the application.
  • FIG. 6A is a sixteenth structural diagram of a conversion circuit provided by an embodiment of this application.
  • FIG. 6B is a seventeenth structural diagram of a conversion circuit provided by an embodiment of this application.
  • FIG. 7A is a first structural diagram of a wireless charging device provided by an embodiment of this application.
  • FIG. 7B is a second structural diagram of a wireless charging device provided by an embodiment of this application.
  • FIG. 1 is a schematic diagram of a system architecture provided by an embodiment of the application.
  • the system architecture provided by the embodiment of the present application may include, but is not limited to: a wireless charging transmitter 1, a wireless charging receiver 2 and an electric energy storage unit 3.
  • the wireless charging transmitter 1 may include but is not limited to: an inverter 11 and a resonance circuit 14 including a resonance capacitor 12 and a transmitting coil 13; the output terminal of the inverter 11 is coupled to both ends of the resonance circuit 14.
  • the above-mentioned inverter 11 is used for inverting the input electric signal; the resonance circuit 14 is used for converting the electric signal obtained by the inverter 11 into an electromagnetic signal and transmitting the electromagnetic signal.
  • the following embodiments of the present application will introduce the achievable manners of the inverter 11 and the wireless charging transmitter 1 described above.
  • the above-mentioned wireless charging transmitter 1 can adjust the output voltage of the wireless charging transmitter 1 by switching the inverter mode of the inverter 11 to meet the voltage required to be coupled to the receiving coil of the receiving end.
  • the above-mentioned wireless charging receiver 2 may include, but is not limited to: a rectifier 21, and a resonant circuit 24 including a resonant capacitor 22 and a receiving coil 23; the input end of the rectifier 21 is coupled to the output end of the resonant circuit 24, and the output end of the rectifier 21 is coupled In the electrical energy storage unit 3.
  • the resonant circuit 24 is used to convert the electromagnetic signal received from the transmitting coil 13 to obtain an electrical signal;
  • the rectifier 21 is used to rectify the electrical signal output by the resonant circuit 24, and store the processed electrical energy into electrical energy.
  • Storage unit 3. The following embodiments of the present application will introduce the achievable manners of the above-mentioned rectifier 21 and the wireless charging receiver 2.
  • the above-mentioned wireless charging receiver 2 can adjust the output voltage of the wireless charging receiver 2 by switching the rectification mode of the rectifier 21 to meet the power supply demand.
  • the numbers “first” and “second” in the embodiments of the present application are used to distinguish similar objects, and are not necessarily used to describe a specific sequence or sequence, and should not constitute any limitation to the embodiments of the present application.
  • the coupling in the embodiments of this application refers to electrical connection, including direct connection or indirect connection, which is not limited in this application.
  • the unidirectional conduction semiconductor tube involved in the embodiments of this application may be: Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) (or MOS tube for short), or diode; of course, it is also It may be other semiconductor tubes with a unidirectional conduction function, which is not limited in the embodiment of the present application.
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • Any MOS transistor involved in the embodiments of the present application is not limited to include only one MOS transistor.
  • multiple MOS transistors can be connected in parallel to achieve lower on-resistance, or multiple MOS transistors can be connected in series to achieve higher withstand voltage.
  • the implementation of this application This is not limited in the example.
  • Any diode involved in the embodiments of the present application is not limited to include only one diode.
  • multiple diodes can be connected in parallel to achieve lower on-resistance, or multiple diodes can be connected in series to achieve higher withstand voltage. In the embodiments of the present application, There is no restriction on this.
  • any unidirectional conducting semiconductor tube is a diode
  • the input terminal of the diode may be the anode of the diode
  • the output terminal of the diode may be the cathode of the diode.
  • Any switch involved in the embodiment of the present application may be a MOS transistor or a mechanical switch; of course, it may also be another device with a switch function, which is not limited in the embodiment of the present application.
  • the MOS transistors involved in the embodiments of the present application may include: PMOS transistors or NMOS transistors.
  • the electronic devices involved in the embodiments of the present application may include, but are not limited to: terminal devices such as mobile phones, tablet computers, and notebooks.
  • the wireless charging transmitter involved in the embodiments of the present application may include, but is not limited to, devices that transmit power to the outside, such as charging disks.
  • the wireless charging receiver involved in the embodiments of the present application may include, but is not limited to: electronic devices with batteries, medical devices, or electric vehicles and other devices capable of receiving wireless charging power.
  • the wireless charging device involved in the embodiments of the present application may include, but is not limited to: a wireless charging transmitter, or a wireless charging receiver.
  • the rectifier or inverter includes: a signal conversion unit and a switchable capacitor unit coupled to each other, wherein the switchable capacitor unit in the rectifier is used to switch the The finishing mode of the rectifier, or the switchable capacitor unit in the inverter is used to switch the inverter mode of the inverter. Therefore, the variable dynamic range of the output voltage of the rectifier or the inverter provided by the embodiment of the present application Larger.
  • FIG. 2A is a first structural diagram of a conversion circuit provided by an embodiment of the application.
  • the conversion circuit 20 provided by the embodiment of the present application may include: a signal conversion unit 201 and a switchable capacitor unit 202.
  • the conversion circuit 20 provided in the embodiment of the present application may be a rectifier or an inverter.
  • the signal conversion unit 201 may include but is not limited to: a first terminal a, a second terminal b, a third terminal c, a fourth terminal d, a first unidirectional conducting semiconductor tube 2011, and a second unidirectional conducting semiconductor pole tube 2012 , The third one-way conduction semiconductor tube 2013 and the fourth one-way conduction semiconductor tube 2014.
  • the connection relationship of the signal conversion unit 201 may be as follows: the output terminal of the first unidirectional conductive semiconductor tube 2011 and the second unidirectional conductive semiconductor tube
  • the input terminal of 2012 is coupled to the first terminal a.
  • the output terminal of the second unidirectional conducting semiconductor tube 2012 and the output terminal of the third unidirectional conducting semiconductor tube 2013 are coupled to the second terminal b.
  • the output terminal of the fourth unidirectional conducting semiconductor tube 2014 and the input terminal of the third unidirectional conducting semiconductor tube 2013 are coupled to the third terminal c.
  • the input terminal of the first unidirectional conducting semiconductor tube 2011 and the input terminal of the fourth unidirectional conducting semiconductor tube 2014 are coupled to the fourth terminal d.
  • the fourth terminal d is used for coupling to a constant voltage, for example, the constant voltage may be a ground voltage.
  • the first terminal a and the third terminal c are the input terminals of the rectifier and are used for coupling to the output terminal of the resonant circuit 24; the second terminal b and the fourth terminal d are the output terminals of the rectifier and are used for coupling In the above-mentioned electric energy storage unit 3.
  • the above-mentioned first unidirectional conducting semiconductor tube 2011, second uniconducting conducting semiconducting tube 2012, third uniconducting conducting semiconducting tube 2013, and fourth uniconducting conducting semiconducting tube 2014 may all be diodes, and correspondingly, each The input terminal of each diode may be the anode of the diode, and the output terminal of each diode may be the cathode of the diode.
  • FIG. 2B is the second structural diagram of the conversion circuit provided by the embodiment of this application. As shown in FIG. 2B, the above-mentioned first unidirectional conducting semiconductor transistor 2011, the second unidirectional conducting semiconductor diode 2012, and the third unidirectional conducting semiconductor transistor in the embodiment of the present application are The unidirectional conducting semiconductor tube 2013 and the fourth unidirectional conducting semiconductor tube 2014 may both be diodes.
  • the above-mentioned first unidirectional conducting semiconductor transistor 2011, second uniconducting semiconductor diode 2012, third uniconducting semiconductor transistor 2013, and fourth uniconducting semiconductor transistor 2014 may all be metal-oxide.
  • -Semiconductor MOS tube wherein, the connection direction of each MOS tube must satisfy: the anode of the body diode of the MOS tube is used as the input terminal of the MOS tube, and the cathode of the body diode of the MOS tube is used as the output terminal of the MOS tube.
  • any unidirectional conductive semiconductor tube is a PMOS tube
  • the input terminal of the unidirectional conductive tube is the drain of the PMOS tube
  • the output terminal of the unidirectional conductive tube is the source of the PMOS tube.
  • the input terminal of the unidirectional conducting tube is the source of the NMOS tube
  • the output terminal of the unidirectional conducting tube is the drain of the NMOS tube.
  • the above-mentioned first uni-conducting semiconductor transistor 2011, second uni-conducting semiconductor transistor 2012, third uni-conducting semiconductor transistor 2013, and fourth uni-conducting semiconductor transistor 2014 may all be PMOS transistors. , Or both can be NMOS tubes.
  • the first unidirectional conducting semiconductor transistor 2011, the second unidirectional conducting semiconductor transistor 2012, and the third unidirectional conducting semiconductor transistor in the embodiment of the present application are
  • the unidirectional conduction semiconductor tube 2013 and the fourth unidirectional conduction semiconductor tube 2014 may both be NMOS tubes.
  • the input terminal of each NMOS tube may be the source of the NMOS tube
  • the output terminal of each NMOS tube may be the NMOS tube.
  • first uni-conducting semiconductor tube 2011, second uni-conducting semi-conductor tube 2012, third uni-conducting semi-conductor tube 2013, and fourth uni-conducting semi-conductor tube 2014 The conducting semiconductor tube may be a PMOS tube, and the other part of the unidirectional conducting semiconductor tube may be an NMOS tube.
  • connection method in this implementation must meet the following connection rules: 1) When the PMOS tube is coupled to the NMOS tube, the source of the PMOS tube is coupled to the source of the NMOS tube or the drain of the PMOS tube is coupled To the drain of the NMOS transistor; 2) The terminal used for coupling to the second end is the source of the PMOS transistor or the drain of the NMOS transistor.
  • the tube can be a diode, and the other part of the uni-conducting semiconductor tube can be a MOS tube.
  • the input terminal of each diode may be the anode of the diode, and the output terminal of each diode may be the cathode of the diode.
  • each MOS tube must satisfy: the anode of the body diode of the MOS tube is used as the input terminal of the MOS tube, and the cathode of the body diode of the MOS tube is used as the output terminal of the MOS tube.
  • the input terminal of the unidirectional conductive tube is the drain of the PMOS tube, and the output terminal of the unidirectional conductive tube is the source of the PMOS tube.
  • the input terminal of the unidirectional conducting tube is the source of the NMOS tube
  • the output terminal of the unidirectional conducting tube is the drain of the NMOS tube.
  • the gate of each MOS transistor involved in the embodiments of the present application can be used as a control terminal to receive a control signal to control the turn-on or turn-off of the MOS transistor.
  • the control signal received by the gate of the above-mentioned NMOS tube 2012 is to control the NMOS tube to turn on, so that the current flows from The input terminal a flows to the output terminal b; when the output voltage of the output terminal of the NMOS tube 2012 is higher than its input voltage, the control signal is to control the NMOS tube to turn off to prevent the current from flowing back from the output terminal b.
  • To input a To input a.
  • the switchable capacitor unit 202 in the embodiment of the present application may be coupled to at least one of the first terminal a and the third terminal c, the second terminal b and the fourth terminal d.
  • the drawings in the embodiments of the present application all take the switchable capacitor unit 202 coupled to the third terminal c, the second terminal b, and the fourth terminal d as an example.
  • the above-mentioned switchable capacitor unit 202 may also be coupled to the first terminal a, the second terminal b, and the fourth terminal d.
  • the switchable capacitor unit 202 in the embodiment of the present application is used to switch the rectification mode of the conversion circuit 20 (ie, the rectifier), where the rectification mode may include, but is not limited to: a voltage double rectification mode and a full-bridge rectification mode.
  • the output voltage of the output terminal of the conversion circuit 20 may be n times the input voltage of the input terminal, where n is a real number greater than zero.
  • the difference between the output voltage of the output terminal of the conversion circuit 20 and the input voltage of the input terminal may be equal to the two single units in the signal conversion unit 201.
  • the conduction voltage drop of the conducting semiconductor tube Since the conduction voltage drop of the unidirectional conduction semiconductor tube is relatively small, in this mode, it can be considered that the output voltage of the output terminal of the conversion circuit 20 is equal to the input voltage of the input terminal.
  • the rectifier provided by the embodiment of the present application includes: a signal conversion unit 201 and a switchable capacitor unit 202 that are coupled to each other.
  • the switchable capacitor unit 202 is used to switch the rectification mode of the rectifier. Therefore, the embodiment of the present application
  • the output voltage of the provided rectifier has a large variable dynamic range.
  • the connection relationship of the signal conversion unit 201 may be as follows: the input end of the first unidirectional conducting semiconductor tube 2011 and the second unidirectional conducting semiconductor tube 2011 The output end of the semiconductor tube 2012 is coupled to the first end a. The input terminal of the second unidirectional conducting semiconductor tube 2012 and the input terminal of the third unidirectional conducting semiconductor tube 2013 are coupled to the second terminal b. The input terminal of the fourth unidirectional conducting semiconductor tube 2014 and the output terminal of the third unidirectional conducting semiconductor tube 2013 are coupled to the third terminal c. The output terminal of the first unidirectional conducting semiconductor tube 2011 and the output terminal of the fourth unidirectional conducting semiconductor tube 2014 are coupled to the fourth terminal d.
  • the fourth terminal d is used for coupling to a constant voltage, for example, the constant voltage may be a ground voltage.
  • the second terminal b and the fourth terminal d are the input terminals of the inverter, and the first terminal a and the third terminal c are the output terminals of the inverter, which are used to couple to the two terminals of the resonance circuit 14 end.
  • the above-mentioned first unidirectional conducting semiconductor tube 2011, second unidirectional conducting semiconducting tube 2012, third unidirectional conducting semiconducting tube 2013 and fourth unidirectional conducting semiconducting tube 2014 may all be metal-oxide-semiconductor MOS tube.
  • the connection direction of each MOS tube should satisfy: the cathode of the body diode of the MOS tube is used as the input terminal of the MOS tube, and the anode of the body diode of the MOS tube is used as the output terminal of the MOS tube.
  • any unidirectional conduction semiconductor tube is a PMOS tube
  • the input terminal of the unidirectional conduction tube is the source of the PMOS tube
  • the output terminal of the unidirectional conduction tube is the drain of the PMOS tube.
  • the input terminal of the unidirectional conducting tube is the drain of the NMOS tube
  • the output terminal of the unidirectional conducting tube is the source of the NMOS tube.
  • the above-mentioned first uni-conducting semiconductor transistor 2011, second uni-conducting semiconductor transistor 2012, third uni-conducting semiconductor transistor 2013, and fourth uni-conducting semiconductor transistor 2014 may all be PMOS transistors. Or, as shown in FIG. 2C, they can all be NMOS transistors. Correspondingly, the input end of each NMOS transistor can be the drain of the NMOS transistor, and the output end of each NMOS transistor can be the source of the NMOS transistor.
  • first uni-conducting semiconductor tube 2011, second uni-conducting semi-conductor tube 2012, third uni-conducting semi-conductor tube 2013, and fourth uni-conducting semi-conductor tube 2014 The semiconductor tube may be a PMOS tube, and the other part of the uni-conducting semiconductor tube may be an NMOS tube.
  • connection method in this example needs to meet the following connection rules: 1) When the PMOS tube is coupled to the NMOS tube, the source of the PMOS tube is coupled to the source of the NMOS tube, or the drain of the PMOS tube is coupled to The drain of the NMOS tube; 2) The terminal used for coupling to the second end is the source of the PMOS tube or the drain of the NMOS tube.
  • the gate of each MOS transistor involved in the embodiments of the present application can be used as a control terminal to receive a control signal to control the turn-on or turn-off of the MOS transistor, thereby controlling current to enter the output terminal of the MOS transistor .
  • the control signal received by the gate of the MOS tube is to control the turning off of the MOS tube, the current can be prevented from flowing through the MOS tube, so that unidirectional conduction can be realized.
  • the control signal received by the gate of the above-mentioned NMOS tube 2012 is to control the NMOS tube to turn on, so that the current flows from The input terminal b flows to the output terminal a; when the output voltage of the output terminal of the NMOS tube 2012 is higher than its input voltage, the above control signal controls the NMOS tube to be turned off to prevent the current from flowing back from the output terminal a.
  • the control signal controls the NMOS tube to be turned off to prevent the current from flowing back from the output terminal a.
  • the switchable capacitor unit 202 in the embodiment of the present application may be coupled to at least one of the first terminal a and the third terminal c, the second terminal b and the fourth terminal d.
  • the drawings in the embodiments of the present application all take the switchable capacitor unit 202 coupled to the third terminal c, the second terminal b, and the fourth terminal d as an example.
  • the above-mentioned switchable capacitor unit 202 may also be coupled to the first terminal a, the second terminal b, and the fourth terminal d.
  • the switchable capacitor unit 202 in the embodiment of the present application is used to switch the inverter mode of the conversion circuit 20 (that is, the inverter), where the inverter mode may include, but is not limited to: voltage division inverter mode, full-bridge inverter mode.
  • the difference between the output voltage of the output terminal of the conversion circuit 20 and the input voltage of the input terminal may be equal to the two single units in the signal conversion unit 201.
  • the conduction voltage drop of the conducting semiconductor tube Since the conduction voltage drop of the unidirectional conduction semiconductor tube is relatively small, in this mode, it can be considered that the output voltage of the output terminal of the conversion circuit 20 is equal to the input voltage of the input terminal.
  • the inverter provided by the embodiment of the present application includes: a signal conversion unit 201 and a switchable capacitor unit 202 that are coupled to each other.
  • the switchable capacitor unit 202 is used to switch the inverter mode of the inverter.
  • the variable dynamic range of the output voltage of the inverter provided by the embodiment of the present application is relatively large.
  • FIG. 3A is a fourth structural diagram of a conversion circuit provided by an embodiment of this application.
  • the embodiment of the present application introduces a possible implementation manner of the above-mentioned switchable capacitor unit 202.
  • the above-mentioned switchable capacitor unit 202 may include, but is not limited to: a first switch 202A and a capacitor unit 202B.
  • the first switch 202A is coupled between the third terminal c and the intermediate node e
  • the capacitor unit 202B is coupled between the second terminal b, the fourth terminal d, and the intermediate node e.
  • the on or off of the first switch 202A in the embodiment of the present application can switch the conversion mode of the conversion circuit 20.
  • the conversion circuit 20 is a rectifier and the first switch 202A is on, the conversion circuit 20 is in the voltage doubler rectification mode; or if the first switch 202A is off, the conversion circuit 20 is in The above-mentioned full bridge rectification mode.
  • the conversion circuit 20 is an inverter and the first switch 202A is turned on, the conversion circuit 20 is in the voltage divided inverter mode; or, if the first switch 202A is turned off, Then the conversion circuit 20 is in the full-bridge inverter mode.
  • the above-mentioned first switch 202A in the embodiment of the present application may be a mechanical switch, or may be a MOS tube, where the MOS tube may be a PMOS tube or an NMOS tube.
  • FIG. 3B is a fifth structural diagram of a conversion circuit provided by an embodiment of the application.
  • the source s of the NMOS transistor 1 may be coupled to the third terminal c, and the NMOS transistor The drain d of 1 is coupled to the aforementioned intermediate node e.
  • the gate g of the NMOS tube 1 is used to receive a control signal to control the turning on or off of the NMOS tube 1.
  • the source s of the NMOS transistor 1 may be coupled to the aforementioned intermediate node e, and the drain d of the NMOS transistor 1 is coupled to the aforementioned third terminal c (this method is not shown in the figure).
  • the source s of the PMOS transistor 1 may be coupled to the third terminal c, and the drain of the PMOS transistor 1 d is coupled to the above-mentioned intermediate node e.
  • the gate g of the PMOS tube 1 is used to receive a control signal to control the on or off of the PMOS tube 1.
  • the source s of the PMOS transistor 1 may be coupled to the intermediate node e, and the drain d of the PMOS transistor 1 is coupled to the third terminal c (this method is not shown in the figure).
  • FIG. 3C is a sixth structural diagram of a conversion circuit provided by an embodiment of the application.
  • the source s of the NMOS transistor 2 may be coupled to the third terminal c.
  • the drain d of the NMOS transistor 2 is coupled to the drain d of the NMOS transistor 3
  • the source s of the NMOS transistor 3 is coupled to the aforementioned intermediate node e.
  • drain d of the NMOS transistor 2 may be coupled to the aforementioned third terminal c
  • the source s of the NMOS transistor 2 is coupled to the source s of the NMOS transistor 3
  • the drain d of the NMOS transistor 3 is coupled to the aforementioned third terminal c.
  • Intermediate node e (not shown in the figure in this way).
  • the gate g of the NMOS tube 2 and the NMOS tube 3 are both used to receive control signals to control the turning on or turning off of the corresponding NMOS tube. Normally, the NMOS transistor 2 and the NMOS transistor 3 will be turned on or off at the same time under the control of a control signal, so that bidirectional anti-reverse flow can be realized. It should be understood that the above-mentioned NMOS tube 2 and NMOS tube 3 for implementing bidirectional anti-reverse flow can also be replaced by a MOS tube.
  • the first switch 202A may also include a PMOS transistor 2 and a PMOS transistor 3.
  • the source s of the PMOS transistor 2 may be coupled to the third terminal c, and the drain d of the PMOS transistor 2 is coupled to the PMOS transistor 3.
  • the drain d, the source s of the PMOS transistor 3 is coupled to the aforementioned intermediate node e (this method is not shown in the figure).
  • the drain d of the PMOS transistor 2 may be coupled to the aforementioned third terminal c
  • the source s of the PMOS transistor 2 is coupled to the source s of the PMOS transistor 3, and the drain d of the PMOS transistor 3 is coupled to the aforementioned third terminal c.
  • Intermediate node e (not shown in the figure in this way).
  • the above-mentioned first switch 202A may also include: a PMOS tube and an NMOS tube, the drain of the PMOS tube may be coupled to the third terminal c, the source of the PMOS tube is coupled to the drain of the NMOS tube, and The source of the NMOS transistor can be coupled to the aforementioned intermediate node e (this method is not shown in the figure).
  • the source of the PMOS tube may be coupled to the third terminal c
  • the drain of the PMOS tube may be coupled to the source of the NMOS tube
  • the drain of the NMOS tube may be coupled to the intermediate node e (in this way Not shown in).
  • the above-mentioned first switch 202A may also be another device with a switch function, which is not limited in the embodiment of the present application.
  • FIG. 3D is a schematic structural diagram 7 of the conversion circuit provided by an embodiment of the application.
  • the capacitor unit 202B may include, but is not limited to: a first capacitor C1 and a second capacitor C2.
  • the first capacitor C1 may be coupled between the intermediate node e and the second terminal b
  • the second capacitor C2 is coupled between the intermediate node e and the fourth terminal d.
  • the conversion circuit 20 is a rectifier
  • the first switch 202A is turned on
  • the unit 202B is located in the voltage doubler rectifier circuit.
  • the first switch 202A is turned off, the first unidirectional conductive semiconductor tube 2011, the second unidirectional conductive semiconductor tube 2012, the third unidirectional conductive semiconductor tube 2013, and the fourth unidirectional conductive semiconductor tube in the signal conversion unit 201 are turned off.
  • the conducting semiconductor tube 2014 and the aforementioned capacitor unit 202B are located in the full-bridge rectifier circuit.
  • the conversion circuit 20 is in the voltage doubler rectifier mode.
  • the first unidirectional conducting semiconductor tube 2011, the second unidirectional conducting semiconducting tube 2012, the third unidirectional conducting semiconducting tube 2013, the fourth unidirectional conducting semiconducting tube 2014, and the aforementioned capacitor unit 202B are located in a full-bridge rectifier circuit , The conversion circuit 20 is in the full-bridge rectification mode.
  • the conversion circuit 20 is an inverter, and the first switch 202A is turned on, the first unidirectional conducting semiconductor transistor 2011 and the second unidirectional conducting semiconductor transistor in the signal conversion unit 201 2012 and the aforementioned capacitor unit 202B are located in the voltage divider inverter circuit.
  • the first switch 202A is turned off, the first unidirectional conductive semiconductor tube 2011, the second unidirectional conductive semiconductor tube 2012, the third unidirectional conductive semiconductor tube 2013, and the fourth unidirectional conductive semiconductor tube in the signal conversion unit 201 are turned off.
  • the conducting semiconductor tube 2014 and the aforementioned capacitor unit 202B are located in the full-bridge inverter circuit.
  • the conversion circuit 20 is in the voltage divider inverter mode.
  • the conversion circuit 20 is in the full-bridge inverter mode.
  • FIG. 3E is the eighth structural diagram of the conversion circuit provided by the embodiment of the application.
  • the capacitor unit 202B further includes a third capacitor C3.
  • the third capacitor C3 is coupled between the second terminal b and the fourth terminal d.
  • the first capacitor C1, the second capacitor C2, and the third capacitor C3 in the foregoing embodiment of the present application may be used to store energy.
  • FIG. 3F is a schematic structural diagram 9 of the conversion circuit provided by an embodiment of the application.
  • the capacitor unit 202B may include, but is not limited to: a first capacitor C1 and a second capacitor C2.
  • the first capacitor C1 may be coupled between the aforementioned intermediate node e and the preset position
  • the second capacitor C2 is coupled between the aforementioned second terminal b and the fourth terminal d.
  • the foregoing preset position may include any one of the following: the foregoing second terminal b, the foregoing fourth terminal d, or a preset voltage.
  • the preset voltage may be a preset DC power supply, or a ground voltage.
  • the conversion circuit 20 is a rectifier
  • the first switch 202A is turned on
  • the unit 202B is located in the voltage doubler rectifier circuit.
  • the first switch 202A is turned off, the first unidirectional conductive semiconductor tube 2011, the second unidirectional conductive semiconductor tube 2012, the third unidirectional conductive semiconductor tube 2013, and the fourth unidirectional conductive semiconductor tube in the signal conversion unit 201 are turned off.
  • the conducting semiconductor tube 2014 and the aforementioned capacitor unit 202B are located in the full-bridge rectifier circuit.
  • the conversion circuit 20 is an inverter, and the first switch 202A is turned on, the first unidirectional conducting semiconductor transistor 2011 and the second uniconducting semiconductor transistor in the signal conversion unit 201 2012 and the aforementioned capacitor unit 202B are located in the voltage divider inverter circuit.
  • the first switch 202A is turned off, the first unidirectional conductive semiconductor tube 2011, the second unidirectional conductive semiconductor tube 2012, the third unidirectional conductive semiconductor tube 2013, and the fourth unidirectional conductive semiconductor tube in the signal conversion unit 201 are turned off.
  • the conducting semiconductor tube 2014 and the aforementioned capacitor unit 202B are located in the full-bridge inverter circuit.
  • FIG. 4A is a tenth structural diagram of a conversion circuit provided by an embodiment of the application.
  • the embodiment of the present application introduces another possible implementation manner of the above-mentioned switchable capacitor unit 202.
  • the above-mentioned switchable capacitor unit 202 may include, but is not limited to: a first switch 202A, a first capacitor C1, and a second capacitor C2.
  • the first capacitor C1 may be coupled between the third terminal c and the intermediate node e
  • the first switch 202A is coupled between the intermediate node e and a preset position
  • the second capacitor C2 is coupled between the second terminal b and the fourth terminal b. Between end d.
  • the on or off of the first switch 202A in the embodiment of the present application can switch the conversion mode of the conversion circuit 20.
  • the conversion circuit 20 is a rectifier and the first switch 202A is on, the conversion circuit 20 is in the voltage doubler rectification mode; or if the first switch 202A is off, the conversion circuit 20 is in The above-mentioned full bridge rectification mode.
  • the conversion circuit 20 is an inverter and the first switch 202A is turned on, the conversion circuit 20 is in the voltage divided inverter mode; or, if the first switch 202A is turned off, The conversion circuit 20 is in the full-bridge inverter mode.
  • the foregoing preset position may include any one of the following: the foregoing second terminal b, the foregoing fourth terminal d, or a preset voltage.
  • the preset voltage may be a preset DC power supply, or a ground voltage.
  • FIG. 4B is an eleventh structural diagram of a conversion circuit provided by an embodiment of this application. As shown in FIG. 4B, based on the embodiment shown in FIG. 4A, the first switch 202A may be coupled between the intermediate node e and the second terminal b.
  • FIG. 4C is a structural diagram twelfth of the conversion circuit provided by the embodiment of the application. As shown in FIG. 4C, based on the embodiment shown in FIG. 4A, the first switch 202A may be coupled between the intermediate node e and the fourth terminal d.
  • the conversion circuit 20 is a rectifier and the first switch 202A is turned on, the first unidirectional conductive semiconductor tube 2011 in the signal conversion unit 201 , The second unidirectional conducting semiconductor tube 2012, the first capacitor C1 and the second capacitor C2 are located in the voltage doubler rectifier circuit.
  • the first switch 202A is turned off, the first unidirectional conductive semiconductor tube 2011, the second unidirectional conductive semiconductor tube 2012, the third unidirectional conductive semiconductor tube 2013, and the fourth unidirectional conductive semiconductor tube in the signal conversion unit 201 are turned off.
  • the conducting semiconductor tube 2014 and the second capacitor C2 are located in the full-bridge rectifier circuit.
  • the conversion circuit 20 is in the voltage doubler rectifier mode.
  • the conversion circuit 20 is in the full-bridge rectifier mode.
  • the conversion circuit 20 is an inverter, and the first switch 202A is turned on, the first unidirectional conducting semiconductor transistor 2011 and the second unidirectional conducting semiconductor transistor in the signal conversion unit 201 2012.
  • the first capacitor C1 and the second capacitor C2 are located in the voltage divider inverter circuit.
  • the first switch 202A is turned off, the first unidirectional conductive semiconductor tube 2011, the second unidirectional conductive semiconductor tube 2012, the third unidirectional conductive semiconductor tube 2013, and the fourth unidirectional conductive semiconductor tube in the signal conversion unit 201 are turned off.
  • the conducting semiconductor tube 2014 and the second capacitor C2 are located in the full-bridge inverter circuit.
  • the conversion circuit 20 is in the above voltage dividing reverse circuit. Change mode. Or, if the above-mentioned first unidirectional conduction semiconductor tube 2011, the second unidirectional conduction semiconductor tube 2012, the third unidirectional conduction semiconductor tube 2013, the fourth unidirectional conduction semiconductor tube 2014, and the second capacitor C2 are located in the full-bridge inverter circuit , The conversion circuit 20 is in the full-bridge inverter mode.
  • the above-mentioned first switch 202A in the embodiment of the present application may be a mechanical switch, or may be a MOS tube, where the MOS tube may be a PMOS tube or an NMOS tube.
  • Fig. 4D is a thirteenth structural diagram of a conversion circuit provided by an embodiment of the application. As shown in FIG. 4D, based on any of the embodiments shown in FIGS. 4A to 4C, when the first switch 202A is an NMOS transistor 1, the source s of the NMOS transistor 1 may be coupled to the intermediate node e, The drain d of the NMOS tube 1 is coupled at the above-mentioned preset position.
  • the gate g of the NMOS tube 1 is used to receive a control signal to control the turning on or off of the NMOS tube 1. It should be understood that the source s of the NMOS transistor 1 can also be coupled to the aforementioned preset position, and the drain d of the NMOS transistor 1 is coupled to the aforementioned intermediate node e (this method is not shown in the figure).
  • the source s of the PMOS transistor 1 may be coupled to the intermediate node e, and the PMOS transistor 1
  • the drain d is coupled at the above-mentioned preset position.
  • the gate g of the PMOS tube 1 is used to receive a control signal to control the turning on or off of the NMOS tube 1.
  • the source s of the PMOS transistor 1 can be coupled to the aforementioned preset position, and the drain d of the PMOS transistor 1 is coupled to the aforementioned intermediate node e (this method is not shown in the figure).
  • FIG. 4E is a fourteenth structural diagram of a conversion circuit provided by an embodiment of this application.
  • the source s of the NMOS transistor 2 may be coupled to the foregoing
  • the drain d of the NMOS transistor 2 is coupled to the drain d of the NMOS transistor 3
  • the source s of the NMOS transistor 3 is coupled to the aforementioned preset position.
  • drain d of the NMOS transistor 2 may be coupled to the aforementioned intermediate node e
  • the source s of the NMOS transistor 2 is coupled to the source s of the NMOS transistor 3
  • the drain d of the NMOS transistor 3 is coupled to the aforementioned pre- Set the position (not shown in the figure in this way).
  • the gate g of the NMOS tube 2 and the NMOS tube 3 are both used to receive control signals to control the turning on or turning off of the corresponding NMOS tube. Normally, the NMOS transistor 2 and the NMOS transistor 3 will be turned on or off at the same time under the control of a control signal, so that bidirectional anti-reverse flow can be realized. It should be understood that the above-mentioned NMOS tube 2 and NMOS tube 3 for implementing bidirectional anti-reverse flow can also be replaced by a MOS tube.
  • the first switch 202A may also include a PMOS transistor 2 and a PMOS transistor 3.
  • the source s of the PNMOS transistor 2 may be coupled to the intermediate node e, and the drain d of the PMOS transistor 2 is coupled to the drain of the PMOS transistor 3. Pole d, the source s of the PMOS tube 3 is coupled at the aforementioned preset position.
  • the drain d of the PMOS transistor 2 may be coupled to the aforementioned intermediate node e
  • the source s of the PMOS transistor 2 is coupled to the source s of the PMOS transistor 3, and the drain d of the PMOS transistor 3 is coupled to the aforementioned pre- Set the position (not shown in the figure in this way).
  • the above-mentioned first switch 202A may also include: a PMOS tube and an NMOS tube, the drain of the PMOS tube may be coupled to the intermediate node e, the source of the PMOS tube is coupled to the drain of the NMOS tube, and the NMOS tube
  • the source of the tube can be coupled to the above-mentioned preset position (this way is not shown in the figure).
  • the source of the PMOS transistor can be coupled to the aforementioned intermediate node e
  • the drain of the PMOS transistor can be coupled to the source of the NMOS transistor
  • the drain of the NMOS transistor can be coupled to the aforementioned preset position (in this way Not shown).
  • the above-mentioned first switch 202A may also be another device with a switch function, which is not limited in the embodiment of the present application.
  • the above-mentioned switchable capacitor unit 202 may further include: a first switching unit and a second switching unit. Switch unit.
  • FIG. 5 is a fifteenth structural schematic diagram of a conversion circuit provided by an embodiment of the application.
  • the above-mentioned switchable capacitor unit 202 may further include: a first switching unit 202C and a second switching unit 202D.
  • the first switching unit 202C is coupled between the intermediate node e and the first terminal a, one end of the second switching unit 202D may be coupled to the fourth terminal d, and the other end of the second switching unit 202D may be coupled to the resonance circuit.
  • connection point between the coil and the resonant capacitor (not shown in the figure).
  • the conversion circuit 20 is an inverter and is provided in the wireless charging transmitter 1
  • the other end of the second switching unit 202D may be coupled between the transmitting coil 13 and the resonant capacitor 12 in the resonant circuit 14 ⁇ Connection points.
  • the conversion circuit 20 is a rectifier and is provided in the wireless charging receiver 2
  • the other end of the second switching unit 202D may be coupled to the connection between the receiving coil 23 and the resonant capacitor in the resonant circuit 24 point.
  • the above-mentioned first switching unit 202C may include, but is not limited to: a fifth unidirectional conducting semiconductor tube 202C1 and a second switch 202C2.
  • the second switch 202C2 may be coupled between the aforementioned intermediate node e and the input terminal of the fifth unidirectional conducting semiconductor tube 202C1, and the output terminal of the fifth unidirectional conducting semiconductor tube 202C1 is coupled to the aforementioned first terminal a. It should be understood that the positions of the second switch 202C2 and the fifth unidirectional conducting semiconductor tube 202C1 can be interchanged.
  • the input terminal of the fifth unidirectional conducting semiconductor tube 202C1 is coupled to the aforementioned intermediate node e, and the second switch 202C2 is coupled to the aforementioned first Between one end a and the output end of the fifth unidirectional conducting semiconductor tube 202C1 (this method is not shown in the figure).
  • the above-mentioned second switch 202C2 in the embodiment of the present application may be a mechanical switch, or may be a MOS tube, where the MOS tube may be a PMOS tube or an NMOS tube.
  • the second switch 202C2 is a MOS transistor, the source and drain of the MOS transistor are used as the two ends of the second switch 202C2 to be coupled to the intermediate node e and the input end of the fifth unidirectional semiconductor transistor 202C1, respectively.
  • the fifth unidirectional conductive semiconductor transistor 202C1 in the embodiment of the present application may be a diode or a MOS transistor, where the MOS transistor may be a PMOS transistor or an NMOS transistor.
  • the input terminal of the fifth uni-conducting semiconductor tube 202C1 may be the anode of the diode
  • the output terminal of the fifth uni-conducting semiconductor tube 202C1 may be The cathode of the diode.
  • the input terminal of the fifth unidirectional conducting semiconductor tube 202C1 may be the source of the MOS tube, and the output of the fifth unidirectional conducting semiconductor tube 202C1
  • the terminal may be the drain of the MOS transistor; or, the input terminal of the fifth uni-conducting semiconductor transistor 202C1 may be the drain of the MOS transistor, and the output terminal of the fifth uni-conducting semiconductor transistor 202C1 may be the source of the MOS transistor. pole.
  • which pole of the MOS transistor is the input terminal and/or output terminal of the fifth uni-conducting semiconductor transistor 202C1 can also be determined according to the type of the second switch 202C2 and the connection relationship between the two. For example, if the second switch 202C2 is an NMOS transistor 4, and the fifth uniconducting semiconductor transistor 202C1 is an NMOS transistor 5, the source of the NMOS transistor 4 may be coupled to the source of the NMOS transistor 5, or the NMOS transistor 5 The drain of the tube 4 is coupled to the drain of the NMOS tube 5.
  • the source of the PMOS transistor 4 may be coupled to the source of the PMOS transistor 5, or the The drain of the PMOS tube 4 is coupled to the drain of the PMOS tube 5.
  • the source of the MOS transistor can be coupled to the mechanical switch, or the drain of the MOS transistor is coupled to the Mechanical switch.
  • the fifth unidirectional conduction semiconductor transistor 202C1 is a PMOS transistor
  • the second switch 202C2 is an NMOS transistor
  • the source of the PMOS transistor may be coupled to the drain of the NMOS transistor, or the drain of the PMOS transistor The pole is coupled to the source of the NMOS tube.
  • the gate of the fifth uni-conducting semiconductor transistor 202C1 is used as a control terminal to receive a control signal to control the turning on or off of the fifth uni-conducting semiconductor transistor 202C1, and to avoid the fifth uni-conducting semiconductor transistor 202C1.
  • the semiconductor tube 202C1 conducts reversely.
  • the above-mentioned second switching unit 202D may include, but is not limited to: a sixth unidirectional conducting semiconductor tube 202D1 and a third switch 202D2.
  • the third switch 202D2 may be coupled between the fourth terminal d and the input terminal of the sixth unidirectional conducting semiconductor tube 202D1, and the output terminal of the sixth unidirectional conducting semiconductor tube 202D1 may be coupled to the coil in the resonant circuit.
  • the connection point between the vibration capacitors (not shown in the figure).
  • the conversion circuit 20 is an inverter and is provided in the wireless charging transmitter 1
  • the output terminal of the sixth unidirectional conducting semiconductor tube 202D1 can be coupled to the transmitting coil 13 and the resonant capacitor in the resonant circuit 14
  • the conversion circuit 20 is a rectifier and is provided in the wireless charging receiver 2
  • the output terminal of the sixth unidirectional semiconductor tube 202D1 can be coupled to one of the receiving coil 23 and the resonant capacitor in the resonant circuit 24. The connection point between.
  • the positions of the third switch 202D2 and the sixth one-way conducting semiconductor transistor 202D1 can be interchanged.
  • the input terminal of the sixth one-way conducting semiconductor transistor 202D1 is coupled to the fourth terminal d
  • the third switch 202D2 is coupled to the fourth terminal d.
  • the connection point between the output end of the six unidirectional conducting semiconductor tube 202D1 and the resonant circuit (this method is not shown in the figure).
  • the above-mentioned third switch 202D2 in the embodiment of the present application may be a mechanical switch, or may be a MOS tube, where the MOS tube may be a PMOS tube or an NMOS tube.
  • the third switch 202D2 is a MOS transistor
  • the source and drain of the MOS transistor serve as the two ends of the third switch 202D2 respectively coupled to the fourth terminal d and the input of the sixth uniconducting semiconductor transistor 202D1. end.
  • the source and drain of the MOS transistor as the two ends of the third switch 202D2 can be coupled to the output end of the sixth unidirectional semiconductor transistor 202D1 and the connection between the coil and the resonant capacitor in the resonant circuit. point.
  • the sixth uniconducting semiconductor transistor 202D1 in the embodiment of the present application may be a diode or a MOS transistor, where the MOS transistor may be a PMOS transistor or an NMOS transistor.
  • the input terminal of the sixth uniconducting semiconductor tube 202D1 may be the anode of the diode
  • the output terminal of the sixth uniconducting semiconductor tube 202D1 may be The cathode of the diode.
  • the input terminal of the sixth unidirectional conducting semiconductor transistor 202D1 may be the source of the MOS transistor, and the output of the sixth unidirectional conducting semiconductor transistor 202D1 The terminal may be the drain of the MOS transistor; or, the input terminal of the sixth unidirectional semiconductor transistor 202D1 may be the drain of the MOS transistor, and the output terminal of the sixth unidirectional semiconductor transistor 202D1 may be the source of the MOS transistor. pole.
  • pole of the MOS transistor is the input terminal and/or output terminal of the sixth unidirectional semiconductor transistor 202D1 can be determined according to the type of the third switch 202D2 and the connection relationship between the two. For example, if the third switch 202D2 is an NMOS transistor 6 and the sixth unidirectional semiconductor transistor 202D1 is an NMOS transistor 7, the source of the NMOS transistor 6 can be coupled to the source of the NMOS transistor 7, or the NMOS transistor The drain of 6 is coupled to the drain of the NMOS transistor 7.
  • the source of the PMOS transistor 6 may be coupled to the source of the PMOS transistor 7, or the PMOS transistor
  • the drain of the tube 6 is coupled to the drain of the PMOS tube 7.
  • the source of the MOS transistor can be coupled to the mechanical switch, or the drain of the MOS transistor is coupled to the Mechanical switch.
  • the sixth uniconducting semiconductor transistor 202D1 is a PMOS transistor
  • the third switch 202D2 is an NMOS transistor
  • the source of the PMOS transistor may be coupled to the drain of the NMOS transistor, or the drain of the PMOS transistor The pole is coupled to the source of the NMOS tube.
  • the gate of the sixth uni-conducting semiconductor transistor 202D1 is used as a control terminal to receive a control signal to control the turn-on or turn-off of the sixth uni-conducting semiconductor transistor 202D1, and to avoid the sixth uni-conducting transistor 202D1.
  • the semiconductor tube 202D1 conducts reversely. It should be understood that the positions of the sixth unidirectional conducting semiconductor tube 202D1 and the third switch 202D2 can be exchanged.
  • the fifth unidirectional conducting semiconductor tube 202C1 and the second switch 202C2 in the first switching unit 202C are turned on or off, and the sixth unidirectional conducting semiconductor tube 202D in the second switching unit 202D is turned on or off.
  • the conduction or disconnection of the tube 202D1 and the third switch 202D2, in conjunction with the conduction or disconnection of the first switch 202A, can switch the conversion mode of the conversion circuit 20.
  • the conversion circuit 20 is a rectifier
  • the first switch 202A is turned on, and the fifth unidirectional conductive semiconductor transistor 202C1 and/or the second switch 202C2 in the first switching unit 202C are turned off, and the second switch
  • the sixth unidirectional conductive semiconductor transistor 202D1 and/or the third switch 202D2 in the unit 202D are turned off, and the conversion circuit 20 is in the n1 voltage doubler rectification mode.
  • the conversion circuit 20 is an inverter
  • the first switch 202A is turned on, and the fifth unidirectional conductive semiconductor transistor 202C1 and/or the second switch 202C2 in the first switching unit 202C are turned off
  • the sixth unidirectional conducting semiconductor transistor 202D1 and/or the third switch 202D2 in the second switching unit 202D are turned off, and the conversion circuit 20 is in the above 1/n1 voltage division inverter mode.
  • the conversion circuit 20 is a rectifier, and the first switch 202A, the second switch 202C2 in the first switching unit 202C, and the third switch 202D2 in the second switching unit 202D are in a conducting state,
  • the conversion circuit 20 is in the above-mentioned n2 (for example, 3) voltage doubler rectification mode.
  • the conversion circuit 20 is an inverter, and the first switch 202A, the second switch 202C2 in the first switching unit 202C, and the third switch 202D2 in the second switching unit 202D are in a conducting state ,
  • the conversion circuit 20 is in the 1/n2 voltage division inverter mode.
  • the conduction voltage drop of the conducting semiconductor tube-the conduction voltage drop of the fifth unidirectional conducting semiconductor tube 202C1 and the second switch 202C2 in the above-mentioned first switching unit 202C-the sixth unidirectional conducting voltage of the above second switching unit 202D The conduction voltage drop of the semiconductor tube 202D1 and the third switch 202D2.
  • the conversion circuit 20 is a rectifier, and the first switch 202A is turned off, the fifth unidirectional conducting semiconductor transistor 202C1 and/or the second switch 202C2 in the first switching unit 202C are turned off, and The sixth unidirectional conducting semiconductor transistor 202D1 and/or the third switch 202D2 in the second switching unit 202D are turned off, and the conversion circuit 20 is in the full-bridge rectification mode.
  • the conversion circuit 20 is an inverter, and the first switch 202A is turned off, the fifth unidirectional conducting semiconductor transistor 202C1 and/or the second switch 202C2 in the first switching unit 202C are turned off , And the sixth unidirectional conducting semiconductor transistor 202D1 and/or the third switch 202D2 in the second switching unit 202D are turned off, and the conversion circuit 20 is in the full-bridge inverter mode.
  • the conversion circuit 20 provided by the embodiment of the present application can be turned on or off by the first switching unit 202C and the second switching unit 202D in conjunction with the on or off of the first switch 202A. More conversion modes of the conversion circuit 20 are switched. For example, if the conversion circuit 20 is a rectifier, the first switching unit 202C and the second switching unit 202D are turned on or off, and the above-mentioned first switch 202A is turned on or off to switch more of the rectifier. Rectification mode; or, if the conversion circuit 20 is an inverter, the first switching unit 202C and the second switching unit 202D can be switched on or off in conjunction with the on or off of the first switch 202A.
  • the inverter has more inverter modes. It can be seen that the dynamic range of the variable output voltage of the rectifier or inverter provided in the embodiments of the present application is further increased.
  • the above-mentioned switchable capacitor unit 202 can be implemented with reference to the above-mentioned embodiment based on the above-mentioned embodiment shown in FIG. 3D.
  • the related description of the switchable capacitor unit 202 mentioned above will not be repeated here.
  • FIG. 6A is a sixteenth structural diagram of a conversion circuit provided by an embodiment of this application.
  • the conversion circuit 20 is a rectifier, considering that the voltage at the input terminal of the conversion circuit 20 may be small in individual cases, in order not to affect the switching of the rectification mode of the conversion circuit 20, the conversion circuit 20 provided in the embodiment of the present application may also Including: auxiliary boost circuit.
  • the conversion circuit 20 further includes an auxiliary boost circuit 203.
  • the auxiliary boost circuit 203 may be coupled between the first terminal a and the second terminal b, and the output terminal O of the auxiliary boost circuit 203 may be used for coupling to the controller.
  • the auxiliary boost circuit 203 is used to boost the voltage of the first terminal a, so that the boosted voltage meets the starting voltage of the controller, so that the controller can generate and control the aforementioned
  • the switching signal of the capacitor unit 202 can be switched, and the control signal used to control each unidirectional conductive semiconductor tube in the signal conversion unit 201, so as to switch the rectification mode of the conversion circuit 20.
  • the specific control process of the controller refer to the related description of the controller in the subsequent FIG. 7A or FIG. 7B.
  • FIG. 6B is a seventeenth structural diagram of a conversion circuit provided by an embodiment of this application.
  • the embodiment of the present application introduces the realization of the above-mentioned auxiliary boost circuit 203.
  • the auxiliary boost circuit 203 may include, but is not limited to: a first diode D1, a second diode D2, a fourth capacitor C4, and a fifth capacitor C5.
  • the input terminal of the first diode D1 is coupled to the second terminal b, the input terminal of the second diode D2 and the first terminal of the fourth capacitor C4 are coupled to the output terminal of the first diode D1,
  • the second terminal of the four capacitor C4 is coupled to the first terminal a, the output terminal of the second diode D2 and the first terminal of the fifth capacitor C5 are coupled to the output terminal O, and the second terminal of the fifth capacitor C5 is grounded.
  • the auxiliary boost circuit 203 provided by the embodiment of the present application, in the first half cycle, when the voltage of the first terminal a is less than the voltage of the third terminal c, the third unidirectional conducting semiconductor tube 2013 and the first diode D1 charge the fourth capacitor C4 so that the voltage at the upper end of the fourth capacitor C4 is approximately equal to the voltage between the first terminal a and the third terminal c; in the second half cycle, when the voltage at the third terminal c When the voltage is less than the first terminal a, the fifth capacitor C5 is charged through the fourth capacitor C4 and the second diode D2.
  • the voltage at the upper end of the fifth capacitor C5 (that is, the above-mentioned output terminal O) is approximately equal to the voltage between the first terminal a and the third terminal c and the fourth terminal The sum of the voltages across capacitor C4. It can be seen that the voltage at the output terminal O may be approximately equal to twice the voltage at the first terminal a, so as to meet the starting voltage of the controller.
  • the auxiliary boost circuit 203 can increase the voltage of the output terminal O, so as to meet the starting voltage of the controller and improve the degree of freedom in the Ping phase.
  • the degree of freedom involved in the embodiments of the present application refers to the positional relationship between the wireless charging transmitter and the wireless charging receiver, including horizontal and spatial distance.
  • the above-mentioned wireless charging device is used to receive wireless charging signals, and the above-mentioned wireless charging device is the above-mentioned wireless charging receiver 2.
  • the wireless charging receiver 2 may include, but is not limited to: a resonance circuit 24 and a rectifier. twenty one.
  • the conversion circuit 20 shown in FIG. 2A is the foregoing rectifier 21, and the resonant circuit 24 includes the receiving coil 23 and the resonant capacitor 22 as an example.
  • the example provides an introduction to the implementation of the wireless charging device.
  • FIG. 7A is a first structural diagram of a wireless charging device provided by an embodiment of the application.
  • the wireless charging device 70 provided by an embodiment of the present application may include, but is not limited to: the above-mentioned resonance circuit 24, the above-mentioned rectifier 21, and a controller. 701 and a charging management unit 702.
  • the controller 701 is coupled to the above-mentioned rectifier 21 for controlling the signal conversion unit 201 and the switchable capacitor unit 202 in the above-mentioned rectifier 21.
  • the controller 701 may be connected to the gate of the unidirectional conducting semiconductor tube in the signal conversion unit 201 and to the switch in the switchable capacitor unit 202 and the gate of the unidirectional conducting semiconductor tube.
  • the first terminal a and the third terminal c of the above-mentioned rectifier 21 are respectively coupled to the two ends of the resonance circuit 24 as input terminals, and are used to receive the electromagnetic signal obtained by converting the electromagnetic signal received from the transmitting coil of the opposite terminal by the resonance circuit 24. electric signal.
  • the second terminal b and the fourth terminal d of the rectifier 21 are the output terminals of the rectifier 21, which are used for coupling to the charging management unit 702, and are used for voltage conversion (for example, step-down) of the output voltage of the output terminal of the rectifier 21. Processing, etc.) to match the storage voltage of the subsequent power storage unit.
  • the electrical energy storage unit may include, but is not limited to: a battery. It should be noted that the electric energy storage unit may belong to the wireless charging device 70 or belong to an electronic device connected to the wireless charging device 70.
  • the inductance value of the receiving coil 23 in the resonant circuit 24 in the embodiment of the present application is smaller than the inductance value of the standard receiving coil, which can reduce the resistance of the receiving coil and reduce the Heat consumption, thereby improving the current flow capacity of the receiving coil.
  • WPC Wireless Power Consortium
  • the voltage requirements for the coupling of the standard receiving coil are as follows : In the ping phase, the coupled voltage must be greater than 2.7V, so that the chip of the wireless charging device can be normally powered on; at the beginning of the power transmission phase, the coupled voltage must be greater than 5V in order to charge the subsequent device.
  • the inductance value of the receiving coil in the embodiment of the present application may be 1/(n ⁇ 2) of the inductance value of the standard receiving coil.
  • the above-mentioned controller 701 is used to control the switchable capacitor unit 202 in the above-mentioned rectifier 21 to switch the rectification mode of the rectifier 21; wherein, the rectification mode includes: the above-mentioned voltage doubler rectification mode or the above-mentioned full-bridge rectification mode. It should be understood that the controller 701 is also used to control the turning on or turning off of the unidirectional conductive semiconductor tubes in the signal conversion unit 201.
  • the controller 701 can switch the rectification mode of the rectifier 21 by controlling the unidirectional conducting semiconductor tube and/or the switch in the switchable capacitor unit 202 to be turned on or off.
  • the above-mentioned controller 701 is configured to control the above-mentioned switchable capacitor unit according to the wireless charging operation status information of the device 70 to switch the rectification mode of the rectifier 21.
  • the controller 701 is configured to control the switchable capacitor unit according to the preset voltage threshold and the preset terminal voltage to The rectification mode of the rectifier 21 is switched.
  • the preset terminal voltage may include but is not limited to: the input voltage of the input terminal of the rectifier 21 or the output voltage of the output terminal of the rectifier 21.
  • the controller 701 is used to control the conduction or conduction of the unidirectional conducting semiconductor transistor and/or the switch in the switchable capacitor unit 202. Turning off makes the rectifier 21 in the voltage doubler rectification mode, so that the output voltage of the output terminal of the rectifier 21 can be greater than the input voltage of the input terminal, so that the device 70 can supply power to the downstream device.
  • the controller 701 is used to control the conduction or conduction of the unidirectional conducting semiconductor transistor and/or the switch in the switchable capacitor unit 202. Turning off makes the rectifier 21 in a full-bridge rectification mode, so that the output voltage of the output terminal of the rectifier 21 is almost equal to the input voltage of its input terminal.
  • the controller 701 is configured to control the switchable capacitor unit according to the charging mode of the device 70 to switch the conversion circuit 20 rectifier mode.
  • the charging mode of the device 70 may include, but is not limited to: Extended Power Profile (EPP) mode, Baseline Power Profile (BPP) mode, or private fast charge mode
  • the above control The rectifier 701 is configured to control the above-mentioned switchable capacitor unit according to the above-mentioned preset voltage threshold and the above-mentioned preset terminal voltage to switch the rectification mode of the rectifier 21, so as to ensure the stability of the output voltage of the device.
  • the device 70 provided in the embodiment of the present application can adjust the output voltage of the device 70 by switching the rectification mode of the rectifier 21 to meet the power supply demand.
  • the wireless charging device involved in the embodiment of the present application is used to send a wireless charging signal
  • the above-mentioned wireless charging device is the above-mentioned wireless charging transmitter 1, where the wireless charging transmitter 1 may include but not Limited to: inverter 11 and resonance circuit 14.
  • the conversion circuit 20 shown in FIG. 2A is the inverter 11, and the resonant circuit 14 includes the transmitting coil 13 and the resonant capacitor 12 as an example.
  • the implementation of the wireless charging device provided by the embodiment is introduced.
  • FIG. 7B is the second structural diagram of the wireless charging device provided by the embodiment of the application.
  • the wireless charging device 80 provided by the embodiment of the application may include, but is not limited to: the above-mentioned resonance circuit 14, the above-mentioned inverter 11, and Controller 801.
  • the controller 801 is coupled to the inverter 11 to control the signal conversion unit 201 and the switchable capacitor unit 202 in the inverter 11.
  • the controller 801 may be connected to the gate of the unidirectional conducting semiconductor tube in the signal conversion unit 201, and to the switch in the switchable capacitor unit 202 and the gate of the unidirectional conducting semiconductor tube.
  • the second terminal b and the fourth terminal d of the above-mentioned inverter 11 are the input terminals of the inverter 11.
  • the first terminal a and the third terminal c in the inverter 11 are respectively coupled to both ends of the resonance circuit 14 as output terminals, so that the resonance circuit 14 can convert the electrical signal output by the inverter 11 into an electromagnetic signal. Transmit the electromagnetic signal.
  • the controller 801 is used to control the switchable capacitor unit 202 in the inverter 11 to switch the inverter mode of the inverter 11; wherein, the inverter mode includes: Variable mode, or the above-mentioned full-bridge inverter mode. It should be understood that the controller 801 is also used to control the turning on or turning off of the unidirectional conductive semiconductor tubes in the signal conversion unit 201. Specifically, the controller 801 controls the on or off of the unidirectional conducting semiconductor tube and/or the switch in the switchable capacitor unit 202 to switch the inverter mode of the inverter 11.
  • the above-mentioned controller 801 is configured to control the above-mentioned switchable capacitor unit according to the wireless charging operation status information of the device 80 to switch the inverter mode of the inverter 11.
  • the controller 801 is configured to control the switchable capacitor unit according to the preset voltage threshold and the preset terminal voltage.
  • the preset terminal voltage may include but is not limited to: the input voltage of the input terminal of the inverter 11 or the output voltage of the output terminal of the inverter 11.
  • the controller 801 is used to control the on or off of the unidirectional conducting semiconductor transistor and/or the switch in the switchable capacitor unit 202 , So that the inverter 11 is in the voltage-divided inverter mode, so that the output voltage of the output terminal of the inverter 11 can be less than the input voltage of its input terminal, so as to ensure that the receiving coil of the receiving terminal can be coupled to the predetermined coupling voltage range. Voltage.
  • the controller 801 is used to control the conduction of the unidirectional conducting semiconductor transistor and/or the switch in the switchable capacitor unit 202 Or turn off, so that the inverter 11 is in the full-bridge inverter mode, so that the output voltage of the output terminal of the inverter 11 is almost equal to the input voltage of its input terminal, so as to ensure that the receiving coil of the receiving terminal can be coupled to meet the preset coupling The voltage of the voltage range.
  • the above-mentioned controller 801 can also control the above-mentioned switchable capacitor unit in other achievable manners according to the wireless charging operation status information of the device 80 to switch the inverter mode of the inverter 11.
  • the device 80 provided in the embodiment of the present application can adjust the output voltage of the device 80 by switching the inverter mode of the inverter 11 to meet the voltage required to be coupled to the receiving coil at the receiving end.

Abstract

本申请提供一种整流器、逆变器及无线充电设备，该整流器包括：相互耦合连接的信号变换单元和可切换电容单元，其中，可切换电容单元用于切换该整流器的整流模式，该整流模式可以包括但不限于以下任一项：倍压整流模式、全桥整流模式，因此，本申请实施例提供的整流器的输出电压可变的动态范围较大。

Description

整流器、逆变器及无线充电设备 技术领域
本申请涉及无线充电技术领域，尤其涉及一种整流器、逆变器及无线充电设备。
背景技术
随着无线充电技术的发展，无线充电技术越来越多地应用于不同电子产品。无线充电技术是指充电器与用电设备之间以磁场传送电能，两者之间不需要电线连接，即可实现为用户设备进行充电的技术。
在相关技术中，无线充电接收器中通常包括：谐振电路和整流电路。其中，谐振电路用于对从无线充电发射器获得的电磁信号进行转换，整流电路用于对谐振电路输出的信号进行整流，且整流电路运行在全桥整流模式，即整流电路的输出端的输出电压约等于其输入端的输入电压。
类似地，无线充电发射器中通常包括：谐振电路和逆变电路。其中，谐振电路用于对逆变电路输出的信号转换成电磁信号，逆变电路用于对输入的信号进行逆变处理以供谐振电路发射电磁信号，且逆变电路运行在全桥逆变模式，即逆变电路的输出端的输出电压约等于其输入端的输入电压。
可见，相关技术中的无线充电接收器中的整流电路，或者无线充电发射器中的逆变电路的输出电压均约等于其输入电压，可变的动态范围较小。
发明内容
本申请提供一种整流器、逆变器及无线充电设备，解决了相关技术中的无线充电接收器中的整流电路，或者无线充电发射器中的逆变电路的输出电压可变的动态范围较小的技术问题。
第一方面，本申请实施例提供一种整流器，包括：信号变换单元和可切换电容单元；该信号变换单元包括第一端、第二端、第三端、第四端、第一单向导通半导体管、第二单向导通半导体极管、第三单向导通半导体管和第四单向导通半导体管。该第一单向导通半导体管的输出端与该第二单向导通半导体管的输入端耦合至该第一端，该第二单向导通半导体管的输出端与该第三单向导通半导体管的输出端耦合至第二端，该第四单向导通半导体管的输出端与该第三单向导通半导体管的输入端耦合至该第三端，该第一单向导通半导体管的输入端和该第四单向导通半导体管的输入端耦合至该第四端，该第一端和该第三端用于耦合至谐振电路，该第四端用于耦合至恒定电压。该可切换电容单元，耦合在该第一端和该第三端中的至少一个、该第二端和该第四端。其中，该第一端和该第三端是该整流器的输入端，该第二端和该第四端是该整流器的输出端；该恒定电压可以是接地电压。
本申请实施例中的可切换电容单元用于切换上述整流器的整流模式，其中，该整流模式可以包括但不限于：倍压整流模式、全桥整流模式。
示例性地，上述第一单向导通半导体管、第二单向导通半导体极管、第三单向导通半导体管和第四单向导通半导体管可以均是二极管，对应地，每个二极管的输入端可以是该二极管的阳极，每个二极管的输出端可以是该二极管的阴极。
又一示例性地，上述第一单向导通半导体管、第二单向导通半导体极管、第三单向导通半导体管和第四单向导通半导体管可以均是金属-氧化物-半导体MOS管。其中，每个MOS管的连接方向要满足：该MOS管的体二极管的阳极作为该MOS管的输入端，该MOS管的体二极管的阴极作为该MOS管的输出端。例如，若任意单向导通半导体管是PMOS管，则该单向导通半导体管的输入端是该PMOS管的漏极，该单向导通半导体管的输出端是该PMOS管的源极。或者，若任意单向导通半导体管是NMOS管，则该单向导通半导体管的输入端是该NMOS管的源极，该单向导通半导体管的输出端是该NMOS管的漏极。
在一种实例中，上述第一单向导通半导体管、第二单向导通半导体极管、第三单向导通半导体管和第四单向导通半导体管可以均是PMOS管，或者可以均是NMOS管。
在另一种实例中，上述第一单向导通半导体管、第二单向导通半导体极管、第三单向导通半导体管和第四单向导通半导体管中的部分单向导通半导体管可以是PMOS管，另一部分单向导通半导体管可以是NMOS管。需要说明的是，此实例中的连接方式需满足如下连接规则：1)当PMOS管与NMOS管耦合连接时，PMOS管的源极耦合到NMOS管的源极，或者PMOS管的漏极耦合到NMOS管的漏极；2)用于耦合连接到上述第二端的端点是PMOS管的源极或者NMOS管的漏极。
又一示例性地，上述第一单向导通半导体管、第二单向导通半导体极管、第三单向导通半导体管和第四单向导通半导体管中的部分单向导通半导体管可以是二极管，另一部分单向导通半导体管可以是MOS管。其中，每个二极管的输入端可以是该二极管的阳极，每个二极管的输出端可以是该二极管的阴极。每个MOS管的连接方向要满足：该MOS管的体二极管的阳极作为该MOS管的输入端，该MOS管的体二极管的阴极作为该MOS管的输出端。例如，若任意单向导通半导体管是PMOS管，则该单向导通半导体管的输入端是该PMOS管的漏极，该单向导通半导体管的输出端是该PMOS管的源极。或者，若任意单向导通半导体管是NMOS管，则该单向导通半导体管的输入端是该NMOS管的源极，该单向导通半导体管的输出端是该NMOS管的漏极。
另外，每个MOS管的的栅极可以作为控制端用于接收控制信号以控制该MOS管的导通或关断，从而控制电流进入该MOS管的输出端。
本申请实施例提供的整流器，包括：相互耦合连接的信号变换单元和可切换电容单元，其中，可切换电容单元用于切换该整流器的整流模式，因此，本申请实施例提供的整流器的输出电压可变的动态范围较大。
在一种可能的实现方式中，该可切换电容单元包括第一开关和电容单元，该第一开关耦合在该第三端和中间节点之间，该电容单元耦合在该第二端、该第四端和该中间节点。
在一种可能的实现方式中，该电容单元包括：第一电容和第二电容，该第一电容耦合在该中间节点和该第二端之间，该第二电容耦合在该中间节点和该第四端之间。
在一种可能的实现方式中，该电容单元还包括：第三电容，该第三电容耦合在该第二 端和该第四端之间。
在一种可能的实现方式中，该电容单元包括：第一电容和第二电容，该第一电容耦合在该中间节点和预设位置之间，该第二电容耦合在该第二端和该第四端之间。示例性地，该预设位置包括以下任一项：该第二端、该第四端、或预设电压。
在一种可能的实现方式中，该可切换电容单元包括第一开关、第一电容和第二电容，该第一电容耦合在该第三端和中间节点之间，该第一开关耦合在该中间节点和预设位置之间，该第二电容耦合在该第二端和该第四端之间。示例性地，该预设位置包括以下任一项：该第二端、该第四端、或预设电压。
在一种可能的实现方式中，该可切换电容单元还包括：第一切换单元和第二切换单元，该第一切换单元耦合在该中间节点和该第一端之间，该第二切换单元耦合在该第四端和该谐振电路之间。
本实现方式中，上述第一切换单元和第二切换单元的导通或断开，配合上述第一开关的导通或断开，可以切换整流器的整流模式。
在一种可能的实现方式中，该第一切换单元包括：第五单向导通半导体管和第二开关；该第二开关耦合在该中间节点和该第五单向导通半导体管的输入端之间，该第五单向导通半导体管的输出端耦合在该第一端；或者，该第五单向导通半导体管的输入端耦合在该中间节点，该第二开关耦合在该第一端和该第五单向导通半导体管的输出端之间。
示例性地，上述第二开关可以为机械开关，或者为MOS管；和/或，上述第五单向导通半导体管可以为二极管，或者MOS管；其中，该MOS管可以是PMOS管或NMOS管。
在一种可能的实现方式中，该第二切换单元包括：第六单向导通半导体管和第三开关；该第三开关耦合在该第四端和该第六单向导通半导体管的输入端之间，该第六单向导通半导体管的输出端耦合在该谐振电路；或者，该第六单向导通半导体管的输入端耦合在该第四端，该第三开关耦合在该第六单向导通半导体管的输出端和该谐振电路之间。
示例性地，上述第三开关可以为机械开关，或者为MOS管；和/或，上述第六单向导通半导体管可以为二极管，或者MOS管；其中，该MOS管可以是PMOS管或NMOS管。
在一种实例中，若上述第一开关导通，且第一切换单元和第二切换单元均断开，上述整流器处于n1倍压整流模式，其中，n1为大于0的实数。
在另一种实例中，若上述第一开关、第一切换单元中的第二开关和第二切换单元中的第三开关处于导通状态，上述整流器处于n2倍压整流模式，其中，n2为大于0的实数，且n2大于n1。
在另一种实例中，若上述上述第一开关、第一切换单元和第二切换单元均断开，上述整流器处于上述全桥整流模式。
上述实施例中提供的整流器，通过其中的第一切换单元和第二切换单元的导通或断开，配合上述第一开关的导通或断开，可以切换该整流器更多的整流模式。可见，本申请实施例提供的整流器的输出电压可变的动态范围进一步增大了。
在一种可能的实现方式中，还包括：辅助升压电路，该辅助升压电路耦合在该第一端和该第二端之间，用于对该第一端的电压进行升压处理，使得升压处理后的电压满足控制器的启动电压，以便于该控制器可以控制上述可切换电容单元，以切换上述整流器的整流模式。
第二方面，本申请实施例提供一种无线充电设备，该设备用于接收无线充电信号，该设备包括：如上述第一方面的任意实现方式所述的整流器和谐振电路。
在一种可能的实现方式中，该设备还包括：控制器，用于控制该可切换电容单元，以切换该整流器的整流模式；其中，该整流模式包括：倍压整流模式，或者全桥整流模式；该倍压整流模式包括上述n1倍压整流模式，或者n2倍压整流模式。
应理解，该控制器还用于控制上述信号变换单元中的各单向导通半导体管的导通或关断。
本实现方式提供的设备，通过切换上述整流器的整流模式，可以调整该设备的输出电压，以满足供电需求。
在一种可能的实现方式中，该设备还包括：耦合在该第二端和该第四端之间的充电管理单元，用于将该整流器的输出端的输出电压进行电压转换，以匹配电能存储单元的存储电压。
第三方面，本申请实施例提供一种逆变器，包括：信号变换单元和可切换电容单元；所述信号变换单元包括第一端、第二端、第三端、第四端、第一单向导通半导体管、第二单向导通半导体极管、第三单向导通半导体管和第四单向导通半导体管。该第一单向导通半导体管的输入端与该第二单向导通半导体管的输出端耦合至该第一端，该第二单向导通半导体管的输入端与该第三单向导通半导体管的输入端耦合至第二端，该第四单向导通半导体管的输入端与该第三单向导通半导体管的输出端耦合至该第三端，该第一单向导通半导体管的输出端和该第四单向导通半导体管的输出端耦合至该第四端，该第一端和该第三端用于耦合至谐振电路，该第四端用于耦合至恒定电压。该可切换电容单元，耦合在该第一端和该第三端中的至少一个、该第二端和该第四端；其中，该第一端和该第三端是该逆变器的输出端，该第二端和该第四端是该逆变器的输入端；该恒定电压可以是接地电压。
本申请实施例中的可切换电容单元用于切换上述逆变器的逆变模式，其中，该逆变模式可以包括但不限于：分压逆变模式、全桥逆变模式。
示例性地，上述第一单向导通半导体管、第二单向导通半导体极管、第三单向导通半导体管和第四单向导通半导体管可以均是金属-氧化物-半导体MOS管。其中，每个MOS管的连接方向要满足：该MOS管的体二极管的阴极作为该MOS管的输入端，该MOS管的体二极管的阳极作为该MOS管的输出端。例如，若任意单向导通半导体管是PMOS管，则该单向导通半导体管的输入端是该PMOS管的源极，该单向导通半导体管的输出端是该PMOS管的漏极。或者，若任意单向导通半导体管是NMOS管，则该单向导通半导体管的输入端是该NMOS管的漏极，该单向导通半导体管的输出端是该NMOS管的源极。
在一种实例中，上述第一单向导通半导体管、第二单向导通半导体极管、第三单向导通半导体管和第四单向导通半导体管可以均是PMOS管，或者可以均是NMOS管。
在另一种实例中，上述第一单向导通半导体管、第二单向导通半导体极管、第三单向导通半导体管和第四单向导通半导体管中的部分单向导通半导体管可以是PMOS管，另一部分单向导通半导体管可以是NMOS管。需要说明的是，此实例中的连接方式需满足如下连接规则：1)当PMOS管与NMOS管耦合连接时，PMOS管的源极耦合到NMOS管的源极，或者PMOS管的漏极耦合到NMOS管的漏极；2)用于耦合连接到上述第二端的端点是PMOS管的源极或者NMOS管的漏极。
另外，每个MOS管的的栅极可以作为控制端用于接收控制信号以控制该MOS管的导通或关断，从而控制电流进入该MOS管的输出端。
本申请实施例提供的逆变器，包括：相互耦合连接的信号变换单元和可切换电容单元，其中，可切换电容单元用于切换该逆变器的逆变模式，因此，本申请实施例提供的逆变器的输出电压可变的动态范围较大。
在一种可能的实现方式中，该可切换电容单元包括第一开关和电容单元，该第一开关耦合在该第三端和中间节点之间，该电容单元耦合在该第二端、该第四端和该中间节点。
在一种可能的实现方式中，该电容单元包括：第一电容和第二电容，该第一电容耦合在该中间节点和该第二端之间，该第二电容耦合在该中间节点和该第四端之间。
在一种可能的实现方式中，该电容单元还包括：第三电容，该第三电容耦合在该第二端和该第四端之间。
在一种可能的实现方式中，该电容单元包括：第一电容和第二电容，该第一电容耦合在该中间节点和预设位置之间，该第二电容耦合在该第二端和该第四端之间。示例性地，该预设位置包括以下任一项：该第二端、该第四端、或预设电压。
在一种可能的实现方式中，该可切换电容单元包括第一开关、第一电容和第二电容，该第一电容耦合在该第三端和中间节点之间，该第一开关耦合在该中间节点和预设位置之间，该第二电容耦合在该第二端和该第四端之间。示例性地，该预设位置包括以下任一项：该第二端、该第四端、或预设电压。
在一种可能的实现方式中，该可切换电容单元还包括：第一切换单元和第二切换单元，该第一切换单元耦合在该中间节点和该第一端之间，该第二切换单元耦合在该第四端和该谐振电路之间。
本实现方式中，上述第一切换单元和第二切换单元的导通或断开，配合上述第一开关的导通或断开，可以切换逆变器的逆变模式。
在一种可能的实现方式中，该第一切换单元包括：第五单向导通半导体管和第二开关；该第二开关耦合在该中间节点和该第五单向导通半导体管的输入端之间，该第五单向导通半导体管的输出端耦合在该第一端；或者，该第五单向导通半导体管的输入端耦合在该中间节点，该第二开关耦合在该第一端和该第五单向导通半导体管的输出端之间。
示例性地，上述第二开关可以为机械开关，或者为MOS管；和/或，上述第五单向导通半导体管可以为二极管，或者MOS管；其中，该MOS管可以是PMOS管或NMOS管。
在一种可能的实现方式中，该第二切换单元包括：第六单向导通半导体管和第三开关；该第三开关耦合在该第四端和该第六单向导通半导体管的输入端之间，该第六单向导通半导体管的输出端耦合在该谐振电路；或者，该第六单向导通半导体管的输入端耦合在该第四端，该第三开关耦合在该第六单向导通半导体管的输出端和该谐振电路之间。
示例性地，上述第三开关可以为机械开关，或者为MOS管；和/或，上述第六单向导通半导体管可以为二极管，或者MOS管；其中，该MOS管可以是PMOS管或NMOS管。
在一种实例中，若上述第一开关导通，且第一切换单元和第二切换单元均断开时，上述逆变器处于1/n1分压逆变模式，其中，n1为大于0的实数。
在另一种实例中，若上述第一开关、第一切换单元中的第二开关和第二切换单元中的第三开关处于导通状态，上述逆变器处于1/n2分压逆变模式，其中，n2为大于0的实数， 且n2大于n1。
在另一种实例中，若上述第一开关、第一切换单元和第二切换单元均断开，上述逆变器处于上述全桥逆变模式。
上述实施例中提供的逆变器，通过其中的第一切换单元和第二切换单元的导通或断开，配合上述第一开关的导通或断开，可以切换该逆变器更多的逆变模式。可见，本申请实施例提供的逆变器的输出电压可变的动态范围进一步增大了。
第四方面，本申请实施例提供一种无线充电设备，该设备用于发送无线充电信号，该设备包括：如上述第三方面的任意实现方式所述的逆变器和谐振电路。
在一种可能的实现方式中，该设备还包括：控制器，用于控制该可切换电容单元，以切换该逆变器的逆变模式；其中，该逆变模式包括：分压逆变模式，或者全桥逆变模式；该分压逆变模式包括上述1/n1分压逆变模式，或者1/n2分压逆变模式。
应理解，该控制器还用于控制上述信号变换单元中的各单向导通半导体管的导通或关断。
本实现方式提供的设备，通过切换上述逆变器的逆变模式，可以调整该设备的输出电压，以满足接收端的接收线圈所需耦合的电压。
附图说明
图1为本申请实施例提供的系统架构示意图；
图2A为本申请实施例提供的变换电路的结构示意图一；
图2B为本申请实施例提供的变换电路的结构示意图二；
图2C为本申请实施例提供的变换电路的结构示意图三；
图3A为本申请实施例提供的变换电路的结构示意图四；
图3B为本申请实施例提供的变换电路的结构示意图五；
图3C为本申请实施例提供的变换电路的结构示意图六；
图3D为本申请实施例提供的变换电路的结构示意图七；
图3E为本申请实施例提供的变换电路的结构示意图八；
图3F为本申请实施例提供的变换电路的结构示意图九；
图4A为本申请实施例提供的变换电路的结构示意图十；
图4B为本申请实施例提供的变换电路的结构示意图十一；
图4C为本申请实施例提供的变换电路的结构示意图十二；
图4D为本申请实施例提供的变换电路的结构示意图十三；
图4E为本申请实施例提供的变换电路的结构示意图十四；
图5为本申请实施例提供的变换电路的结构示意图十五；
图6A为本申请实施例提供的变换电路的结构示意图十六；
图6B为本申请实施例提供的变换电路的结构示意图十七；
图7A为本申请实施例提供的无线充电设备的结构示意图一；
图7B为本申请实施例提供的无线充电设备的结构示意图二。
具体实施方式
首先，对本申请实施例所涉及的系统架构和部分词汇进行介绍。图1为本申请实施例提供的系统架构示意图。如图1所示，本申请实施例提供的系统架构中可以包括但不限于：无线充电发射器1、无线充电接收器2和电能存储单元3。其中，无线充电发射器1中可以包括但不限于：逆变器11，以及包括谐振电容12和发射线圈13的谐振电路14；逆变器11的输出端耦合在谐振电路14的两端。其中，上述逆变器11用于对输入的电信号进行逆变处理；谐振电路14用于将逆变器11逆变处理后得到的电信号转换成电磁信号并发射该电磁信号。本申请下述实施例将会对上述逆变器11和无线充电发射器1的可实现方式进行介绍。上述无线充电发射器1通过切换该逆变器11的逆变模式，可以调整该无线充电发射器1的输出电压，以满足接收端的接收线圈所需耦合的电压。
上述无线充电接收器2中可以包括但不限于：整流器21，以及包括谐振电容22和接收线圈23的谐振电路24；整流器21的输入端耦合在谐振电路24的输出端，整流器21的输出端耦合在电能存储单元3。其中，上述谐振电路24用于将从上述发射线圈13接收到的电磁信号转换得到电信号；上述整流器21用于对谐振电路24输出的电信号进行整流处理，并将处理后的电能存储到电能存储单元3。本申请下述实施例将会对上述整流器21和无线充电接收器2的可实现方式进行介绍。上述无线充电接收器2可以通过切换该整流器21的整流模式，可以调整该无线充电接收器2的输出电压，以满足供电需求。
本申请实施例中的编号“第一”以及“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序，不应对本申请实施例构成任何限定。本申请实施例中的耦合是指电性连接，包括直接相连，或者间接相连，本申请对此不做限定。本申请实施例中涉及的单向导通半导体管可以为：金属-氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)(或者简称为MOS管)，或者二极管；当然，还可以为具有单向导通功能的其它半导体管，本申请实施例中对此不做限定。本申请实施例中涉及的任意MOS管不限定只包括一个MOS管。示例性地，在工程应用中，可以采用多个MOS管并联的方式以实现较低的导通阻抗，或者，也可以采用多个MOS管串联的方式以实现较高的耐压，本申请实施例中对此不做限定。本申请实施例中涉及的任意二极管不限定只包括一个二极管。示例性地，在工程应用中，可以采用多个二极管并联的方式以实现较低的导通阻抗，或者，也可以采用多个二极管串联的方式以实现较高的耐压，本申请实施例中对此不做限定。
示例性地，若任意单向导通半导体管是二极管，对应的，该二极管的输入端可以是该二极管的阳极，该二极管的输出端可以是该二极管的阴极。本申请实施例中涉及的任意开关可以为：MOS管，或者机械开关；当然，还可以为具有开关功能的其它器件，本申请实施例中对此不做限定。示例性地，本申请实施例中涉及的MOS管可以包括：PMOS管或NMOS管。本申请实施例中涉及的电子设备可以包括但不限于：如手机、平板电脑、笔记本等终端设备。本申请实施例中涉及的无线充电发射器可以包括但不限于：充电盘等对外发射功率的设备。本申请实施例中涉及的无线充电接收器可以包括但不限于：带电池的电子设备、医疗器，或者电动汽车等能接收无线充电功率的设备。本申请实施例中涉及的无线充电设备可以包括但不限于：无线充电发射器，或无线充电接收器。
针对相关技术中的无线充电接收器中的整流电路，或者无线充电发射器中的逆变电路的输出电压均约等于其输入电压，其输出电压可变的动态范围较小的技术问题，本申请实 施例提供的整流器、逆变器及无线充电设备中，该整流器或逆变器包括：相互耦合连接的信号变换单元和可切换电容单元，其中，该整流器中的可切换电容单元用于切换该整流器的整理模式，或者该逆变器中的可切换电容单元用于切换该逆变器的逆变模式，因此，本申请实施例提供的该整流器或逆变器的输出电压可变的动态范围较大。
下面以具体地实施例对本申请的技术方案进行详细说明。下面这几个具体的实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例中不再赘述。图2A为本申请实施例提供的变换电路的结构示意图一。如图2A所示，本申请实施例提供的变换电路20可以包括：信号变换单元201和可切换电容单元202。可选地，本申请实施例中提供的变换电路20可以为整流器或者逆变器。其中，信号变换单元201可以包括但不限于：第一端a、第二端b、第三端c、第四端d、第一单向导通半导体管2011、第二单向导通半导体极管2012、第三单向导通半导体管2013和第四单向导通半导体管2014。
在一种实例中，若本申请实施例中提供的变换电路20为整流器，则信号变换单元201的连接关系可以如下：第一单向导通半导体管2011的输出端与第二单向导通半导体管2012的输入端耦合至第一端a。第二单向导通半导体管2012的输出端与第三单向导通半导体管2013的输出端耦合至第二端b。第四单向导通半导体管2014的输出端与第三单向导通半导体管2013的输入端耦合至第三端c。第一单向导通半导体管2011的输入端和第四单向导通半导体管2014的输入端耦合至第四端d。其中，第四端d用于耦合至恒定电压，例如，该恒定电压可以是接地电压。其中，上述第一端a和第三端c是该整流器的输入端，用于耦合在谐振电路24的输出端；上述第二端b和第四端d是该整流器的输出端，用于耦合在上述电能存储单元3。
示例性地，上述第一单向导通半导体管2011、第二单向导通半导体极管2012、第三单向导通半导体管2013和第四单向导通半导体管2014可以均是二极管，对应地，每个二极管的输入端可以是该二极管的阳极，每个二极管的输出端可以是该二极管的阴极。
图2B为本申请实施例提供的变换电路的结构示意图二，如图2B所示，本申请实施例中的上述第一单向导通半导体管2011、第二单向导通半导体极管2012、第三单向导通半导体管2013和第四单向导通半导体管2014可以均是二极管。
又一示例性地，上述第一单向导通半导体管2011、第二单向导通半导体极管2012、第三单向导通半导体管2013和第四单向导通半导体管2014可以均是金属-氧化物-半导体MOS管。其中，每个MOS管的连接方向要满足：该MOS管的体二极管的阳极作为该MOS管的输入端，该MOS管的体二极管的阴极作为该MOS管的输出端。例如，若任意单向导通半导体管是PMOS管，则该单向导通半导体管的输入端是该PMOS管的漏极，该单向导通半导体管的输出端是该PMOS管的源极。或者，若任意单向导通半导体管是NMOS管，则该单向导通半导体管的输入端是该NMOS管的源极，该单向导通半导体管的输出端是该NMOS管的漏极。
一种可能的实现方式中，上述第一单向导通半导体管2011、第二单向导通半导体极管2012、第三单向导通半导体管2013和第四单向导通半导体管2014可以均是PMOS管，或者可以均是NMOS管。
图2C为本申请实施例提供的变换电路的结构示意图三，如图2C所示，本申请实施例中的上述第一单向导通半导体管2011、第二单向导通半导体极管2012、第三单向导通半导 体管2013和第四单向导通半导体管2014可以均是NMOS管，对应地，每个NMOS管的输入端可以是该NMOS管的源极，每个NMOS管的输出端可以是该NMOS管的漏极。
另一种可能的实现方式中，上述第一单向导通半导体管2011、第二单向导通半导体极管2012、第三单向导通半导体管2013和第四单向导通半导体管2014中的部分单向导通半导体管可以是PMOS管，另一部分单向导通半导体管可以是NMOS管。需要说明的是，此实现方式中的连接方式需满足如下连接规则：1)当PMOS管与NMOS管耦合连接时，PMOS管的源极耦合到NMOS管的源极，或者PMOS管的漏极耦合到NMOS管的漏极；2)用于耦合连接到上述第二端的端点是PMOS管的源极或者NMOS管的漏极。
又一示例性地，上述第一单向导通半导体管2011、第二单向导通半导体极管2012、第三单向导通半导体管2013和第四单向导通半导体管2014中的部分单向导通半导体管可以是二极管，另一部分单向导通半导体管可以是MOS管。其中，每个二极管的输入端可以是该二极管的阳极，每个二极管的输出端可以是该二极管的阴极。每个MOS管的连接方向要满足：该MOS管的体二极管的阳极作为该MOS管的输入端，该MOS管的体二极管的阴极作为该MOS管的输出端。例如，若任意单向导通半导体管是PMOS管，则该单向导通半导体管的输入端是该PMOS管的漏极，该单向导通半导体管的输出端是该PMOS管的源极。或者，若任意单向导通半导体管是NMOS管，则该单向导通半导体管的输入端是该NMOS管的源极，该单向导通半导体管的输出端是该NMOS管的漏极。
示例性地，本申请实施例中涉及的每个MOS管的的栅极可以作为控制端用于接收控制信号以控制该MOS管的导通或关断。例如，以上述NMOS管2012为例，当上述NMOS管2012的输入端的输入电压高于其输出电压时，则上述NMOS管2012的栅极接收的控制信号是控制该NMOS管导通，使电流从其输入端a流到输出端b；当上述NMOS管2012的输出端的输出电压高于其输入电压时，则上述控制信号是控制该NMOS管关断，防止电流从其输出端b反向流回到输入端a。
示例性地，本申请实施例中的可切换电容单元202，可以耦合在上述第一端a和第三端c中的至少一个、第二端b和第四端d。需要说明的是，为了便于画图，本申请实施例中的附图均以可切换电容单元202耦合在第三端c、第二端b和第四端d为例进行示出的。对于本领域技术人员来说，应该可以理解，上述可切换电容单元202也可以耦合在第一端a、第二端b和第四端d。
本申请实施例中的可切换电容单元202用于切换该变换电路20(即整流器)的整流模式，其中，该整流模式可以包括但不限于：倍压整流模式、全桥整流模式。一种可能的实现方式中，当变换电路20处于倍压整流模式时，变换电路20的输出端的输出电压可以为其输入端的输入电压的n倍，其中，n为大于0的实数。例如，当n＝n1时，对应地，变换电路20处于n1倍压整流模式；或者，当n＝n2时，对应地，变换电路20处于n2倍压整流模式；其中，n2大于n1。
另一种可能的实现方式中，当变换电路20处于全桥整流模式时，变换电路20的输出端的输出电压与其输入端的输入电压之间的差值可以等于上述信号变换单元201中的2个单向导通半导体管的导通压降。由于单向导通半导体管的导通压降较小，在此种模式下，可以认为上述变换电路20的输出端的输出电压与其输入端的输入电压相等。
综上所述，本申请实施例提供的整流器包括：相互耦合连接的信号变换单元201和可 切换电容单元202，其中，可切换电容单元202用于切换整流器的整流模式，因此，本申请实施例提供的整流器的输出电压可变的动态范围较大。
在另一种实例中，若本申请实施例中提供的变换电路20为逆变器，则信号变换单元201的连接关系可以如下：第一单向导通半导体管2011的输入端与第二单向导通半导体管2012的输出端耦合至第一端a。第二单向导通半导体管2012的输入端与第三单向导通半导体管2013的输入端耦合至第二端b。第四单向导通半导体管2014的输入端与第三单向导通半导体管2013的输出端耦合至第三端c。第一单向导通半导体管2011的输出端和第四单向导通半导体管2014的输出端耦合至第四端d。其中，第四端d用于耦合至恒定电压，例如，该恒定电压可以是接地电压。其中，上述第二端b和第四端d是该逆变器的输入端，上述第一端a和第三端c是该逆变器的输出端，用于耦合在上述谐振电路14的两端。
示例性地，上述第一单向导通半导体管2011、第二单向导通半导体极管2012、第三单向导通半导体管2013和第四单向导通半导体管2014可以均是金属-氧化物-半导体MOS管。其中，每个MOS管的连接方向要满足：该MOS管的体二极管的阴极作为该MOS管的输入端，该MOS管的体二极管的阳极作为该MOS管的输出端。例如，若任意单向导通半导体管是PMOS管，则该单向导通半导体管的输入端是该PMOS管的源极，该单向导通半导体管的输出端是该PMOS管的漏极。或者，若任意单向导通半导体管是NMOS管，则该单向导通半导体管的输入端是该NMOS管的漏极，该单向导通半导体管的输出端是该NMOS管的源极。
一种可能的实现方式中，上述第一单向导通半导体管2011、第二单向导通半导体极管2012、第三单向导通半导体管2013和第四单向导通半导体管2014可以均是PMOS管，或者如图2C所示可以均是NMOS管，对应地，每个NMOS管的输入端可以是该NMOS管的漏极，每个NMOS管的输出端可以是该NMOS管的源极。
在另一种实例中，上述第一单向导通半导体管2011、第二单向导通半导体极管2012、第三单向导通半导体管2013和第四单向导通半导体管2014中的部分单向导通半导体管可以是PMOS管，另一部分单向导通半导体管可以是NMOS管。需要说明的是，此实例中的连接方式需满足如下连接规则：1)当PMOS管与NMOS管耦合连接时，PMOS管的源极耦合到NMOS管的源极，或者PMOS管的漏极耦合到NMOS管的漏极；2)用于耦合连接到上述第二端的端点是PMOS管的源极或者NMOS管的漏极。
示例性地，本申请实施例中涉及的每个MOS管的的栅极可以作为控制端用于接收控制信号以控制该MOS管的导通或关断，从而控制电流进入该MOS管的输出端。例如，当该MOS管的栅极接收的控制信号是控制该MOS管的关断时，则可以阻止电流流过该MOS管，从而可以实现单向导通。
例如，以上述NMOS管2012为例，当上述NMOS管2012的输入端的输入电压高于其输出电压时，则上述NMOS管2012的栅极接收的控制信号是控制该NMOS管导通，使电流从其输入端b流到输出端a；当上述NMOS管2012的输出端的输出电压高于其输入电压时，则上述控制信号是控制该NMOS管关断，防止电流从其输出端a反向流回到输入端b。
示例性地，本申请实施例中的可切换电容单元202，可以耦合在上述第一端a和第三 端c中的至少一个、第二端b和第四端d。需要说明的是，为了便于画图，本申请实施例中的附图均以可切换电容单元202耦合在第三端c、第二端b和第四端d为例进行示出的。对于本领域技术人员来说，应该可以理解，上述可切换电容单元202也可以耦合在第一端a、第二端b和第四端d。
本申请实施例中的可切换电容单元202用于切换变换电路20(即逆变器)的逆变模式，其中，该逆变模式可以包括但不限于：分压逆变模式、全桥逆变模式。一种可能的实现方式中，当变换电路20处于分压逆变模式时，变换电路20的输出端的输出电压可以为其输入端的输入电压的1/n倍。例如，当n＝n1时，对应地，变换电路20处于1/n1分压逆变模式；或者，当n＝n2时，对应地，变换电路20处于1/n2分压逆变模式。
另一种的实现方式中，当变换电路20处于全桥逆变模式时，变换电路20的输出端的输出电压与其输入端的输入电压之间的差值可以等于上述信号变换单元201中的2个单向导通半导体管的导通压降。由于单向导通半导体管的导通压降较小，在此种模式下，可以认为上述变换电路20的输出端的输出电压与其输入端的输入电压相等。
综上所述，本申请实施例提供的逆变器包括：相互耦合连接的信号变换单元201和可切换电容单元202，其中，可切换电容单元202用于切换逆变器的逆变模式，因此，本申请实施例提供的逆变器的输出电压可变的动态范围较大。
在上述各实施例的基础上，本申请下述实施例中对上述变换电路20中的可切换电容单元202的可实现方式进行介绍。图3A为本申请实施例提供的变换电路的结构示意图四。在上述图2A-图2C所示任意实施例的基础上，本申请实施例对上述可切换电容单元202的一种可能的实现方式进行介绍。如图3A所示，上述可切换电容单元202可以包括但不限于：第一开关202A和电容单元202B。其中，第一开关202A耦合在上述第三端c和中间节点e之间，电容单元202B耦合在上述第二端b、第四端d和中间节点e。
本申请实施例中的上述第一开关202A的导通或断开，可以切换变换电路20的变换模式。示例性地，若上述变换电路20是整流器，且上述第一开关202A导通，则上述变换电路20处于上述倍压整流模式；或者，若上述第一开关202A断开，则上述变换电路20处于上述全桥整流模式。又一示例性地，若上述变换电路20是逆变器，且上述第一开关202A导通，则上述变换电路20处于上述分压逆变模式；或者，若上述第一开关202A断开时，则上述变换电路20处于上述全桥逆变模式。本申请实施例中的上述第一开关202A可以为机械开关、或者可以为MOS管，其中，该MOS管可以是PMOS管或NMOS管。
图3B为本申请实施例提供的变换电路的结构示意图五。如图3B所示，在上述图3A所示实施例的基础上，当上述第一开关202A为NMOS管1时，该NMOS管1的源极s可以耦合在上述第三端c，该NMOS管1的漏极d耦合在上述中间节点e。需要说明的是，该NMOS管1的栅极g用于接收控制信号以控制该NMOS管1的导通或关断。应理解，该NMOS管1的源极s可以耦合在上述中间节点e，该NMOS管1的漏极d耦合在上述第三端c(此种方式图中未示出)。
另外，在上述图3A所示实施例的基础上，当上述第一开关202A为PMOS管1时，该PMOS管1的源极s可以耦合在上述第三端c，该PMOS管1的漏极d耦合在上述中间节点e。需要说明的是，该PMOS管1的栅极g用于接收控制信号以控制该PMOS管1的导通或关断。应理解，该PMOS管1的源极s可以耦合在上述中间节点e，该PMOS管1 的漏极d耦合在上述第三端c(此种方式图中未示出)。
图3C为本申请实施例提供的变换电路的结构示意图六。如图3C所示，在上述图3A所示实施例的基础上，当上述第一开关202A包括NMOS管2和NMOS管3时，该NMOS管2的源极s可以耦合在上述第三端c，该NMOS管2的漏极d耦合在该NMOS管3的漏极d，该NMOS管3的源极s耦合在上述中间节点e。应理解，该NMOS管2的漏极d可以耦合在上述第三端c，该NMOS管2的源极s耦合在该NMOS管3的源极s，该NMOS管3的漏极d耦合在上述中间节点e(此种方式图中未示出)。
需要说明的是，该NMOS管2和该NMOS管3的栅极g均用于接收控制信号以控制对应的NMOS管的导通或关断。通常情况下，该NMOS管2和该NMOS管3在控制信号的控制下会同时导通或关断，从而可以实现双向防反流。应理解，用于实现双向防反流的上述NMOS管2和NMOS管3也可以用一个MOS管代替。
另外，上述第一开关202A也可以包括PMOS管2和PMOS管3，该PMOS管2的源极s可以耦合在上述第三端c，该PMOS管2的漏极d耦合在该PMOS管3的漏极d，该PMOS管3的源极s耦合在上述中间节点e(此种方式图中未示出)。应理解，该PMOS管2的漏极d可以耦合在上述第三端c，该PMOS管2的源极s耦合在该PMOS管3的源极s，该PMOS管3的漏极d耦合在上述中间节点e(此种方式图中未示出)。
另外，上述第一开关202A也可以包括：一个PMOS管和一个NMOS管，该PMOS管的漏极可以耦合在上述第三端c，该PMOS管的源极耦合在该NMOS管的漏极，该NMOS管的源极可以耦合在上述中间节点e(此种方式图中未示出)。或者，该PMOS管的源极可以耦合在上述第三端c，该PMOS管的漏极耦合在该NMOS管的源极，该NMOS管的漏极可以耦合在上述中间节点e(此种方式图中未示出)。当然，上述第一开关202A还可以为具有开关功能的其它器件，本申请实施例中对此不做限定。
在上述各实施例的基础上，本申请下述实施例中对上述可切换电容单元202中的电容单元202B的可实现方式进行介绍。示例性地，以上述图3A所示实施例的基础上为例，本申请实施例对上述电容单元202B的一种可能的实现方式进行介绍。图3D为本申请实施例提供的变换电路的结构示意图七，如图3D所示，上述电容单元202B可以包括但不限于：第一电容C1和第二电容C2。其中，第一电容C1可以耦合在上述中间节点e和上述第二端b之间，第二电容C2耦合在上述中间节点e和上述第四端d之间。
示例性地，若上述变换电路20是整流器，且上述第一开关202A导通，则上述信号变换单元201中的上述第一单向导通半导体管2011、第二单向导通半导体管2012和上述电容单元202B位于倍压整流电路中。或者，若上述第一开关202A断开，则上述信号变换单元201中的上述第一单向导通半导体管2011、第二单向导通半导体管2012、第三单向导通半导体管2013、第四单向导通半导体管2014和上述电容单元202B位于全桥整流电路中。
应理解，若上述第一单向导通半导体管2011、第二单向导通半导体管2012和上述电容单元202B位于倍压整流电路中，则上述变换电路20处于上述倍压整流模式。或者，若上述第一单向导通半导体管2011、第二单向导通半导体管2012、第三单向导通半导体管2013、第四单向导通半导体管2014和上述电容单元202B位于全桥整流电路中，则上述变换电路20处于上述全桥整流模式。
又一示例性地，若上述变换电路20是逆变器，且上述第一开关202A导通，则上述信 号变换单元201中的上述第一单向导通半导体管2011、第二单向导通半导体管2012和上述电容单元202B位于分压逆变电路中。或者，若上述第一开关202A断开，则上述信号变换单元201中的上述第一单向导通半导体管2011、第二单向导通半导体管2012、第三单向导通半导体管2013、第四单向导通半导体管2014和上述电容单元202B位于全桥逆变电路中。
应理解，若上述第一单向导通半导体管2011、第二单向导通半导体管2012以及上述电容单元202B位于分压逆变电路中，则上述变换电路20处于上述分压逆变模式。或者，若上述第一单向导通半导体管2011、第二单向导通半导体管2012、第三单向导通半导体管2013、第四单向导通半导体管2014和上述电容单元202B位于全桥逆变电路中，则上述变换电路20处于上述全桥逆变模式。
图3E为本申请实施例提供的变换电路的结构示意图八。如图3E所示，在上述图3D所示实施例的基础上，上述电容单元202B还包括：第三电容C3。其中，第三电容C3耦合在上述第二端b和第四端d之间。本申请上述实施例中的第一电容C1、第二电容C2和第三电容C3可以用于存储能量。
示例性地，以上述图3A所示实施例的基础上为例，本申请实施例对上述可切换电容单元202中的电容单元202B的另一种可能的实现方式进行介绍。图3F为本申请实施例提供的变换电路的结构示意图九，如图3F所示，上述电容单元202B可以包括但不限于：第一电容C1和第二电容C2。其中，第一电容C1可以耦合在上述中间节点e和预设位置之间，第二电容C2耦合在上述第二端b和第四端d之间。示例性地，上述预设位置可以包括以下任一项：上述第二端b、上述第四端d、或预设电压。例如，预设电压可以为预设直流电源、或者接地电压等。
示例性地，若上述变换电路20是整流器，且第一上述开关202A导通，则上述信号变换单元201中的上述第一单向导通半导体管2011、第二单向导通半导体管2012和上述电容单元202B位于倍压整流电路中。或者，若上述第一开关202A断开，则上述信号变换单元201中的上述第一单向导通半导体管2011、第二单向导通半导体管2012、第三单向导通半导体管2013、第四单向导通半导体管2014和上述电容单元202B位于全桥整流电路中。
又一示例性地，若上述变换电路20是逆变器，且第一上述开关202A导通，则上述信号变换单元201中的上述第一单向导通半导体管2011、第二单向导通半导体管2012和上述电容单元202B位于分压逆变电路中。或者，若上述第一开关202A断开，则上述信号变换单元201中的上述第一单向导通半导体管2011、第二单向导通半导体管2012、第三单向导通半导体管2013、第四单向导通半导体管2014和上述电容单元202B位于全桥逆变电路中。
图4A为本申请实施例提供的变换电路的结构示意图十。在上述图2A-图2C所示任意实施例的基础上，本申请实施例对上述可切换电容单元202的另一种可能的实现方式进行介绍。如图4A所示，上述可切换电容单元202可以包括但不限于：第一开关202A、第一电容C1和第二电容C2。其中，第一电容C1可以耦合在上述第三端c和中间节点e之间，第一开关202A耦合在中间节点e和预设位置之间，第二电容C2耦合在第二端b和第四端d之间。
本申请实施例中的上述第一开关202A的导通或断开，可以切换变换电路20的变换模 式。示例性地，若上述变换电路20是整流器，且上述第一开关202A导通，则上述变换电路20处于上述倍压整流模式；或者，若上述第一开关202A断开，则上述变换电路20处于上述全桥整流模式。又一示例性地，若上述变换电路20是逆变器，且上述第一开关202A导通，则上述变换电路20处于上述分压逆变模式；或者，若上述第一开关202A断开，则上述变换电路20处于上述全桥逆变模式。示例性地，上述预设位置可以包括以下任一项：上述第二端b、上述第四端d、或预设电压。例如，预设电压可以为预设直流电源、或者接地电压等。
图4B为本申请实施例提供的变换电路的结构示意图十一。如图4B所示，在上述图4A所示实施例的基础上，上述第一开关202A可以耦合在中间节点e和上述第二端b之间。图4C为本申请实施例提供的变换电路的结构示意图十二。如图4C所示，在上述图4A所示实施例的基础上，上述第一开关202A可以耦合在中间节点e和上述第四端d之间。
如图4B或图4C所示实施例中，示例性地，若上述变换电路20是整流器，且上述第一开关202A导通，则上述信号变换单元201中的上述第一单向导通半导体管2011、第二单向导通半导体管2012、第一电容C1和第二电容C2位于倍压整流电路中。或者，若上述第一开关202A断开，则上述信号变换单元201中的上述第一单向导通半导体管2011、第二单向导通半导体管2012、第三单向导通半导体管2013、第四单向导通半导体管2014和第二电容C2位于全桥整流电路中。
应理解，若上述第一单向导通半导体管2011、第二单向导通半导体管2012、第一电容C1和第二电容C2位于倍压整流电路中，则上述变换电路20处于上述倍压整流模式。或者，若上述第一单向导通半导体管2011、第二单向导通半导体管2012、第三单向导通半导体管2013、第四单向导通半导体管2014和第二电容C2位于全桥整流电路中，则上述变换电路20处于上述全桥整流模式。
又一示例性地，若上述变换电路20是逆变器，且上述第一开关202A导通，则上述信号变换单元201中的上述第一单向导通半导体管2011、第二单向导通半导体管2012、第一电容C1和第二电容C2位于分压逆变电路中。或者，若上述第一开关202A断开，则上述信号变换单元201中的上述第一单向导通半导体管2011、第二单向导通半导体管2012、第三单向导通半导体管2013、第四单向导通半导体管2014和第二电容C2位于全桥逆变电路中。
应理解，若上述第一单向导通半导体管2011、第二单向导通半导体管2012、第一电容C1和第二电容C2位于分压逆变电路中，则上述变换电路20处于上述分压逆变模式。或者，若上述第一单向导通半导体管2011、第二单向导通半导体管2012、第三单向导通半导体管2013、第四单向导通半导体管2014和第二电容C2位于全桥逆变电路中，则上述变换电路20处于上述全桥逆变模式。
本申请实施例中的上述第一开关202A可以为机械开关、或者可以为MOS管，其中，该MOS管可以是PMOS管或NMOS管。图4D为本申请实施例提供的变换电路的结构示意图十三。如图4D所示，在上述图4A-图4C所示任意实施例的基础上，当上述第一开关202A为NMOS管1时，该NMOS管1的源极s可以耦合在上述中间节点e，该NMOS管1的漏极d耦合在上述预设位置。需要说明的是，该NMOS管1的栅极g用于接收控制信号以控制该NMOS管1的导通或关断。应理解，该NMOS管1的源极s也可以耦合在上 述预设位置，该NMOS管1的漏极d耦合在上述中间节点e(此种方式图中未示出)。
另外，在上述图4A-图4C所示任意实施例的基础上，当上述第一开关202A为PMOS管1时，该PMOS管1的源极s可以耦合在上述中间节点e，该PMOS管1的漏极d耦合在上述预设位置。需要说明的是，该PMOS管1的栅极g用于接收控制信号以控制该NMOS管1的导通或关断。应理解，该PMOS管1的源极s可以耦合在上述预设位置，该PMOS管1的漏极d耦合在上述中间节点e(此种方式图中未示出)。
图4E为本申请实施例提供的变换电路的结构示意图十四。如图4E所示，在上述图4A-图4C所示任意实施例的基础上，当上述第一开关202A包括NMOS管2和NMOS管3时，该NMOS管2的源极s可以耦合在上述中间节点e，该NMOS管2的漏极d耦合在该NMOS管3的漏极d，该NMOS管3的源极s耦合在上述预设位置。应理解，该NMOS管2的漏极d可以耦合在上述中间节点e，该NMOS管2的源极s耦合在该NMOS管3的源极s，该NMOS管3的漏极d耦合在上述预设位置(此种方式图中未示出)。
需要说明的是，该NMOS管2和该NMOS管3的栅极g均用于接收控制信号以控制对应的NMOS管的导通或关断。通常情况下，该NMOS管2和该NMOS管3在控制信号的控制下会同时导通或关断，从而可以实现双向防反流。应理解，用于实现双向防反流的上述NMOS管2和NMOS管3也可以用一个MOS管代替。
另外，上述第一开关202A也可以包括PMOS管2和PMOS管3，该PNMOS管2的源极s可以耦合在上述中间节点e，该PMOS管2的漏极d耦合在该PMOS管3的漏极d，该PMOS管3的源极s耦合在上述预设位置。应理解，该PMOS管2的漏极d可以耦合在上述中间节点e，该PMOS管2的源极s耦合在该PMOS管3的源极s，该PMOS管3的漏极d耦合在上述预设位置(此种方式图中未示出)。
另外，上述第一开关202A也可以包括：一个PMOS管和一个NMOS管，该PMOS管的漏极可以耦合在上述中间节点e，该PMOS管的源极耦合在该NMOS管的漏极，该NMOS管的源极可以耦合在上述预设位置(此种方式图中未示出)。或者，该PMOS管的源极可以耦合在上述中间节点e，该PMOS管的漏极耦合在该NMOS管的源极，该NMOS管的漏极可以耦合在上述预设位置(此种方式图中未示出)。当然，上述第一开关202A还可以为具有开关功能的其它器件，本申请实施例中对此不做限定。
为了实现上述变换电路的输出电压具有更大的可变动态范围，在上述图3A-图3F所示任意实施例的基础上，上述可切换电容单元202还可以包括：第一切换单元和第二切换单元。
示例性地，以上述图3D所示实施例的基础上为例，本申请实施例中对上述可切换电容单元202作进一步介绍。图5为本申请实施例提供的变换电路的结构示意图十五，如图5所示，上述可切换电容单元202还可以包括：第一切换单元202C和第二切换单元202D。其中，第一切换单元202C耦合在上述中间节点e和第一端a之间，第二切换单元202D的一端可以耦合在上述第四端d，第二切换单元202D的另一端可以耦合在谐振电路中的线圈和谐振电容之间的连接点(图中未示出)。例如，若上述变换电路20是逆变器，设置在上述无线充电发射器1中，则上述第二切换单元202D的另一端可以耦合在上述谐振电路14中的发射线圈13和谐振电容12之间的连接点。又例如，若上述变换电路20是整流器，设置在上述无线充电接收器2中，则上述第二切换单元202D的另一端可以耦合在上述谐 振电路24中的接收线圈23和谐振电容之间的连接点。
示例性地，上述第一切换单元202C可以包括但不限于：第五单向导通半导体管202C1和第二开关202C2。其中，第二开关202C2可以耦合在上述中间节点e和第五单向导通半导体管202C1的输入端之间，第五单向导通半导体管202C1的输出端耦合在上述第一端a。应理解，第二开关202C2和第五单向导通半导体管202C1的位置可以互换，例如，第五单向导通半导体管202C1的输入端耦合在上述中间节点e，第二开关202C2耦合在上述第一端a和第五单向导通半导体管202C1的输出端之间(此种方式图中未示出)。
本申请实施例中的上述第二开关202C2可以为机械开关，或者可以为MOS管，其中，该MOS管可以是PMOS管或NMOS管。当上述第二开关202C2为MOS管时，该MOS管的源极和漏极作为上述第二开关202C2的两端分别耦合在上述中间节点e和第五单向导通半导体管202C1的输入端。
本申请实施例中的第五单向导通半导体管202C1可以为二极管，或者MOS管，其中，该MOS管可以是PMOS管或NMOS管。示例性地，若第五单向导通半导体管202C1是二极管，对应的，第五单向导通半导体管202C1的输入端可以是该二极管的阳极，第五单向导通半导体管202C1的输出端可以是该二极管的阴极。
又一示例性地，若第五单向导通半导体管202C1是MOS管，则第五单向导通半导体管202C1的输入端可以是该MOS管的源极，第五单向导通半导体管202C1的输出端可以是该MOS管的漏极；或者，第五单向导通半导体管202C1的输入端可以是该MOS管的漏极，第五单向导通半导体管202C1的输出端可以是该MOS管的源极。
应理解，上述第五单向导通半导体管202C1的输入端和/或输出端是该MOS管的哪个极，还可以根据上述第二开关202C2的类型和二者连接关系来确定。例如，若上述第二开关202C2为NMOS管4，且第五单向导通半导体管202C1为NMOS管5，则该NMOS管4的源极可以耦合在该NMOS管5的源极，或者，该NMOS管4的漏极耦合在该NMOS管5的漏极。又例如，若上述第二开关202C2为PMOS管4，且第五单向导通半导体管202C1为PMOS管5，则该PMOS管4的源极可以耦合在该PMOS管5的源极，或者，该PMOS管4的漏极耦合在该PMOS管5的漏极。
又例如，若上述第二开关202C2为机械开关和第五单向导通半导体管202C1为MOS管，则该MOS管的源极可以耦合在该机械开关，或者，该MOS管的漏极耦合在该机械开关。又例如，若第五单向导通半导体管202C1为PMOS管，且上述第二开关202C2为NMOS管，则该PMOS管的源极可以耦合在该NMOS管的漏极，或者，该PMOS管的漏极耦合在该NMOS管的源极。
需要说明的是，此时第五单向导通半导体管202C1的栅极作为控制端用于接收控制信号以控制第五单向导通半导体管202C1的导通或关断，且避免第五单向导通半导体管202C1反向导通。
应理解，上述第五单向导通半导体管202C 1与第二开关202C2的位置可以互换。
示例性地，上述第二切换单元202D可以包括但不限于：第六单向导通半导体管202D1和第三开关202D2。其中，第三开关202D2可以耦合在上述第四端d和第六单向导通半导体管202D1的输入端之间，第六单向导通半导体管202D1的输出端可以耦合在上述谐振电路中的线圈和谐振电容之间的连接点(图中未示出)。例如，若上述变换电路20是逆变 器，设置在上述无线充电发射器1中，则上述第六单向导通半导体管202D1的输出端可以耦合在上述谐振电路14中的发射线圈13和谐振电容12之间的连接点。又例如，若上述变换电路20是整流器，设置在上述无线充电接收器2中，则上述第六单向导通半导体管202D1的输出端可以耦合在上述谐振电路24中的接收线圈23和谐振电容之间的连接点。
应理解，第三开关202D2和第六单向导通半导体管202D1的位置可以互换，例如，第六单向导通半导体管202D1的输入端耦合在上述第四端d，第三开关202D2耦合在第六单向导通半导体管202D1的输出端和该谐振电路之间的连接点(此种方式图中未示出)。
本申请实施例中的上述第三开关202D2可以为机械开关，或者可以为MOS管，其中，该MOS管可以是PMOS管或NMOS管。例如，当上述第三开关202D2为MOS管时，该MOS管的源极和漏极作为上述第三开关202D2的两端分别耦合在上述第四端d和第六单向导通半导体管202D1的输入端。应理解，该MOS管的源极和漏级作为上述第三开关202D2的两端可以分别耦合在第六单向导通半导体管202D1的输出端和上述谐振电路中的线圈和谐振电容之间的连接点。
本申请实施例中的第六单向导通半导体管202D1可以为二极管，或者MOS管，其中，该MOS管可以是PMOS管或NMOS管。示例性地，若第六单向导通半导体管202D1是二极管，对应的，第六单向导通半导体管202D1的输入端可以是该二极管的阳极，第六单向导通半导体管202D1的输出端可以是该二极管的阴极。
又一示例性地，若第六单向导通半导体管202D1是MOS管，则第六单向导通半导体管202D1的输入端可以是该MOS管的源极，第六单向导通半导体管202D1的输出端可以是该MOS管的漏极；或者，第六单向导通半导体管202D1的输入端可以是该MOS管的漏极，第六单向导通半导体管202D1的输出端可以是该MOS管的源极。
应理解，上述第六单向导通半导体管202D1的输入端和/或输出端是该MOS管的哪个极，可以根据上述第三开关202D2的类型和二者连接关系来确定。例如，若上述第三开关202D2为NMOS管6和第六单向导通半导体管202D1为NMOS管7，则该NMOS管6的源极可以耦合在该NMOS管7的源极，或者，该NMOS管6的漏极耦合在该NMOS管7的漏极。又例如，若上述第三开关202D2为PMOS管6和第六单向导通半导体管202D1为PMOS管7，则该PMOS管6的源极可以耦合在该PMOS管7的源极，或者，该PMOS管6的漏极耦合在该PMOS管7的漏极。
又例如，若上述第三开关202D2为机械开关和第六单向导通半导体管202D1为MOS管，则该MOS管的源极可以耦合在该机械开关，或者，该MOS管的漏极耦合在该机械开关。又例如，若第六单向导通半导体管202D1为PMOS管，且上述第三开关202D2为NMOS管，则该PMOS管的源极可以耦合在该NMOS管的漏极，或者，该PMOS管的漏极耦合在该NMOS管的源极。
需要说明的是，此时第六单向导通半导体管202D1的栅极作为控制端用于接收控制信号以控制第六单向导通半导体管202D1的导通或关断，且避免第六单向导通半导体管202D1反向导通。应理解，上述第六单向导通半导体管202D1与第三开关202D2的位置可以互换。
如图5所示实施例中，第一切换单元202C中的第五单向导通半导体管202C1和第二开关202C2的导通或断开，以及第二切换单元202D中的第六单向导通半导体管202D1和 第三开关202D2的导通或断开，配合上述第一开关202A的导通或断开，可以切换变换电路20的变换模式。
示例性地，若上述变换电路20是整流器，上述第一开关202A导通，且第一切换单元202C中的第五单向导通半导体管202C1和/或第二开关202C2断开，以及第二切换单元202D中的第六单向导通半导体管202D1和/或第三开关202D2断开，上述变换电路20处于上述n1倍压整流模式。例如，上述变换电路20在n1(例如取2)倍压整流模式下其输出电压与输入电压之间的关系可以满足如下等式：该输出电压＝该输入电压的2倍-上述信号变换单元201中的单向导通半导体管的导通压降-上述第一开关202A的导通压降。
又一示例性地，若上述变换电路20是逆变器，上述第一开关202A导通，且第一切换单元202C中的第五单向导通半导体管202C1和/或第二开关202C2断开，以及第二切换单元202D中的第六单向导通半导体管202D1和/或第三开关202D2断开，上述变换电路20处于上述1/n1分压逆变模式。例如，上述变换电路20在1/n1分压逆变模式下其输入电压与输出电压之间的关系可以满足如下等式：该输入电压＝该输出电压的2倍-上述信号变换单元201中的单向导通半导体管的导通压降-上述第一开关202A的导通压降。
又一示例性地，若上述变换电路20是整流器，且上述第一开关202A、第一切换单元202C中的第二开关202C2以及第二切换单元202D中的第三开关202D2处于导通状态，上述变换电路20处于上述n2(例如取3)倍压整流模式。例如，变换电路20在n2倍压整流模式下其输出电压与输入电压之间的关系可以满足如下等式：该输出电压＝该输入电压的3倍-上述信号变换单元201中的单向导通半导体管的导通压降-上述第一切换单元202C中的第五单向导通半导体管202C1和第二开关202C2的导通压降-上述第二切换单元202D中的第六单向导通半导体管202D1和第三开关202D2的导通压降。
又一示例性地，若上述变换电路20是逆变器，且上述第一开关202A、第一切换单元202C中的第二开关202C2以及第二切换单元202D中的第三开关202D2处于导通状态，上述变换电路20处于上述1/n2分压逆变模式。例如，变换电路20在1/n2分压逆变模式下其输入电压与输出电压之间的关系可以满足如下等式：该输入电压＝该输出电压的3倍-上述信号变换单元201中的单向导通半导体管的导通压降-上述第一切换单元202C中的第五单向导通半导体管202C1和第二开关202C2的导通压降-上述第二切换单元202D中的第六单向导通半导体管202D1和第三开关202D2的导通压降。
又一示例性地，若上述变换电路20是整流器，且上述第一开关202A断开、上述第一切换单元202C中的第五单向导通半导体管202C1和/或第二开关202C2断开，以及第二切换单元202D中的第六单向导通半导体管202D1和/或第三开关202D2断开，上述变换电路20处于上述全桥整流模式。
又一示例性地，若上述变换电路20是逆变器，且上述第一开关202A断开、上述第一切换单元202C中的第五单向导通半导体管202C1和/或第二开关202C2断开，以及第二切换单元202D中的第六单向导通半导体管202D1和/或第三开关202D2断开，上述变换电路20处于上述全桥逆变模式。
综上所述，本申请实施例提供的变换电路20，通过其中的第一切换单元202C和第二切换单元202D的导通或断开，配合上述第一开关202A的导通或断开，可以切换该变换电路20更多的变换模式。例如，若变换电路20是整流器，通过其中的第一切换单元202C和 第二切换单元202D的导通或断开，配合上述第一开关202A的导通或断开，可以切换该整流器更多的整流模式；或者，若变换电路20是逆变器，通过其中的第一切换单元202C和第二切换单元202D的导通或断开，配合上述第一开关202A的导通或断开，可以切换该逆变器更多的逆变模式。可见，本申请实施例提供的整流器或逆变器的输出电压可变的动态范围进一步增大了。
需要说明的是，以上述图3E、3F、4A-4E任意所示实施例的基础上，上述可切换电容单元202的可实现方式，可以参考上述以上述图3D所示实施例的基础上对上述可切换电容单元202的相关描述，此处不再赘述。
图6A为本申请实施例提供的变换电路的结构示意图十六。若上述变换电路20为整流器，考虑到上述变换电路20的输入端的电压在个别情况下会较小，为了不影响上述变换电路20的整流模式的切换，本申请实施例提供的变换电路20还可以包括：辅助升压电路。如图6A所示，在上述任意实施例的基础上，上述变换电路20还包括：辅助升压电路203。其中，辅助升压电路203可以耦合在上述第一端a和第二端b之间，该辅助升压电路203的输出端O可以用于耦合在控制器。
示例性地，该辅助升压电路203用于对第一端a的电压进行升压处理，使得升压处理后的电压满足该控制器的启动电压，以便于该控制器可以产生用于控制上述可切换电容单元202的切换信号，以及用于控制上述信号变换单元201中的各单向导通半导体管的控制信号，从而实现切换上述变换电路20的整流模式。控制器的具体控制过程可参照后续图7A或图7B中控制器的相关描述。
图6B为本申请实施例提供的变换电路的结构示意图十七。在上述图6A所示实施例的基础上，本申请实施例对上述辅助升压电路203的可实现方式进行介绍。如图6B所示，上述辅助升压电路203可以包括但不限于：第一二极管D1、第二二极管D2、第四电容C4和第五电容C5。其中，第一二极管D1的输入端耦合在上述第二端b，第二二极管D2的输入端和第四电容C4的第一端耦合在第一二极管D1的输出端，第四电容C4的第二端耦合在上述第一端a，第二二极管D2的输出端和第五电容C5的第一端耦合在上述输出端O，第五电容C5的第二端接地。
以一个时间周期为例，本申请实施例提供的辅助升压电路203中，在上半周期，当上述第一端a的电压小于第三端c的电压时，通过第三单向导通半导体管2013和第一二极管D1给第四电容C4充电，使第四电容C4上端的电压近似等于第一端a与第三端c之间的电压；在下半周期，当第三端c的电压小于第一端a的电压时，通过第四电容C4和第二二极管D2给第五电容C5充电。由于C4在上半周期已经充电至一定电压，下半周期的充电使第五电容C5上端(即上述输出端O)的电压约等于第一端a与第三端c之间的电压与第四电容C4两端的电压之和。可见，上述输出端O的电压可以约等于上述第一端a的电压的2倍，从而可以满足控制器的启动电压。例如，在Ping(或者称之为协议初始上电)阶段时，通过该辅助升压电路203可以提高上述输出端O的电压，从而可以满足控制器的启动电压，提高了Ping阶段的自由度。本申请实施例中涉及的自由度是指：无线充电发射器与无线充电接收器之间摆放的位置关系，包括水平和空间距离。
本申请下述实施例对上述无线充电设备的可实现方式进行介绍。一种可能的实现方式中，上述无线充电设备用于接收无线充电信号，则上述无线充电设备为上述无线充电接收 器2，其中，无线充电接收器2可以包括但不限于：谐振电路24和整流器21。
为了便于理解，在上述实施例的基础上，本申请实施例中以上述图2A所示的变换电路20为上述整流器21，以及谐振电路24包括接收线圈23和谐振电容22为例，对本申请实施例提供的无线充电设备的可实现方式进行介绍。
图7A为本申请实施例提供的无线充电设备的结构示意图一，如图7A所示，本申请实施例提供的无线充电设备70可以包括但不限于：上述谐振电路24、上述整流器21、控制器701以及充电管理单元702。其中，控制器701与上述整流器21耦合连接，用于控制上述整流器21中的信号变换单元201和可切换电容单元202。示例性地，控制器701可以与上述信号变换单元201中的单向导通半导体管的栅极连接，以及与上述可切换电容单元202中的开关和单向导通半导体管的栅极连接。
其中，上述整流器21的第一端a和第三端c作为输入端分别耦合在谐振电路24的两端，用于接收谐振电路24将从对端的发射线圈接收到的电磁信号进行转换所得到的电信号。上述整流器21的第二端b和第四端d是该整流器21的输出端，用于耦合连接到上述充电管理单元702，用于将该整流器21的输出端的输出电压进行电压转换(例如降压处理等)，以匹配后级的电能存储单元的存储电压。示例性地，该电能存储单元可以包括但不限于：电池。需要说明的是，该电能存储单元可以属于该无线充电设备70，或者属于与该无线充电设备70连接的电子设备。
为了实现提高电流的方式以实现大功率充电，本申请实施例中的谐振电路24中的接收线圈23的电感值小于标准接收线圈的电感值，可以减小接收线圈的电阻，降低了接收线圈的热耗，从而提升接收线圈的通流能力。其中，对于遵从无线充电联盟(Wireless Power Consortium，WPC)推出的国际无线充电标准Qi协议的无线充电设备，协议里面明确规定了发射端线圈的形状和规格，对于标准接收线圈耦合到的电压要求如下：在ping阶段，其耦合到的电压要大于2.7V，以便无线充电设备的芯片能正常上电；在开始功率传输阶段，其耦合到的电压要大于5V以便能给后级的设备充电。示例性地，本申请实施例中的接收线圈的电感值可以为该标准接收线圈的电感值的1/(n^2)。
在减小接收线圈的电感值的情况下，势必会导致接收线圈23从对端的发射线圈耦合到的电压会降低，为了保证上述无线充电设备的输出电压要求，本申请实施例中，上述控制器701用于控制上述整流器21中的可切换电容单元202，以切换该整流器21的整流模式；其中，该整流模式包括：上述倍压整流模式，或者上述全桥整流模式。应理解，该控制器701还用于控制上述信号变换单元201中的各单向导通半导体管的导通或关断。
具体地，该控制器701可以通过控制上述可切换电容单元202中的上述单向导通半导体管和/或上述开关的导通或关断，以切换该整流器21的整流模式。示例性地，上述控制器701用于根据该设备70的无线充电运行状态信息，控制上述可切换电容单元，以切换该整流器21的整流模式。
一种可能的实现方式，若该无线充电运行状态信息包括整流器21的预设端电压，则上述控制器701用于根据预设电压阈值和该预设端电压，控制上述可切换电容单元，以切换该整流器21的整流模式。可选地，该预设端电压可以包括但不限于：该整流器21的输入端的输入电压，或者整流器21的输出端的输出电压。
示例性地，若该预设端电压小于或等于该预设电压阈值，则上述控制器701用于控制 上述可切换电容单元202中的上述单向导通半导体管和/或上述开关的导通或关断，使得该整流器21处于倍压整流模式，使得整流器21的输出端的输出电压可以大于其输入端的输入电压，从而可以保证该设备70可以给后级设备供电。
又一示例性地，若该预设端电压大于该预设电压阈值，则上述控制器701用于控制上述可切换电容单元202中的上述单向导通半导体管和/或上述开关的导通或关断，使得该整流器21处于全桥整流模式，使得整流器21的输出端的输出电压几乎等于其输入端的输入电压。
另一种可能的实现方式，若该无线充电运行状态信息包括该设备70的充电模式，则上述控制器701用于根据该设备70的充电模式，控制上述可切换电容单元，以切换该变换电路20的整流模式。示例性地，若该设备70的充电模式可以包括但不限于：扩展功率等级(Extended Power Profile，EPP)模式、基准功率等级(Baseline Power Profile，BPP)模式，或者私有快充模式，则上述控制器701用于根据上述预设电压阈值和上述预设端电压，控制上述可切换电容单元，以切换该整流器21的整流模式，从而可以保证该设备的输出电压的稳定性。
具体的方式可以参考上述可能的实现方式中的相关内容，此处不再赘述。综上所述，本申请实施例提供的该设备70通过切换上述整流器21的整流模式，可以调整该设备70的输出电压，以满足供电需求。
另一种可能的实现方式中，本申请实施例中涉及的无线充电设备用于发送无线充电信号，则上述无线充电设备为上述无线充电发射器1，其中，无线充电发射器1可以包括但不限于：逆变器11和谐振电路14。
为了便于理解，在上述实施例的基础上，本申请实施例中以上述图2A所示变换电路20为上述逆变器11，以及谐振电路14包括发射线圈13和谐振电容12为例，对本申请实施例提供的无线充电设备的可实现方式进行介绍。
图7B为本申请实施例提供的无线充电设备的结构示意图二，如图7B所示，本申请实施例提供的无线充电设备80可以包括但不限于：上述谐振电路14、上述逆变器11和控制器801。其中，控制器801与上述逆变器11耦合连接，用于控制上述逆变器11中的信号变换单元201和可切换电容单元202。示例性地，控制器801可以与上述信号变换单元201中的单向导通半导体管的栅极连接，以及与上述可切换电容单元202中的开关和单向导通半导体管的栅极连接。其中，上述逆变器11的第二端b和第四端d是该逆变器11的输入端。上述逆变器11中的第一端a和第三端c作为输出端分别耦合在谐振电路14的两端，以便于谐振电路14将上述逆变器11所输出的电信号转换成电磁信号并发射该电磁信号。
本申请实施例中，上述控制器801用于控制上述逆变器11中的可切换电容单元202，以切换该逆变器11的逆变模式；其中，该逆变模式包括：上述分压逆变模式，或者上述全桥逆变模式。应理解，该控制器801还用于控制上述信号变换单元201中的各单向导通半导体管的导通或关断。具体地，该控制器801通过控制上述可切换电容单元202中的上述单向导通半导体管和/或上述开关的导通或关断，以切换该逆变器11的逆变模式。示例性地，上述控制器801用于根据该设备80的无线充电运行状态信息，控制上述可切换电容单元，以切换该逆变器11的逆变模式。
一种可能的实现方式，若该无线充电运行状态信息包括逆变器11的预设端电压，则上 述控制器801用于根据预设电压阈值和该预设端电压，控制上述可切换电容单元，以切换该逆变器11的逆变模式。可选地，该预设端电压可以包括但不限于：该逆变器11的输入端的输入电压，或者逆变器11的输出端的输出电压。
示例性地，若该预设端电压大于该预设电压阈值，则上述控制器801用于控制上述可切换电容单元202中的上述单向导通半导体管和/或上述开关的导通或关断，使得该逆变器11处于分压逆变模式，使得逆变器11的输出端的输出电压可以小于其输入端的输入电压，从而可以保证接收端的接收线圈可以耦合到符合上述预设耦合电压范围的电压。
又一示例性地，若该预设端电压不大于该预设电压阈值，则上述控制器801用于控制上述可切换电容单元202中的上述单向导通半导体管和/或上述开关的导通或关断，使得该逆变器11处于全桥逆变模式，使得逆变器11的输出端的输出电压几乎等于其输入端的输入电压，从而可以尽量保证接收端的接收线圈可以耦合到符合预设耦合电压范围的电压。
当然，上述控制器801根据该设备80的无线充电运行状态信息，还可以通过其它可实现方式，控制上述可切换电容单元，以切换该逆变器11的逆变模式。综上所述，本申请实施例提供的该设备80通过切换上述逆变器11的逆变模式，可以调整该设备80的输出电压，以满足接收端的接收线圈所需耦合的电压。
以上的实施方式、结构示意图仅为示意性说明本申请的技术方案，其中的尺寸比例等并不构成对该技术方案保护范围的限定，任何在上述实施方式的精神和原则之内所做的修改、等同替换和改进等，均应包含在该技术方案的保护范围之内。

Claims (31)

  1. 一种整流器，其特征在于，包括：信号变换单元和可切换电容单元；
    所述信号变换单元包括第一端、第二端、第三端、第四端、第一单向导通半导体管、第二单向导通半导体极管、第三单向导通半导体管和第四单向导通半导体管，所述第一单向导通半导体管的输出端与所述第二单向导通半导体管的输入端耦合至所述第一端，所述第二单向导通半导体管的输出端与所述第三单向导通半导体管的输出端耦合至第二端，所述第四单向导通半导体管的输出端与所述第三单向导通半导体管的输入端耦合至所述第三端，所述第一单向导通半导体管的输入端和所述第四单向导通半导体管的输入端耦合至所述第四端，所述第一端和所述第三端用于耦合至谐振电路，所述第四端用于耦合至恒定电压；
    所述可切换电容单元，耦合在所述第一端和所述第三端中的至少一个、所述第二端和所述第四端；
    其中，所述第一端和所述第三端是所述整流器的输入端，所述第二端和所述第四端是所述整流器的输出端。
  2. 根据权利要求1所述的整流器，其特征在于，所述可切换电容单元包括第一开关和电容单元，所述第一开关耦合在所述第三端和中间节点之间，所述电容单元耦合在所述第二端、所述第四端和所述中间节点。
  3. 根据权利要求2所述的整流器，其特征在于，所述电容单元包括：第一电容和第二电容，所述第一电容耦合在所述中间节点和所述第二端之间，所述第二电容耦合在所述中间节点和所述第四端之间。
  4. 根据权利要求3所述的整流器，其特征在于，所述电容单元还包括：第三电容，所述第三电容耦合在所述第二端和所述第四端之间。
  5. 根据权利要求2所述的整流器，其特征在于，所述电容单元包括：第一电容和第二电容，所述第一电容耦合在所述中间节点和预设位置之间，所述第二电容耦合在所述第二端和所述第四端之间。
  6. 根据权利要求1所述的整流器，其特征在于，所述可切换电容单元包括第一开关、第一电容和第二电容，所述第一电容耦合在所述第三端和中间节点之间，所述第一开关耦合在所述中间节点和预设位置之间，所述第二电容耦合在所述第二端和所述第四端之间。
  7. 根据权利要求5或6所述的整流器，其特征在于，所述预设位置包括以下任一项：所述第二端、所述第四端、或预设电压。
  8. 根据权利要求2-7中任一项所述的整流器，其特征在于，所述可切换电容单元还包括：第一切换单元和第二切换单元，所述第一切换单元耦合在所述中间节点和所述第一端之间，所述第二切换单元耦合在所述第四端和所述谐振电路之间。
  9. 根据权利要求8所述的整流器，其特征在于，所述第一切换单元包括：第五单向导通半导体管和第二开关；
    所述第二开关耦合在所述中间节点和所述第五单向导通半导体管的输入端之间，所述第五单向导通半导体管的输出端耦合在所述第一端；或者，所述第五单向导通半导体管的输入端耦合在所述中间节点，所述第二开关耦合在所述第一端和所述第五单向单向半导体管的输出端之间。
  10. 根据权利要求8或9所述的整流器，其特征在于，所述第二切换单元包括：第六单向导通半导体管和第三开关；
    所述第三开关耦合在所述第四端和所述第六单向导通半导体管的输入端之间，所述第六单向导通半导体管的输出端耦合在所述谐振电路；或者，所述第六单向导通半导体管的输入端耦合在所述第四端，所述第三开关耦合在所述第六单向导通半导体管的输出端和所述谐振电路之间。
  11. 根据权利要求1-10中任一项所述的整流器，其特征在于，所述恒定电压是接地电压。
  12. 根据权利要求1-11中任一项所述的整流器，其特征在于，每个单向导通半导体管是二极管，所述二极管的输入端是阳极，所述二极管的输出端是阴极。
  13. 根据权利要求1-11中任一项所述的整流器，其特征在于，每个单向导通半导体管是金属-氧化物-半导体MOS管，所述MOS管的栅极接收控制信号以阻止电流进入所述MOS管的输出端。
  14. 根据权利要求1-13中任一项所述的整流器，其特征在于，还包括：辅助升压电路，所述辅助升压电路耦合在所述第一端和所述第二端之间，用于对所述第一端的电压进行升压处理。
  15. 一种无线充电设备，其特征在于，所述设备用于接收无线充电信号，所述设备包括：如权利要求1-14中任一项所述的整流器和所述谐振电路。
  16. 根据权利要求15所述的设备，其特征在于，所述设备还包括：控制器，用于控制所述可切换电容单元，以切换所述整流器的整流模式；
    其中，所述整流模式包括：倍压整流模式，或者全桥整流模式。
  17. 根据权利要求15或16所述的设备，其特征在于，所述设备还包括：耦合在所述第二端和所述第四端之间的充电管理单元，用于将所述整流器的输出端的输出电压进行电压转换，以匹配电能存储单元的存储电压。
  18. 一种逆变器，其特征在于，包括：信号变换单元和可切换电容单元；
    所述信号变换单元包括第一端、第二端、第三端、第四端、第一单向导通半导体管、第二单向导通半导体极管、第三单向导通半导体管和第四单向导通半导体管，所述第一单向导通半导体管的输入端与所述第二单向导通半导体管的输出端耦合至所述第一端，所述第二单向导通半导体管的输入端与所述第三单向导通半导体管的输入端耦合至第二端，所述第四单向导通半导体管的输入端与所述第三单向导通半导体管的输出端耦合至所述第三端，所述第一单向导通半导体管的输出端和所述第四单向导通半导体管的输出端耦合至所述第四端，所述第一端和所述第三端用于耦合至谐振电路，所述第四端用于耦合至恒定电压；
    所述可切换电容单元，耦合在所述第一端和所述第三端中的至少一个、所述第二端和所述第四端；
    其中，所述第一端和所述第三端是所述逆变器的输出端，所述第二端和所述第四端是所述逆变器的输入端。
  19. 根据权利要求18所述的逆变器，其特征在于，所述可切换电容单元包括第一开关和电容单元，所述第一开关耦合在所述第三端和中间节点之间，所述电容单元耦合在所述第二端、所述第四端和所述中间节点。
  20. 根据权利要求19所述的逆变器，其特征在于，所述电容单元包括：第一电容和第二电容，所述第一电容耦合在所述中间节点和所述第二端之间，所述第二电容耦合在所述中间节点和所述第四端之间。
  21. 根据权利要求20所述的逆变器，其特征在于，所述电容单元还包括：第三电容，所述第三电容耦合在所述第二端和所述第四端之间。
  22. 根据权利要求19所述的逆变器，其特征在于，所述电容单元包括：第一电容和第二电容，所述第一电容耦合在所述中间节点和预设位置之间，所述第二电容耦合在所述第二端和所述第四端之间。
  23. 根据权利要求18所述的逆变器，其特征在于，所述可切换电容单元包括第一开关、第一电容和第二电容，所述第一电容耦合在所述第三端和中间节点之间，所述第一开关耦合在所述中间节点和预设位置之间，所述第二电容耦合在所述第二端和所述第四端之间。
  24. 根据权利要求22或23所述的逆变器，其特征在于，所述预设位置包括以下任一项：所述第二端、所述第四端、或预设电压。
  25. 根据权利要求19-24中任一项所述的逆变器，其特征在于，所述可切换电容单元还包括：第一切换单元和第二切换单元，所述第一切换单元耦合在所述中间节点和所述第一端之间，所述第二切换单元耦合在所述第四端和所述谐振电路之间。
  26. 根据权利要求25所述的逆变器，其特征在于，所述第一切换单元包括：第五单向导通半导体管和第二开关；
    所述第二开关耦合在所述中间节点和所述第五单向导通半导体管的输入端之间，所述第五单向导通半导体管的输出端耦合在所述第一端；或者，所述第五单向导通半导体管的输入端耦合在所述中间节点，所述第二开关耦合在所述第一端和所述第五单向导通半导体管的输出端之间。
  27. 根据权利要求25或26所述的逆变器，其特征在于，所述第二切换单元包括：第六单向导通半导体管和第三开关；
    所述第三开关耦合在所述第四端和所述第六单向导通半导体管的输入端之间，所述第六单向导通半导体管的输出端耦合在所述谐振电路；或者，所述第六单向导通半导体管的输入端耦合在所述第四端，所述第三开关耦合在所述第六单向导通半导体管的输出端和所述谐振电路之间。
  28. 根据权利要求18-27中任一项所述的逆变器，其特征在于，所述恒定电压是接地电压。
  29. 根据权利要求18-27中任一项所述的逆变器，其特征在于，每个单向导通半导体管是金属-氧化物-半导体MOS管，所述MOS管的栅极接收控制信号以阻止电流进入所述MOS管的输出端。
  30. 一种无线充电设备，其特征在于，所述设备用于发送无线充电信号，所述设备包括：如权利要求18-29中任一项所述的逆变器和所述谐振电路。
  31. 根据权利要求30所述的设备，其特征在于，所述设备还包括：控制器，用于控制所述可切换电容单元，以切换所述逆变器的逆变模式；
    其中，所述逆变模式包括：分压逆变模式，或者全桥逆变模式。
PCT/CN2019/119991 2019-11-21 2019-11-21 整流器、逆变器及无线充电设备 WO2021097763A1 (zh)

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