WO2022016988A1 - 显示面板母板及制备方法 - Google Patents

显示面板母板及制备方法 Download PDF

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Publication number
WO2022016988A1
WO2022016988A1 PCT/CN2021/095719 CN2021095719W WO2022016988A1 WO 2022016988 A1 WO2022016988 A1 WO 2022016988A1 CN 2021095719 W CN2021095719 W CN 2021095719W WO 2022016988 A1 WO2022016988 A1 WO 2022016988A1
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WIPO (PCT)
Prior art keywords
layer
test
display panel
mother substrate
area
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PCT/CN2021/095719
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English (en)
French (fr)
Inventor
杨凯
崔雪
刘明星
李伟丽
李文星
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昆山国显光电有限公司
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Application filed by 昆山国显光电有限公司 filed Critical 昆山国显光电有限公司
Publication of WO2022016988A1 publication Critical patent/WO2022016988A1/zh
Priority to US17/868,027 priority Critical patent/US20220352264A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/88—Dummy elements, i.e. elements having non-functional features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/70—Testing, e.g. accelerated lifetime tests

Definitions

  • the present application belongs to the technical field of electronic products, and particularly relates to a display panel motherboard and a preparation method.
  • OLED Organic Light Emitting Display
  • flat panel display devices are widely used in mobile phones, TVs, personal digital assistants due to their advantages of high image quality, power saving, thin body and wide application range.
  • digital cameras, notebook computers, desktop computers and other consumer electronic products have become the mainstream of display devices.
  • the embodiments of the present application provide a display panel motherboard and a preparation method.
  • a light-dark contrast is generated with the target test layer to display the actual position outline of the target test layer, so as to accurately obtain the actual position of the target test layer. Determines the positional accuracy when the target test layer is formed.
  • an embodiment of the present application provides a display panel motherboard, the display panel motherboard has a display panel forming area distributed in an array and a test area adjacent to the display panel forming area, including: an array motherboard a substrate; a light-emitting layer, disposed on one side surface of the array mother substrate and located in each of the display panel forming areas; a test component, disposed on the surface of the array mother substrate and located in the test area, the test component It includes a test block, and the test block includes: a phosphor layer, which is arranged on the surface of the array mother substrate, and the phosphor layer can emit light after being irradiated by activation light; a target test layer is arranged on the phosphor layer facing away from the one side of the surface, and the orthographic projection of the phosphor layer on the test area covers the orthographic projection of the target test layer on the test area; the positioning reference part is provided on the outer peripheral side of the target test layer.
  • the display panel motherboard provided by the embodiment of the present application includes an array motherboard, a light-emitting layer, and a test assembly, and a test block of the test assembly includes a phosphor layer, a target test layer, and a positioning reference portion.
  • the predetermined setting position of the target test layer can be determined by the positioning reference part, and then the phosphor layer and the target test layer are formed. Since the target test layer itself does not emit light, the actual setting position of the target test layer cannot be accurately determined, so the target test layer is close to the array mother.
  • a phosphor layer is provided on one side of the substrate.
  • the phosphor layer can emit light after being irradiated by the activation light, and the orthographic projection of the phosphor layer in the test area covers the orthographic projection of the target test layer in the test area, so that the phosphor layer and the target test layer can produce light and dark contrast when emitting light to make the target test layer's orthographic projection.
  • the actual position outline is displayed to facilitate the accurate acquisition of the actual position of the target test layer. Compare the actual position of the target test layer with the predetermined setting position of the target test layer determined by the positioning reference part, determine the position accuracy of the target test layer when forming, provide data reference for the formation of the light-emitting layer in the display panel formation area, and improve the formation of the light-emitting layer. position accuracy.
  • FIG. 1 is a schematic structural diagram of a display panel motherboard according to an embodiment of the present application
  • Fig. 2 is the partial enlarged schematic diagram of Q region in Fig. 1;
  • FIG. 3 is a schematic structural diagram of an example of a test block according to an embodiment of the present application.
  • Fig. 4 is the film structure diagram at C in Fig. 2;
  • Fig. 5 is the film layer structure diagram of the test block of the embodiment of the present application.
  • FIG. 6 is a flowchart of a method for manufacturing a display panel motherboard according to an embodiment of the present application.
  • FIG. 7 is a flowchart of an accuracy detection step in an embodiment of the present application.
  • Fig. 1 shows a schematic structural diagram of a display panel motherboard according to an embodiment of the present application
  • Fig. 2 shows a partially enlarged schematic diagram of the Q area in Fig. 1
  • Fig. 3 shows a schematic diagram of a test block according to an embodiment of the present application Schematic. As shown in FIGS.
  • an embodiment of the present application provides a display panel motherboard, the display panel motherboard has a display panel forming area B distributed in an array and a test area A adjacent to the display panel forming area B, It includes: an array mother substrate 1; a light-emitting layer 2, which is arranged on one side surface of the array mother substrate 1 and located in each display panel forming area B; a test component 30, which is arranged on the surface of the array mother substrate 1 and located in the testing area A, and the testing component 30 A test block 3 is included, and the test block 3 includes: a fluorescent layer 31 arranged on the surface of the array mother substrate 1, the fluorescent layer 31 can emit light after being irradiated by activation light; a target test layer 32 is arranged on the side of the fluorescent layer 31 that faces away from the surface , and the orthographic projection of the phosphor layer 31 in the test area A covers the orthographic projection of the target test layer 32 in the test area A;
  • the display panel motherboard provided in the embodiment of the present application includes an array motherboard 1 , a light-emitting layer 2 and a test assembly 30 , and a test block 3 of the test assembly 30 includes the phosphor layer 31 , the target test layer 32 and the positioning reference portion 33.
  • the predetermined setting position of the target test layer 32 can be determined by the positioning reference portion 33 , and then the phosphor layer 31 and the target test layer 32 are formed. Since the target test layer 32 itself does not emit light, the actual location of the target test layer 32 cannot be accurately determined. Therefore, the fluorescent layer 31 is provided on the side of the target test layer 32 close to the array mother substrate 1 .
  • the fluorescent layer 31 can emit light after being irradiated by the activation light, and the orthographic projection of the fluorescent layer 31 in the test area A covers the orthographic projection of the target test layer 32 in the test area A, so that the fluorescent layer 31 and the target test layer 32 are bright and dark when emitting light. By comparison, the actual position outline of the target test layer 32 is displayed, so that the actual position of the target test layer 32 can be accurately obtained.
  • test area A and the display panel forming area B are arranged adjacent to each other.
  • the test area A may be set around the display panel formation area B, or may be set only on one side of the display panel formation area B.
  • the area of the test area A is usually smaller than or equal to the area of the display panel formation area B.
  • the array mother substrate 1 can be a substrate with a substrate and a substrate with some layer structures formed on the substrate at any stage in the process of the display panel motherboard. This application does not limit its specific structure.
  • the array mother substrate 1 may specifically include a device layer and a substrate, and the device layer refers to some functional film layers formed on the substrate, for example, the source, gate, and drain of a thin film transistor.
  • the corresponding test area A can form some test components 30 similar to the functional film layer of the device layer. By testing these test components 30 in the test area A, the positional accuracy of the light-emitting layer 2 in the display panel forming area B or other characteristic.
  • the light-emitting layer 2 includes an electron injection layer, an electron transport layer, an organic light-emitting layer, a hole transport layer, and a hole injection layer;
  • the fluorescent layer 31 includes a material constituting an electron injection layer, a material constituting an electron transport layer at least one of the material, the material constituting the organic light-emitting layer, the material constituting the hole transport material layer, and the material constituting the hole injection layer.
  • the materials constituting the electron injection layer, the electron transport layer, the organic light-emitting layer, the hole transport layer, and the hole injection layer generally include fluorescent materials, which can emit light under activation light. Therefore, in order to reduce the process and material cost, the fluorescent layer 31 can be formed by using the materials constituting the electron injection layer, the electron transport layer, the organic light-emitting layer, the hole transport layer or the hole injection layer, because the fluorescent layer 31 does not need to realize functions such as display. , so only one layer needs to be set, which can emit light under the activation light.
  • the light-emitting layer 2 has a first display area and a second display area at least partially surrounding the first display area.
  • the pixel density of the first display area is less than the pixel density of the second display area;
  • the test assembly 30 includes a plurality of test blocks 3; some of the test blocks 3 in the plurality of test blocks 3 form a first test group, and the distribution density of the test blocks 3 in the first test group is the same as that of the first display
  • the pixel density of the area is the same; another part of the test blocks 3 in the plurality of test blocks 3 forms a second test group, and the distribution density of the test blocks 3 in the second test group is the same as the pixel density of the second display area.
  • the first display area is usually provided with optical devices, and the pixel density of the first display area is set to be smaller than that of the second display area, in order to improve the light transmission area of In the lower optical device scheme, the optical device is arranged in the first display area, which can increase the amount of light received by the optical device.
  • the test assembly 30 includes a plurality of test blocks 3; some of the test blocks 3 are tested
  • the block 3 forms a first test group, and the distribution density of the test blocks 3 in the first test group is the same as the pixel density of the first display area; another part of the test blocks 3 in the plurality of test blocks 3 forms a second test group, and the second test group
  • the distribution density of the middle test block 3 is the same as the pixel density of the second display area.
  • the entire test assembly 30 does not only have one test block 3, but has a plurality of test blocks 3, and the measured data samples are more. Through data processing methods such as averaging, it can effectively improve the formation of the target test layer 32. position accuracy. And the distribution densities of the test blocks 3 in the first test group and the test blocks 3 in the second test group are set to be the same as the pixel densities of the first display area and the second display area, respectively, so as to truly simulate the distribution density of each pixel of the light-emitting layer 2.
  • the layer may be a patterned film layer such as a cathode layer, an anode layer, and the like.
  • the positioning reference portion 33 includes a first positioning component and a second positioning component that are spaced apart from each other, and the first positioning component includes at least one first positioning portion 331 .
  • 331 is cross-shaped
  • the second positioning component includes a plurality of second positioning portions
  • the second positioning portions 332 are in-line.
  • the first positioning portion 331 is in the shape of a cross, specifically, to facilitate the positioning of the test assembly 30 by the external image acquisition portion used for testing.
  • the second positioning assembly includes at least two second positioning portions 332 , and the second positioning portions 332 are in a line shape to determine the preset formation position of the target test layer 32 .
  • the two second positioning portions can be The intersection points of the extension lines 332 along the first direction and the second direction respectively are set as the preset center point of the target test layer 32 , wherein the first direction and the second direction are perpendicular to each other.
  • the three second positioning portions 332 are distributed in a zigzag shape to determine the setting angle of the target test layer 32 relative to the array mother substrate 1 .
  • the target test layer 32 includes a cathode material layer, and the edge of the projection of the cathode material layer on the array mother substrate 1 reaches the edge of the phosphor layer 31 on the array mother substrate 1 .
  • the distances of the projected edges are equal everywhere, and at least one second positioning portion 332 is disposed at a position of the array mother substrate 1 close to each edge of the cathode material layer.
  • the target test layer 32 includes a cathode material layer
  • the cathode material layer specifically refers to a film layer made of the same material as the cathode layer of the light-emitting layer 2. Since the cathode layer of the light-emitting layer 2 uses a fine mask (FMM) To perform vapor deposition, it is necessary to measure the positional accuracy of the vapor deposition of the cathode layer. Therefore, the cathode material layer is used for evaporation, and the evaporation of the cathode layer of the light-emitting layer 2 is simulated to determine the positional accuracy of evaporation when a fine mask is used. The positional accuracy of the layer evaporation meets the requirements.
  • FMM fine mask
  • the projection of the cathode material layer on the array mother substrate 1 is a square, and the projection of the square cathode material layer on the array mother substrate 1
  • the distances from the edge of the phosphor layer 31 to the projected edge of the phosphor layer 31 on the array mother substrate 1 are equal everywhere, that is, the phosphor layer 31 is a square whose side length is longer than that of the cathode material layer, and the center points of the two coincide.
  • At least one second positioning portion 332 is provided on each edge of the cathode material layer close to the cathode material layer, that is, at least one second positioning portion 332 is correspondingly provided on the outer edges of the four sides of the cathode material layer, and the second positioning portion 332 is raised. The accuracy of the determined predetermined evaporation position of the cathode material layer.
  • the anode material layer 4 further includes an anode material layer 4 disposed on the side of the fluorescent layer 31 facing away from the target test layer 32 , and the orthographic projection of the anode material layer 4 in the test area A covers the fluorescent layer 31 Orthographic projection on test area A.
  • the anode material layer 4 specifically refers to a film layer made of the same material as the anode layer of the light-emitting layer 2 to simulate the anode layer of the light-emitting layer 2, and the anode material layer 4 is in the test area A.
  • the orthographic projection covers the orthographic projection of the phosphor layer 31 in the test area A, that is, during the test, the anode material layer 4 serves as the substrate of the entire test assembly 30 to highlight the phosphor layer 31 and the target test layer 32 .
  • the positioning reference portion 33 is a pixel definition material, that is, a portion made of the same material as the pixel definition layer of the light-emitting layer 2 .
  • an embodiment of the present application further provides a method for preparing a display panel motherboard, which is applied to the above-mentioned display panel motherboard, including:
  • S110 Provide an array mother substrate 1;
  • S130 forming a fluorescent layer 31 in an area defined by the positioning reference portion 33, and the fluorescent layer 31 can emit light after being irradiated with activation light;
  • the array mother substrate 1 is a substrate having a substrate at any stage in the manufacturing process of the display panel mother plate and some layer structures are formed on the substrate. This application does not limit its specific structure.
  • the positioning reference portion 33 is formed in the test area A of the array mother substrate 1 , and the purpose of setting the positioning reference portion 33 is to determine the predetermined formation position of the target test layer 32 after the setting position of the positioning reference portion 33 is determined.
  • the fluorescent layer 31 since the fluorescent layer 31 needs to emit light to highlight the target test layer 32, and the formation position of the target test layer 32 is determined by the positioning reference part 33, the fluorescent layer 31 is arranged in the area limited by the positioning reference part 33, So that the target test layer 32 can be disposed on the phosphor layer 31 later.
  • the target test layer 32 is formed on the side of the fluorescent layer 31 away from the array mother substrate 1. Specifically, the orthographic projection of the fluorescent layer 31 in the test area A covers the front side of the target test layer 32 in the test area A. Projection is performed to ensure that the fluorescent layer 31 can highlight the target test layer 32 when it emits light, so as to accurately determine the actual position of the target test layer 32 .
  • the fluorescent layer 31 is formed on the side of the target test layer 32 close to the array mother substrate 1, and the fluorescent layer 31 can emit light after being irradiated by the activation light, so that the fluorescent layer 31 can emit light.
  • 31 produces a light-dark contrast with the target test layer 32 when emitting light to display the actual position outline of the target test layer 32, so as to accurately obtain the actual position of the target test layer 32, and determine the actual position of the target test layer 32 with the positioning reference part 33.
  • the preset formation positions of the target test layer 32 are compared to determine the positional accuracy of the target test layer 32 when the target test layer 32 is formed.
  • the accuracy detection step includes:
  • S220 Calculate the preset position parameter of the target test layer 32 according to the reference position parameter
  • S240 Obtain the second image of the test area A, and obtain the actual position parameter of the target test layer 32 according to the second image;
  • the image acquisition unit may be used to acquire the first image of the test area A of the display panel motherboard, and the reference position parameters of the positioning reference unit 33 may be acquired according to the first image, and the image acquisition unit may specifically be an industrial camera capable of shooting
  • the reference position parameter of the positioning reference portion 33 may specifically be the abscissa and ordinate values of the positioning reference portion 33 relative to a zero point position set on the array mother substrate 1 .
  • the preset position parameter of the target test layer 32 of the display panel motherboard is calculated according to the reference position parameter, and the specific reference position parameter includes the reference abscissa value and the reference ordinate value. According to the reference abscissa value and the reference ordinate The coordinate value obtains the preset position parameter.
  • the reference abscissa value and the reference ordinate value do not refer to the coordinate value of the same positioning reference part 33, but the reference abscissa value of one positioning reference part 33 and the other
  • the reference ordinate value of the positioning reference part 33 that is, one positioning reference part 33 is used to determine the abscissa in the preset position parameter of the target test layer 32
  • the other positioning reference part 33 is used to determine the preset position of the target test layer 32 .
  • the vertical coordinate in the position parameter, the combination of the two is the coordinate of the center point of the target test layer 32 .
  • the phosphor layer 31 of the display panel motherboard is irradiated with activation light, so that the phosphor layer 31 emits light, and the activation light can be a light source such as red light or blue light.
  • the actual position parameter of the target test layer 32 of the display panel motherboard is obtained according to the second image. Ordinate value.
  • the preset position parameter and the actual position parameter of the target test layer 32 are compared to obtain the position accuracy parameter of the target test layer 32 .
  • components such as a fine mask used to form the target test layer 32 can be adjusted through the position accuracy parameter to adjust the position accuracy of the target test layer 32 during formation, so that it can meet the production requirements.
  • the fluorescent layer 31 is arranged to generate a light-dark contrast with the target test layer 32, so as to display the actual position outline of the target test layer 32, so as to facilitate the accurate acquisition of the target test layer
  • the actual position parameters of the target test layer 32 are compared with the preset position parameters of the target test layer 32 determined by the positioning reference unit 33 to accurately determine the position accuracy parameters of the target test layer 32 when the target test layer 32 is formed.
  • the method further includes: forming a light-emitting layer 2 on a surface of one side of the array mother substrate 1 corresponding to each display panel forming area B.
  • the positional accuracy of the target test layer 32 can be determined through the precision detection step before, and the position of the target test layer 32 can be adjusted by adjusting components such as a fine mask used to form the target test layer 32. Then use the fine mask and other components that meet the requirements to form the light-emitting layer 2 on the surface of the array mother substrate 1 corresponding to each display panel forming area B, so as to improve the corresponding film of the light-emitting layer 2 Positional accuracy of layer formation.

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Abstract

本申请公开了一种显示面板母板及制备方法，显示面板母板具有呈阵列分布的显示面板形成区域及与显示面板形成区域相邻的测试区域，包括：阵列母基板；发光层，设于阵列母基板一侧表面且位于各显示面板形成区域设置；测试组件，设于阵列母基板的表面且位于测试区域设置，测试组件包括测试块，测试块包括：荧光层，设置于阵列母基板的表面，荧光层被激活光线照射后可发光；目标测试层，设置于荧光层背向表面的一侧；定位基准部，设于目标测试层的外周侧。荧光层在发光时与目标测试层产生明暗对比以将目标测试层的实际位置轮廓显示出来，便于准确获取目标测试层的实际位置。

Description

显示面板母板及制备方法
相关申请的交叉引用
本申请要求享有于2020年07月24日提交的名称为“显示面板母板及制备方法”的中国专利申请第202010728399.0号的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本申请属于电子产品技术领域，尤其涉及一种显示面板母板及制备方法。
背景技术
有机发光二极管(Organic Light Emitting Display，OLED)显示装置作为平面显示装置，因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
现有OLED产品因有屏下摄像功能要求，对于OLED屏体透过率提升日趋严峻，现阶段大部门公司因对阴极进行整面蒸镀会导致屏体透过率低，难以达成屏下摄像设计需求。因此需要使用精细掩膜板(Fine Metal Mask，FMM)进行蒸镀阴极。但若使用FMM进行蒸镀阴极，由于在线监控FMM位置精度时需使用荧光下抓取位置测量点位，而阴极在荧光下不发光，所以目前的测量点位方案无法测量阴极蒸镀的位置精度。
因此，亟需一种新的显示面板母板及制备方法。
发明内容
本申请实施例提供了一种显示面板母板及制备方法，荧光层在发光时与目标测试层产生明暗对比以将目标测试层的实际位置轮廓显示出来，便于准确获取目标测试层的实际位置，确定目标测试层形成时的位置精度。
第一方面，本申请实施例提供了一种显示面板母板，所述显示面板母板具有呈阵列分布的显示面板形成区域及与所述显示面板形成区域相邻的测试区域，包括：阵列母基板；发光层，设于所述阵列母基板一侧表面且位于各所述显示面板形成区域；测试组件，设于所述阵列母基板的所述表面且位于所述测试区域，所述测试组件包括测试块，所述测试块包括：荧光层，设置于所述阵列母基板的所述表面，所述荧光层被激活光线照射后可发光；目标测试层，设置于所述荧光层背向所述表面的一侧，且所述荧光层在所述测试区域的正投影覆盖所述目标测试层在所述测试区域的正投影；定位基准部，设于所述目标测试层的外周侧。
本申请实施例提供的显示面板母板包括阵列母基板、发光层以及测试组件，测试组件的测试块包括荧光层、目标测试层以及定位基准部。通过定位基准部能够确定目标测试层的预定设置位置，之后形成荧光层和目标测试层，由于目标测试层自身不发光，无法准确确定目标测试层的实际设置位置，因而在目标测试层靠近阵列母基板的一侧设置荧光层。荧光层被激活光线照射后可发光，且荧光层在测试区域的正投影覆盖目标测试层在测试区域的正投影，以使荧光层在发光时与目标测试层产生明暗对比以将目标测试层的实际位置轮廓显示出来，便于准确获取目标测试层的实际位置。将目标测试层的实际位置与定位基准部确定目标测试层的预定设置位置进行比较，确定目标测试层形成时的位置精度，为之后在显示面板形成区域形成发光层提供数据参考，提高发光层形成的位置精度。
附图说明
图1是根据本申请实施例的显示面板母板的结构示意图；
图2是图1中Q区域的局部放大示意图；
图3是本申请实施例的测试块的示例的结构示意图；
图4是图2中C处的膜层结构图；
图5是本申请实施例的测试块的膜层结构图；
图6是根据本申请实施例的显示面板母板的制备方法的流程图；
图7是本申请实施例的精度检测步骤的流程图。
具体实施方式
下面将详细描述本申请的各个方面的特征和示例性实施例，为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及具体实施例，对本申请进行进一步详细描述。应理解，此处所描述的具体实施例仅意在解释本申请，而不是限定本申请。对于本领域技术人员来说，本申请可以在不需要这些具体细节中的一些细节的情况下实施。下面对实施例的描述仅仅是为了通过示出本申请的示例来提供对本申请更好的理解。
为了更好地理解本申请，下面结合图1至图7根据本申请实施例的显示面板母板及制备方法进行详细描述。
图1示出了本申请实施例的一种显示面板母板的结构示意图；图2示出了图1中Q区域的局部放大示意图；图3示出了本申请实施例的一种测试块的结构示意图。如图1至图3所示，本申请实施例提供了一种显示面板母板，显示面板母板具有呈阵列分布的显示面板形成区域B及与显示面板形成区域B相邻的测试区域A，包括：阵列母基板1；发光层2，设于阵列母基板1一侧表面且位于各显示面板形成区域B；测试组件30，设于阵列母基板1的表面且位于测试区域A，测试组件30包括测试块3，测试块3包括：荧光层31，设置于阵列母基板1的表面，荧光层31被激活光线照射后可发光；目标测试层32，设置于荧光层31背向表面的一侧，且荧光层31在测试区域A的正投影覆盖目标测试层32在测试区域A的正投影；定位基准部33，设于目标测试层32的外周侧。
本申请实施例提供的显示面板母板包括阵列母基板1、发光层2以及测试组件30，测试组件30的测试块3包括所述荧光层31、所述目标测试层32以及所述定位基准部33。通过所述定位基准部33能够确定目标测试层32的预定设置位置，之后形成所述荧光层31和目标测试层32。由于目标测试层32自身不发光，无法准确确定目标测试层32的实际设置位置，因而在目标测试层32靠近阵列母基板1的一侧设置荧光层31。荧光层31被激活光线照射后可发光，且荧光层31在测试区域A的正投影覆盖目标测试层32在测试区域A的正投影，以使荧光层31在发光时与目标测试层32 产生明暗对比以将目标测试层32的实际位置轮廓显示出来，便于准确获取目标测试层32的实际位置。将目标测试层的实际位置与定位基准部33确定目标测试层32的预定设置位置进行比较，确定目标测试层32形成时的位置精度，为之后在显示面板形成区域B形成发光层2提供数据参考，提高发光层2形成的位置精度。
需要说明的是，如图2中所示，图2是图1中Q区域的局部放大示意图，测试区域A和与显示面板形成区域B相邻设置。具体是指，测试区域A可以围绕显示面板形成区域B设置，也可以只在显示面板形成区域B的某一侧设置，测试区域A的面积通常小于或等于显示面板形成区域B的面积。
阵列母基板1可以为显示面板母板制程中任意阶段的具有衬底的以及在衬底上形成一些层结构的基板。对于其具体的结构本申请不做限制。阵列母基板1具体可以包括器件层和衬底，器件层是指形成在衬底上的一些功能膜层，例如，可以为薄膜晶体管的源极、栅极、漏极等。对应的测试区域A可以形成一些与器件层的功能膜层类似的测试组件30，通过对测试区域A的这些测试组件30进行测试，以反映显示面板形成区域B的发光层2的位置精度或者其他特性。
在一些可选的实施例中，发光层2包括电子注入层、电子传输层、有机发光层、空穴传输层、空穴注入层；荧光层31包括构成电子注入层的材料、构成电子传输层的材料、构成有机发光层的材料、构成空穴传输材料层的材料及构成空穴注入层的材料中的至少一者。
需要说明的是，构成电子注入层、电子传输层、有机发光层、空穴传输层、空穴注入层的材料中通常均具有荧光材料，本身可以在激活光线下发光。因而，为了降低工艺以及材料成本，可以采用构成电子注入层、电子传输层、有机发光层、空穴传输层或空穴注入层的材料形成荧光层31，由于荧光层31不需要实现显示等功能，因而只需设置一层，能够在激活光线下发光即可。
为了进一步提高测试组件30测试的精准度，在一些可选的实施例中，发光层2具有第一显示区域和至少部分环绕第一显示区域设置的第二显示 区域，第一显示区域的像素密度小于第二显示区域的像素密度；测试组件30包括多个测试块3；多个测试块3中部分测试块3形成第一测试组，第一测试组中测试块3的分布密度与第一显示区域的像素密度相同；多个测试块3中另一部分测试块3形成第二测试组，第二测试组中测试块3的分布密度与第二显示区域的像素密度相同。
可以理解的是，第一显示区域通常设置有光学器件，将第一显示区域的像素密度设置为小于第二显示区域的像素密度，是为了提高第一显示区的透光面积，在应用在屏下光学器件方案中，光学器件设置于第一显示区，能够增大光学器件接收的光量。
为了更加真实的模拟发光层2的设置形式，使得测试组件30的测量位置精度与发光层2的实际位置精度更加贴近，将测试组件30包括多个测试块3；多个测试块3中部分测试块3形成第一测试组，第一测试组中测试块3的分布密度与第一显示区域的像素密度相同；多个测试块3中另一部分测试块3形成第二测试组，第二测试组中测试块3的分布密度与第二显示区域的像素密度相同。
整个测试组件30并不仅仅具有一个测试块3，而是具有多个测试块3，所测得的数据样本更多，通过取平均值等数据处理方法，能够有效提高形成目标测试层32时的位置精度。且将第一测试组中的测试块3和第二测试组测试块3的分布密度设置为分别与第一显示区域和第二显示区域的像素密度相同，以真实模拟发光层2的各个像素的排布，以使测试组件30的测量的目标测试层32的位置精度与发光层2中与目标测试层32对应的膜层的位置精度更接近，发光层2中与目标测试层32对应的膜层具体可以为阴极层、阳极层等图案化膜层。
请参阅图3，在一些可选的实施例中，定位基准部33包括相互间隔设置的第一定位组件和第二定位组件，第一定位组件包括至少一个第一定位部331，第一定位部331呈十字型，第二定位组件包括多个第二定位部，第二定位部332呈一字型。
需要说明的是，第一定位部331呈十字型，具体是为了方便用于测试的外部图像获取部对测试组件30进行定位。而第二定位组件包括至少两个 第二定位部332，第二定位部332呈一字型，是为了确定目标测试层32的预设的形成位置，具体的，可以将两个第二定位部332分别沿第一方向和第二方向的延伸线交点设置为目标测试层32的预设中心点，其中，第一方向和第二方向相互垂直。
可选的，第二定位部332设置有三个，且三个第二定位部332呈品字形分布，以确定目标测试层32的相对于阵列母基板1的设置角度。
请参阅图3和图4，在一些可选的实施例中，目标测试层32包括阴极材料层，阴极材料层在阵列母基板1上的投影的边缘到荧光层31在阵列母基板1上的投影的边缘的距离处处相等，且在阵列母基板1靠近阴极材料层的每个边缘的位置上至少设置有一个第二定位部332。
需要说明的是，目标测试层32包括阴极材料层，阴极材料层具体是指与发光层2的阴极层采用相同材料制作的膜层，由于发光层2的阴极层采用精细掩膜板(FMM)进行蒸镀，需要测量阴极层蒸镀的位置精度。因而采用阴极材料层进行蒸镀，模拟发光层2的阴极层的蒸镀以确定采用精细掩膜板时蒸镀的位置精度，根据测试结果对精细掩膜板或其他装置进行改进，以使阴极层蒸镀的位置精度满足要求。
为了确保荧光层31所发出的光能够将阴极材料层均匀凸显出来，可选的，阴极材料层在阵列母基板1上的投影呈方形，呈方形的阴极材料层在阵列母基板1上的投影的边缘到荧光层31在阵列母基板1上的投影的边缘的距离处处相等，即荧光层31为边长大于阴极材料层的方形，且两者的中心点重合。在阴极材料层靠近阴极材料层的每个边缘至少设置有一个第二定位部332，即在阴极材料层的四个边的外缘至少对应设置一个第二定位部332，提高第二定位部332所确定的阴极材料层的预设蒸镀位置的准确性。
请参阅图5，在一些可选的实施例中，还包括设于荧光层31背向目标测试层32一侧的阳极材料层4，阳极材料层4在测试区域A的正投影覆盖荧光层31在测试区域A的正投影。
可以理解的是，与阴极材料层类似，阳极材料层4具体是指与发光层2的阳极层采用相同材料制作的膜层，以模拟发光层2的阳极层，阳极材 料层4在测试区域A的正投影覆盖荧光层31在测试区域A的正投影，即在测试时，阳极材料层4作为整个测试组件30的衬底来凸显荧光层31和目标测试层32。可选的，定位基准部33为像素定义材料，即指与发光层2的像素定义层采用相同材料制作的部分。
请参阅图6，本申请实施例还提供了一种显示面板母板的制备方法，应用于上述的显示面板母板，包括：
S110：提供阵列母基板1；
S120：在阵列母基板1的测试区域A形成定位基准部33；
S130：在定位基准部33所限定的区域内形成荧光层31，荧光层31被激活光线照射后可发光；
S140：在荧光层31远离阵列母基板1的一侧形成目标测试层32。
在S110的步骤中，阵列母基板1为显示面板母板制程中任意阶段的具有衬底的以及在衬底上形成一些层结构的基板。对于其具体的结构本申请不做限制。
在S120的步骤中，在阵列母基板1的测试区域A形成定位基准部33，设置定位基准部33的目的在于，通过定位基准部33的设置位置确定之后目标测试层32的预设形成位置。
在S130的步骤中，由于荧光层31需要发光凸显目标测试层32，而目标测试层32的形成位置由定位基准部33确定，因而将荧光层31设置在定位基准部33所限定的区域内，以使之后目标测试层32能够设置于荧光层31上。
在S140的步骤中，在荧光层31远离阵列母基板1的一侧形成目标测试层32，具体的，荧光层31在所述测试区域A的正投影覆盖目标测试层32在测试区域A的正投影，以确保荧光层31在发光时能够将目标测试层32凸显，便于准确确定目标测试层32的实际位置。
在本申请实施例提供的显示面板母板的制备方法中，通过在目标测试层32靠近阵列母基板1的一侧形成荧光层31，荧光层31被激活光线照射后可发光，以使荧光层31在发光时与目标测试层32产生明暗对比以将目标测试层32的实际位置轮廓显示出来，便于准确获取目标测试层32的实 际位置，将目标测试层32的实际位置与定位基准部33确定目标测试层32的预设形成位置进行比较，确定目标测试层32形成时的位置精度。
请参阅图7，在荧光层31远离阵列母基板1的一侧形成目标测试层32的步骤之后，还包括精度检测步骤；精度检测步骤包括：
S210：获取测试区域A的第一图像，根据第一图像获取定位基准部33的基准位置参数；
S220：根据基准位置参数计算目标测试层32的预设位置参数；
S230：采用激活光线照射荧光层31，以使荧光层31发光；
S240：获取测试区域A的第二图像，并根据第二图像获取目标测试层32的实际位置参数；
S250：比较目标测试层32的预设位置参数和实际位置参数以获取目标测试层32的位置精度参数。
在S210的步骤中，可以采用图像获取部获取显示面板母板的测试区域A的第一图像，根据第一图像获取定位基准部33的基准位置参数，图像获取部具体可以为工业摄像头等能够拍摄图像的设备，而定位基准部33的基准位置参数，具体可以为定位基准部33相对于阵列母基板1上设置的一零点位置的横纵坐标值。
在S220的步骤中，根据基准位置参数计算显示面板母板的目标测试层32的预设位置参数，具体的基准位置参数包括基准横坐标值和基准纵坐标值，根据基准横坐标值和基准纵坐标值得到预设位置参数，需要说明的是，基准横坐标值和基准纵坐标值并不是指同一个定位基准部33的坐标值，而是一个定位基准部33的基准横坐标值和另一个定位基准部33的基准纵坐标值，即一个定位基准部33用于确定目标测试层32的预设位置参数中的横坐标，另一个一个定位基准部33用于确定目标测试层32的预设位置参数中的纵坐标，两者相结合即目标测试层32的中心点的坐标。
在S230的步骤中，采用激活光线照射显示面板母板的荧光层31，以使荧光层31发光，激活光线具体可以为红光、蓝光等光源。
在S240的步骤中，根据第二图像获取显示面板母板的目标测试层32的实际位置参数，实际位置参数具体可以为目标测试层32相对于阵列母基 板1上设置的一零点位置的横纵坐标值。
在S250的步骤中，比较目标测试层32的预设位置参数和实际位置参数以获取目标测试层32的位置精度参数。之后可以通过位置精度参数来调整用于形成目标测试层32的精细掩膜板等部件来调整目标测试层32形成时的位置精度，以使其能满足生产要求。
在本申请实施例提供的显示面板母板的制备方法中，通过设置荧光层31来与目标测试层32产生明暗对比，以将目标测试层32的实际位置轮廓显示出来，便于准确获取目标测试层32的实际位置参数，与定位基准部33确定目标测试层32的预设位置参数进行比较，以精准确定目标测试层32形成时的位置精度参数。
在一些可选的实施例中，在精度检测步骤之后，还包括：在阵列母基板1一侧表面对应各显示面板形成区域B形成发光层2。
需要说明的是，之前通过精度检测步骤可以确定目标测试层32形成时的位置精度，并可以通过调整用于形成目标测试层32的精细掩膜板等部件来调整目标测试层32形成时的位置精度，以使其能满足生产要求，之后再使用符合要求的精细掩膜板等部件来在阵列母基板1一侧表面对应各显示面板形成区域B形成发光层2，提高发光层2的对应膜层形成的位置精度。
以上，仅为本申请的具体实施方式，所属领域的技术人员可以清楚地了解到，为了描述的方便和简洁，上述描述的系统、模块和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。应理解，本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到各种等效的修改或替换，这些修改或替换都应涵盖在本申请的保护范围之内。
还需要说明的是，本申请中提及的示例性实施例，基于一系列的步骤或者装置描述一些方法或系统。但是，本申请不局限于上述步骤的顺序，也就是说，可以按照实施例中提及的顺序执行步骤，也可以不同于实施例中的顺序，或者若干步骤同时执行。

Claims (13)

  1. 一种显示面板母板，具有呈阵列分布的显示面板形成区域及与所述显示面板形成区域相邻的测试区域，所述显示面板母板包括：
    阵列母基板；
    发光层，设于所述阵列母基板一侧表面且位于各所述显示面板形成区域；
    测试组件，设于所述阵列母基板的所述表面且位于所述测试区域，所述测试组件包括测试块，所述测试块包括：
    荧光层，设置于所述阵列母基板的所述表面，所述荧光层被激活光线照射后可发光；
    目标测试层，设置于所述荧光层背向所述表面的一侧，且所述荧光层在所述测试区域的正投影覆盖所述目标测试层在所述测试区域的正投影；
    定位基准部，设于所述目标测试层的外周侧。
  2. 根据权利要求1所述的显示面板母板，其中，所述发光层包括电子注入层、电子传输层、有机发光层、空穴传输层、空穴注入层；
    所述荧光层的形成材料包括构成所述电子注入层的材料、构成所述电子传输层的材料、构成所述有机发光层的材料、构成所述空穴传输材料层的材料及构成所述空穴注入层的材料中的至少一者。
  3. 根据权利要求1所述的显示面板母板，其中，所述发光层具有第一显示区域和至少部分环绕所述第一显示区域设置的第二显示区域，所述第一显示区域的像素密度小于所述第二显示区域的像素密度。
  4. 根据权利要求3所述的显示面板母板，其中，
    所述测试组件包括多个所述测试块；
    多个所述测试块中部分所述测试块形成第一测试组，所述第一测试组中所述测试块的分布密度与所述第一显示区域的像素密度相同；
    多个所述测试块中另一部分所述测试块形成第二测试组，所述第二测试组中所述测试块的分布密度与所述第二显示区域的像素密度相同。
  5. 根据权利要求1所述的显示面板母板，其中，所述定位基准部包括 相互间隔设置的第一定位组件和第二定位组件，所述第一定位组件包括至少一个第一定位部，所述第一定位部呈十字型，所述第二定位组件包括多个第二定位部，所述第二定位部呈一字型。
  6. 根据权利要求5所述的显示面板母板，其中，所述第二定位组件包括三个所述第二定位部，且三个所述第二定位部呈品字形分布。
  7. 根据权利要求5所述的显示面板母板，其中，所述目标测试层包括阴极材料层，所述阴极材料层在所述阵列母基板上的投影的边缘到所述荧光层在所述阵列母基板上的投影的边缘的距离处处相等，且在所述阵列母基板靠近所述阴极材料层的每个边缘的位置上至少设置有一个第二定位部。
  8. 根据权利要求7所述的显示面板母板，其中，所述阴极材料层在所述阵列母基板上的投影呈方形，呈方形的所述阴极材料层在所述阵列母基板上的投影的边缘到所述荧光层在所述阵列母基板上的投影的边缘的距离处处相等，所述阴极材料层和所述荧光层的中心点相重合。
  9. 根据权利要求8所述的显示面板母板，还包括设于所述荧光层背向所述目标测试层一侧的阳极材料层，所述阳极材料层在所述测试区域的正投影覆盖所述荧光层在所述测试区域的正投影。
  10. 一种显示面板母板的制备方法，应用于权利要求1至9任一项所述的显示面板母板，所述方法包括：
    提供阵列母基板；
    在所述阵列母基板的测试区域形成定位基准部；
    在所述定位基准部所限定的区域内形成荧光层，所述荧光层被激活光线照射后可发光；
    在所述荧光层远离所述阵列母基板的一侧形成目标测试层。
  11. 根据权利要求10所述的显示面板母板的制备方法，所述在所述荧光层远离所述阵列母基板的一侧形成目标测试层的步骤之后，还包括精度检测步骤，
    所述精度检测步骤包括：
    获取所述测试区域的第一图像，根据所述第一图像获取所述定位基准部的基准位置参数；
    根据所述基准位置参数计算所述目标测试层的预设位置参数；
    采用激活光线照射所述荧光层，以使所述荧光层发光；
    获取所述测试区域的第二图像，并根据所述第二图像获取所述目标测试层的实际位置参数；
    比较所述目标测试层的所述预设位置参数和所述实际位置参数以获取所述目标测试层的位置精度参数。
  12. 根据权利要求11所述的显示面板母板的制备方法，所述精度检测步骤之后还包括：
    在所述阵列母基板一侧表面对应各所述显示面板形成区域形成发光层。
  13. 根据权利要求11所述的显示面板母板的检测方法，其中，所述基准位置参数包括基准横坐标值和基准纵坐标值，根据所述基准横坐标值和所述基准纵坐标值得到所述预设位置参数。
PCT/CN2021/095719 2020-07-24 2021-05-25 显示面板母板及制备方法 WO2022016988A1 (zh)

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