WO2022012050A1 - 数字视像信号生成电路、数字视像信号生成系统、数字视像信号生成方法及非易失性存储介质 - Google Patents

数字视像信号生成电路、数字视像信号生成系统、数字视像信号生成方法及非易失性存储介质 Download PDF

Info

Publication number
WO2022012050A1
WO2022012050A1 PCT/CN2021/077664 CN2021077664W WO2022012050A1 WO 2022012050 A1 WO2022012050 A1 WO 2022012050A1 CN 2021077664 W CN2021077664 W CN 2021077664W WO 2022012050 A1 WO2022012050 A1 WO 2022012050A1
Authority
WO
WIPO (PCT)
Prior art keywords
video signal
digital video
data
unit
serial transmission
Prior art date
Application number
PCT/CN2021/077664
Other languages
English (en)
French (fr)
Inventor
山室美規男
Original Assignee
海信视像科技股份有限公司
东芝视频解决方案株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 海信视像科技股份有限公司, 东芝视频解决方案株式会社 filed Critical 海信视像科技股份有限公司
Priority to CN202180001649.3A priority Critical patent/CN114430912A/zh
Publication of WO2022012050A1 publication Critical patent/WO2022012050A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/66—Transforming electric information into light information

Definitions

  • the embodiments of the present application relate to a digital video signal generation circuit, a digital video signal generation system, a digital video signal generation method, and a nonvolatile storage medium.
  • Liquid crystal panels and OLED panels are used for screen panels of thin TVs as receivers of digital TVs.
  • video signal data has become The sending of screen panels is increasing day by day.
  • video signal data is transmitted to the screen panel through a channel for serial data transmission.
  • a multi-channel system formed by providing a plurality of channels for serial data transmission is used.
  • a flat cable composed of channels, a plurality of flat cables.
  • Patent Document 1 Japanese Patent No. 5290473
  • Patent Document 2 Japanese Patent Application Laid-Open No. 2015-75495
  • Patent Document 3 Japanese Patent No. 4529443
  • the receiving timing may be staggered (timing deviation) between the video signal data of one screen on the screen panel, resulting in the possibility of video cannot be displayed properly.
  • the problem to be solved by the present application is to provide a digital video signal generation circuit, system, method and non-volatile storage medium that eliminate the misalignment of the reception timing of video signal data on the screen panel.
  • a digital video signal generating circuit simultaneously receives a plurality of video signal data divided for displaying one video signal on a plurality of screens, and generates a plurality of video signal data corresponding to the plurality of video signal data.
  • Each digital video signal is output to different serial transmission paths at different timings.
  • FIG. 1 is a block diagram showing an example of a functional configuration of a receiving apparatus according to the first embodiment
  • FIG. 2 is a block diagram showing an example of a functional configuration of a channel group data signal output unit of the receiving apparatus according to the embodiment
  • FIG. 3 is a diagram showing an example of a screen display area of the screen panel of the embodiment.
  • FIG. 4 is a block diagram showing an example of the functional configuration of the channel data signal output unit of the receiving apparatus according to the embodiment
  • FIG. 5 is a diagram showing an example of the configuration of a shift register of the receiving apparatus according to the embodiment.
  • FIG. 6 is a block diagram showing an example of a functional configuration of a channel group data receiving unit of the receiving apparatus according to the embodiment
  • FIG. 7 is a block diagram showing an example of a physical configuration related to the transmission of digital video signals in the receiving apparatus of this embodiment
  • FIG. 8 is a block diagram showing an example of the physical configuration of the screen panel of the receiving apparatus of the embodiment.
  • FIG. 9 is an example of transmission and reception of digital video signals in the reception device of the second embodiment.
  • Communication section 47...delay amount comparison section, 51-1 to 51-4...output signal, 52-1 to 52-4...input signal, 53-1 to 53-4...flat cable , L1 ⁇ L16...screen panel area, 310...BEP, 311...Channel group data division, 312...Channel data signal output portion, 312-1 ⁇ 311-NL...Channel data signal Output unit, 331, 331-1 to 331-4... Channel group video signal output unit, 410... T-CON, 411... Channel data reception unit, 411-1 to 411-NL...
  • Channel data receiving unit 412...Channel group data output unit, 421...Screen panel unit, 421-1 to 421-4...Screen panel area, 422...Panel driver, 510...Transmission path , 3121...symbol data output unit, 3122...shift register, 3123...selection unit, 3124...parallel-serial conversion unit, 3125...8B10B conversion unit, 3126...interface unit , 3311-1 to 3311-4... delay section, 3312-1 to 3312-4... Vby1 driver, 4211-1 to 4211-4... scan path, 4212-1 to 4212-4... pixel.
  • an example is shown in the case where, for example, a display screen of 8K video is divided into a plurality of pieces and the data of each divided display screen is distributed to different cables for transmission.
  • the length of each cable is adjusted to adjust the output timing of the digital video signal transmitted by each cable.
  • An example in which the output timing (delay time) of the digital video signal is collectively adjusted for each picture channel group (cable) in units of image data in symbol units is shown.
  • FIG. 1 is a block diagram showing an example of the functional configuration of the reception apparatus according to the first embodiment.
  • the image data acquisition unit 1 is, for example, a receiver of digital television broadcasting, receives broadcast signals of advanced broadband digital satellite broadcasting (4K/8K broadcasting), and acquires video signals (data related to video content).
  • broadcast signals may be, for example, video signals for digital television broadcasting acquired from storage media such as DVDs and hard disks, and the Internet.
  • the tuner 11 receives and processes broadcast signal waves of a desired frequency band via an antenna (not shown), a coaxial cable based on cable broadcasting, or the like.
  • the demodulation unit 12 extracts data related to the video signal from the digital data obtained by demodulating the radio wave of the broadcast signal.
  • the video signal processing unit 13 performs data processing such as decoding by a predetermined method on the data related to the video signal extracted by the demodulation unit 12, and acquires the video signal.
  • the image data processing unit 2 performs data processing for the purpose of improving the image quality, dividing the image data, and the like on the video signal output from the video signal processing unit 13 .
  • the image processing unit 21 performs data processing on the video signal output from the video signal processing unit 13 for the purpose of increasing the resolution, improving the frame rate, adjusting the image quality, etc., and outputs a video for displaying the video on the screen panel unit 421 signal data. These methods are common methods, so details are omitted.
  • the image dividing unit 22 divides and outputs the video signal data according to a predetermined area on the screen panel unit 421 (referred to as a screen panel area). Thereby, the video signal data can be transmitted in parallel for each screen panel area, which also contributes to shortening the transmission delay.
  • the divided video signal data output from the image dividing unit 22 is referred to as picture channel group data.
  • the picture channel group data are respectively transmitted by different transmission paths. In FIG. 1 , an example is shown in the case where the data of each screen channel group is transmitted from the image dividing unit 22 via four transmission paths. The screen panel area will be described later.
  • the image data transmission unit 3 receives the screen channel group data output from the image division unit 22 , and transmits the screen channel group data, that is, the divided video signal data, to the screen display unit 4 via an interface for serial transmission.
  • a channel refers to a channel using a transmission method of one serial transmission line (called a serial transmission line), which is the smallest unit of a transmission path for serial data transmission, and is also called a serial channel.
  • the manner in which data is transmitted using multiple serial channels is referred to as multi-channel. Multi-channel is used when there is a data transfer volume of this magnitude that cannot be handled by serial channels.
  • the amount of data per screen has further increased, and there has been a situation where it cannot handle multiple channels.
  • each multi-channel in a scheme using a plurality of multi-channels is referred to as a picture channel group.
  • the channel group data signal output unit 31 - 1 , the channel group data signal output unit 31 - 2 , the channel group data signal output unit 31 - 3 , and the channel group data signal output unit 31 - 4 respectively respond to the screen channels input from the image dividing unit 22 .
  • the group data (divided video signal data) is subjected to parallel-serial conversion, encoding, etc. to generate a digital video signal, and is sent to interface 5-1, interface 5-2, interface 5-3, and interface 5-4. Output digital video signal.
  • the functions of the channel group data signal output unit 31-1, the channel group data signal output unit 31-2, the channel group data signal output unit 31-3, and the channel group data signal output unit 31-4 are the same. When the functions are not particularly distinguished, it is called the channel group data signal output unit 31 in the sense of indicating each channel group data signal output unit.
  • the image display unit 4 receives the digital video signal of each screen channel group, and displays the video content on the screen unit 42 so that the user can watch it.
  • the channel group data receiving unit 41-1, the channel group data receiving unit 41-2, the channel group data receiving unit 41-3, and the channel group data receiving unit 41-4 pass through the interface unit 5-1, the interface unit 5-2, and the interface, respectively. part 5-3, interface part 5-4 to receive channel group data signal output part 31-1, channel group data signal output part 31-2, channel group data signal output part 31-3, channel group data signal output part 31- 4
  • the functions of the channel group data receiving unit 41 - 1 , the channel group data receiving unit 41 - 2 , the channel group data receiving unit 41 - 3 , and the channel group data receiving unit 41 - 4 are the same, and they are not specially distinguished.
  • Each channel group data receiving unit 41 reproduces the screen channel group data from the digital video signal, and outputs it to the screen unit 42 .
  • the screen portion 42 is a monitor, and in particular, in this embodiment, it is a large-scale monitor of a thin TV for digital TV such as a liquid crystal panel and an OLED panel.
  • the screen unit 42 receives video signal data from the channel group data receiving unit 41-1, the channel group data receiving unit 41-2, the channel group data receiving unit 41-3, and the channel group data receiving unit 41-4, and based on the video signal data
  • a panel driver or the like controls the screen panel to display the video content, thereby presenting the video content to the user.
  • the delay amount measuring unit 45 has a function of measuring the delay amount between the picture channel group data.
  • the measured delay amount is used for the set delay amount set in the channel group data signal output unit 31 .
  • the set delay amount is a delay amount added to the output timing of the digital video signal, which will be described later.
  • the communication unit 46 exchanges data between the image display unit 4 and the image data transmission unit 3 using a communication method such as I2C.
  • the delay amount comparison unit 47 compares, for example, the delay amount between the respective picture channel group data calculated by the delay amount measurement unit 45 based on the arrival timing of the respective picture channel group data, and transmits the delay difference to the control unit 6 via the communication unit 46 .
  • the control unit 6 sets the received delay difference as a set delay amount for each channel group data signal output unit 31 .
  • the interface unit 5 - 1 , the interface unit 5 - 2 , the interface unit 5 - 3 , and the interface unit 5 - 4 are, for example, flat cables for serial data transmission, and are used to transmit digital data from the image data transmission unit 3 to the image display unit 4 . Harness of serial transmission line for video signal.
  • the interface unit 5 includes a protocol for transmitting digital video signals, and in this embodiment, Vbyone (registered trademark), which is a standard for serial data transmission, is applied.
  • Vbyone is a standard for serial data transmission usually used when transmitting digital video signals to screen panels and the like, and includes a pair of differential lines.
  • a pair of differential lines corresponds to a channel, and a flat cable in which a plurality of (for example, 16 in the present embodiment) serial transmission lines are bundled corresponds to a picture channel group (multi-channel).
  • Vbyone is a common technology, details are omitted.
  • the functions of the interface unit 5-1, the interface unit 5-2, the interface unit 5-3, and the interface unit 5-4 are the same, and if not specifically distinguished, they are expressed as the meaning of each interface unit. It is called the interface part 5.
  • a clock can be generated on the receiving side based on data transmitted by each serial transmission line, so that a clock can be provided for each channel.
  • the generated clock cycle is UI
  • the timing shift of the clock cycles between the channels on the Vbyone receiving side is suppressed to 5UI.
  • 1UI is about 350ps, so it must be suppressed within 5UI ⁇ 1.7ns.
  • the data reception timing shift on the receiving side of the Vbyone may become a problem.
  • the dielectric constant is 1, which is equal to air
  • the transmission speed of the electrical signal is 3 ⁇ 10 8 m/s
  • the propagation distance of one clock is about 100 mm.
  • the propagation distance becomes shorter in printed circuit boards and flat cables with a high dielectric constant. Therefore, when the pattern design on the printed circuit board and the length of the cables connecting the boards are different, the cables may The data reception timing may be misaligned (timing deviation).
  • an interface part 5 - 1 , an interface part 5 - 2 , an interface part 5 - 3 , and an interface part 5 - 4 (corresponding to each flat cable) having different cable lengths are used.
  • the lengths are the same within one picture channel group (within flat cables), but there is a possibility that the lengths may be different for each picture channel group (between flat cables).
  • the possibility of timing bias is high.
  • timing deviation is eliminated by adjusting a clock (Symbol clock) of symbol data (Symbol data), which will be described later.
  • the control unit 6 sets, in each channel group data signal output unit 31, a set delay amount for changing the output timing of the digital video signal output from each channel group data signal output unit 31.
  • the set delay amount can be calculated by the user based on the difference between the cable lengths of the interface unit 5 - 1 , the interface unit 5 - 2 , the interface unit 5 - 3 , and the interface unit 5 - 4 .
  • the set delay amount is set to 0 for the channel group data signal output unit 31 of the interface unit 5 with the longest cable length.
  • the transmission time obtained by adding the set delay amount to the cable length (transmission time) of the interface unit 5 to which it is connected is determined to be the same as the transmission time of the longest interface unit 5 Set the delay amount.
  • the determined set delay amount can be set to each channel group data signal output unit 31 via the control unit 6 through a user interface such as a not-shown computer keyboard or a remote control of a television, for example.
  • video signal data (referred to as input video signal data) input to each channel group data signal output unit 31 and video signal data (referred to as output) output from the channel group data reception unit 41 may be input to the control unit 6 .
  • video signal data the control unit 6 adjusts and determines the set delay amount while comparing the input video signal data with the output video signal data. For example, a set delay amount for matching the input video signal data with the output video signal data may be set from the control unit 6 to each channel group data signal output unit 31 .
  • a method using learning realized by artificial intelligence or the like may be used. Specifically, a delay amount of an appropriate intermediate value is given to each channel group data signal output unit 31 as a set delay amount to operate. Compare the input video signal data and output video signal data of any group of channels. If it is confirmed that it operates normally, adjust the set delay amount of other groups of channels, and perform a comparison between the input video signal data and the output video signal data. Compare and confirm its normal operation. By implementing this method for all group channels, the set delay amount for all group channels is determined, and the determined set delay amount is set in each channel group data signal output unit 31 .
  • control unit 6 and the image data transmission unit 3 or the image display unit 4 may exchange data by a communication method such as I2C.
  • FIG. 2 is a block diagram showing an example of the functional configuration of the channel group data signal output unit of the receiving apparatus according to the embodiment.
  • the channel group data dividing unit 311 divides the screen channel group data (divided video signal data) input from the image dividing unit 22 and outputs the data to a plurality of serial transmission lines as digital video signals.
  • the data output by the channel group data dividing unit 311 is referred to as channel data.
  • channel data By dividing into channel data, the picture channel group data can be transmitted even when the transmission speed of one serial transmission line is limited.
  • the channel data signal output unit 312-1, the channel data signal output unit 312-2, and the channel data signal output unit 311-NL respectively generate digital video signals for output to the serial transmission line.
  • NL is the maximum number of channels to which one picture channel group data can be allocated, and is equivalent to the number of serial transmission lines in the flat cable. In this embodiment, NL is set to 16. It should be noted that the functions of the channel data signal output unit 312 - 1 , the channel data signal output unit 312 - 2 , and the channel data signal output unit 311 -NL are the same, so as long as no special distinction is made, each channel data is displayed according to The meaning of the signal output unit is referred to as the channel data signal output unit 312 .
  • Each channel data signal output unit 312 generates a digital video signal for the channel data input from the channel group data division unit 311 according to the protocol of the interface unit 5 and the like, and outputs the digital video signal to the interface unit 5 .
  • FIG. 3 is a diagram showing an example of a screen display area of the screen panel of the embodiment.
  • the screen panel area 421-1, the screen panel area 421-2, the screen panel area 421-3, and the screen panel area 421-4 respectively correspond to the picture channel group data. That is, the screen panel of the screen portion 42 (for example, the screen panel portion 421 described later) is divided into four screen panel areas 421-1, 421-2, 421-3, and 421-4. , and set the pixel information in each screen panel area as the picture channel group data respectively.
  • the screen panel area 421-1, the screen panel area 421-2, the screen panel area 421-3, and the screen panel area 421-4 are the same areas in the screen panel. The meaning of each screen panel area is referred to as a screen panel area 421 .
  • Scanning path 4211-1, scanning path 4211-2, scanning path 4211-3, and scanning path 4211-4 respectively schematically represent screen panel area 421-1, screen panel area 421-2, screen panel area 421-3, screen Path of scan lines in panel area 421-4. It should be noted that the scan path 4211-1, the scan path 4211-2, the scan path 4211-3, and the scan path 4211-4 are the same scan line paths, and unless otherwise distinguished, the scan paths are displayed according to the The meaning is called scan path 4211.
  • the scan path 4211 is composed of solid arrows and dashed arrows, and the solid arrows indicate scan lines. Dashed arrows indicate movement between scan lines. For example, the case where the screen panel of the screen section 42 is scanned from left to right in order starting from the uppermost solid arrow (scanning line) is shown. Scanning is performed for the screen panel area 421-1, the screen panel area 421-2, the screen panel area 421-3, and the screen panel area 421-4, respectively. It should be noted that, in FIG. 3 , only 10 scanning lines are shown in each screen panel area 421 , but there are actually 4000 lines that match the corresponding pixels of the digital TV.
  • the reason for the division as the screen panel area will be described in detail below. Due to the enlargement of digital televisions in recent years, the number of pixels per screen has increased.
  • the digital video signal of digital TV is originally a signal sent by a serial data transmission channel, but since the video picture display cycle (hereinafter referred to as the frame rate) does not change, the increase in the number of pixels means the frequency of the digital video signal. Increase. For example, to simply calculate the pixel part of an 8K image, set the frame rate to 120Hz, set the number of pixels to 7680 ⁇ 4320, set the RGB color to 8bit resolution, and convert the video signal data to 8B10B. At this time, it must be transmitted from the image data transmission unit 3 to the screen display unit 4 at a clock frequency of about 150 GHz.
  • the 8K screen is divided into four and the data is processed independently. Further, for example, a bundle of 16 serial transmission channels is bundled as a screen channel group, and four screen channel groups (four flat cables) are used. ) to transmit a digital video signal to each screen panel area divided into 4, even if the blanks in the format are included, the clock frequency will drop to about 3GHz, so data transmission can be performed.
  • the data of each pixel of each screen panel area 421 is input to each channel group data signal output unit 31 in the order of the scan path 4211 .
  • the data of each pixel includes R, G, and B symbol data.
  • Symbol data is bit data (Bit data) assigned to R, G, and B of 1 pixel.
  • the symbol data of R, G, and B are each composed of, for example, 8-bit data.
  • the pixel 4212-1, the pixel 4212-2, the pixel 4212-3, and the pixel 4212-4 respectively represent the screen panel area 421-1, the screen panel area 421-2, the screen panel area 421-3, and the screen panel area 421-4.
  • An example of a pixel It should be noted that the pixel 4212-1, the pixel 4212-2, the pixel 4212-3, and the pixel 4212-4 are examples of the same pixel, and are referred to as the pixel 4212 in accordance with the meaning of each pixel unless otherwise distinguished. .
  • the respective pixels of the four screen panel areas 421 three pixels (P11, P12, P13), (P21, P22, P23), (P31, P32, P33), (P41, P42, P43) are respectively shown , are output from the screen dividing unit 22 in the order of the scan path 4211 in the screen panel area 421 .
  • These pixel data are simultaneously input to the channel group data signal output unit 31 .
  • the data of the respective pixels P11 , P21 , P31 , and P41 of the screen panel area 421 are simultaneously input to the data signal output unit 31 of each channel group, and to the channel data signal output unit 312 - 1 of the data signal output unit 31 of each channel group. Enter at the same timing.
  • the pixels ( P11 , P12 , P13 ) are input to the channel group data signal output unit 31 - 1
  • the pixels ( P11 , P12 , P13 ) are output to the channel data signal output unit 312 - 1 and the channel data signals, respectively.
  • part 312-2 and channel data signal output part 312-3 input.
  • an example of three pixels is shown, but the data of the NL pixels are input to the channel data signal output unit 312-1 to the channel data signal output unit 312-NL, respectively.
  • the data of these pixels P11 , P21 , P31 , and P41 need to be output from the channel group data receiving unit 41 at the same timing and input to the screen unit 42 at the same timing.
  • FIG. 4 is a block diagram showing an example of the functional configuration of the channel data signal output unit of the receiving apparatus according to the embodiment.
  • the symbol data output unit 3121 divides the channel data input from the channel group data dividing unit 311 into R, G, and B symbol data and outputs it.
  • the symbol data output unit 3121 outputs symbol data at the timing of the input symbol clock.
  • the symbol clock is a time interval for processing data of one pixel (one-symbol data of each of R, G, and B).
  • the shift register 3122 - 1 , the shift register 3122 - 2 , and the shift register 3122 - NSR are each a one-stage shift register in which, for example, NFF flip-flops are arranged in parallel.
  • NFF is the number of flip-flops. Since the shift register 3122 - 1 , the shift register 3122 - 2 , and the shift register 3122 - NSR have the same function, they are referred to as shift registers in the sense of indicating each shift register without distinguishing the functions. 3122.
  • NSR is the number of shift registers.
  • the shift register 3122 is a shift register that operates at the timing of the input symbol clock.
  • the shift register 3122 outputs the data of the flip-flop together with the data of one pixel (one-symbol data of each of R, G, and B) being input.
  • the input data of one pixel (one-symbol data of R, G, and B) is input to the flip-flop. That is, the shift register 3122-1, the shift register 3122-2, and the shift register 3122-NSR can give the output of data of one pixel (one-symbol data of R, G, and B) in units of symbol clocks
  • the delay time (maximum is the delay time corresponding to NSR symbol clocks).
  • FIG. 5 is a block diagram showing an example of the configuration of a shift register of the receiving apparatus according to the embodiment.
  • one-symbol data (8 bits) of each picture channel group is input to the shift register 3122 in parallel.
  • the output of data from the flip-flop (FF) and the input of data to the FF are performed simultaneously at the timing of the symbol clock.
  • the selection unit 3123 determines which of the shift register 3122 - 1 , the shift register 3122 - 2 , and the shift register 3122 - NSR the output from which is to be output to the subsequent stage, and then selects the determined shift register.
  • the output of the bit register is output to the back segment.
  • a set delay amount input from the control unit 6 for each channel group data signal output unit 31 is set, and the selection unit 3123 selects the shift register corresponding to the set delay amount. Shift register for output to the back segment.
  • the same set delay amount is set in all the channel data signal output units 312 in each channel group data signal output unit 31 .
  • the parallel-serial conversion unit 3124 converts the output from any one of the shift registers 3122-1, 3122-2, and 3122-NSR specified by the selection unit 3123 (the R, G, and B data bits for one pixel). parallel data) to serial data (also known as serial channel data).
  • the 8B10B conversion unit 3125 performs 8B10B conversion on the serial channel data input from the parallel-serial conversion unit 3124, and outputs the converted serial channel data (referred to as converted serial channel data).
  • 8B10B conversion (also referred to as 8B10B modulation) is a common coding method, and the detailed description is omitted.
  • the interface unit 3126 converts the converted serial channel data input from the 8B10B conversion unit 3125, performs various data conversion, frame data generation, signal generation, etc. according to the protocol of the interface unit 5 to generate a digital video signal, and generates a digital video signal.
  • the digital video signal is output to the interface unit 5 .
  • the interface unit 3126 since Vbyone is applied to the interface unit 5 , the interface unit 3126 generates a digital video signal according to the Vbyone protocol and outputs it to the interface unit 5 .
  • the clock of the Vbyone necessary for the receiving side of the Vbyone is determined according to the number of bits transmitted by the serial transmission line.
  • the Vbyone clock is simply set to a value that is 10 times or more the symbol clock.
  • the delay amount actually added to the output timing of the digital video signal is an integer multiple of the symbol clock delay amount.
  • the shift register 3122, the parallel-serial conversion unit, the 8B10B conversion unit, and the interface unit are described for each channel data signal output unit 312, but the data signal output unit may be divided by channel group.
  • the shift register 3122, the parallel-serial conversion unit, the 8B10B conversion unit, and the interface unit are provided on a one-to-one basis, so that each channel data signal output unit 312 shares the shift register 3122, the parallel-serial conversion unit, and the 8B10B conversion unit. Department, Interface Department.
  • FIG. 6 is a block diagram showing an example of the functional configuration of the channel group data reception unit of the reception apparatus according to the embodiment.
  • the channel data receiving unit 411 - 1 , the channel data receiving unit 411 - 2 , and the channel data receiving unit 411 -NL respectively receive the digital video signal from the interface unit 5 , perform conversion of various data, etc., and output the channel data.
  • the channel data receiving unit 411-1, the channel data receiving unit 411-2, and the channel data receiving unit 411-NL respectively receive from the channel data signal output unit 312-1, the channel data signal output unit 312-2, and the channel data signal output unit 312. -3.
  • channel data receiving unit 411 - 1 the channel data receiving unit 411 - 2 , and the channel data receiving unit 411 -NL have the same functions, and unless they are not specifically distinguished, the channel data receiving units are used to indicate the meanings of the respective channel data receiving units. It is called the channel data receiving unit 411 .
  • the channel data receiving unit 411 includes an interface unit 3126 , an 8B10B converting unit 3125 , and a parallel-serial converting unit 3124 corresponding to the channel data signal output unit 312 , an interface unit (not shown), a serial-parallel converting unit, and an 8B10B decoding unit, which are not shown, respectively. .
  • the interface unit of the channel data receiving unit 411 receives the digital video signal received from the interface unit 5 by using a receiving method corresponding to the protocol of the interface unit 3126 (in this embodiment, a receiving method based on the Vbyone protocol), and acquires The serial channel data is converted and output to the 8B10B decoding unit.
  • the 8B10B decoding unit outputs the serial channel data according to the protocol based on the 8B10B modulation with respect to the input converted serial channel data.
  • the serial-parallel conversion unit converts serial channel data into parallel channel data and outputs it.
  • the channel group data output unit 412 reproduces the screen channel group data based on the channel data output from the respective channel data reception units 411, and outputs it to the screen unit 42 at a predetermined timing.
  • each converted serial channel data received at the interface unit of each channel data receiving unit 411 is synchronized, the serial channel data output by each channel data receiving unit 411 is also synchronized. Furthermore, the picture channel group data output from each channel group data receiving unit 41 is also synchronized between the picture channel group data. Specifically, P11 , P21 , P31 , and P41 in FIG. 3 are simultaneously output from each channel group data receiving unit 41 . The reason for this is that the output timing of the digital video signal is changed for each screen channel group data in the selection unit 3123 of each channel group data output unit 31 .
  • FIG. 7 is a block diagram showing an example of a physical configuration related to the transmission of digital video signals in the receiving apparatus of this embodiment.
  • the video signal generation board 33 has, for example, the function of the video data transmission unit 2 and the channel group data signal output unit 31 of the video data transmission unit 3 , processes the received video signal, and outputs a digital video signal.
  • the panel display control board 43 has the function of the channel group data receiving unit 41 and includes pixel driving elements for controlling the pixels of the screen panel 421 .
  • the flat cable 53-1, the flat cable 53-2, the flat cable 53-3, and the flat cable 53-4 correspond to the interface part 5-1, the interface part 5-2, the interface part 5-3, and the interface part 5-4, respectively.
  • the selection unit 3123 changes the output timing of the digital video signal output from the video signal generation board 33 in consideration of the set delay amount of the flat cable set for each screen channel group, thereby causing the display to the panel.
  • the timing of the digital video signal input from the control board 43 is matched to absorb the difference in length of the flat cable.
  • the present embodiment shows an example in which the delay amount is set in units of symbol clocks for parallel data (a state in which bits of symbol data are parallelized).
  • the video signal has symbol data (eg, 8 bits) relative to a video portion (pixel) on the screen.
  • the video signal is processed as parallel data because processing such as image quality improvement is performed in units of the symbol data.
  • Parallel data processing uses a clock that is slower than the Vbyone clock (eg, one-eighth of the Vbyone clock), such as a symbol clock.
  • the output of pixel data is delayed by the symbol clock through the shift register in units of time using the symbol clock, and the selection unit 3123 determines which stage of the shift register pixel data is to be used as the output data. Determines the amount of delay to the output timing.
  • a shift register using a Vbyone clock instead of the symbol clock may be used.
  • the flip-flops FF are not connected in parallel like the shift register 3122, but the FFs are connected in series.
  • the shift register needs to have a higher operating speed than the parallel shift register 3122 . That is, when the shift register is used to set the delay amount for serial data, there is a disadvantage that the clock of the shift register is fast and the number of segments increases.
  • power consumption and layout design in the IC become difficult, so it is preferable to adjust in units of symbols like the shift register 3122 .
  • the selector 3123 to adjust the delay amount for each picture channel group in symbol clock time units, it is possible to eliminate the time difference of the digital video signal.
  • the adjustment is performed in symbol clock time units, there is also an effect that an accuracy of ⁇ 5 UI can be ensured between the picture channel groups with respect to the reference channel defined by Vbyone.
  • FIG. 8 is a block diagram showing an example of the physical configuration of the screen panel of the receiving apparatus according to the embodiment.
  • the screen portion 42 is, for example, a liquid crystal panel or an OLED panel including a screen panel portion 421 and a panel driver 422 .
  • the screen panel portion 421 is a portion that provides a user with viewing images as viewing information by controlling the RGB light sources and the like on a pixel-by-pixel basis by the panel driver 422 .
  • the panel driver 422 receives the picture channel group data from the channel group data output unit 412, and controls the display of the screen panel unit 421 according to the picture channel group data. Specifically, the panel driver 422 controls the display of the area of the screen panel portion 421 corresponding to the received screen channel group data.
  • the BEP 310 Since the BEP 310 , the T-CON 410 , and the transmission path 510 are provided on the back side of the screen panel portion 421 , that is, on the side that cannot be viewed, they are shown by dotted lines.
  • the T-CON 410 is provided at the lower center of the screen panel portion 421, and the BEP 310 is provided beside the T-CON 410.
  • the BEP310 is a back end processing circuit (Back End Processor) for the screen display unit 4, and has the function of the image data transmission unit 3.
  • the T-CON 410 is a timing controller included in the channel group data receiving unit 41 and controlling the timing at which the channel group data output unit 412 outputs the screen channel group data to the panel driver 422 .
  • the transmission path 510 is a transmission path of the digital video signal connecting the BEP 310 and the T-CON 410, and includes all the flat cables 53-1, 53-2, 53-3, and 53-4.
  • the T-CON 410 can synchronize the respective channel group data with respect to the screen channel group data output from the respective channel group data receiving units 41 .
  • the reason for this is that in the selection unit 3123 of each channel group data output unit 31 of the image data transmission unit 3, the output timing of the digital video signal is changed for each screen channel group data. Therefore, the timings between the screen channel group data output from the channel group data receiving units 41 are not shifted (there is no timing difference), and no problem in display occurs.
  • a video signal generation substrate 33 (including BEP 310 ) for generating digital video signals and a screen panel 421 for driving (controlling) the received digital video signal are divided into The panel display control substrate 43 (including the T-CON 410 ) of each pixel element of . If the receiving timings of the digital video signals transmitted between the two circuit boards are staggered among the picture channel groups, the desired video cannot be displayed on the screen panel 421 .
  • the number of pixels is about 4K resolution, with a clock frequency of 3GHz, 16 channels can be transmitted with a single flat cable, so the fluctuation range of timing deviation does not increase.
  • the screen may be divided (vertically or horizontally).
  • video signal data for each divided screen is simultaneously transmitted from the BEP310 using a plurality of flat cables.
  • the lengths of the flat cables of the respective screen channel groups are different, not only the transmission delay time but also the characteristics of the cables are changed. will also change.
  • the characteristics of the cable change, the state of waveform distortion of the digital video signal transmitted by the cable changes.
  • the state of waveform distortion depends on the length of the flat cable.
  • the waveform of the digital video signal is delayed due to waveform distortion, which affects the reception timing of the digital video signal. That is, the difference in cable length between the flat cables that transmit the data of each picture channel group leads to the difference in the state of waveform distortion, and also causes the difference in the transmission delay time of the digital video signal to be transmitted.
  • the present embodiment describes an example in which the above-mentioned problem is solved by changing the degree of pre-emphasis in the Vbyone driver according to the set delay amount (cable length) set for each picture channel group .
  • FIG. 9 is an example of transmission and reception of digital video signals in the reception device of the second embodiment.
  • the channel group video signal output unit 331 - 1 , the channel group video signal output unit 331 - 2 , the channel group video signal output unit 331 - 3 , and the channel group video signal output unit 331 - 4 are provided with a channel group for each screen.
  • the channel group data signal output unit 31 of FIG. 1 has the same function. In this figure, unlike the channel group data signal output unit 31 of FIG. 1 , only the function for one channel data in the channel group data signal output unit 31 is shown, but the function for all the channel data is included.
  • the channel group video signal output unit 331-2 From the image dividing unit 22 to the channel group video signal output unit 331-1, the channel group video signal output unit 331-2, the channel group video signal output unit 331-3, and the channel group video signal output unit 331-4, respectively Input the picture channel group data of each screen panel area, from the channel group video signal output part 331-1, the channel group video signal output part 331-2, the channel group video signal output part 331-3, the channel group video signal
  • the output unit 331-4 outputs the digital video signal of each channel.
  • channel group video signal output unit 331-1, the channel group video signal output unit 331-2, the channel group video signal output unit 331-3, and the channel group video signal output unit 331-4 have the same Therefore, unless it is specially distinguished, it is referred to as a channel group video signal output unit 331 in the sense of indicating each channel group video signal output unit.
  • the delay unit 3311 - 1 , the delay unit 3311 - 2 , the delay unit 3311 - 3 , and the delay unit 3311 - 4 respectively control the output timing of the digital video signal of the input channel data, and output it as parallel data. It should be noted that the delay unit 3311 - 1 , the delay unit 3311 - 2 , the delay unit 3311 - 3 , and the delay unit 3311 - 4 have the same function, so unless they are not distinguished, they are referred to as the meaning of each delay unit. is the delay part 3311. Each delay unit 3311 has the same function as the shift register 3122 and the selection unit 3123 in FIG. 5 .
  • the Vby1 driver 3312-1, the Vby1 driver 3312-2, the Vby1 driver 3312-3, and the Vby1 driver 3312-4 correct the output waveform of the digital video signal as necessary with respect to the input serial channel data and output it. .
  • the operation of modifying the output waveform of a digital video signal is called pre-emphasis. Pre-emphasis is a common technique, and the description of the specific method is omitted.
  • the Vby1 driver 3312-1, the Vby1 driver 3312-2, the Vby1 driver 3312-3, and the Vby1 driver 3312-4 have the same function, so unless they are distinguished, they will be referred to as the Vby1 driver 3312 in the sense of each Vby1 driver.
  • the Vby1 driver 3312 is included in the interface unit 3126 of FIG. 4 , for example.
  • the parallel-serial conversion part 3124 and the 8B10B conversion part 3125 in FIG. 4 are not shown in FIG. 9, the same function is also included in FIG. Therefore, the data input to the Vby1 driver 3312 is serial data output by a function equivalent to the 8B10B conversion unit 3125 .
  • the flat cable 53 - 1 , the flat cable 53 - 2 , the flat cable 53 - 3 , and the flat cable 53 - 4 are respectively connected with the interface section 5 - 1 , the interface section 5 - 2 , the interface section 5 - 3 , and the interface section 5 - in FIG. 1 . 4 corresponds to a transmission path for transmitting digital video signals output by Vby1 driver 3312-1, Vby1 driver 3312-2, Vby1 driver 3312-3, and Vby1 driver 3312-4 under the Vbyone protocol, such as a flat cable.
  • the flat cable 53 - 1 , the flat cable 53 - 2 , the flat cable 53 - 3 , and the flat cable 53 - 4 each include 16 differential lines (multi-channel).
  • the flat cable 53 - 1 , the flat cable 53 - 2 , the flat cable 53 - 3 , and the flat cable 53 - 4 have the same functions, so unless they are distinguished, they are called as the meanings of the respective flat cables. It is the flat cable 53 .
  • the output signal 51-1, the output signal 51-2, the output signal 51-3, and the output signal 51-4 respectively represent the channel group video signal output unit 331-1, the channel group video signal output unit 331-2, the channel group video signal output unit 331-2, and the channel group video signal output unit 331-2. Examples of digital signal waveforms output by the video signal output unit 331-3 and the channel group video signal output unit 331-4. It should be noted that the output signal 51 - 1 , the output signal 51 - 2 , the output signal 51 - 3 , and the output signal 51 - 4 are the same signal, so as long as no special distinction is made, they are called according to the meaning of each output signal. is the output signal 51.
  • the input signal 52-1, the input signal 52-2, the input signal 52-3, and the input signal 52-4 respectively represent the channel group video signal output unit 331-1, the channel group video signal output unit 331-2, the channel group video signal output unit 331-2, and the channel group video signal output unit 331-2.
  • the digital video signals output by the video signal output unit 331 - 3 and the channel group video signal output unit 331 - 4 are immediately passed through the flat cable 53 - 1 , the flat cable 53 - 2 , the flat cable 53 - 3 , and the flat cable 53 - 4 , respectively.
  • An example of the waveform before reaching the panel display control board 43 An example of the waveform before reaching the panel display control board 43 .
  • the input signal 52 - 1 , the input signal 52 - 2 , the input signal 52 - 3 , and the input signal 52 - 4 are the same signal, so as long as there is no special distinction, they will be called according to the meaning of each input signal. is the input signal 52 .
  • the panel display control board 43 is the same as that described in FIG. 7 .
  • FIG. 9 shows an example in a case where the cable lengths of the flat cables 53 are different from each other.
  • Each delay unit 3311 adds a delay to the output timing of the digital video signal according to the cable length of each of the connected flat cables 53. Specifically, since the cable length becomes longer in the order of the flat cable 53 - 1 , the flat cable 53 - 2 , the flat cable 53 - 3 , and the flat cable 53 - 4 , the delay unit 3311 - 1 , the delay unit 3311 - 2 , the delay unit 3311 - 2 , The order of the delay unit 3311-3 and the delay unit 3311-4 increases the amount of delay added to the output timing of the digital video signal.
  • the difference in length between the serial transmission lines in each flat cable 53 is considered negligible, and the set delay amount set to the selection unit 3123 in the delay unit 3311 is set to the same value.
  • the set delay amount determined by the video signal output unit 331 for each channel group is set in the selection unit 3123 of each delay unit 3311 .
  • the selection unit 3123 determines the shift register 3122 to which the channel data is output based on the set delay amount.
  • the Vby1 driver 3312 since the degree of degradation of the waveform of the digital video signal depends on the cable length of each flat cable 53 that transmits the digital video signal, in the Vby1 driver 3312, according to the cable length of the flat cable 53 connected to each Vby1 driver 3312
  • the waveform of the output signal 51 is corrected.
  • the Vby1 driver 3312-1, the Vby1 driver 3312-2, the Vby1 driver 3312-3, and the Vby1 driver 3312-4 make the input signal 52-1, the input signal 52-2, and the input signal 52 as shown in FIG. 9 . -3.
  • the output signal 51-1, the output signal 51-2, the output signal 51-3, and the output signal 51-4 are respectively corrected.
  • FIG. 1 the example of FIG.
  • the respective waveform correction amounts of Vby1 driver 3312 - 1 , Vby1 driver 3312 - 2 , Vby1 driver 3312 - 3 , and Vby1 driver 3312 - 4 can be determined, for example, by the control unit 6 , and the control unit 6 can set each Vby1 driver 3312 by the control unit 6 . middle.
  • the correction amount of the waveform may be determined by the user and set to the control unit 6 through a user interface (not shown).
  • the control unit 6 may compare the input video signal data and the output video signal data of each channel group data signal output unit 31 to determine the correction amount of the waveform and set it in each Vby1 driver 3312 .
  • the control unit 6 may determine the correction amount of the waveform by using a learning method realized by artificial intelligence or the like, and set it in each Vby1 driver 3312 .
  • the method for determining the setting delay amount and the correction amount of the waveform is characterized in that, for example, each channel group data signal output unit 31 has a function of transmitting data such that the delay amount of each screen channel group can be known, and the corresponding channel group data on the receiving side.
  • the signal receiving unit 41 reports the data reception timing to the transmitting side based on the data, whereby the control unit 6 on the transmitting side can grasp the delay amount and change the setting value of the delay amount and/or the waveform correction amount for the picture channel group.
  • informative data also referred to as a synchronization code
  • the delay amount based on the detection time difference is set in the selection unit 3123 of the channel group data signal output unit 31 as the set delay amount.
  • the transmitted digital video signal is affected by the inductive and capacitive components based on the length of the cable, and the waveform is distorted.
  • This distortion is mainly manifested as a delay in the rise of the waveform, and in order to prevent this phenomenon, there is a technique of pre-emphasis, that is, a technique of enhancing the rise of the signal before transmission.
  • a technique of pre-emphasis that is, a technique of enhancing the rise of the signal before transmission.
  • using this technique to enhance the high-frequency components on the cable may increase the noise of the entire system, so unnecessary enhancement is generally not performed. Therefore, it is not considered preferable to apply the same pre-emphasis to all picture channel groups.
  • the pre-emphasis according to the length of the transmission cable flat cable 53 ) is performed for each picture channel group, so that it is possible to reduce the absolute amount of high-frequency components and suppress an increase in the noise of the entire system.

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Transforming Electric Information Into Light Information (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

提供消除屏幕面板上的视像信号数据的接收时机错开的数字视像信号生成电路、数字视像信号生成系统、数字视像信号生成方法及非易失性存储介质。数字视像信号生成电路同时接收为了将一个视像信号在多个画面上显示而分割出的多个视像信号数据，并且将与所述多个视像信号数据对应的各数字视像信号在不同的时机向不同的串行传输路径输出，以发送时间为单位来调整将各所述数字视像信号向各所述串行传输路径输出的时机，其中，所述发送时间是将各所述视像信号数据中的1符号的量的数据由各所述串行传输路径传输所需的时间。

Description

数字视像信号生成电路、数字视像信号生成系统、数字视像信号生成方法及非易失性存储介质
本申请要求在2020年7月15日提交日本专利局、申请号为2020-121511、发明名称为“数字视像信号生成电路、系统、方法及程序”的日本专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施方式涉及数字视像信号生成电路、数字视像信号生成系统、数字视像信号生成方法及非易失性存储介质。
背景技术
就作为数字电视的接收装置的薄型电视的屏幕面板而言，使用了液晶面板、OLED面板，但伴随着屏幕面板的大型化所导致的每一画面的像素数的增加等，视像信号数据向屏幕面板的发送量日渐增加。
通常，视像信号数据通过串行数据传输的信道来向屏幕面板发送，但为了发送增加的一画面的视像信号数据，使用了由将串行数据传输用的信道设置多条而形成的多信道来构成的扁平电缆(Flat cable)、多个扁平电缆。
在先技术文献
专利文献
专利文献1：日本专利第5290473号公报
专利文献2：日本特开2015－75495号公报
专利文献3：日本专利第4529443号公报
发明内容
然而，若是在不同的扁平电缆之间电缆的长度(以下称为电缆长)不同，则在屏幕面板上的一画面的视像信号数据之间接收时机会错开(时机偏差)， 导致视像可能无法正常显示。
本申请要解决的课题是提供消除屏幕面板上的视像信号数据的接收时机错开的数字视像信号生成电路、系统、方法及非易失性存储介质。
本申请一实施方式的数字视像信号生成电路同时接收为了将一个视像信号在多个画面上显示而分割出的多个视像信号数据，并且将与所述多个视像信号数据对应的各数字视像信号在不同的时机向不同的串行传输路径输出。
附图说明
图1是表示第一实施方式的接收装置的功能构成的示例的框图；
图2是表示该实施方式的接收装置的信道组数据信号输出部的功能构成的示例的框图；
图3是表示该实施方式的屏幕面板的画面显示区域的示例的图；
图4是表示该实施方式的接收装置的信道数据信号输出部的功能构成的示例的框图；
图5是表示该实施方式的接收装置的移位寄存器的构成的示例的图；
图6是表示该实施方式的接收装置的信道组数据接收部的功能构成的示例的框图；
图7是表示该实施方式的接收装置中的涉及到数字视像信号的传输的物理构成的示例的框图；
图8是表示该实施方式的接收装置的屏幕面板的物理构成的示例的框图；
图9是第二实施方式的接收装置中的数字视像信号的收发的示例。
附图标记说明
1···图像数据获取部，2···图像数据处理部，3···图像数据传输部，4···图像显示部，5···接口部，6···控制部，11···调谐部，12···解调部，13···视像信号处理部，21···图像处理部，22···图像分割部，31···信道组数据信号输出部，33···视像信号生成基板，41···信道组数据接收部，42···画面部，43···面板显示控制基板，45···延迟量测定部，46···通信部，47···延 迟量比较部，51－1～51－4···输出信号，52－1～52－4···输入信号，53－1～53－4···扁平电缆，L1～L16···屏幕面板区域，310···BEP，311···信道组数据分割部，312···信道数据信号输出部，312－1～311－NL···信道数据信号输出部，331、331－1～331－4···信道组视像信号输出部，410···T－CON，411···信道数据接收部，411－1～411－NL···信道数据接收部，412···信道组数据输出部，421···屏幕面板部，421－1～421－4···屏幕面板区域，422···面板驱动器，510···传输路径，3121···符号数据输出部，3122···移位寄存器，3123···选择部，3124···并行-串行转换部，3125···8B10B转换部，3126···接口部，3311－1～3311－4···延迟部，3312－1～3312－4···Vby1驱动器，4211－1～4211－4···扫描路径，4212－1～4212－4···像素。
具体实施方式
以下，参照附图来说明实施方式。
第一实施方式
在本实施方式中，示出的是如下情况下的示例：在将例如8K视像的显示画面分割为多个并将被分割的各显示画面的数据分别向不同的电缆分配来传输时，根据各电缆长来调整由各电缆传输的数字视像信号的输出时机。
通常，图像数据按照像素的颜色(RGB)而由1符号(1symbol)＝8bit的数据构成。示出将图像数据以符号为单位按各画面信道组(电缆)来统一调整数字视像信号的输出时机(延迟时间)的示例。
图1是表示第一实施方式的接收装置的功能构成的示例的框图。图像数据获取部1例如是数字电视广播的接收机，接收高级宽带数字卫星广播(4K/8K广播)的广播信号，并且获取视像信号(与视像内容相关的数据)。另外，并不局限于广播信号，例如也可以是从DVD、硬盘等存储介质、互联网获取到的数字电视广播用的视像信号等。
调谐部11经由未图示的天线、基于电缆广播的同轴电缆等，对期望的频带的广播信号电波进行接收处理。
解调部12从对广播信号电波进行解调所得的数字数据中提取与视像信号相关的数据。
视像信号处理部13对解调部12提取出的与视像信号相关的数据以规定的方法进行解码等数据处理，并且获取视像信号。
图像数据处理部2对视像信号处理部13输出的视像信号，进行以画质提高、图像数据的分割等为目的的数据处理。
图像处理部21对视像信号处理部13输出的视像信号进行以提高分辨率、提高帧速率、调整画质等为目的的数据处理，输出用于使屏幕面板部421显示视像的视像信号数据。这些方法是通常的方法，因此省略详情。
图像分割部22将视像信号数据按照预先确定的屏幕面板部421上的区域(称为屏幕面板区域)分开来输出。由此，能够将视像信号数据按屏幕面板区域并列地发送，还有助于缩短传输延迟。将图像分割部22输出的被分割的各视像信号数据称为画面信道组数据。画面信道组数据分别由不同的传输路径来传输。在图1中，示出从图像分割部22经由四个传输路径来发送各画面信道组数据的情况下的示例。针对屏幕面板区域将会在后进行叙述。
图像数据传输部3接收图像分割部22输出的画面信道组数据，经由串行传输用的接口，将画面信道组数据即被分割的视像信号数据向画面显示部4传输。这里，信道(lane)是指使用了串行数据传输的传输路径的最小单位即一根串行传输路径(称为串行传输线)的传输方式的信道，也称为串行信道。将使用多个串行信道来传输数据的方式称为多信道。在存在凭借串行信道无法应对这种程度的数据传输量的情况下，使用多信道。然而，由于近年来的屏幕面板大型化而使得1画面的数据量进一步增大，出现了连多信道都无法应对的状况。在本实施方式中，针对这种状况，采用使用多个多信道来应对的方式。另外，在本实施方式中，将使用多个多信道的方式中的各多信道称为画面信道组。
信道组数据信号输出部31－1、信道组数据信号输出部31－2、信道组数据信号输出部31－3、信道组数据信号输出部31－4对从图像分割部22分别 输入的画面信道组数据(被分割的视像信号数据)实施并行-串行转换、编码化等来生成数字视像信号，并分别向接口5－1、接口5－2、接口5－3、接口5－4输出数字视像信号。需要说明的是，信道组数据信号输出部31－1、信道组数据信号输出部31－2、信道组数据信号输出部31－3、信道组数据信号输出部31－4的功能是同样的，在不特意区分功能的情况下，按照表示各个信道组数据信号输出部的意思来称为信道组数据信号输出部31。
图像显示部4接收各画面信道组的数字视像信号，在画面部42显示视像内容，从而使得用户能够收看。
信道组数据接收部41－1、信道组数据接收部41－2、信道组数据接收部41－3、信道组数据接收部41－4分别经由接口部5－1、接口部5－2、接口部5－3、接口部5－4来接收信道组数据信号输出部31－1、信道组数据信号输出部31－2、信道组数据信号输出部31－3、信道组数据信号输出部31－4分别发送来的数字视像信号。需要说明的是，信道组数据接收部41－1、信道组数据接收部41－2、信道组数据接收部41－3、信道组数据接收部41－4的功能是同样的，在不特意区分功能的情况下，按照表示各个信道组数据接收部的意思来称为信道组数据接收部41。各信道组数据接收部41从数字视像信号中再生出画面信道组数据，将其向画面部42输出。
画面部42是显示器(monitor)，尤其是在本实施方式中，例如是液晶面板、OLED面板等数字电视用的薄型电视的大型显示器。画面部42从信道组数据接收部41－1、信道组数据接收部41－2、信道组数据接收部41－3、信道组数据接收部41－4接收视像信号数据，基于视像信号数据使面板驱动器等控制屏幕面板来显示视像内容，从而向用户提示视像内容。
延迟量测定部45具备对画面信道组数据之间的延迟量进行测定的功能。测定出的延迟量被利用于在信道组数据信号输出部31中设定的设定延迟量。设定延迟量是附加在数字视像信号的输出时机上的延迟量，将会在后叙述。
通信部46使用I2C等通信方式来在图像显示部4与图像数据传输部3之间进行数据的交换。延迟量比较部47例如对延迟量测定部45根据各画面信 道组数据到达时机算出的各画面信道组数据之间的延迟量进行比较，并将延迟差经由通信部46向控制部6发送。控制部6将接收到的延迟差作为针对各信道组数据信号输出部31而言的设定延迟量来设定。
接口部5－1、接口部5－2、接口部5－3、接口部5－4例如是串行数据传输用的扁平电缆，是用于从图像数据传输部3向图像显示部4传输数字视像信号的串行传输线的线束。接口部5包含用于传输数字视像信号的协议，在本实施方式中适用作为串行数据传输的标准的Vbyone(注册商标)。
Vbyone通常是在将数字视像信号向屏幕面板等传输时使用的串行数据传输的标准，包括一对差分线。一对差分线(串行传输线)与信道对应，多根(例如在本实施方式中为16根)串行传输线成束而构成的扁平电缆与画面信道组(多信道)对应。需要说明的是，由于Vbyone为通常的技术，因此省略详细情况。需要说明的是，接口部5－1、接口部5－2、接口部5－3、接口部5－4的功能是同样的，在不特意区分的情况下，按照表示各个接口部的意思来称为接口部5。
在Vbyone的标准中，能够根据由各串行传输线传输的数据而在接收侧生成时钟，因此能够按信道来具有时钟。另外，根据Vbyone的标准，若将生成的时钟周期设为UI，则Vbyone的接收侧的各信道之间的时钟周期的时机错开被抑制为5UI。具体而言，在8K电视中，1UI约为350ps，因此必须抑制在5UI≈1.7ns以内。
即便各信道的时钟周期的时机错开被抑制得小，Vbyone的接收侧的数据接收时机错开也可能会成为问题。具体而言，若设为与空气相等的介电常数1且将电信号的传输速度设为3×10 8m/s，则1时钟的传播距离为100mm这种程度。传播距离在介电常数高的印制电路板、扁平电缆中会变得更短，因此在印制电路板上的图案设计、连结电路板彼此的电缆长不同的情况下，在电缆之间可能会发生数据接收时机错开(时机偏差)。
在本实施方式中，如图1所示，使用电缆长存在差异的接口部5－1、接口部5－2、接口部5－3、接口部5－4(相当于各扁平电缆)。这种情况下， 在一个画面信道组内(扁平电缆内)长度一致，但存在按画面信道组(扁平电缆之间)而长度不同的可能性，这种情况下，延迟时间差变得显著，发生时机偏差的可能性高。在本实施方式中，通过后述的调整符号数据(Symbol data)的时钟(Symbol clock，符号时钟)来消除时机偏差。
控制部6向各信道组数据信号输出部31设定用于改变从各信道组数据信号输出部31输出的数字视像信号的输出时机的设定延迟量。设定延迟量可以是用户根据接口部5－1、接口部5－2、接口部5－3、接口部5－4的电缆长之差来计算。例如针对电缆长最长的接口部5的信道组数据信号输出部31将设定延迟量设为0。针对其他的信道组数据信号输出部31，以使其连接的接口部5的电缆长(传输时间)加上设定延迟量所得的传输时间与最长的接口部5的传输时间相同的方式确定设定延迟量。确定出的设定延迟量例如可以从未图示的计算机用键盘、电视的遥控器等用户接口经由控制部6而向各信道组数据信号输出部31设定。
另外，可以针对控制部6输入向各信道组数据信号输出部31输入的视像信号数据(称为输入视像信号数据)和从信道组数据接收部41输出的视像信号数据(称为输出视像信号数据)，控制部6一边对输入视像信号数据与输出视像信号数据进行比较一边调节并确定设定延迟量。例如，可以从控制部6向各信道组数据信号输出部31设定用于使输入视像信号数据与输出视像信号数据一致的设定延迟量。
另外，也可以是使用了基于人工智能等实现的学习的方法。具体而言，针对各信道组数据信号输出部31赋予适当的中间值的延迟量来作为设定延迟量并使其动作。对任一组信道的输入视像信号数据与输出视像信号数据进行比较，若确认其正常动作，则调节其他组信道的设定延迟量，对输入视像信号数据与输出视像信号数据进行比较并确认其正常动作。通过将该方法针对全部组信道进行实施来确定对全部组信道而言的设定延迟量，并将确定出的设定延迟量向各信道组数据信号输出部31设定。
控制部6和图像数据传输部3或图像显示部4也可以通过I2C等通信方 式来进行数据的交换。
图2是表示该实施方式的接收装置的信道组数据信号输出部的功能构成的示例的框图。信道组数据分割部311对从图像分割部22输入的画面信道组数据(被分割的视像信号数据)进行分割而作为数字视像信号向多个串行传输线输出。将信道组数据分割部311输出的数据称为信道数据。通过分割为信道数据，由此即便在一根串行传输线中的传输速度受限的情况下也能够发送画面信道组数据。
信道数据信号输出部312－1、信道数据信号输出部312－2、信道数据信号输出部311－NL分别生成用于向串行传输线输出的数字视像信号。NL是能够分配一个画面信道组数据的最大信道数，相当于扁平电缆内的串行传输线的数目。在本实施方式中，NL设为16。需要说明的是，信道数据信号输出部312－1、信道数据信号输出部312－2、信道数据信号输出部311－NL的功能是同样的，因此只要不特意进行区分，则按照表示各个信道数据信号输出部的意思来称为信道数据信号输出部312。
各信道数据信号输出部312针对从信道组数据分割部311输入的信道数据，按照接口部5的协议等来生成数字视像信号并将其向接口部5输出。
图3是表示该实施方式的屏幕面板的画面显示区域的示例的图。屏幕面板区域421－1、屏幕面板区域421－2、屏幕面板区域421－3、屏幕面板区域421－4分别对应于画面信道组数据。即，将画面部42的屏幕面板(例如后述的屏幕面板部421)分割为四个屏幕面板区域421－1、屏幕面板区域421－2、屏幕面板区域421－3、屏幕面板区域421－4，将各屏幕面板区域中的像素(pixel)信息分别设为画面信道组数据。需要说明的是，屏幕面板区域421－1、屏幕面板区域421－2、屏幕面板区域421－3、屏幕面板区域421－4是屏幕面板内的同样的区域，在不特意区分的情况下，按照表示各个屏幕面板区域的意思来称为屏幕面板区域421。
扫描路径4211－1、扫描路径4211－2、扫描路径4211－3、扫描路径4211－4分别示意性地表示屏幕面板区域421－1、屏幕面板区域421－2、屏幕面 板区域421－3、屏幕面板区域421－4中的扫描线的路径。需要说明的是，扫描路径4211－1、扫描路径4211－2、扫描路径4211－3、扫描路径4211－4是同样的扫描线的路径，在不特意区分的情况下，按照表示各个扫描路径的意思来称为扫描路径4211。
扫描路径4211由实线箭头和虚线箭头构成，实线箭头表示扫描线。虚线箭头表示扫描线之间的移动。例如，示出在画面部42的屏幕面板上从最上部的实线箭头(扫描线)开始按顺序从左到右地扫描的情形。扫描分别按屏幕面板区域421－1、屏幕面板区域421－2、屏幕面板区域421－3、屏幕面板区域421－4来实施。需要说明的是，在图3中，各屏幕面板区域421的扫描线仅示出10条线，但实际上具有4000条线等与数字电视的对应像素相匹配的线。
以下，详细示出作为屏幕面板区域来分割的理由。由于近年来的数字电视的大型化，每一画面的像素数增加。数字电视的数字视像信号原本是由一根串行数据传输信道发送的信号，但由于视像画面显示循环(以下称为帧速率)不变，因此像素数增加意味着数字视像信号的频率增加。例如，简单对8K图像的像素部分进行计算的话，将帧速率设为120Hz，将像素数设为7680×4320，将RGB各色设为8bit的分辨率，将视像信号数据进行了8B10B转换，此时，必须以约150GHz的时钟频率从图像数据传输部3向画面显示部4传送。由于实际上针对同步信号、画面设有空白部分，因此成为更高的频率，在物理上不可能将数字视像信号用一根串行传输线来发送。在本实施方式中，对8K画面进行4分割并分别独立地处理数据，进而，将例如16根串行传输信道的束作为画面信道组来成束，使用四个画面信道组(四个扁平电缆)对4分割后的各屏幕面板区域进行数字视像信号的发送，这样的话，即便包含格式上的空白，时钟频率也会下降至3GHz这样的程度，因此能够进行数据传送。
各屏幕面板区域421的各像素的数据按照扫描路径4211的顺序向各信道组数据信号输出部31输入。各像素的数据包括R、G和B的符号数据。符号数据是指向1像素(pixel)的R、G、B分别分配的位数据(Bit data)。通常， 在基于8K广播形成的视像图像的情况下，R、G、B的符号数据例如分别由8bit的数据构成。
像素4212－1、像素4212－2、像素4212－3、像素4212－4分别表示屏幕面板区域421－1、屏幕面板区域421－2、屏幕面板区域421－3、屏幕面板区域421－4上的像素(pixel)的示例。需要说明的是，像素4212－1、像素4212－2、像素4212－3、像素4212－4是同样的像素的示例，在不特意区分的情况下，按照表示各个像素的意思来称为像素4212。
作为四个屏幕面板区域421各自的像素的示例，分别示出三个像素(P11、P12、P13)、(P21、P22、P23)、(P31、P32、P33)、(P41、P42、P43)，按屏幕面板区域421以扫描路径4211的顺序从画面分割部22输出。这些像素数据同时向信道组数据信号输出部31输入。具体而言，屏幕面板区域421各自的像素P11、P21、P31、P41的数据同时向各信道组数据信号输出部31输入，向各信道组数据信号输出部31的信道数据信号输出部312－1以同样的时机输入。例如在像素(P11、P12、P13)的数据向信道组数据信号输出部31－1输入的情况下，像素(P11、P12、P13)分别向信道数据信号输出部312－1、信道数据信号输出部312－2、信道数据信号输出部312－3输入。这里，示出了三个像素的示例，但NL个像素的数据分别向信道数据信号输出部312－1～信道数据信号输出部312－NL输入。
需要说明的是，这些像素P11、P21、P31、P41的数据需要从信道组数据接收部41以同样的时机输出而向画面部42以同样的时机输入。
图4是表示该实施方式的接收装置的信道数据信号输出部的功能构成的示例的框图。符号数据输出部3121将从信道组数据分割部311输入的信道数据分割为R、G、B的符号数据来输出。符号数据输出部3121在输入的符号时钟的时机下输出符号数据。符号时钟是对1像素(R、G、B各自的1符号数据)的数据进行处理的时间间隔。
移位寄存器3122－1、移位寄存器3122－2、移位寄存器3122－NSR分别是例如将NFF个触发器(flip-flop)并行地排列而成的一段移位寄存器。NFF 是触发器的数目。由于移位寄存器3122－1、移位寄存器3122－2、移位寄存器3122－NSR具有同样的功能，因此在不特意区分功能的情况下，按照表示各个移位寄存器的意思来称为移位寄存器3122。NSR是移位寄存器的数目。移位寄存器3122是在输入的符号时钟的时机下动作的移位寄存器。具体而言，移位寄存器3122在被输入1像素(R、G、B各自的1符号数据)的数据的同时输出触发器的数据。被输入了的1像素(R、G、B各自的1符号数据)的数据向触发器输入。即，能够通过移位寄存器3122－1、移位寄存器3122－2、移位寄存器3122－NSR来对1像素(R、G、B各自的1符号数据)的数据的输出赋予以符号时钟为单位的延迟时间(最大为与NSR个符号时钟对应的延迟时间)。
图5是表示该实施方式的接收装置的移位寄存器的构成的示例的框图。
在符号时钟的时机下，各画面信道组的1符号数据(8bit)向移位寄存器3122并行地输入。触发器(FF)的数据的输出与数据向FF的输入在符号时钟的时机下同时进行。
返回到图4，选择部3123确定将来自移位寄存器3122－1、移位寄存器3122－2、移位寄存器3122－NSR中的哪个移位寄存器的输出向后段输出，并将确定了的移位寄存器的输出向后段输出。在本实施方式的选择部3123中设定有从控制部6按信道组数据信号输出部31输入的设定延迟量，选择部3123将与设定好的设定延迟量对应的移位寄存器选择为向后段输出的移位寄存器。在本实施方式中，在各信道组数据信号输出部31内的全部的信道数据信号输出部312中设定相同的设定延迟量。
并行-串行转换部3124将来自选择部3123确定了的移位寄存器3122－1、3122－2、3122－NSR中的任一个的输出(针对1像素来说的R、G、B数据位的并行数据)转换为串行数据(也称为串行信道数据)。
8B10B转换部3125对从并行-串行转换部3124输入的串行信道数据实施8B10B转换，并输出转换后的串行信道数据(称为转换串行信道数据)。8B10B转换(也称为8B10B调制)是通常的编码化的方式，省略对详细情况的说明。
接口部3126对从8B10B转换部3125输入的转换串行信道数据，按照接口部5的协议进行各种数据的转换、帧数据的生成、信号的生成等来生成数字视像信号，并将生成了的数字视像信号向接口部5输出。在本实施方式中，由于在接口部5适用Vbyone，因此，接口部3126按照Vbyone的规约来生成数字视像信号并向接口部5输出。Vbyone的接收侧所必须的Vbyone的时钟根据由串行传输线发送的位(bit)数来确定。Vbyone的时钟简单设为符号时钟的10倍以上的值。
由于如上所述那样移位寄存器3122按照符号时钟来动作，因此，就设定延迟量而言，实际上附加在数字视像信号的输出时机上的延迟量成为符号时钟的整数倍的延迟量。
需要说明的是，在本实施方式中，按信道数据信号输出部312来记载了移位寄存器3122、并行-串行转换部、8B10B转换部、接口部，但也可以按信道组数据信号输出部31来一对一地设置移位寄存器3122、并行-串行转换部、8B10B转换部、接口部，从而使各信道数据信号输出部312共有移位寄存器3122、并行-串行转换部、8B10B转换部、接口部。
图6是表示该实施方式的接收装置的信道组数据接收部的功能构成的示例的框图。
信道数据接收部411－1、信道数据接收部411－2、信道数据接收部411－NL分别从接口部5接收数字视像信号并实施各种数据的转换等，输出信道数据。信道数据接收部411－1、信道数据接收部411－2、信道数据接收部411－NL分别接收从信道数据信号输出部312－1、信道数据信号输出部312－2、信道数据信号输出部312－3、信道数据信号输出部312－4输出的数字视像信号。NL表示各接口部5内的信道的数目，在本实施方式中NL＝16。需要说明的是，信道数据接收部411－1、信道数据接收部411－2、信道数据接收部411－NL具备同样的功能，在不特意区分的情况下，按照表示各个信道数据接收部的意思来称为信道数据接收部411。
信道数据接收部411具备与信道数据信号输出部312的接口部3126、 8B10B转换部3125、并行-串行转换部3124分别对应的未图示的接口部、串行-并行转换部、8B10B解码部。
信道数据接收部411的接口部利用与接口部3126的协议对应的接收方法(在本实施方式中为基于Vbyone的规约的接收方法)来接收从接口部5接收到的数字视像信号，并获取转换串行信道数据而向8B10B解码部输出。8B10B解码部对输入了的转换串行信道数据，按照基于8B10B调制的规约来输出串行信道数据。串行-并行转换部将串行信道数据转换为并行的信道数据来输出。
信道组数据输出部412根据各信道数据接收部411输出的信道数据，再生画面信道组数据，并在既定的时机下向画面部42输出。
在本实施方式中，在各信道数据接收部411的接口部处接收到的各转换串行信道数据取得了同步，因此各信道数据接收部411输出的串行信道数据之间也取得了同步。进而，就从各信道组数据接收部41输出的画面信道组数据而言，也在各画面信道组数据之间取得了同步。具体而言，图3的P11、P21、P31、P41被从各信道组数据接收部41同时输出。其理由是因为在各信道组数据输出部31的选择部3123中按各画面信道组数据来变更了数字视像信号的输出时机。
图7是表示该实施方式的接收装置中的涉及到数字视像信号的传输的物理构成的示例的框图。
视像信号生成基板33例如具备图像数据传输部2、图像数据传输部3的信道组数据信号输出部31的功能，对接收到的视像信号进行处理并输出数字视像信号。
面板显示控制基板43具备信道组数据接收部41的功能，包括用于控制屏幕面板421的像素的像素驱动元件。
扁平电缆53－1、扁平电缆53－2、扁平电缆53－3、扁平电缆53－4分别对应于接口部5－1、接口部5－2、接口部5－3、接口部5－4。
随着电视的大型化、高清化，与各画面信道组对应的扁平电缆的长度之差趋向于变大。在本实施方式中，选择部3123考虑按画面信道组来设定的扁 平电缆的设定延迟量来变更从视像信号生成基板33输出的数字视像信号的输出时机，由此使向面板显示控制基板43输入的数字视像信号的时机一致以吸收扁平电缆的长度之差。
在本实施方式中，示出按并行数据(将符号数据的位(bit)并行了的状态)以符号时钟为单位来进行延迟量的设定的情况下的示例。视像信号相对于画面上的一视像部位(像素)具有符号数据(例如8bit)。视像信号以该符号数据为单位被进行画质提高等处理，因此被作为并行数据来处理。并行数据的处理使用符号时钟这样的比Vbyone的时钟慢的时钟(例如是Vbyone的时钟的八分之一)。在本实施方式中，使用该符号时钟来将像素数据的输出以符号时钟为时间单位地通过移位寄存器进行延迟，选择部3123通过确定将第几段移位寄存器的像素数据用作输出数据来确定对输出时机的延迟量。
需要说明的是，延迟量的附加也可以使用取代符号时钟而利用了Vbyone的时钟的移位寄存器。这种情况下，不是像移位寄存器3122那样将触发器FF并行地连接，而是串行地连接FF。然而，在串行地连接FF的情况下，移位寄存器与并行的移位寄存器3122相比需要将动作速度设为高速。即，在要用移位寄存器对串行数据设定延迟量时，存在移位寄存器的时钟快且段数增加的缺点。另外，若是以高速时钟动作的电路多，则消耗电力、IC内的布局设计变得困难，因此优选像移位寄存器3122那样以符号为单位进行调整。
像本实施方式那样，通过利用选择部3123，以符号时钟时间单位按画面信道组来调整延迟量，由此能够消除数字视像信号的时间偏差。另外，若是以符号时钟时间单位进行调整，则还具有能够在画面信道组之间确保相对于Vbyone所规定的作为基准的信道而言±5UI的精度这样的效果。
图8是表示该实施方式的接收装置的屏幕面板的物理构成的示例的框图。
画面部42是包括屏幕面板部421和面板驱动器422的例如液晶面板或OLED面板。
屏幕面板部421是通过利用面板驱动器422按像素来控制RGB的光源等而将视像作为收看信息提供给用户的部分。
面板驱动器422从信道组数据输出部412接收画面信道组数据，按照画面信道组数据来控制屏幕面板部421的显示。具体而言，面板驱动器422对与接收到的画面信道组数据对应的屏幕面板部421的区域，执行显示的控制。
由于BEP310、T－CON410、传输路径510设置在屏幕面板部421的背面侧、即无法收看的一侧，因此虚线示出。T－CON410设置在屏幕面板部421的中央下部，BEP310设置在T－CON410的旁边。
BEP310是针对画面显示部4的后端处理电路(Back End Processor)，具备图像数据传输部3的功能。
T－CON410是包含在信道组数据接收部41中的、对信道组数据输出部412向面板驱动器422输出画面信道组数据的时机进行控制的时机控制器。
传输路径510是将BEP310与T－CON410连接的数字视像信号的传输路径，包括所有的扁平电缆53－1、扁平电缆53－2、扁平电缆53－3、扁平电缆53－4。
在本实施方式中，T－CON410针对从各信道组数据接收部41输出的画面信道组数据能在各信道组数据之间取得同步。其理由是因为在图像数据传输部3的各信道组数据输出部31的选择部3123中，按画面信道组数据变更了数字视像信号的输出时机。因此，各信道组数据接收部41输出的画面信道组数据之间的时机不会错开(没有时机偏差)，不会产生显示上的问题。
如图7所示，在薄型电视等面板型电视中，分为生成数字视像信号的视像信号生成基板33(包括BEP310)和根据接收到的数字视像信号来驱动(控制)屏幕面板421的各像素元件的面板显示控制基板43(包括T－CON410)。若是两个电路基板之间传输的数字视像信号的接收时机在各画面信道组之间错开，则无法在屏幕面板421显示所期望的视像。在像素数为4K程度的分辨率的情况下，以3GHz这样的时钟频率16信道的话一根扁平电缆就能够传输，因此时机偏差的变动范围不会变大。
另一方面，在与8K电视等大型高清电视对应的单体的大型面板的情况下，为了高效地向面板的元件逐一地施加信号，可以进行画面的分割(纵向分割 或横向分割)。在8K电视等中进行了画面分割的情况下，按各分割出的画面的视像信号数据，从BEP310使用多个扁平电缆来同时进行传输。
然而，若扁平电缆的电缆长存在不均，则会产生数字视像信号的接收时机错开的问题(时机偏差)，在8K电视等高速传输时该问题变得显著。
通过以上所示的本实施方式，能够解决在大型高清电视中发生的因电缆长不均而导致的时机偏差的问题。另外，通过本实施方式，无需在不同的扁平电缆之间使电缆长一致，与电视的结构设计及电缆的布线相关的自由度增加，能够实现性能提高且制造成本降低的设计。需要说明的是，在本实施例中，将1符号作为8bit来进行了说明，但当然也可以容易地将1符号扩大为10bit、12bit。
(第二实施方式)
若各画面信道组(例如接口部5－1、接口部5－2、接口部5－3、接口部5－4)的扁平电缆的长度不同，则不仅是传输延迟时间会改变，电缆的特性也会改变。若电缆的特性改变，则由电缆传输的数字视像信号的波形失真的状态会改变。波形失真的状态取决于扁平电缆的长度。由于产生波形失真而导致数字视像信号的波形产生迟缓，因此对数字视像信号的接收时机产生影响。即，传输各画面信道组数据的扁平电缆之间的电缆长的差异牵涉到波形失真的状态的差异，还会使被传输的数字视像信号的传输延迟时间也产生差异。在本实施方式中，说明了如下示例：根据针对各画面信道组设定的设定延迟量(电缆长)，改变Vbyone的驱动器中的预加重(Pre-emphasis)的程度，由此解决上述问题。
图9是第二实施方式的接收装置中的数字视像信号的收发的示例。
信道组视像信号输出部331－1、信道组视像信号输出部331－2、信道组视像信号输出部331－3、信道组视像信号输出部331－4具备与针对各画面信道组的图1的信道组数据信号输出部31同样的功能。在本图中，与图1的信道组数据信号输出部31不同，仅示出针对信道组数据信号输出部31内的一个信道数据的功能，但包括针对全部的信道数据的功能。从图像分割部22向 信道组视像信号输出部331－1、信道组视像信号输出部331－2、信道组视像信号输出部331－3、信道组视像信号输出部331－4分别输入各屏幕面板区域的画面信道组数据，从信道组视像信号输出部331－1、信道组视像信号输出部331－2、信道组视像信号输出部331－3、信道组视像信号输出部331－4输出各信道的数字视像信号。需要说明的是，信道组视像信号输出部331－1、信道组视像信号输出部331－2、信道组视像信号输出部331－3、信道组视像信号输出部331－4具备同样的功能，因此在不特意进行区分的情况下，按照表示各个信道组视像信号输出部的意思来称为信道组视像信号输出部331。
延迟部3311－1、延迟部3311－2、延迟部3311－3、延迟部3311－4分别控制输入了的信道数据的数字视像信号的输出时机，并将其作为并行数据来输出。需要说明的是，延迟部3311－1、延迟部3311－2、延迟部3311－3、延迟部3311－4具备同样的功能，因此只要不特意进行区分，则按照表示各个延迟部的意思来称为延迟部3311。各延迟部3311具备与图5中的移位寄存器3122、选择部3123同样的功能。
Vby1驱动器3312－1、Vby1驱动器3312－2、Vby1驱动器3312－3、Vby1驱动器3312－4分别针对输入了的串行的信道数据，根据需要来修正数字视像信号的输出的波形并将其输出。修正数字视像信号的输出波形的操作被称为预加重。预加重为通常的技术，省略对具体的方法的说明。Vby1驱动器3312－1、Vby1驱动器3312－2、Vby1驱动器3312－3、Vby1驱动器3312－4具备同样的功能，因此只要不特意进行区分，则按照表示各个Vby1驱动器的意思来称为Vby1驱动器3312。
Vby1驱动器3312例如包含在图4的接口部3126中。需要说明的是，在图9中，没有示出图4中的并行-串行转换部3124、8B10B转换部3125，但在图9中也包括同样的功能。因此，向Vby1驱动器3312输入的数据是与8B10B转换部3125相当的功能输出的串行数据。
扁平电缆53－1、扁平电缆53－2、扁平电缆53－3、扁平电缆53－4分别与图1的接口部5－1、接口部5－2、接口部5－3、接口部5－4对应，是 将Vby1驱动器3312－1、Vby1驱动器3312－2、Vby1驱动器3312－3、Vby1驱动器3312－4输出的数字视像信号在Vbyone的协议下传输的传输路径，例如是扁平电缆。在图中，针对扁平电缆53－1、扁平电缆53－2、扁平电缆53－3、扁平电缆53－4分别仅示出一对(pair)差分线(1根串行传输线)，但扁平电缆53－1、扁平电缆53－2、扁平电缆53－3、扁平电缆53－4分别具备未图示的多个串行传输线。在本实施方式中，扁平电缆53－1、扁平电缆53－2、扁平电缆53－3、扁平电缆53－4分别具备16根差分线(多信道)。需要说明的是，扁平电缆53－1、扁平电缆53－2、扁平电缆53－3、扁平电缆53－4具备同样的功能，因此只要不特意进行区分，则按照表示各个扁平电缆的意思来称为扁平电缆53。
输出信号51－1、输出信号51－2、输出信号51－3、输出信号51－4分别表示信道组视像信号输出部331－1、信道组视像信号输出部331－2、信道组视像信号输出部331－3、信道组视像信号输出部331－4输出的数字信号波形的示例。需要说明的是，输出信号51－1、输出信号51－2、输出信号51－3、输出信号51－4是同样的信号，因此只要不特意进行区分，则按照表示各个输出信号的意思来称为输出信号51。
输入信号52－1、输入信号52－2、输入信号52－3、输入信号52－4分别表示信道组视像信号输出部331－1、信道组视像信号输出部331－2、信道组视像信号输出部331－3、信道组视像信号输出部331－4输出的数字视像信号分别经由扁平电缆53－1、扁平电缆53－2、扁平电缆53－3、扁平电缆53－4马上到达面板显示控制基板43之前的波形的示例。需要说明的是，输入信号52－1、输入信号52－2、输入信号52－3、输入信号52－4是同样的信号，因此只要不特意进行区分，则按照表示各个输入信号的意思来称为输入信号52。
面板显示控制基板43与图7中的说明同样。
图9示出扁平电缆53的电缆长彼此不同的情况下的示例。根据连接的各扁平电缆53的电缆长，在各延迟部3311中对数字视像信号的输出时机附加 延迟。具体而言，由于电缆长按照扁平电缆53－1、扁平电缆53－2、扁平电缆53－3、扁平电缆53－4的顺序变长，因此按照延迟部3311－1、延迟部3311－2、延迟部3311－3、延迟部3311－4的顺序，增大对数字视像信号的输出时机附加的延迟量。这里，将各扁平电缆53内的各串行传输线之间的长度差视作可以忽视，将向延迟部3311中的选择部3123设定的设定延迟量设为相同的值。将按信道组视像信号输出部331确定了的设定延迟量设定在各延迟部3311的选择部3123中。选择部3123基于设定好的设定延迟量来确定输出信道数据的移位寄存器3122。
接着，由于数字视像信号的波形的劣化程度取决于传输数字视像信号的各扁平电缆53的电缆长，因此在Vby1驱动器3312中，根据与各Vby1驱动器3312连接的扁平电缆53的电缆长来修正输出信号51的波形。具体而言，Vby1驱动器3312－1、Vby1驱动器3312－2、Vby1驱动器3312－3、Vby1驱动器3312－4如图9所示那样以使输入信号52－1、输入信号52－2、输入信号52－3、输入信号52－4的波形相同的方式，对输出信号51－1、输出信号51－2、输出信号51－3、输出信号51－4分别进行修正。在图9的示例中，由于电缆长按照扁平电缆53－1、扁平电缆53－2、扁平电缆53－3、扁平电缆53－4的顺序变长，因此按照Vby1驱动器3312－1、Vby1驱动器3312－2、Vby1驱动器3312－3、Vby1驱动器3312－4的顺序来增加波形的修正量(增大预加重)。
Vby1驱动器3312－1、Vby1驱动器3312－2、Vby1驱动器3312－3、Vby1驱动器3312－4各自的波形的修正量例如可以由控制部6来确定，并由控制部6设定在各Vby1驱动器3312中。也可以由用户来确定波形的修正量，从未图示的用户接口向控制部6设定。另外，还可以是控制部6对各信道组数据信号输出部31的输入视像信号数据与输出视像信号数据进行比较来确定波形的修正量，并设定在各Vby1驱动器3312中。另外，还可以是控制部6使用利用了基于人工智能等实现的学习方法来确定波形的修正量，并设定在各Vby1驱动器3312中。
设定延迟量、波形的修正量的确定方法的特征在于，例如各信道组数据信号输出部31具备发送可知晓各画面信道组的延迟量这样的数据的功能，接收侧的对应的信道组数据信号接收部41基于该数据来将数据的接收时机向发送侧报告，由此发送侧的控制部6能够掌握延迟量来变更针对画面信道组的延迟量及/或波形修正量的设定值。作为可知晓画面信道组的延迟量这样的数据，可以使用通过串行传输发送的提示性数据(也称为同步代码)。通过按各画面信道组来检测同步代码并测定检测时间差，由此将基于检测时间差的延迟量作为设定延迟量而设定在各信道组数据信号输出部31的选择部3123中。
通过以上的步骤，在各画面信道组的作为传输路径的扁平电缆的长度不同的情况下，即便是不仅传输延迟时间不同连基于电缆的特性的波形失真的状态也不同，也能够消除由各扁平电缆传输的数字视像信号在面板显示基板43中的接收时机的错开，从而消除向屏幕面板输出的画面信道组数据的输出时机的错开。
传输的数字视像信号受到基于电缆的长度的电感成分和电容成分的影响而会发生波形的失真。该失真主要表现为波形的上升的迟缓，为了预防该现象，有预加重这样的技术、即增强传输前的信号的上升的技术。但是，通过进行该技术而使电缆上的高频成分增强，可能会导致系统整体的噪声增加，因此通常不进行不必要的增强。因此，认为对全部的画面信道组实施同样的预加重是不优选的。根据本实施方式，按画面信道组来实施与传输的电缆(扁平电缆53)的长度相匹配的预加重，因此具有能够减小高频成分的绝对量并且抑制系统整体的噪声的增加的效果。
根据以上所述的至少一个实施方式，能够提供消除屏幕面板上的视像信号数据的接收时机错开的数字视像信号生成电路、系统、方法及计算机可读的非易失性存储介质。
说明了本申请的几个实施方式，但这些实施方式是作为示例来提示的，并不意在限定申请的范围。这些新的实施方式可以以其他各种各样的形态来实施，可以在不脱离申请的主旨的范围内进行各种省略、置换、变更。这些 实施方式及其变形包含在申请的范围、主旨内，并且包含在权利要求书所记载的发明及与其等同的范围内。进而，就权利要求的各构成要素而言，将构成要素分割表述、将多个构成要素合在一起表述或者组合上述两种方式来表述的情况都包含在本申请的范畴中。另外，也可以组合多个实施方式，由该组合构成的实施例也包含在申请的范畴中。
另外，附图用于更一步明确说明，与实际的方案相比有时将各部的宽度、厚度、形状等示意性地表示。在框图中，有时也在没有连线的功能块之间或者即便连线但不是箭头所示的方向上进行数据、信号的交换。框图所示的各功能、流程图、序列图所示的处理可以通过硬件(IC芯片等)、软件(程序等)、数字信号处理用运算芯片(Digital Signal Processor、DSP)或者上述的硬件与软件的组合来实现。另外，在将权利要求表述为控制逻辑、将权利要求表述为包含使计算机执行的指令的程序以及将权利要求表述为记载有所述指令的可供计算机读取的存储介质的情况下，都可以适用本申请的装置。另外，对于所使用的名称、用语也没有限定，其他的表述只要实质上内容相同、意思相同，则也包含在本申请中。

Claims (9)

  1. 一种数字视像信号生成电路，其中，
    所述数字视像信号生成电路同时接收为了将一个视像信号在多个画面上显示而分割出的多个视像信号数据，并且将与所述多个视像信号数据对应的各数字视像信号在不同的时机向不同的串行传输路径输出。
  2. 根据权利要求1所述的数字视像信号生成电路，其中，
    以发送时间为单位来调整将各所述数字视像信号向各所述串行传输路径输出的时机，其中，所述发送时间是将各所述视像信号数据中的1符号的量的数据由各所述串行传输路径传输所需的时间。
  3. 根据权利要求1或2所述的数字视像信号生成电路，其中，
    以发送时间为单位来调整将各所述数字视像信号向各所述串行传输路径输出的时机，其中，所述发送时间是将各所述视像信号数据中的1符号内的比特由各所述串行传输路径传输所需的时间。
  4. 根据权利要求1～3中任一项所述的数字视像信号生成电路，其中，各所述数字视像信号向所述串行传输路径的输出时机由传输各所述数字视像信号的所述串行传输路径的长度来确定。
  5. 根据权利要求1～4中任一项所述的数字视像信号生成电路，其中，所述数字视像信号生成电路以第一数字视像信号向各所述串行传输路径中的具有最大的长度的第一串行传输路径的输出时机为基准，来延迟第二数字视像信号向除第一串行传输路径以外的第二串行传输路径的输出时机，
    将由所述第一串行传输路径的长度确定的第一传输时间与由所述第二串行传输路径的长度确定的第二传输时间之差，设为针对所述第二数字视像信号的输出时机的延迟量。
  6. 根据权利要求1～5中任一项所述的数字视像信号生成电路，其中，各所述数字视像信号根据取决于各所述串行传输路径的长度的波形失真的特性被修正，并且向各所述串行传输路径输出。
  7. 一种数字视像信号生成系统，其中，所述数字视像信号生成系统具备：
    数字视像信号生成电路，其同时接收为了将一个视像信号在多个画面上显示而分割出的多个视像信号数据，并且将与所述多个视像信号数据对应的各数字视像信号在不同的时机向不同的串行传输路径输出；以及
    画面显示机构，其与所述串行传输路径连接，对各所述数字视像信号进行接收处理，并且获取所述多个视像信号数据，
    所述数字视像信号生成电路将特定的数据包含在各数字视像信号中来发送，
    所述画面显示机构具备延迟差测定机构，该延迟差测定机构从各数字视像信号中接收所述特定的数据，并且根据所述特定的数据来测定各数字视像信号之间的延迟差，
    所述数字视像信号生成电路基于从所述延迟差测定机构接收到的各所述数字视像信号之间的延迟差，确定针对各所述数字视像信号的输出时机的延迟量。
  8. 一种数字视像信号生成方法，其中，所述方法包括：
    同时接收为了将一个视像信号在多个画面上显示而分割出的多个视像信号数据，并将与所述多个视像信号数据对应的各数字视像信号在不同的时机向不同的串行传输路径输出。
  9. 一种非易失性存储介质，其存储有程序或计算机指令，其中，该程序或计算机指令在计算机上被执行并且使计算机执行：
    同时接收为了将一个视像信号在多个画面上显示而分割出的多个视像信号数据，并且将与所述多个视像信号数据对应的各数字视像信号在不同的时机向不同的串行传输路径输出。
PCT/CN2021/077664 2020-07-15 2021-02-24 数字视像信号生成电路、数字视像信号生成系统、数字视像信号生成方法及非易失性存储介质 WO2022012050A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202180001649.3A CN114430912A (zh) 2020-07-15 2021-02-24 数字视像信号生成电路、数字视像信号生成系统、数字视像信号生成方法及非易失性存储介质

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2020-121511 2020-07-15
JP2020121511A JP7330928B2 (ja) 2020-07-15 2020-07-15 デジタル映像信号生成回路およびシステム

Publications (1)

Publication Number Publication Date
WO2022012050A1 true WO2022012050A1 (zh) 2022-01-20

Family

ID=79556109

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/077664 WO2022012050A1 (zh) 2020-07-15 2021-02-24 数字视像信号生成电路、数字视像信号生成系统、数字视像信号生成方法及非易失性存储介质

Country Status (3)

Country Link
JP (1) JP7330928B2 (zh)
CN (1) CN114430912A (zh)
WO (1) WO2022012050A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011234181A (ja) * 2010-04-28 2011-11-17 Panasonic Corp 表示装置
CN103986960A (zh) * 2014-06-03 2014-08-13 王军明 一种单视频画面分割多路由远传精确同步拼接显示的方法
CN105472287A (zh) * 2015-12-05 2016-04-06 武汉精测电子技术股份有限公司 一种单路hdmi视频信号单路转多路的装置及方法
CN105472288A (zh) * 2015-12-05 2016-04-06 武汉精测电子技术股份有限公司 一种v-by-one视频信号单路转多路的装置及方法
CN105491373A (zh) * 2015-12-05 2016-04-13 武汉精测电子技术股份有限公司 一种lvds视频信号单路转多路的装置及方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010288109A (ja) 2009-06-12 2010-12-24 Nippon Telegr & Teleph Corp <Ntt> 並列映像伝送システム、並列映像伝送方法、受信器、受信方法、及び受信プログラム
JP5687041B2 (ja) 2010-12-09 2015-03-18 三菱電機株式会社 情報表示装置および情報表示方法
JP6385057B2 (ja) 2013-12-25 2018-09-05 キヤノン株式会社 制御装置及び制御方法
JP2016038514A (ja) 2014-08-08 2016-03-22 キヤノン株式会社 表示制御装置、表示装置、それらの制御方法、およびプログラム
JP2017011338A (ja) 2015-06-16 2017-01-12 株式会社リコー 通信システム、送信装置、通信方法及びプログラム
WO2019031308A1 (ja) 2017-08-09 2019-02-14 シャープ株式会社 表示装置、テレビジョン受像機、映像処理方法、制御プログラム、および記録媒体

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011234181A (ja) * 2010-04-28 2011-11-17 Panasonic Corp 表示装置
CN103986960A (zh) * 2014-06-03 2014-08-13 王军明 一种单视频画面分割多路由远传精确同步拼接显示的方法
CN105472287A (zh) * 2015-12-05 2016-04-06 武汉精测电子技术股份有限公司 一种单路hdmi视频信号单路转多路的装置及方法
CN105472288A (zh) * 2015-12-05 2016-04-06 武汉精测电子技术股份有限公司 一种v-by-one视频信号单路转多路的装置及方法
CN105491373A (zh) * 2015-12-05 2016-04-13 武汉精测电子技术股份有限公司 一种lvds视频信号单路转多路的装置及方法

Also Published As

Publication number Publication date
JP2022018416A (ja) 2022-01-27
CN114430912A (zh) 2022-05-03
JP7330928B2 (ja) 2023-08-22

Similar Documents

Publication Publication Date Title
JP5119655B2 (ja) マルチスクリーン表示装置
KR101743776B1 (ko) 영상 표시 기기, 방법 및 영상 전송 방법
JP5010733B2 (ja) 情報スキューおよび冗長制御情報によるデータ送信装置および方法
US7308059B2 (en) Synchronization of data links in a multiple link receiver
TW543329B (en) Data transmission method and data receiving method, video data transmitting apparatus and receiving apparatus
US7283132B2 (en) Display panel driver
JP2011211756A (ja) データ伝送システム、送信デジタル処理システム、受信デジタル処理システム
WO2020192004A1 (en) Display controller, display control method, display control system, display apparatus
JP6574493B2 (ja) Ｌｖｄｓビデオ信号をｄｐビデオ信号に変換するための方法およびシステム
KR20090056047A (ko) 표시장치 및 이의 구동방법
CN111327858B (zh) Lvds视频信号转hdmi接口信号方法、系统、装置
KR20210144130A (ko) 캐스케이드된 디스플레이 드라이버 ic 및 이를 포함하는 멀티 비전 디스플레이 장치
WO2022012050A1 (zh) 数字视像信号生成电路、数字视像信号生成系统、数字视像信号生成方法及非易失性存储介质
JP4322673B2 (ja) 大きなビット幅データを狭いビット幅データパスによって送る装置及び方法
JP7379194B2 (ja) 表示装置及びソースドライバ
WO2006040898A1 (ja) 表示装置
JP4265619B2 (ja) 表示装置および表示装置の制御方法
US20080129871A1 (en) Video and Audio Synchronization Method and Related Apparatus for a Multimedia Interface
US8144075B2 (en) Display system for outputting analog and digital signals to a plurality of display apparatuses, system and method
WO2017175828A1 (ja) 映像信号送信装置、映像信号受信装置、および映像信号伝送システム
US11302243B2 (en) Image display system and image data transmission apparatus and method thereof having synchronous data transmission mechanism
CN111566986A (zh) 信号处理装置和信号处理方法
KR102582966B1 (ko) 인터페이스 보드 및 이를 이용한 표시장치
CN101202868B (zh) 用于多媒体接口的影音数据同步方法及其相关装置
US20230128574A1 (en) Method for data transmission

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21842356

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21842356

Country of ref document: EP

Kind code of ref document: A1