WO2022011838A1 - Oled显示面板及oled显示装置 - Google Patents

Oled显示面板及oled显示装置 Download PDF

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Publication number
WO2022011838A1
WO2022011838A1 PCT/CN2020/117754 CN2020117754W WO2022011838A1 WO 2022011838 A1 WO2022011838 A1 WO 2022011838A1 CN 2020117754 W CN2020117754 W CN 2020117754W WO 2022011838 A1 WO2022011838 A1 WO 2022011838A1
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WIPO (PCT)
Prior art keywords
test
area
thin film
fan
oled display
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PCT/CN2020/117754
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English (en)
French (fr)
Inventor
王朝欢
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武汉华星光电半导体显示技术有限公司
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Priority to US17/263,144 priority Critical patent/US12033549B2/en
Publication of WO2022011838A1 publication Critical patent/WO2022011838A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/70—Testing, e.g. accelerated lifetime tests

Definitions

  • the present application relates to the field of display technology, and in particular, to an OLED display panel and an OLED display device.
  • AMOLED (Active-matrix organic light-emitting diode, active matrix organic light-emitting diode) display screen has strong competitiveness in the new generation of display due to its advantages of wide color gamut, high contrast ratio, energy saving, foldability, etc. There are already many related products on it.
  • the production process of AMOLED display screen the production process from Cell (array substrate into a box) state to Module (module) state, and the cost of Module (module) production and consumables is extremely high, the first step of the Module (module) process The process binding process is particularly important.
  • the COF (Chip On FPC, the chip is mounted on the flexible circuit board) bonding process is through the COF pad (pad) and panel
  • the pad (panel pad) is bonded together to realize the transmission of the COF signal to the panel (panel), wherein the COF pad includes the GOA (Gate) on the left and right sides.
  • GOA Gate
  • the prior art OLED display panel and OLED display device cannot effectively detect whether the fan-out data line in the binding area is abnormal.
  • an embodiment of the present application provides an OLED display panel, which has a display area and a non-display area surrounding the display area.
  • the non-display area further includes a binding area, a first fan-out routing area, and a bending area. and a second fan-out routing area, the bending area is located between the first fan-out routing area and the second fan-out routing area, the first fan-out routing area and the second fan-out routing area
  • Each area is provided with a plurality of fan-out data lines
  • the binding area is provided with an integrated circuit chip and a plurality of pads, and the fan-out data lines are connected to the pads through the binding area;
  • a binding test area is further set between the binding area and the first fan-out routing area, and a binding test circuit is set in the binding test area, and the binding test circuit is used to detect the passing Whether there is an abnormality in the fan-out data line of the binding area.
  • the bonding test circuit includes a first test input line, a second test input line, a test data line, and a plurality of thin film transistors, and the plurality of thin film transistors are arranged along the first test line. Arranged in one direction D1.
  • test data voltage range of the test data line is 2-5V.
  • the materials of the fan-out data line, the first test input line, the second test input line and the test data line are all the same as the source material of the thin film transistor.
  • the drain stage material is the same.
  • the first test input line and the second test input line are used to control switches of a plurality of the thin film transistors, and the test data line is used to input a test data signal to the binding area.
  • a plurality of the thin film transistors are all PMOS devices.
  • the plurality of thin film transistors include a first type of thin film transistor and a second type of thin film transistor, and the gate of the first type of thin film transistor is in phase with the first test input line connection, the source of the first type of thin film transistor is connected to the test data line, the drain of the first type of thin film transistor is connected to the fan-out data line; the gate of the second type of thin film transistor The electrode is connected to the second test input line, the source electrode of the second type thin film transistor is connected to the fan-out data line, and the drain electrode of the second type thin film transistor is connected to the fan-out data line. connect.
  • the voltage of the first test input line is a high-level voltage
  • the first type thin film transistor is turned off
  • the voltage of the second test input line is a low level voltage
  • the second type thin film transistor is turned on
  • the fan-out data line inputs a first data signal to the binding area.
  • the voltage of the first test input line is a low level voltage
  • the first type thin film transistor is turned on
  • the voltage of the second test input line is a high level voltage voltage
  • the second type thin film transistor is turned off, and the test data line inputs a second data signal to the bonding area.
  • the fan-out data line located in the binding area is in an abnormal state.
  • embodiments of the present application further provide an OLED display device, including an OLED display panel, wherein the OLED display panel has a display area and a non-display area surrounding the display area, and the non-display area further includes a binding A fixed area, a first fan-out routing area, a bending area and a second fan-out routing area, the bending area is located between the first fan-out routing area and the second fan-out routing area, the first fan-out routing area A fan-out routing area and the second fan-out routing area are each provided with a plurality of fan-out data lines, the binding area is provided with an integrated circuit chip and a plurality of pads, and the fan-out data lines are provided through the binding area.
  • the fixed area is connected to the pad;
  • a binding test area is further set between the binding area and the first fan-out routing area, and a binding test circuit is set in the binding test area, and the binding test circuit is used to detect the passing Whether there is an abnormality in the fan-out data line of the binding area.
  • the bonding test circuit includes a first test input line, a second test input line, a test data line, and a plurality of thin film transistors, and the plurality of thin film transistors are arranged along the first test line. Arranged in one direction D1.
  • test data voltage range of the test data line is 2-5V.
  • the materials of the fan-out data line, the first test input line, the second test input line and the test data line are all the same as the source material of the thin film transistor.
  • the drain stage material is the same.
  • the first test input line and the second test input line are used to control switches of a plurality of the thin film transistors, and the test data line is used to input a test data signal to the binding area.
  • a plurality of the thin film transistors are all PMOS devices.
  • the plurality of thin film transistors include a first type of thin film transistor and a second type of thin film transistor, and the gate of the first type of thin film transistor is in phase with the first test input line connection, the source of the first type of thin film transistor is connected to the test data line, the drain of the first type of thin film transistor is connected to the fan-out data line; the gate of the second type of thin film transistor The electrode is connected to the second test input line, the source electrode of the second type thin film transistor is connected to the fan-out data line, and the drain electrode of the second type thin film transistor is connected to the fan-out data line. connect.
  • the voltage of the first test input line is a high-level voltage
  • the first type of thin film transistor is turned off
  • the voltage of the second test input line is a low level voltage
  • the second type thin film transistor is turned on
  • the fan-out data line inputs a first data signal to the binding area.
  • the voltage of the first test input line is a low level voltage
  • the first type thin film transistor is turned on
  • the voltage of the second test input line is a high level voltage voltage
  • the second type thin film transistor is turned off, and the test data line inputs a second data signal to the bonding area.
  • the fan-out data line located in the binding area is in an abnormal state.
  • the OLED display panel and the OLED display device provided by the embodiments of the present application are provided with a binding test circuit above the binding area, which can effectively detect whether there is an abnormality in the fan-out data line in the binding area. , which further improves the product yield of OLED display panels.
  • FIG. 1 is a schematic plan view of an OLED display panel provided by an embodiment of the present application.
  • FIG. 2 is a schematic design diagram of a bonding test circuit in an OLED display panel provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a switching circuit of a thin film transistor in an OLED display panel provided by an embodiment of the present application.
  • the embodiments of the present application are aimed at the technical problem that the OLED display panel and the OLED display device of the prior art cannot effectively detect whether the fan-out data lines in the binding area are abnormal. This embodiment can solve the problem.
  • FIG. 1 it is a schematic plan view of an OLED display panel provided by an embodiment of the present application. It can be clearly seen from the figure that each component of the embodiment of the present application and the relative positional relationship between each component.
  • the OLED display panel has a display area 11 and a non-display area 11 surrounding the display area 11.
  • the non-display area 12 further includes a binding area 121, a first fan-out wiring area 123, a bending area 124 and The second fan-out routing area 125, the bending area 124 is located between the first fan-out routing area 123 and the second fan-out routing area 125, the first fan-out routing area 123 and the first fan-out routing area 123
  • the two fan-out routing areas 125 are each provided with a plurality of fan-out data lines, the bonding area 121 is provided with an integrated circuit chip and a plurality of pads, and the fan-out data lines are connected to the bonding area 121 via the bonding area 121 .
  • a binding test area 122 is further set between the binding area 121 and the first fan-out routing area 123, and a binding test circuit is set in the binding test area 122.
  • the binding test The circuit is used to detect whether the fan-out data line passing through the binding area 121 is abnormal.
  • GOA traces 126 are further provided in the non-display area 12 near both ends of the edge of the display area 11 , and the GOA traces 126 are used to provide scanning signals for pixels in the display area 11 .
  • both ends of the edge of the binding area 121 are also provided with a boxed test pad (Cell Test Pad) 127, the box test pad is used to perform box test on the OLED display panel.
  • Cell Test Pad Cell Test Pad
  • the bonding test circuit includes a first test input line (Test-EN-1), a second test input line (Test-EN-2), a test data line (Test-data) and a plurality of thin film transistors (TFTs) ), a plurality of the thin film transistors are arranged along the first direction D1.
  • the first test input line (Test-EN-1), the second test input line (Test-EN-2) and the test data line (Test-data) are all connected to the binding area 121 , that is, 3 pins (pins) are added to the binding areas 121 on the left and right sides of the first fan-out data line (S1) and the 2160th fan-out data line (S2160). to provide a signal to the thin film transistor.
  • test data voltage range of the test data line is 2-5V, that is, the OLED display panel can be turned on.
  • the fan-out data lines (S1, S2... S2159, S2160), the first test input line (Test-EN-1), the second test input line (Test-EN-2) and
  • the material of the test data line is the same as the material of the source and drain stages of the thin film transistor (TFT); optionally, the material of the source and drain stages may be molybdenum (Mo), aluminum (Al) ), copper (Cu), titanium (Ti) one or more of the stacked combination.
  • the first test input line (Test-EN-1) and the second test input line (Test-EN-2) are used to control switches of a plurality of the thin film transistors, and the test data line ( Test-data) is used to input test data signals to the binding area 121 .
  • a plurality of the thin film transistors are PMOS (Metal Oxide Semiconductor Field Effect Transistor) devices, which are turned on at a low level and turned off at a high level.
  • PMOS Metal Oxide Semiconductor Field Effect Transistor
  • the plurality of thin film transistors include a first type thin film transistor 241 and a second type thin film transistor 242, and the gate of the first type thin film transistor 241 is connected to the first test input line (Test-EN-1 ), the source of the first type thin film transistor 241 is connected to the test data line (Test-data), and the drain of the first type thin film transistor 241 is connected to the fan-out data line (S1, S2 .
  • the fan-out data lines ( S1 , S2 . . . S2159 , S2160 ) are connected, and the drains of the second type thin film transistors 242 are connected to the fan-out data lines ( S1 , S2 . . . S2159 , S2160 ).
  • the voltage of the first test input line (Test-EN-1) is a high-level voltage, and the first type thin film transistor 241 is turned off, the voltage of the second test input line (Test-EN-2) is a low level voltage, the second type thin film transistor 242 is turned on, the fan-out data lines (S1, S2...S2159, S2160) A first data signal is input to the binding area 121 .
  • the voltage of the first test input line (Test-EN-1) is a low level voltage
  • the first type thin film transistor 241 is turned on
  • the voltage of the second test input line (Test-EN-2) When the voltage is a high-level voltage, the second type thin film transistor 242 is turned off, and the test data line (Test-data) inputs a second data signal to the bonding area 121 .
  • FIG. 3 a schematic diagram of a switching circuit of a thin film transistor in an OLED display panel provided by an embodiment of the present application is shown.
  • the TFT switch controls the writing of the test data line (Test-data) or the fan-out data line.
  • the present application adopts the method of adding a TFT switch, and detects whether there is a problem with the fan-out data line connected to the binding area through a binding test circuit, so as to quickly identify the problem and improve the production efficiency.
  • a binding test circuit is arranged above the binding area, which can effectively detect whether the fan-out data line in the binding area is abnormal, and further The product yield of the OLED display panel is improved.

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  • Physics & Mathematics (AREA)
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  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
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Abstract

一种OLED显示面板及OLED显示装置，具有显示区以及围绕所述显示区的非显示区，所述非显示区还包括绑定区、第一扇出走线区、弯折区以及第二扇出走线区；其中，所述绑定区与所述第一扇出走线区之间还设置有绑定测试区，所述绑定测试区内设置有绑定测试电路，所述绑定测试电路用于检测经过所述绑定区的扇出数据线是否存在异常。

Description

OLED显示面板及OLED显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种OLED显示面板及OLED显示装置。
 背景技术
AMOLED(Active-matrix organic light-emitting diode，有源矩阵有机发光二极体)显示屏凭借着具有色域广、对比度高、节能、可折叠性等优点，在新世代显示器中具有强有力的竞争力，现如今市场上已经有很多相关的产品。AMOLED显示屏生产过程中经过了从Cell（阵列基板成盒）态向Module(模组)态的制作，且Module(模组)制作及耗材成本极高，Module(模组)工艺的第一道制程绑定工艺就显得尤为重要了。
其中COF（Chip On FPC，芯片被贴装在柔性电路板上）绑定工艺是通过COF pad（衬垫）与panel pad（面板衬垫）粘结在一起来实现COF信号向panel（面板）内的传输，其中COF pad包括左右两侧的GOA(Gate on array，阵列基板行驱动)信号以及中间的数据信号，而数据线有数千根，虽然可以通过绑定阻抗的测量来监测绑定工艺中的数据电路是否异常，然而此方法仅可以说明test pad（测试衬垫）的绑定工艺没有问题，并不能够说明数千根的数据线的绑定工艺均没有问题。若其中一个数据线或少数数据线的绑定工艺出现问题，目前还没有方法可以证明。因此就存在一些无法解析的面板，难以探求到异常面板的真因。现有技术中最常用的方法为通过退绑定技术对面板进行成盒测试点灯，以此来区分绑定工艺是否存在问题，然而退绑定工艺的困难较大，极易损坏bonding pad（绑定衬垫），且目前针对COP（Chip On Plastic，芯片被贴装在塑料基板上）的绑定工艺没有有效的退绑定方法。
因此，有必要提供一种OLED显示面板，以解决现有技术中无法有效检测绑定区的扇出数据线是否存在异常的技术问题。
 技术问题
现有技术的OLED显示面板及OLED显示装置，无法有效检测出绑定区的扇出数据线是否存在异常。
 技术解决方案
第一方面，本申请实施例提供一种OLED显示面板，具有显示区以及围绕所述显示区的非显示区，所述非显示区还包括绑定区、第一扇出走线区、弯折区以及第二扇出走线区，所述弯折区位于所述第一扇出走线区与所述第二扇出走线区之间，所述第一扇出走线区与所述第二扇出走线区均设有多条扇出数据线，所述绑定区设有集成电路芯片和多个焊盘，所述扇出数据线经由所述绑定区与所述焊盘连接；
其中，所述绑定区与所述第一扇出走线区之间还设置有绑定测试区，所述绑定测试区内设置有绑定测试电路，所述绑定测试电路用于检测经过所述绑定区的所述扇出数据线是否存在异常。
在本申请实施例提供的OLED显示面板中，所述绑定测试电路包括第一测试输入线、第二测试输入线、测试数据线以及多个薄膜晶体管，多个所述薄膜晶体管均沿着第一方向D1排列。
在本申请实施例提供的OLED显示面板中，所述测试数据线的测试数据电压范围为2~5V。
在本申请实施例提供的OLED显示面板中，所述扇出数据线、所述第一测试输入线、所述第二测试输入线以及所述测试数据线的材料均与所述薄膜晶体管中源漏级的材料相同。
在本申请实施例提供的OLED显示面板中，所述第一测试输入线以及所述第二测试输入线用于控制多个所述薄膜晶体管的开关，所述测试数据线用于输入测试数据信号至所述绑定区。
在本申请实施例提供的OLED显示面板中，多个所述薄膜晶体管均为PMOS器件。
在本申请实施例提供的OLED显示面板中，多个所述薄膜晶体管包括第一类薄膜晶体管以及第二类薄膜晶体管，所述第一类薄膜晶体管的栅极与所述第一测试输入线相连接，所述第一类薄膜晶体管的源极与所述测试数据线相连接，所述第一类薄膜晶体管的漏极与所述扇出数据线相连接；所述第二类薄膜晶体管的栅极与所述第二测试输入线相连接，所述第二类薄膜晶体管的源极与所述扇出数据线相连接，所述第二类薄膜晶体管的漏极与所述扇出数据线相连接。
在本申请实施例提供的OLED显示面板中，当所述OLED显示面板处于模组测试阶段时，所述第一测试输入线的电压为高电平电压，所述第一类薄膜晶体管关闭，所述第二测试输入线的电压为低电平电压，所述第二类薄膜晶体管开启，所述扇出数据线输入第一数据信号至所述绑定区。当所述OLED显示面板处于绑定测试阶段时，所述第一测试输入线的电压为低电平电压，所述第一类薄膜晶体管开启，所述第二测试输入线的电压为高电平电压，所述第二类薄膜晶体管关闭，所述测试数据线输入第二数据信号至所述绑定区。
在本申请实施例提供的OLED显示面板中，当所述OLED显示面板在所述模组测试阶段存在垂直线类不良现象，而在所述绑定测试阶段时不存在垂直线类不良现象时，位于所述绑定区的所述扇出数据线处于异常状态。
第二方面，本申请实施例还提供一种OLED显示装置，包括OLED显示面板，其中，所述OLED显示面板具有显示区以及围绕所述显示区的非显示区，所述非显示区还包括绑定区、第一扇出走线区、弯折区以及第二扇出走线区，所述弯折区位于所述第一扇出走线区与所述第二扇出走线区之间，所述第一扇出走线区与所述第二扇出走线区均设有多条扇出数据线，所述绑定区设有集成电路芯片和多个焊盘，所述扇出数据线经由所述绑定区与所述焊盘连接；
其中，所述绑定区与所述第一扇出走线区之间还设置有绑定测试区，所述绑定测试区内设置有绑定测试电路，所述绑定测试电路用于检测经过所述绑定区的所述扇出数据线是否存在异常。
在本申请实施例提供的OLED显示装置中，所述绑定测试电路包括第一测试输入线、第二测试输入线、测试数据线以及多个薄膜晶体管，多个所述薄膜晶体管均沿着第一方向D1排列。
在本申请实施例提供的OLED显示装置中，所述测试数据线的测试数据电压范围为2~5V。
在本申请实施例提供的OLED显示装置中，所述扇出数据线、所述第一测试输入线、所述第二测试输入线以及所述测试数据线的材料均与所述薄膜晶体管中源漏级的材料相同。
在本申请实施例提供的OLED显示装置中，所述第一测试输入线以及所述第二测试输入线用于控制多个所述薄膜晶体管的开关，所述测试数据线用于输入测试数据信号至所述绑定区。
在本申请实施例提供的OLED显示装置中，多个所述薄膜晶体管均为PMOS器件。
在本申请实施例提供的OLED显示装置中，多个所述薄膜晶体管包括第一类薄膜晶体管以及第二类薄膜晶体管，所述第一类薄膜晶体管的栅极与所述第一测试输入线相连接，所述第一类薄膜晶体管的源极与所述测试数据线相连接，所述第一类薄膜晶体管的漏极与所述扇出数据线相连接；所述第二类薄膜晶体管的栅极与所述第二测试输入线相连接，所述第二类薄膜晶体管的源极与所述扇出数据线相连接，所述第二类薄膜晶体管的漏极与所述扇出数据线相连接。
在本申请实施例提供的OLED显示装置中，当所述OLED显示面板处于模组测试阶段时，所述第一测试输入线的电压为高电平电压，所述第一类薄膜晶体管关闭，所述第二测试输入线的电压为低电平电压，所述第二类薄膜晶体管开启，所述扇出数据线输入第一数据信号至所述绑定区。当所述OLED显示面板处于绑定测试阶段时，所述第一测试输入线的电压为低电平电压，所述第一类薄膜晶体管开启，所述第二测试输入线的电压为高电平电压，所述第二类薄膜晶体管关闭，所述测试数据线输入第二数据信号至所述绑定区。
在本申请实施例提供的OLED显示装置中，当所述OLED显示面板在所述模组测试阶段存在垂直线类不良现象，而在所述绑定测试阶段时不存在垂直线类不良现象时，位于所述绑定区的所述扇出数据线处于异常状态。
 有益效果
相较于现有技术，本申请实施例所提供的OLED显示面板及OLED显示装置，在绑定区上方设置有绑定测试电路，能够有效检测出绑定区内的扇出数据线是否存在异常，进一步提高了OLED显示面板的产品良率。
 附图说明
图1为本申请实施例提供的OLED显示面板的平面示意图。
图2为本申请实施例提供的OLED显示面板中绑定测试电路的设计示意图。
图3为本申请实施例提供的OLED显示面板中薄膜晶体管开关电路示意图。
 本发明的实施方式
本申请实施例针对现有技术的OLED显示面板及OLED显示装置，无法有效检测出绑定区的扇出数据线是否存在异常的技术问题，本实施例能够解决该缺陷。
如图1所示，为本申请实施例提供的OLED显示面板的平面示意图。从图中可以很直观地看到本申请实施例的各组成部分，以及各组成部分之间的相对位置关系。
其中，所述OLED显示面板具有显示区11以及围绕所述显示区11的非显示区11，所述非显示区12还包括绑定区121、第一扇出走线区123、弯折区124以及第二扇出走线区125，所述弯折区124位于所述第一扇出走线区123与所述第二扇出走线区125之间，所述第一扇出走线区123与所述第二扇出走线区125均设有多条扇出数据线，所述绑定区121设有集成电路芯片和多个焊盘，所述扇出数据线经由所述绑定区121与所述焊盘连接；
具体地，所述绑定区121与所述第一扇出走线区123之间还设置有绑定测试区122，所述绑定测试区122内设置有绑定测试电路，所述绑定测试电路用于检测经过所述绑定区121的所述扇出数据线是否存在异常。
进一步地，靠近所述显示区11边缘两端的部分所述非显示区12内还设置有GOA走线126，所述GOA走线126用于提供所述显示区11内像素的扫描信号。
进一步地，所述绑定区121的边缘两端还设置有成盒测试衬垫（Cell Test Pad）127，所述成盒测试衬垫用于对所述OLED显示面板进行成盒测试。
如图2所示，为本申请实施例提供的OLED显示面板中绑定测试电路的设计示意图（以2160根扇出数据线为例）。其中，所述绑定测试电路包括第一测试输入线（Test-EN-1）、第二测试输入线（Test-EN-2）、测试数据线（Test-data）以及多个薄膜晶体管(TFT)，多个所述薄膜晶体管均沿着第一方向D1排列。所述第一测试输入线（Test-EN-1）、所述第二测试输入线（Test-EN-2）以及所述测试数据线（Test-data）均接入至所述绑定区121，即在第一条所述扇出数据线（S1）和第2160条所述扇出数据线（S2160）的左右两侧的所述绑定区121内各增加3根pin（引脚）用来给所述薄膜晶体管提供信号。
可选地，所述测试数据线的测试数据电压范围为2~5V，即能实现所述OLED显示面板点亮即可。
可选地，所述扇出数据线（S1、S2…S2159、S2160）、所述第一测试输入线（Test-EN-1）、所述第二测试输入线（Test-EN-2）以及所述测试数据线（Test-data）的材料均与所述薄膜晶体管（TFT）中源漏级的材料相同；可选地，所述源漏级的材料可以是钼(Mo)、铝(Al)、铜(Cu)、钛(Ti)中的一种或多种的堆栈组合。
具体地，所述第一测试输入线（Test-EN-1）以及所述第二测试输入线（Test-EN-2）用于控制多个所述薄膜晶体管的开关，所述测试数据线（Test-data）用于输入测试数据信号至所述绑定区121。
具体地，多个所述薄膜晶体管均为PMOS（金属氧化物半导体场效应晶体管）器件，在低电平时开启，高电平时关闭。
可选地，多个所述薄膜晶体管包括第一类薄膜晶体管241以及第二类薄膜晶体管242，所述第一类薄膜晶体管241的栅极与所述第一测试输入线（Test-EN-1）相连接，所述第一类薄膜晶体管241的源极与所述测试数据线（Test-data）相连接，所述第一类薄膜晶体管241的漏极与所述扇出数据线（S1、S2…S2159、S2160）相连接；所述第二类薄膜晶体管242的栅极与所述第二测试输入线（Test-EN-2）相连接，所述第二类薄膜晶体管242的源极与所述扇出数据线（S1、S2…S2159、S2160）相连接，所述第二类薄膜晶体管242的漏极与所述扇出数据线（S1、S2…S2159、S2160）相连接。可选地，当所述OLED显示面板处于模组测试阶段（Module Test）时，所述第一测试输入线（Test-EN-1）的电压为高电平电压，所述第一类薄膜晶体管241关闭，所述第二测试输入线（Test-EN-2）的电压为低电平电压，所述第二类薄膜晶体管242开启，所述扇出数据线（S1、S2…S2159、S2160）输入第一数据信号至所述绑定区121。
可选地，当所述OLED显示面板处于绑定测试阶段时（Bonding Test），所述第一测试输入线（Test-EN-1）的电压为低电平电压，所述第一类薄膜晶体管241开启，所述第二测试输入线（Test-EN-2）的电压为高电平电压，所述第二类薄膜晶体管242关闭，所述测试数据线（Test-data）输入第二数据信号至所述绑定区121。
具体地，当所述OLED显示面板在所述模组测试阶段（Module Test）存在垂直线类不良现象，而在所述绑定测试阶段（Bonding Test）时仍然存在垂直线类不良现象时，则可判定位于所述绑定区121的所述扇出数据线（S1、S2…S2159、S2160）无异常状态；当所述OLED显示面板在所述模组测试阶段（Module Test）存在垂直线类不良现象，而在所述绑定测试阶段（Bonding Test）时不存在垂直线类不良现象时，则可判定位于所述绑定区121的所述扇出数据线（S1、S2…S2159、S2160）处于异常状态。
如图3所示，为本申请实施例提供的OLED显示面板中薄膜晶体管开关电路示意图。其中TFT开关控制所述测试数据线（Test-data）或所述扇出数据线的写入。
本申请采用增加TFT开关的方法，通过绑定测试电路来检测出连接到绑定区的扇出数据线是否存在问题，快速甄别问题，提高生产效率。
以上各个操作的具体实施可参见前面的实施例，在此不再赘述。
综上所述，本申请实施例所提供的OLED显示面板及OLED显示装置，在绑定区上方设置有绑定测试电路，能够有效检测出绑定区内的扇出数据线是否存在异常，进一步提高了OLED显示面板的产品良率。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (18)

  1. 一种OLED显示面板，具有显示区以及围绕所述显示区的非显示区，其中，所述非显示区还包括绑定区、第一扇出走线区、弯折区以及第二扇出走线区，所述弯折区位于所述第一扇出走线区与所述第二扇出走线区之间，所述第一扇出走线区与所述第二扇出走线区均设有多条扇出数据线，所述绑定区设有集成电路芯片和多个焊盘，所述扇出数据线经由所述绑定区与所述焊盘连接；
    其中，所述绑定区与所述第一扇出走线区之间还设置有绑定测试区，所述绑定测试区内设置有绑定测试电路，所述绑定测试电路用于检测经过所述绑定区的所述扇出数据线是否存在异常。
  2. 根据权利要求1所述的OLED显示面板，其中，所述绑定测试电路包括第一测试输入线、第二测试输入线、测试数据线以及多个薄膜晶体管，多个所述薄膜晶体管均沿着第一方向D1排列。
  3. 根据权利要求2所述的OLED显示面板，其中，所述测试数据线的测试数据电压范围为2~5V。
  4. 根据权利要求2所述的OLED显示面板，其中，所述扇出数据线、所述第一测试输入线、所述第二测试输入线以及所述测试数据线的材料均与所述薄膜晶体管中源漏级的材料相同。
  5. 根据权利要求2所述的OLED显示面板，其中，所述第一测试输入线以及所述第二测试输入线用于控制多个所述薄膜晶体管的开关，所述测试数据线用于输入测试数据信号至所述绑定区。
  6. 根据权利要求2所述的OLED显示面板，其中，多个所述薄膜晶体管均为PMOS器件。
  7. 根据权利要求6所述的OLED显示面板，其中，多个所述薄膜晶体管包括第一类薄膜晶体管以及第二类薄膜晶体管，所述第一类薄膜晶体管的栅极与所述第一测试输入线相连接，所述第一类薄膜晶体管的源极与所述测试数据线相连接，所述第一类薄膜晶体管的漏极与所述扇出数据线相连接；所述第二类薄膜晶体管的栅极与所述第二测试输入线相连接，所述第二类薄膜晶体管的源极与所述扇出数据线相连接，所述第二类薄膜晶体管的漏极与所述扇出数据线相连接。
  8. 根据权利要求7所述的OLED显示面板，其中，当所述OLED显示面板处于模组测试阶段时，所述第一测试输入线的电压为高电平电压，所述第一类薄膜晶体管关闭，所述第二测试输入线的电压为低电平电压，所述第二类薄膜晶体管开启，所述扇出数据线输入第一数据信号至所述绑定区；当所述OLED显示面板处于绑定测试阶段时，所述第一测试输入线的电压为低电平电压，所述第一类薄膜晶体管开启，所述第二测试输入线的电压为高电平电压，所述第二类薄膜晶体管关闭，所述测试数据线输入第二数据信号至所述绑定区。
  9. 根据权利要求8所述的OLED显示面板，其中，当所述OLED显示面板在所述模组测试阶段存在垂直线类不良现象，而在所述绑定测试阶段时不存在垂直线类不良现象时，位于所述绑定区的所述扇出数据线处于异常状态。
  10. 一种OLED显示装置，包括OLED显示面板，其特征在于，所述OLED显示面板具有显示区以及围绕所述显示区的非显示区，其中，所述非显示区还包括绑定区、第一扇出走线区、弯折区以及第二扇出走线区，所述弯折区位于所述第一扇出走线区与所述第二扇出走线区之间，所述第一扇出走线区与所述第二扇出走线区均设有多条扇出数据线，所述绑定区设有集成电路芯片和多个焊盘，所述扇出数据线经由所述绑定区与所述焊盘连接；
    其中，所述绑定区与所述第一扇出走线区之间还设置有绑定测试区，所述绑定测试区内设置有绑定测试电路，所述绑定测试电路用于检测经过所述绑定区的所述扇出数据线是否存在异常。
  11. 根据权利要求10所述的OLED显示装置，其中，所述绑定测试电路包括第一测试输入线、第二测试输入线、测试数据线以及多个薄膜晶体管，多个所述薄膜晶体管均沿着第一方向D1排列。
  12. 根据权利要求11所述的OLED显示装置，其中，所述测试数据线的测试数据电压范围为2~5V。
  13. 根据权利要求11所述的OLED显示装置，其中，所述扇出数据线、所述第一测试输入线、所述第二测试输入线以及所述测试数据线的材料均与所述薄膜晶体管中源漏级的材料相同。
  14. 根据权利要求11所述的OLED显示装置，其中，所述第一测试输入线以及所述第二测试输入线用于控制多个所述薄膜晶体管的开关，所述测试数据线用于输入测试数据信号至所述绑定区。
  15. 根据权利要求11所述的OLED显示装置，其中，多个所述薄膜晶体管均为PMOS器件。
  16. 根据权利要求15所述的OLED显示装置，其中，多个所述薄膜晶体管包括第一类薄膜晶体管以及第二类薄膜晶体管，所述第一类薄膜晶体管的栅极与所述第一测试输入线相连接，所述第一类薄膜晶体管的源极与所述测试数据线相连接，所述第一类薄膜晶体管的漏极与所述扇出数据线相连接；所述第二类薄膜晶体管的栅极与所述第二测试输入线相连接，所述第二类薄膜晶体管的源极与所述扇出数据线相连接，所述第二类薄膜晶体管的漏极与所述扇出数据线相连接。
  17. 根据权利要求16所述的OLED显示装置，其中，当所述OLED显示面板处于模组测试阶段时，所述第一测试输入线的电压为高电平电压，所述第一类薄膜晶体管关闭，所述第二测试输入线的电压为低电平电压，所述第二类薄膜晶体管开启，所述扇出数据线输入第一数据信号至所述绑定区；当所述OLED显示面板处于绑定测试阶段时，所述第一测试输入线的电压为低电平电压，所述第一类薄膜晶体管开启，所述第二测试输入线的电压为高电平电压，所述第二类薄膜晶体管关闭，所述测试数据线输入第二数据信号至所述绑定区。
  18. 根据权利要求17所述的OLED显示装置，其中，当所述OLED显示面板在所述模组测试阶段存在垂直线类不良现象，而在所述绑定测试阶段时不存在垂直线类不良现象时，位于所述绑定区的所述扇出数据线处于异常状态。
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