WO2022001892A1 - 重传方法及通信装置 - Google Patents

重传方法及通信装置 Download PDF

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Publication number
WO2022001892A1
WO2022001892A1 PCT/CN2021/102519 CN2021102519W WO2022001892A1 WO 2022001892 A1 WO2022001892 A1 WO 2022001892A1 CN 2021102519 W CN2021102519 W CN 2021102519W WO 2022001892 A1 WO2022001892 A1 WO 2022001892A1
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WIPO (PCT)
Prior art keywords
amplitude
signal
threshold
data block
output signal
Prior art date
Application number
PCT/CN2021/102519
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English (en)
French (fr)
Inventor
陆玉春
李亮
马林
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP21833295.5A priority Critical patent/EP4160957A4/en
Publication of WO2022001892A1 publication Critical patent/WO2022001892A1/zh
Priority to US18/147,526 priority patent/US20230136077A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1867—Arrangements specially adapted for the transmitter end
    • H04L1/1887—Scheduling and prioritising arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1812—Hybrid protocols; Hybrid automatic repeat request [HARQ]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1829—Arrangements specially adapted for the receiver end
    • H04L1/1864—ARQ related signaling

Definitions

  • the present application relates to the field of communication, and in particular, to a retransmission method and a communication device.
  • the continuous deterioration of the channel transmission environment leads to a decrease in the signal-to-noise ratio and an increase in the bit error rate.
  • the following technical solutions are further proposed to improve the bit error performance under low signal-to-noise ratio.
  • the automatic repeat-request (ARQ) technology implements a cyclic redundancy check (CRC) at the data link layer (DLL).
  • CRC cyclic redundancy check
  • the data receiving device performs a cyclic redundancy check on the data, and if the check fails, requests the data sending device to resend the corresponding data to reduce the bit error rate.
  • the number of retransmissions will be high and the reliability of data transmission will be low.
  • the above-mentioned technology combining ARQ and forward error correction (FEC) is called a hybrid automatic repeat request (HARQ) technology.
  • the data receiving device can correct the erroneous data through the decoding algorithm.
  • HARQ technology implements hybrid automatic retransmission at the media access control (media access control, MAC) layer.
  • media access control media access control, MAC
  • the RS(132,128)+CRC32 scheme has a simple error correction process and can meet the low-latency requirements of data transmission, but the error correction capability is weak. When the bit error rate is high, it is difficult to meet the reliability requirements of data transmission.
  • Another example is the RS(544,514)+CRC32 scheme. This scheme has strong error detection capability and can meet the reliability requirements when the link error rate is high, but the error detection process is more complicated and it is difficult to meet the low latency of data transmission. need.
  • the embodiments of the present application provide a retransmission method and apparatus, which can take into account the communication requirements of low latency and high reliability of data transmission, and can improve the efficiency of data transmission and the reliability of data transmission.
  • a retransmission method includes: the first device determines a first quantity, and according to the relationship between the first quantity and the first threshold, determines whether to request the second device to send the first data block.
  • the first number is the number of errors that occur in the signal received from the second device, the signal is used to transmit the first data block, and the first threshold is the error that can be corrected when the first device decodes the first data block greatest amount.
  • the first device can count the number of errors in the physical layer signal corresponding to the first data block received from the second device, and according to the number of errors in the signal and the interpretation of the first device
  • the code error correction capability such as the maximum number of errors that can be corrected when the first device performs decoding, determines whether to request the second device to resend the first data block. In this way, before decoding and verifying the first data block, the error information is extracted from the physical layer signal, which can reduce the data transmission delay and improve the error detection capability of the first device, thereby improving the efficiency of data transmission and data transmission. reliability.
  • the occurrence of an error in the signal includes: the amplitude of the first decoded output signal is smaller than the first boundary value or larger than the second boundary value.
  • the second boundary value is greater than the first boundary value, and the amplitude of the first decoded output signal is determined according to the amplitude of the current first decoded input signal and the amplitude of the previous first decoded output signal. That is to say, the amplitude interval of the signal is from the first boundary value to the second boundary value.
  • the amplitude threshold of the signal includes a first amplitude threshold, a second amplitude threshold, a third amplitude threshold and a fourth amplitude threshold, the first amplitude threshold is smaller than the second amplitude threshold, the second amplitude threshold is smaller than the third amplitude threshold, the The third amplitude threshold is smaller than the fourth amplitude threshold.
  • the retransmission method may further include: determining the amplitude of the signal according to the amplitude interval between the amplitude of the first decoded output signal and the amplitude threshold of the signal. That is, the amplitude of the first decoded output signal may be determined as one of the amplitude thresholds included in the signal.
  • the above-mentioned determining the amplitude of the signal according to the amplitude interval between the amplitude of the first decoded output signal and the amplitude threshold of the signal may include: if the amplitude of the first decoded output signal is less than If the amplitude of the first decoded output signal is greater than the second boundary value, the amplitude of the signal is determined as the fourth amplitude threshold. That is, if an error occurs in the signal, the amplitude of the first decoded output signal can be determined as one of the amplitude thresholds included in the signal, and the amplitude of the first decoded output signal can be corrected, thereby improving the reliability of data transmission. .
  • the first device determines whether to request the second device to send the first data block according to the relationship between the first number and the first threshold, which may include: if the first number is greater than the first threshold, then the first A device requests the second device to send the first data block. That is to say, if the number of errors in the signal is greater than the decoding and error correction capability of the first device, such as the maximum number of errors that can be corrected by the first device during decoding, the second device can be requested to resend the first device. data block.
  • the retransmission method may further include: the first device decodes the first data block, and/or performs a cyclic redundancy check on the first data block. That is to say, FEC technology may be used to decode the first data block, and/or CRC technology may be used to perform cyclic redundancy check on the first data block, so as to further reduce the probability of error and missed detection, and improve the reliability of data transmission. reliability.
  • the retransmission method may further include: if the first number is less than or equal to the first threshold and the first condition is satisfied, requesting the second device to send the first data block.
  • the first condition includes a failure to decode the first data block and/or a failure to verify the first data block. That is to say, when the first number is less than or equal to the first threshold, the FEC technology and the CRC technology can be used to further reduce the probability of error and missed detection, and improve the reliability of data transmission.
  • the retransmission method may further include: if the second condition is satisfied, the first device requests the second device to send the first data block.
  • the second condition may include one or more of the first number being greater than the first threshold, the failure to decode the first data block, and the failure to verify the first data block. That is, when any one or more of the conditions included in the second condition are satisfied, the first device can request the second device to send the first data block, so that the reliability of data transmission can be improved.
  • the retransmission method may further include: if the first number is greater than the first threshold and the third condition is satisfied, the first device requests the second device to send the first data block.
  • the third condition may include successful decoding of the first data block and/or successful verification of the first data block.
  • the first data block includes: an FEC codeword or a CRC frame, or an Ethernet frame, or a specified bit set.
  • a communication device in a second aspect, includes: a processing module and a processing module.
  • the processing module is used to determine the first quantity.
  • the first number is the number of errors in receiving the signal from the second device, and the signal is used to transmit the first data block;
  • the processing module is further configured to determine whether to control the transceiver module to request the second device to send the first data block according to the relationship between the first quantity and the first threshold.
  • the first threshold is the maximum number of errors that can be corrected when the processing module decodes the first data block.
  • the occurrence of an error in the signal may include: the amplitude of the first decoded output signal is smaller than the first boundary value or larger than the second boundary value.
  • the second boundary value is greater than the first boundary value, and the amplitude of the first decoded output signal is determined according to the amplitude of the current first decoded input signal and the amplitude of the previous first decoded output signal.
  • the amplitude threshold of the signal includes a first amplitude threshold, a second amplitude threshold, a third amplitude threshold and a fourth amplitude threshold, the first amplitude threshold is smaller than the second amplitude threshold, the second amplitude threshold is smaller than the third amplitude threshold, the The third amplitude threshold is smaller than the fourth amplitude threshold.
  • the processing module is further configured to determine the amplitude of the signal according to the amplitude interval between the amplitude of the first decoded output signal and the amplitude threshold of the signal.
  • the processing module is further configured to determine the amplitude of the signal as the first amplitude threshold if the amplitude of the first decoded output signal is smaller than the first boundary value.
  • the processing module is further configured to determine the amplitude of the signal as a fourth amplitude threshold if the amplitude of the first decoded output signal is greater than the second boundary value.
  • the processing module is further configured to control the transceiver module to request the second device to send the first data block if the first quantity is greater than the first threshold.
  • the processing module is further configured to decode the first data block, and/or the processing module is further configured to perform a cyclic redundancy check on the first data block.
  • the processing module is further configured to control the transceiver module to request the second device to send the first data block if the first quantity is less than or equal to the first threshold and satisfies the first condition; wherein the first condition Including the failure to decode the first data block and/or the failure to check the first data block.
  • the processing module is further configured to control the transceiver module to request the second device to send the first data block if the second condition is satisfied.
  • the second condition may include one or more of the first number being greater than the first threshold, failure to decode the first data block, and failure to verify the first data block.
  • the processing module is further configured to control the transceiver module to request the second device to send the first data block if the first quantity is greater than the first threshold and satisfies the third condition.
  • the third condition may include successful decoding of the first data block and/or successful verification of the first data block.
  • the first data block includes: an FEC codeword or a CRC frame, or an Ethernet frame, or a specified bit set.
  • the transceiver module described in the second aspect may include a receiving module and a sending module.
  • the receiving module is used to receive data and/or signaling from the second device;
  • the sending module is used to send a first request to the second device, and the first request is used to request the second device to send the first data block, or used for Send other data and/or signaling to the second device.
  • This application does not specifically limit the specific implementation manner of the transceiver module.
  • the communication device may further include a storage module, where the storage module stores programs or instructions.
  • the processing module executes the program or the instruction
  • the communication apparatus described in the second aspect can execute the retransmission method described in the first aspect.
  • the communication device described in the second aspect may be the first device, or may be a chip (system) or other components or components that can be provided in the first device, which is not limited in this application.
  • a communication device in a third aspect, includes a processor coupled to a memory for storing a computer program.
  • the processor is configured to execute the computer program stored in the memory, so that the communication apparatus executes the retransmission method described in any possible implementation manner of the first aspect.
  • the communication device described in the third aspect may further include a transceiver.
  • the transceiver may be a transceiver circuit or an input/output port.
  • the transceiver may be used for the communication device to communicate with other communication devices.
  • the communication apparatus described in the third aspect may be the first device, or a chip or a chip system provided inside the first device.
  • a chip system in a fourth aspect, includes a processor and an input/output port, the processor is used to implement the processing functions involved in the first aspect, and the input/output port is used to implement the first aspect The transceiver functions involved.
  • the chip system further includes a memory for storing program instructions and data for implementing the functions involved in the first aspect.
  • the chip system may be composed of chips, or may include chips and other discrete devices.
  • a communication system in a fifth aspect, includes a first device and a second device.
  • a computer-readable storage medium comprising: computer instructions are stored in the computer-readable storage medium.
  • the computer instructions When executed on a computer, the computer is caused to perform the retransmission method described in any possible implementation manner of the first aspect.
  • a seventh aspect provides a computer program product containing instructions, including computer programs or instructions that, when the computer program or instructions are run on a computer, cause the computer to perform any of the possible implementations of the first aspect.
  • FIG. 1 is a schematic structural diagram of a communication system provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a first device provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram 1 of a communication device provided by an embodiment of the present application.
  • FIG. 4 is a schematic flowchart 1 of a retransmission method provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram 1 of an operation model provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram 1 of an operation process provided by an embodiment of the present application.
  • FIG. 7 is a second schematic diagram of an operation model provided by an embodiment of the present application.
  • FIG. 8 is a second schematic diagram of an operation process provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a PAM4 signal provided by an embodiment of the present application.
  • FIG. 10 is a second schematic structural diagram of a communication apparatus according to an embodiment of the present application.
  • At least one (a) of a, b or c may represent: a, b, c, a-b, a-c, b-c or a-b-c, where a, b and c may be single or multiple.
  • FIG. 1 is a schematic structural diagram of a communication system to which the retransmission method provided by the embodiment of the present application is applicable.
  • the communication system includes a first device and a second device.
  • the second device is used to send a signal to the first device, the signal is used to transmit the first data block, and the first device is used to receive the signal sent by the second device.
  • the first device and the second device may communicate in a wired or wireless manner, and the first device and the second device may be integrated together, for example, may be interconnected through a backplane, or may be set independently.
  • the second device may include a cyclic redundancy check CRC generation module, a forward error correction (FEC) encoding module, a modulation module, and the like.
  • FEC forward error correction
  • FIG. 2 is a schematic structural diagram of a first device according to an embodiment of the present application.
  • the first device may include a digital signal processing (DSP) module and a retry logic module.
  • DSP digital signal processing
  • the first device may further include a forward error correction FEC module and/or a cyclic redundancy check CRC module.
  • the digital signal processing module is applied to the physical layer, and the digital signal processing module may include an analog to digital converter (ADC), a feed forward equalizer (FFE), and a decision feedback equalizer (decision feedback equalizer). , DFE), end of burst error detection (end of burst error detection, EoBD) device, etc.
  • the digital signal processing module may include a 7-level decider and a 1/(1+D) decoder. Among them, the 7-level decider and the 1/(1+D) decoder can replace the above decision feedback equalizer, thereby forming two different schemes.
  • An analog-to-digital converter ADC is used to convert the received analog signal into a digital signal.
  • the feedforward equalizer FFE is used to filter the signal to eliminate the intersymbol interference signal.
  • the decision feedback equalizer DFE is used to decode the received signal, obtain the amplitude of the decoded signal, judge the amplitude of the decoded signal, and determine whether the signal has an error. Send error indication information to EoBD.
  • the 1/(1+D) decoder is used to decode the signal, such as determining the amplitude of the current decoded output signal according to the difference between the amplitude of the current decoded input signal and the amplitude of the previous decoded output signal, and is also used to determine the amplitude of the current decoded output signal. Determine whether an error occurs in the signal, and if an error occurs, send error indication information to EoBD.
  • the burst error end detection EoBD device is used to determine the number of errors in the received signal from the second device according to the error indication information sent by the decision feedback equalizer DFE or the 1/(1+D) decoder. If an error occurs If the number of errors is greater than the error correction capability of the first device, the following retransmission logic module sends information that the number of signal errors is greater than the error correction capability of the first device.
  • the forward error correction FEC module is used to decode the first data block. If the decoding fails, it sends the decoding failure information to the following retransmission logic module. If the decoding is successful, it sends the following retransmission logic module to the following Send decoding success information.
  • the cyclic redundancy check CRC module is used to perform cyclic redundancy check on the first data block. If the check fails, it will send the check failure information to the following retransmission logic module, and if the check is successful, it will be sent to the following The retransmission logic module sends the verification success message.
  • the retransmission logic module is used to receive the information sent by the above-mentioned burst error end detection EoBD device, the forward error correction FEC module, and the cyclic redundancy check CRC module, and is also used for the above-mentioned burst error end detector, forward correction Error information sent by the FEC module and the cyclic redundancy check CRC module is used to determine whether to request the second device to resend the first data block.
  • FIG. 1 is a simplified schematic diagram exemplified for ease of understanding, and other devices may also be included in the communication system, which are not shown in FIG. 1 .
  • the structure of the first device shown in FIG. 2 does not constitute a limitation to the first device, and the actual first device may include more or less components than those shown in the figure, or combine some components, or different components layout.
  • FIG. 3 is a schematic structural diagram of a communication apparatus 300 that can be used to execute the retransmission method provided by the embodiment of the present application.
  • the communication apparatus 300 may be the first device shown in FIG. 1 , or may be a chip (system) or other components or assemblies applied in the first device.
  • the communication apparatus 300 may include a processor 301 .
  • the communication device 300 may also include a memory 302 and a transceiver 303 .
  • the processor 301 is coupled with the memory 302 and the transceiver 303, such as can be connected through a communication bus.
  • the processor 301 is the control center of the communication device 300, and may be a processor or a general term for multiple processing elements.
  • the processor 301 is one or more central processing units (central processing units, CPUs), may also be specific integrated circuits (application specific integrated circuits, ASICs), or is configured to implement one or more of the embodiments of the present application
  • An integrated circuit such as: one or more microprocessors (digital signal processor, DSP), or, one or more field programmable gate array (field programmable gate array, FPGA).
  • the processor 301 may execute various functions of the communication device 300 by running or executing software programs stored in the memory 302 and calling data stored in the memory 302 .
  • the processor 301 may include one or more CPUs, such as CPU0 and CPU1 shown in FIG. 3 .
  • the communication apparatus 300 may also include multiple processors, for example, the processor 301 and the processor 304 shown in FIG. 3 .
  • processors can be a single-core processor (single-CPU) or a multi-core processor (multi-CPU).
  • a processor herein may refer to one or more communication devices, circuits, and/or processing cores for processing data (eg, computer program instructions).
  • the memory 302 may be a read-only memory (ROM) or other type of static storage communication device that can store static information and instructions, a random access memory (RAM) or other type of static storage communication device that can store information. and other types of dynamic storage communication devices for instructions, which may also be electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or Other optical disc storage, optical disc storage (including compact disc, laser disc, optical disc, digital versatile disc, blu-ray disc, etc.), magnetic disk storage medium or other magnetic storage communication device, or capable of being used to carry or store desired in the form of instructions or data structures program code and any other medium that can be accessed by a computer, without limitation.
  • the memory 302 may be integrated with the processor 301, or may exist independently, and be coupled to the processor 301 through an input/output port (not shown in FIG. 3) of the communication device 300, which is not specifically limited in this embodiment of the present application.
  • the memory 302 is used for storing the software program for executing the solution of the present application, and the execution is controlled by the processor 301 .
  • the processor 301 controls the execution of the software program for executing the solution of the present application.
  • the transceiver 303 is used for communication with other communication devices.
  • the communication apparatus 300 is the first device, and the transceiver 303 may be used to communicate with the second device.
  • the transceiver 303 may include a receiver and a transmitter (not shown separately in FIG. 3). Among them, the receiver is used to realize the receiving function, and the transmitter is used to realize the sending function.
  • the transceiver 303 may be integrated with the processor 301, or may exist independently, and be coupled to the processor 301 through an input/output port (not shown in FIG. 3) of the communication device 300, which is not specifically limited in this embodiment of the present application .
  • the structure of the communication device 300 shown in FIG. 3 does not constitute a limitation on the communication device, and an actual communication device may include more or less components than those shown in the figure, or combine some components, or Different component arrangements.
  • FIG. 4 is a first schematic flowchart of a retransmission method provided by an embodiment of the present application.
  • the retransmission method may be applicable to the communication between various modules/devices included in the first device shown in FIG. 2 .
  • the retransmission method includes the following steps:
  • a first device receives a signal from a second device.
  • the first device may be a signal receiving device
  • the second device may be a signal sending device
  • the second device may send a signal to the first device, and the signal is used to transmit the first data block.
  • the amplitude threshold of the signal may include a first amplitude threshold, a second amplitude threshold, a third amplitude threshold and a fourth amplitude threshold, where the first amplitude threshold is smaller than the second amplitude threshold, and the second amplitude threshold is smaller than the third amplitude threshold, The third amplitude threshold is smaller than the fourth amplitude threshold.
  • the signal may be a four-level pulse amplitude modulation signal (4 pulse amplitude modulation, PAM4).
  • PAM4 signal adopts 4 different signal levels for signal transmission, such as -3, -1, 1, 3, and each signal symbol period can represent 2 bits of logic information (0, 1, 2, 3).
  • the four signal levels of -3, -1, 1, 3 can be used to transmit data 0, 1, 2, 3 respectively
  • the first amplitude threshold of the PAM4 signal can be -3, -1, 1, -3 of 3 or 0 of 0,1,2,3
  • second amplitude threshold can be -1 of -3,-1,1,3 or 1 of 0,1,2,3,
  • the amplitude threshold can be 1 of -3,-1,1,3 or 2 of 0,1,2,3
  • the fourth amplitude threshold can be 3 of -3,-1,1,3 or 0,1 , 3 of 2, 3.
  • the first data block may include: an FEC codeword or a CRC frame, or an Ethernet frame, or a specified set of bits.
  • the CRC frame is a data unit composed of valid data and redundancy check bits.
  • a CRC frame may include one or more FEC codewords, and the specified bit set may also be a specified bit sequence.
  • FIG. 5 is a schematic diagram 1 of an operation model provided by an embodiment of the present application. Take the second device sending the PAM4 signal through the 1+a*D (0 ⁇ a ⁇ 1) channel as an example.
  • the PAM4 signal passes through the 1/(1+D) encoder (encoder) and 1+a*D (0 ⁇ a ⁇ 1) channel (channel) of the second device in sequence, and then arrives at the first device after adding noise. equipment.
  • the first device receives the signal, it first decodes and judges the signal through the decision feedback equalizer DFE, and then secondly decodes the signal through a (1+D) decoder. If the first device includes the FEC module and /or CRC module (not shown in Figure 5), which can input signals into the FEC module and/or the CRC module.
  • the second device can perform operations such as coding and modulation on the signal, and then the signal passes through the 1+a*D (0 ⁇ a ⁇ 1) channel, superimposed noise and then arrives at the first device.
  • step 1 the signal is encoded by a 1/(1+D) encoder to obtain an encoded output signal.
  • the first amplitude threshold of the PAM4 signal is 0 in 0, 1, 2, 3
  • the second amplitude threshold is 1 in 0, 1, 2, 3
  • the third amplitude threshold is 0, 1, 2 in 2, 3
  • the fourth amplitude threshold is 3 in 0, 1, 2, 3 as an example, assuming that the 1/(1+D) encoder of the second device is in the symbol identity (symbol identity) 1 to 20
  • the input signals are 1, 0, 1, 3, 3, 0, 3, 2, 0, 1, 3, 3, 0, 3, 2, 1, 1, 0, 3, 3, respectively.
  • the above encoding process is used to obtain the amplitudes of the encoded output signals at the symbol identifiers 4 to 20 (as shown in FIG. 6 ), and the specific operation process will not be repeated here.
  • step 2 the encoded output signal is used as the channel input signal, and the channel output signal is obtained through the 1+D channel.
  • the amplitude of the output signal of the current channel is equal to the amplitude of the input signal of the current channel plus the amplitude of the input signal of the previous channel.
  • the amplitude of the previous edited channel input signal is 0.
  • the above channel processing process is used to obtain the amplitudes of the channel output signals at the symbol identifiers 4 to 20 (as shown in FIG. 6 ), and the specific operation process will not be repeated here.
  • step 3 the channel output signal and the noise are superimposed to obtain the DFE input signal, which may also be referred to as the first decoded input signal.
  • the obtained DFE input signal is not necessarily an integer as shown in FIG. 6 , but can also be a decimal number.
  • the DFE input signals in FIG. 6 are all integers, which is just an example.
  • the amplitude 1 of the channel output signal at the symbol identification 1 is 1 after being superimposed with the noise, and the amplitude of the DFE input signal at the symbol identification 1 is 1.
  • the amplitude 4 of the channel output signal at the symbol identification 2 is 4 after being superimposed with the noise, and the amplitude of the DFE input signal at the symbol identification 2 is 4.
  • the amplitude 5 of the channel output signal at symbol 3 is superimposed with noise to be 4, then the amplitude of the DFE input signal at symbol 3 is 4. If there is no noise influence, the amplitude of the DFE input signal at symbol 3 is 4. Should be equal to the amplitude 5 of the channel output signal at symbol ID 3, so an error is generated here.
  • the channel output signal and the noise are superimposed to obtain the amplitudes of the DFE input signals at the symbol identifiers 4 to 20 (as shown in FIG. 6 ), and the specific process will not be repeated here. Affected by noise, the amplitudes of the DFE input signals at the symbols 4 to 20 may be wrong.
  • the embodiments of the present application illustrate that the amplitudes of the DFE input signals at the symbols 4 to 20 do not introduce errors as an example.
  • FIG. 7 is a second schematic diagram of an operation model provided by an embodiment of the present application.
  • the schematic diagram of the operation model shown in FIG. 7 is only applicable to a 1+D channel scenario. The following description is given by taking an example that the second device sends the PAM4 signal through the 1+D channel.
  • the random 4-level signal passes through the 1/(1+D) encoder and the 1+D channel of the second device in sequence, and then arrives at the first device after adding noise.
  • the first device judges the signal through a 7-level slicer, first decodes the signal through the 1/(1+D) decoder, and then uses the (1+D) decoder to decode the signal.
  • the signal is subjected to second decoding, and if the first device includes an FEC module and/or a CRC module (not shown in FIG. 7 ), the signal may be input into the FEC module and/or the CRC module.
  • the second device may perform operations such as encoding on the signal, and then the signal passes through the 1+D channel, superimposes noise and then reaches the first device, which will be described below with reference to FIGS. 7 and 8 .
  • Step 4 Encode the signal through a 1/(1+D) encoder to obtain an encoded output signal.
  • the first amplitude threshold of the PAM4 signal is or 0 in 0, 1, 2, 3
  • the second amplitude threshold is 1 in 0, 1, 2, 3
  • the third amplitude threshold is 0, 1, 2 in 2, 3
  • the fourth amplitude threshold is 3 in 0, 1, 2, 3 as an example, assuming that the input signals of the 1/(1+D) encoder of the second device at the symbol marks 1 to 20 are respectively is 1,0,1,3,3,0,3,2,0,1,3,3,0,3,2,1,1,0,3,3.
  • the obtained encoded output signal reference may be made to FIG. 8 , and for a specific implementation manner, reference may be made to the foregoing step 1, which will not be repeated here.
  • Step 5 the encoded output signal is used as the channel input signal, and the channel output signal is obtained through the 1+D channel.
  • Step 6 superimpose the channel output signal and the noise to obtain the input signal of the 7-level decider, that is, the input signal of the first device.
  • the amplitude 1 of the channel output signal at symbol 1 is 1 after being superimposed with noise, and the amplitude of the input signal of the 7-level decider at symbol 1 is 1.
  • the amplitude 4 of the channel output signal at the symbol identification 2 is 4 after being superimposed with the noise, and the amplitude of the input signal of the 7-level decider at the symbol identification 2 is 4.
  • the amplitude 5 of the channel output signal at the symbol mark 3 is 4 after being superimposed with the noise, then the amplitude of the input signal of the 7-level decider at the symbol mark 3 is 4. If there is no noise influence, the 7-level voltage at the symbol mark 3 is 4.
  • the amplitude of the input signal of the flat decision maker should be equal to the amplitude 5 of the channel output signal at symbol 3, so an error is generated here.
  • the channel output signal and noise are superimposed to obtain the amplitudes of the input signals of the 7-level decider at symbols 4 to 20 (as shown in FIG. 8 ), and the specific process will not be repeated here.
  • the amplitude of the input signal of the 7-level decider at the symbol marks 4 to 20 may cause errors.
  • the amplitude of the input signal of the 7-level decider at the symbol marks 4 to 20 is not introduced. The error is explained as an example.
  • the first device performs first decoding on the signal to obtain an amplitude value of the first decoded output signal.
  • the first decoding is performed on the physical layer signal of the first data block to obtain the amplitude of the first decoded output signal.
  • the first decoding of the signal may include: using the decision feedback equalizer DFE to decode the signal to obtain a first decoded output signal, where the first decoded output signal can be used as the output signal of the decision (slicer) module of the DFE. input signal.
  • the first decoding of the signal may include: using a 1/(1+D) decoder to decode the signal to obtain a first decoded output signal, where the first decoded output signal may be 1/( 1+D) Decoder output signal.
  • the amplitude of the current first decoded output signal is determined according to the amplitude of the current first decoded input signal and the amplitude of the previous first decoded output signal.
  • a is a factor, for example, a is a tap coefficient of the decision feedback equalizer DFE, 0 ⁇ a ⁇ 1, and the DFE output signal is determined according to the first decoded output signal.
  • the DFE output signal is the signal after the first decoded output signal is judged by the DFE decision module, the first decoded input signal is the DFE input signal, and the first decoded output signal is the input signal of the DFE decision module.
  • the first decoded input signal is the output signal of the 7-level decider
  • the first decoded output signal is the output signal of the 1/(1+D) decoder.
  • the retransmission method of the embodiment of the present application may further include: determining the signal according to the amplitude interval between the amplitude of the first decoded output signal and the amplitude threshold of the signal the magnitude of .
  • FIG. 9 is a schematic diagram of a PAM4 signal provided by an embodiment of the present application.
  • the abscissa represents the amplitude x of the signal
  • the ordinate represents the probability density f of the signal amplitude
  • the first amplitude threshold of the PAM4 signal is -3
  • the second amplitude threshold is -1
  • the third amplitude threshold is 1.
  • the fourth amplitude threshold is 3, d1 is the amplitude interval 2 between adjacent amplitude thresholds, N is the first boundary value, and K is the second boundary value.
  • the first amplitude threshold of the PAM4 signal may be 0, the second amplitude threshold may be 1, the third amplitude threshold may be 2, the fourth amplitude threshold may be 3 (not shown in FIG. 9 ), and d1 is the adjacent amplitude Amplitude interval 1 between thresholds.
  • a is a factor, such as a is the tap coefficient of the decision feedback equalizer DFE, 0 ⁇ a ⁇ 1, d1 is the amplitude interval between adjacent amplitude thresholds, and M is the first amplitude threshold.
  • a is a factor, such as a is the tap coefficient of the decision feedback equalizer DFE, 0 ⁇ a ⁇ 1, d1 is the amplitude interval between adjacent amplitude thresholds, and P is the fourth amplitude threshold.
  • b is the empirical value
  • a is the factor, such as a is the tap coefficient of the decision feedback equalizer DFE
  • 0 ⁇ a ⁇ 1 is the amplitude interval between adjacent amplitude thresholds
  • M is The first amplitude threshold.
  • b is the empirical value
  • 0 ⁇ b ⁇ 1 is the factor, such as a is the tap coefficient of the decision feedback equalizer DFE
  • 0 ⁇ a ⁇ 1 is the amplitude interval between adjacent amplitude thresholds
  • P is Fourth amplitude threshold. That is, the first boundary value and the second boundary value of the signal can be set according to experience.
  • the embodiment of the present application only takes the four-level pulse amplitude modulation signal as an example, and does not limit the number of levels of the signal.
  • the amplitude threshold included in the signal is greater than 4 amplitude thresholds, or the amplitude threshold included in the signal is less than 4
  • the first amplitude threshold may be the smallest amplitude threshold among the amplitude thresholds included in the signal
  • the fourth amplitude threshold may be the largest amplitude threshold among the amplitude thresholds included in the signal.
  • determining the amplitude of the signal according to the amplitude interval between the amplitude of the first decoded output signal and the amplitude threshold of the signal may include: determining the amplitude of the signal to be the same as that of the first decoded output signal The amplitude threshold of the amplitude interval with the smallest amplitude.
  • the amplitude interval between the amplitude value -3.5 and the amplitude threshold value -3 is 0.5
  • the amplitude interval between the amplitude value -3.5 and the amplitude threshold value -1 is 2.5
  • the amplitude interval between amplitude -3.5 and amplitude threshold 1 is 4.5
  • the amplitude interval between amplitude -3.5 and amplitude threshold 3 is 6.5
  • the amplitude interval between amplitude -3.5 and amplitude threshold -3 is the smallest.
  • the magnitude is determined to be -3.
  • the above-mentioned determining the amplitude of the signal according to the amplitude interval between the amplitude of the first decoded output signal and the amplitude threshold of the signal may include: determining the amplitude of the signal according to a decision rule.
  • the decision rule may include: if the first boundary value ⁇ Q ⁇ (the first amplitude threshold value+0.5*d1), the amplitude of the signal may be determined as the first amplitude threshold value; if (the first amplitude threshold value+0.5 *d1) ⁇ Q ⁇ (the second amplitude threshold+0.5*d1), then the amplitude of the signal can be determined as the second amplitude threshold; if (the second amplitude threshold+0.5*d1) ⁇ Q ⁇ (the third amplitude threshold +0.5*d1), the amplitude of the signal can be determined as the third amplitude threshold; if (the third amplitude threshold+0.5*d1) ⁇ Q ⁇ the second boundary value, the amplitude of the signal can be determined as the fourth threshold Amplitude threshold.
  • Q is the amplitude of the first decoded output signal
  • d1 is the amplitude interval between adjacent amplitude thresholds.
  • the first amplitude threshold is -3
  • the second amplitude threshold is -1
  • the third amplitude threshold is 1
  • the second amplitude threshold is 1
  • the third amplitude threshold is 2
  • the fourth amplitude threshold is 3
  • the amplitude of the first decoded output signal is 3.5
  • the amplitude of the signal can be determined is 3.
  • determining the amplitude of the signal according to the amplitude interval between the amplitude of the first decoded output signal and the amplitude threshold of the signal may include: if the amplitude of the first decoded output signal is smaller than the first boundary value, the amplitude of the signal is determined as the first amplitude threshold; if the amplitude of the first decoded output signal is greater than the second boundary value, the amplitude of the signal is determined as the fourth amplitude threshold.
  • the first amplitude threshold is -3
  • the second amplitude threshold is -1
  • the third amplitude threshold is 1
  • the amplitude of the signal can be determined as 3.
  • steps seven to eight refer to the following steps seven to eight.
  • Step 7 Perform first decoding on the first decoded input signal to obtain a first decoded output signal.
  • the first decoded output signal is the input signal of the DFE decider in FIG. 6 , and the implementation of the amplitude of the DFE output signal may refer to the following step 9.
  • the amplitudes of the first decoded output signals at the symbol identifiers 4 to 20 are obtained (as shown in FIG. 6 ), and the specific operation process is not repeated here.
  • Step 8 Obtain the DFE output signal according to the amplitude interval between the amplitude of the first decoded output signal and the amplitude threshold of the signal.
  • the amplitude 1 of the first decoded output signal at the symbol identification 1 is determined as the amplitude threshold value 1, the amplitude of the DFE output signal at the symbol identification 1 is 1.
  • the amplitude value 3 of the first decoded output signal at the symbol identification 2 is determined as the amplitude threshold value 3, and the amplitude value of the DFE output signal at the symbol identification 2 is 3.
  • the above-mentioned decision process is used to obtain the amplitudes of the DFE output signals at symbols 3 to 17, 19, and 20 (as shown in FIG. 6 ), and the specific operation process will not be repeated here. Since in the above-mentioned step 3, at symbol identification 3, errors are introduced by noise, the amplitude of the first decoded output signal begins to generate errors at symbol identification 3, and then the DFE output signal at symbol identification 3 obtained above has an error. Amplitude produces an error, which is transmitted to symbol 17 due to the influence of the DFE structure.
  • the decision is that the amplitude threshold value is 3, the amplitude of the DFE output signal at the symbol identification 18 is 3, the amplitude of the DFE output signal is corrected, and the wrong transmission of the signal is terminated, so that the amplitude of the DFE output signal at the symbol identification 19 and 20 is is correct.
  • the amplitude of the first decoded output signal is obtained, and the signal is determined according to the amplitude interval between the amplitude of the first decoded output signal and the amplitude threshold of the signal.
  • the amplitude is explained.
  • steps 9 to 10 refer to the following steps 9 to 10.
  • Step 9 Perform first decoding on the first decoded input signal to obtain a first decoded output signal.
  • the amplitude of the first decoded input signal is the amplitude of the output signal of the 7-level decider in FIG. 8
  • the amplitude of the first decoded output signal is the output signal of the 1/(1+D) decoder in FIG. 8 the magnitude of .
  • the amplitude of the output signal of the previous 1/(1+D) decoder for which there is no first decoded output signal at symbol 1 can be regarded as the amplitude of the output signal of the previous 1/(1+D) decoder. The value is 0.
  • the amplitudes of the first decoded output signals at the symbol identifiers 3 to 18 and 20 are obtained, and the specific operation process will not be repeated here.
  • the implementation manner of the 1/(1+D) decoder judging the amplitude of the output signal may refer to the following step ten, which will not be repeated here.
  • Step ten according to the amplitude interval between the amplitude of the first decoded output signal and the amplitude threshold of the signal, obtain a 1/(1+D) decoder decision output signal.
  • the amplitude 1 of the first decoded output signal at symbol identification 1 is determined as the amplitude threshold 1
  • the 1/(1+D) decoder at symbol identification 1 determines that the amplitude of the output signal is 1.
  • the above-mentioned decision process is used to obtain the amplitude values of the 1/(1+D) decoder decision output signals at the symbols 2 to 17, 19, and 20 (as shown in FIG. 8 ), and the specific operation process is omitted here.
  • step 6 Since in the above-mentioned step 6, at the symbol mark 3, due to the noise introduced by the error, the amplitude of the first decoded output signal starts to generate an error at the symbol mark 3, so that 1/(1 at the symbol mark 3 obtained above is +D)
  • the amplitude of the output signal determined by the decoder produces an error, which is affected by the 1/(1+D) decoder, and the error is transmitted to the symbol identifier 17 .
  • the value 4 is determined as the amplitude threshold value 3, then the 1/(1+D) decoder at the symbol identification 18 determines that the amplitude of the output signal is 3, and the amplitude of the first decoded output signal at the symbol identification 18 is corrected. Error delivery terminated.
  • the first device determines whether an error occurs in the signal.
  • determining that the signal has an error may include: if the amplitude of the first decoded output signal is smaller than the first boundary value or greater than the second boundary value, the signal is erroneous.
  • the first decoded output signal may be a physical layer transmission signal of the first data block.
  • the second boundary value is greater than the first boundary value.
  • first boundary value and the second boundary value reference may be made to the above S402, which will not be repeated here.
  • the second amplitude threshold is 1
  • the third amplitude threshold is 2
  • Step 11 Determine whether an error occurs in the first decoded output signal.
  • the first amplitude threshold is 0, the second amplitude threshold is 1, the third amplitude threshold is 2, and the fourth amplitude threshold is 3.
  • the amplitudes of the first decoded output signals at symbol identifications 1-17, symbol identification 19, and symbol identification 20 are all between -0.55 and 3.55, and the amplitude of the first decoded output signal at symbol identification 18 (Fig. 6 If the amplitude of the input signal of the DFE decider is greater than the second boundary value of 3.55, it is determined that the signal is in error.
  • step 8 the determination of whether an error occurs in the signal will be described.
  • step 12 the determination of whether an error occurs in the signal.
  • Step 12 Determine whether an error occurs in the first decoded output signal.
  • the signal is in error; otherwise, the signal is not in error.
  • step eleven reference may be made to the above-mentioned step eleven, which will not be repeated here.
  • the first device determines the first quantity.
  • the first number is the number of errors occurred in receiving the signal from the second device.
  • the first device may, according to the above S403, the first device determines whether an error occurs in the signal, and counts the number of errors in the signal.
  • the first device may use an FEC codeword, or a CRC frame, or an Ethernet frame, or a specified bit set as a basic granularity to determine the first quantity. That is to say, the first number may be the number of signals with errors in a signal of a specific length.
  • the EoBD determines the number of errors in the received signal from the second device, the signal error is detected at the symbol identifier 18 , and the EoBD is set to 1.
  • the first device may perform a second decoding on the signal, which will be described below with reference to FIG. 5 and FIG. 6 .
  • Step 13 decode the signal by the (1+D) decoder to obtain the output signal of the (1+D) decoder.
  • the (1+D) decoder input signal is the DFE output signal.
  • the amplitudes of the (1+D) decoder output signals at the symbol identifiers 4 to 17 are obtained by using the above-mentioned second decoding process (as shown in FIG. 6 ), and the specific operation process will not be repeated here.
  • the amplitude of the output signal of the (1+D) decoder at other symbols is the same as the amplitude of the input signal of the 1/(1+D) encoder.
  • the second decoding will be described below with reference to FIG. 7 and FIG. 8 .
  • Step 14 Decode the signal by the (1+D) decoder to obtain the output signal of the (1+D) decoder.
  • the input signal of the (1+D) decoder is the decision output signal of the 1/(1+D) decoder.
  • the foregoing step thirteen reference may be made to the foregoing step thirteen, which will not be repeated here.
  • the first device determines whether to request the second device to send the first data block according to the relationship between the first quantity and the first threshold.
  • the first device determines whether to request the second device to send the first data block according to the relationship between the first number and the first threshold, which may include: if the first number is greater than the first threshold, then the first A device may perform the following S406.
  • the first threshold may be the maximum number of errors that can be corrected when the first device decodes the first data block.
  • the maximum number of errors that can be corrected when the first data block is decoded may refer to the error correction capability of the FEC module.
  • the first threshold may be 0.
  • the error correction capability t of the FEC module may be: the maximum number of symbols that can be successfully corrected by one RS codeword and allow errors.
  • RS 528, 514
  • 528 is the length of the RS codeword
  • 514 is the length of the RS codeword information
  • 544 is the length of the RS codeword
  • 514 is the length of the RS codeword information
  • the retransmission method may further include: decoding the first data block and/or performing a cyclic redundancy check on the first data block. That is to say, the scheme of determining whether an error occurs in a signal at the physical layer can be used in combination with the FEC technology and/or the CRC technology to further reduce the probability of missed error detection and improve the reliability of data transmission.
  • the first device may use the FEC codeword length as the basic granularity to decode the first data block, and/or the first device may use the CRC frame length as the basic granularity to perform cyclic redundancy check on the first data block .
  • the first device may perform the following S406.
  • the second condition may include one or more of the first number being greater than the first threshold, failure to decode the first data block, and failure to verify the first data block. That is, when any one or more of the conditions included in the second condition are satisfied, the first device can request the second device to resend the first data block, thereby improving the reliability of data transmission.
  • the first device may perform the following S406.
  • the third condition may include successful decoding of the first data block and/or successful verification of the first data block.
  • error correction occurs and the problem of low reliability of data transmission can be solved. That is to say, when it is determined that the first number is greater than the first threshold, the decoding is successful, which may be because a miscorrection has occurred, and the erroneous data has not actually been corrected, and the first device can request to retransmit the first data block to improve the data Transmission reliability.
  • the first device may perform the following S406.
  • the first condition may include a failure to decode the first data block and/or a failure to verify the first data block. That is to say, when the first number is less than or equal to the first threshold, the FEC technology and the CRC technology can be used to reduce the probability of error and missed detection and improve the reliability of data transmission.
  • the first device requests the second device to send the first data block.
  • the first device requesting the second device to send the first data block may include: sending the first request to the second device.
  • the first request may be used to request the second device to send the first data block.
  • the first device can count the number of errors in the physical layer signal corresponding to the first data block received from the second device, and according to the number of errors in the signal and the decoding of the first device
  • the error correction capability such as the maximum number of errors that can be corrected by the first device during decoding, determines whether to request the second device to resend the first data block. In this way, before decoding and verifying the first data block, the error information is extracted from the physical layer signal, which can reduce the data transmission delay and improve the error detection capability of the first device, thereby improving the efficiency of data transmission and data transmission. reliability.
  • the retransmission method provided by the embodiment of the present application has been described in detail above with reference to FIG. 4 to FIG. 9 .
  • the communication device provided by the embodiment of the present application will be described in detail below with reference to FIG. 10 .
  • FIG. 10 is a second schematic structural diagram of a communication apparatus provided by an embodiment of the present application.
  • the communication apparatus is applicable to the communication system shown in FIG. 1 , and performs the function of the first device in the retransmission method shown in FIG. 4 .
  • FIG. 10 only shows the main components of the communication device.
  • the communication device 1000 includes: a transceiver module 1001 and a processing module 1002 .
  • the processing module 1002 is used to determine the first quantity.
  • the first number is the number of errors in receiving the signal from the second device, and the signal is used to transmit the first data block;
  • the processing module 1002 is further configured to determine whether to control the transceiver module 1001 to request the second device to send the first data block according to the relationship between the first quantity and the first threshold.
  • the first threshold is the maximum number of errors that can be corrected when the processing module 1002 decodes the first data block.
  • the occurrence of an error in the signal may include: the amplitude of the first decoded output signal is smaller than the first boundary value or larger than the second boundary value.
  • the second boundary value is greater than the first boundary value, and the amplitude of the first decoded output signal is determined according to the amplitude of the current first decoded input signal and the amplitude of the previous first decoded output signal.
  • the amplitude threshold of the signal includes a first amplitude threshold, a second amplitude threshold, a third amplitude threshold and a fourth amplitude threshold, the first amplitude threshold is smaller than the second amplitude threshold, the second amplitude threshold is smaller than the third amplitude threshold, the The third amplitude threshold is smaller than the fourth amplitude threshold.
  • the processing module 1002 is further configured to determine the amplitude of the signal according to the amplitude interval between the amplitude of the first decoded output signal and the amplitude threshold of the signal.
  • the processing module 1002 is further configured to determine the amplitude of the signal as the first amplitude threshold if the amplitude of the first decoded output signal is smaller than the first boundary value.
  • the processing module 1002 is further configured to determine the amplitude of the signal as a fourth amplitude threshold if the amplitude of the first decoded output signal is greater than the second boundary value.
  • the processing module 1002 is further configured to control the transceiver module 1001 to request the second device to send the first data block if the first quantity is greater than the first threshold.
  • the processing module 1002 is further configured to decode the first data block and/or the processing module 1002 is further configured to perform a cyclic redundancy check on the first data block.
  • the processing module 1002 is further configured to control the transceiver module 1001 to request the second device to send the first data block if the first quantity is less than or equal to the first threshold and the first condition is satisfied.
  • the first condition includes a failure to decode the first data block and/or a failure to verify the first data block.
  • the processing module 1002 is further configured to control the transceiver module 1001 to request the second device to send the first data block if the second condition is satisfied.
  • the second condition includes one or more of the first number being greater than the first threshold, the failure to decode the first data block, and the failure to verify the first data block.
  • the processing module 1002 is further configured to control the transceiver module 1001 to request the second device to send the first data block if the first quantity is greater than the first threshold and satisfies the third condition.
  • the third condition includes successful decoding of the first data block and/or successful verification of the first data block.
  • the first data block includes: an FEC codeword or a CRC frame, or an Ethernet frame, or a specified bit set.
  • the transceiver module 1001 may include a receiving module and a sending module (not shown in FIG. 10 ).
  • the receiving module is used to receive data and/or signaling from the second device;
  • the sending module is used to send a first request to the second device, and the first request is used to request the second device to send the first data block, or used for Send other data and/or signaling to the second device.
  • This application does not specifically limit the specific implementation manner of the transceiver module 1001 .
  • the communication apparatus 1000 may further include a storage module (not shown in FIG. 10 ), where the storage module stores programs or instructions.
  • the processing module 1002 executes the program or the instruction, the communication apparatus 1000 can perform the function of the first device in the retransmission method shown in FIG. 4 .
  • the communication apparatus 1000 may be the first device shown in FIG. 1 or the communication apparatus 300 shown in FIG. 3 , or may be a chip (system) or other components or component, which is not limited in this application.
  • Embodiments of the present application provide a communication system.
  • the system includes a first device and a second device.
  • An embodiment of the present application provides a computer-readable storage medium, where the computer-readable storage medium includes a computer program or instruction; when the computer program or instruction is run on a computer, the computer is made to perform the retransmission described in the foregoing method embodiments method.
  • the embodiments of the present application provide a computer program product, including a computer program or an instruction, when the computer program or instruction runs on a computer, the computer is made to execute the retransmission method described in the above method embodiments.
  • processors in the embodiments of the present application may be a central processing unit (central processing unit, CPU), and the processor may also be other general-purpose processors, digital signal processors (digital signal processors, DSP), dedicated integrated Circuit (application specific integrated circuit, ASIC), off-the-shelf programmable gate array (field programmable gate array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • a general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
  • the memory in the embodiments of the present application may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically programmable Erase programmable read-only memory (electrically EPROM, EEPROM) or flash memory.
  • Volatile memory may be random access memory (RAM), which acts as an external cache.
  • RAM random access memory
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • DRAM synchronous dynamic random access memory
  • SDRAM synchronous dynamic random access memory
  • DDR SDRAM double data rate synchronous dynamic random access memory
  • enhanced SDRAM enhanced synchronous dynamic random access memory
  • SLDRAM synchronous connection dynamic random access memory Fetch memory
  • direct memory bus random access memory direct rambus RAM, DR RAM
  • the above embodiments may be implemented in whole or in part by software, hardware (eg, circuits), firmware, or any other combination.
  • the above-described embodiments may be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of the present application are generated.
  • the computer may be a general purpose computer, special purpose computer, computer network, or other programmable device.
  • the computer instructions may be stored in or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions may be downloaded from a website site, computer, server or data center Transmission to another website site, computer, server or data center by wire (eg, infrared, wireless, microwave, etc.).
  • the computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, a data center, or the like that contains one or more sets of available media.
  • the usable media may be magnetic media (eg, floppy disks, hard disks, magnetic tapes), optical media (eg, DVDs), or semiconductor media.
  • the semiconductor medium may be a solid state drive.
  • At least one means one or more, and “plurality” means two or more.
  • At least one item(s) below” or similar expressions thereof refer to any combination of these items, including any combination of single item(s) or plural items(s).
  • at least one item (a) of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple .
  • the size of the sequence numbers of the above-mentioned processes does not mean the sequence of execution, and the execution sequence of each process should be determined by its functions and internal logic, and should not be dealt with in the embodiments of the present application. implementation constitutes any limitation.
  • the disclosed system, apparatus and method may be implemented in other manners.
  • the apparatus embodiments described above are only illustrative.
  • the division of the above-mentioned units or modules is only a logical function division.
  • multiple units or modules may be combined.
  • the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units/modules, and may be in electrical, mechanical or other forms.
  • the units/modules described as separate components may or may not be physically separated, and components shown as units/modules may or may not be physical units/modules, that is, they may be located in one place, or may be distributed to on multiple network units/modules. Some or all of the units/modules may be selected according to actual needs to achieve the purpose of the solution in this embodiment.
  • each functional unit/module in each embodiment of the present application may be integrated into one processing unit/module, or each unit/module may exist physically alone, or two or more units/modules may be integrated into one unit/module.
  • the functions, if implemented in the form of software functional units/modules and sold or used as independent products, may be stored in a computer-readable storage medium.
  • the technical solution of the present application can be embodied in the form of a software product in essence, or the part that contributes to the prior art or the part of the technical solution.
  • the computer software product is stored in a storage medium, including Several instructions are used to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage medium includes: U disk, removable hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk and other media that can store program codes .

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  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

本申请提供一种重传方法及通信装置，能够兼顾数据传输的低时延和高可靠性这两方面的通信需求，可以提高数据传输的效率和数据传输的可靠性，可应用于无线或有线通信系统中。该方法包括：第一设备接收来自第二设备的信号后，对信号进行第一解码，然后确定信号是否发生错误以及第一数量，最后根据第一数量与第一阈值的关系，确定是否请求第二设备发送第一数据块，其中，第一数量为接收来自第二设备的信号发生错误的个数，信号用于传输第一数据块，第一阈值为第一设备对第一数据块进行译码时所能纠正的错误的最大数量。

Description

重传方法及通信装置
本申请要求于2020年06月29日提交国家知识产权局、申请号为202010606226.1、申请名称为“重传方法及通信装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信领域，尤其涉及一种重传方法及通信装置。
背景技术
信道传输环境的不断恶化，导致信噪比下降，误码率升高，进而提出如下技术方案，以改善低信噪比下的误码性能。
例如，自动重传请求(automatic repeat-request，ARQ)技术，在数据链路层(data link layer,DLL)实现循环冗余校验(cyclic redundancy check，CRC)。具体地，数据接收设备对数据进行循环冗余校验，若校验失败，则请求数据发送设备重新发送相应数据，以降低误码率。然而，在误码率较高的场景中，由于链路质量差，会导致重传次数多，数据传输的可靠性低。
上述ARQ与前向纠错(forward error correction，FEC)相结合的技术称为混合自动重传请求(hybrid automatic repeat request，HARQ)技术。在FEC技术中，数据接收设备可以通过译码算法将错误数据纠正。HARQ技术在媒体接入控制(media access control，MAC)层实现混合自动重传。例如，RS(132,128)+CRC32方案，该方案纠错过程简单，能够满足数据传输的低时延需求，但纠错能力弱，在误码率较高时，难以满足数据传输的可靠性需求。又例如，RS(544,514)+CRC32方案，该方案的检错能力较强，在链路误码率较高时能满足可靠性需求，但检错过程更复杂，难以满足数据传输的低时延需求。
也就是说，现有技术中存在不能兼顾数据传输的低时延和高可靠性这两方面的通信需求的问题。
发明内容
本申请实施例提供一种重传方法及装置，能够兼顾数据传输的低时延和高可靠性这两方面的通信需求，可以提高数据传输的效率和数据传输的可靠性。
为达到上述目的，本申请采用如下技术方案：
第一方面，提供一种重传方法。该重传方法包括：第一设备确定第一数量，根据第一数量与第一阈值的关系，确定是否请求第二设备发送第一数据块。其中，第一数量为接收来自第二设备的信号发生错误的个数，信号用于传输第一数据块，第一阈值为第一设备对第一数据块进行译码时所能纠正的错误的最大数量。
基于第一方面所述的重传方法，第一设备可以统计接收来自第二设备的第一数据块对应的物理层信号发生错误的个数，根据信号发生错误的个数与第一设备的译码纠 错能力，如第一设备进行译码时所能纠正的错误的最大数量，确定是否请求第二设备重新发送该第一数据块。如此，在对第一数据块进行译码和校验前，从物理层信号提取错误信息，能够降低数据传输延时、提高第一设备的检错能力，从而可以提高数据传输的效率和数据传输的可靠性。
可选地，信号发生错误，包括：第一解码输出信号的幅值小于第一边界值或大于第二边界值。其中，第二边界值大于第一边界值，第一解码输出信号的幅值是根据当前第一解码输入信号的幅值和前一第一解码输出信号的幅值确定的。也就是说，信号的幅值区间为第一边界值至第二边界值，当第一解码输出信号的幅值不属于信号的幅值区间时，可以确定信号发生错误。
可选地，信号的幅度阈值包括第一幅度阈值、第二幅度阈值、第三幅度阈值和第四幅度阈值，第一幅度阈值小于第二幅度阈值，第二幅度阈值小于第三幅度阈值，第三幅度阈值小于第四幅度阈值。第一边界值N为：N＝M-a*d1。其中，a为因子，0＜a≤1，d1为相邻幅度阈值之间的幅值间隔，M为第一幅度阈值。第二边界值K为：K＝P+a*d1。其中，a为因子，0＜a≤1，d1为相邻幅度阈值之间的幅值间隔，P为第四幅度阈值。
在一种可能的设计方案中，所述重传方法还可以包括：根据第一解码输出信号的幅值与信号的幅度阈值之间的幅值间隔，确定信号的幅值。也就是说，可以将第一解码输出信号的幅值确定为信号包括的幅度阈值中的一个幅度阈值。
在一种可能的设计方案中，上述根据第一解码输出信号的幅值与信号的幅度阈值之间的幅值间隔，确定信号的幅值，可以包括：若第一解码输出信号的幅值小于第一边界值，则将信号的幅值确定为第一幅度阈值；若第一解码输出信号的幅值大于第二边界值，则将信号的幅值确定为第四幅度阈值。也就是说，若信号发生错误，可以将第一解码输出信号的幅值确定为信号包括的幅度阈值中的一个幅度阈值，纠正第一解码输出信号的幅值，从而可以提高数据传输的可靠性。
在一种可能的设计方案中，上述第一设备根据第一数量与第一阈值的关系，确定是否请求第二设备发送第一数据块，可以包括：若第一数量大于第一阈值，则第一设备请求第二设备发送第一数据块。也就是说，若信号发生错误的个数大于第一设备的译码纠错能力，如第一设备进行译码时所能纠正的错误的最大数量，则可以请求第二设备重新发送该第一数据块。
在一种可能的设计方案中，所述重传方法还可以包括：第一设备对第一数据块进行译码，和/或，对第一数据块进行循环冗余校验。也就是说，可以采用FEC技术对第一数据块进行译码，和/或，采用CRC技术对第一数据块进行循环冗余校验，以进一步降低错误漏检发生的概率，提高数据传输的可靠性。
在一种可能的设计方案中，所述重传方法还可以包括：若第一数量小于或等于第一阈值且满足第一条件，则请求第二设备发送第一数据块。其中，第一条件包括对第一数据块译码失败和/或对第一数据块校验失败。也就是说，当第一数量小于或等于第一阈值时，可以采用FEC技术和CRC技术，进一步降低错误漏检发生的概率，提高数据传输的可靠性。
在另一种可能的设计方案中，所述重传方法还可以包括：若满足第二条件，则第一设备请求第二设备发送第一数据块。其中，第二条件可以包括第一数量大于第一阈 值、对第一数据块译码失败、对第一数据块校验失败中的一项或多项。也就是说，当满足第二条件包括的条件中的任一条件或多个条件时，第一设备均可以请求第二设备发送第一数据块，从而可以提高数据传输的可靠性。
再一种可能的设计方案中，所述重传方法还可以包括：若第一数量大于第一阈值且满足第三条件，则第一设备请求第二设备发送第一数据块。其中，第三条件可以包括对第一数据块译码成功和/或对第一数据块校验成功。如此，可以解决在对第一数据块译码的过程中，发生误纠，数据传输可靠性低的问题。也就是说，当确定第一数量大于第一阈值时，译码成功，可能是因为发生了误纠，实际未将错误数据纠正，则第一设备可以请求重传第一数据块，以提高数据传输的可靠性。
可选地，第一数据块包括：FEC码字或CRC帧、或以太网帧、或指定比特集合。
第二方面，提供一种通信装置。该通信装置包括：处理模块和处理模块。
其中，处理模块，用于确定第一数量。其中，第一数量为接收来自第二设备的信号发生错误的个数，信号用于传输第一数据块；
处理模块，还用于根据第一数量与第一阈值的关系，确定是否控制收发模块请求第二设备发送第一数据块。其中，第一阈值为处理模块对第一数据块进行译码时所能纠正的错误的最大数量。
可选地，信号发生错误，可以包括：第一解码输出信号的幅值小于第一边界值或大于第二边界值。其中，第二边界值大于第一边界值，第一解码输出信号的幅值是根据当前第一解码输入信号的幅值和前一第一解码输出信号的幅值确定的。
可选地，信号的幅度阈值包括第一幅度阈值、第二幅度阈值、第三幅度阈值和第四幅度阈值，第一幅度阈值小于第二幅度阈值，第二幅度阈值小于第三幅度阈值，第三幅度阈值小于第四幅度阈值。第一边界值N为：N＝M-a*d1。其中，a为因子，0＜a≤1，d1为相邻幅度阈值之间的幅值间隔，M为第一幅度阈值。第二边界值K为：K＝P+a*d1。其中，a为因子，0＜a≤1，d1为相邻幅度阈值之间的幅值间隔，P为第四幅度阈值。
在一种可能的设计方案中，处理模块，还用于根据第一解码输出信号的幅值与信号的幅度阈值之间的幅值间隔，确定信号的幅值。
在一种可能的设计方案中，处理模块，还用于若第一解码输出信号的幅值小于第一边界值，则将信号的幅值确定为第一幅度阈值。处理模块，还用于若第一解码输出信号的幅值大于第二边界值，则将信号的幅值确定为第四幅度阈值。
在一种可能的设计方案中，处理模块，还用于若第一数量大于第一阈值，则控制收发模块请求第二设备发送第一数据块。
在一种可能的设计方案中，处理模块，还用于对第一数据块进行译码，和/或，处理模块，还用于对第一数据块进行循环冗余校验。
在一种可能的设计方案中，处理模块，还用于若第一数量小于或等于第一阈值且满足第一条件，则控制收发模块请求第二设备发送第一数据块；其中，第一条件包括对第一数据块译码失败和/或对第一数据块校验失败。
在另一种可能的设计方案中，处理模块，还用于若满足第二条件，则控制收发模块请求第二设备发送第一数据块。其中，第二条件可以包括第一数量大于第一阈值、对第一数据块译码失败、对第一数据块校验失败中的一项或多项。
再一种可能的设计方案中，处理模块，还用于若第一数量大于第一阈值且满足第三条件，则控制收发模块请求第二设备发送第一数据块。其中，第三条件可以包括对第一数据块译码成功和/或对第一数据块校验成功。
可选地，其特征在于，第一数据块包括：FEC码字或CRC帧、或以太网帧、或指定比特集合。
需要说明的是，第二方面所述的收发模块可以包括接收模块和发送模块。其中，接收模块用于接收来自第二设备的数据和/或信令；发送模块用于向第二设备发送第一请求，第一请求用于请求第二设备发送第一数据块，或用于向第二设备发送其它数据和/或信令。本申请对于收发模块的具体实现方式，不做具体限定。
可选地，第二方面所述的通信装置还可以包括存储模块，该存储模块存储有程序或指令。当处理模块执行该程序或指令时，使得第二方面所述的通信装置可以执行第一方面所述的重传方法。
需要说明的是，第二方面所述的通信装置可以是第一设备，也可以是可设置于第一设备的芯片(系统)或其他部件或组件，本申请对此不做限定。
此外，第二方面所述的通信装置的技术效果可以参考第一方面中任一种可能的实现方式所述的重传方法的技术效果，此处不再赘述。
第三方面，提供一种通信装置。该通信装置包括：处理器，该处理器与存储器耦合，存储器用于存储计算机程序。处理器用于执行存储器中存储的计算机程序，以使得该通信装置执行如第一方面中任一种可能的实现方式所述的重传方法。
在一种可能的设计方案中，第三方面所述的通信装置还可以包括收发器。该收发器可以为收发电路或输入/输出端口。所述收发器可以用于该通信装置与其他通信装置通信。
在本申请中，第三方面所述的通信装置可以为第一设备，或者设置于第一设备内部的芯片或芯片系统。
此外，第三方面所述的通信装置的技术效果可以参考第一方面中任一种实现方式所述的重传方法的技术效果，此处不再赘述。
第四方面，提供了一种芯片系统，该芯片系统包括处理器和输入/输出端口，所述处理器用于实现第一方面所涉及的处理功能，所述输入/输出端口用于实现第一方面所涉及的收发功能。
在一种可能的设计方案中，该芯片系统还包括存储器，该存储器用于存储实现第一方面所涉及功能的程序指令和数据。
该芯片系统，可以由芯片构成，也可以包含芯片和其他分立器件。
第五方面，提供一种通信系统。该系统包括第一设备和第二设备。
第六方面，提供一种计算机可读存储介质，包括：该计算机可读存储介质中存储有计算机指令。当该计算机指令在计算机上运行时，使得该计算机执行如第一方面中任一种可能的实现方式所述的重传方法。
第七方面，提供了一种包含指令的计算机程序产品，包括计算机程序或指令，当该计算机程序或指令在计算机上运行时，使得该计算机执行如第一方面中任一种可能的实现方式所述的重传方法。
附图说明
图1为本申请实施例提供的通信系统的架构示意图；
图2为本申请实施例提供的第一设备的结构示意图；
图3为本申请实施例提供的通信装置的结构示意图一；
图4为本申请实施例提供的重传方法的流程示意图一；
图5为本申请实施例提供的运算模型示意图一；
图6为本申请实施例提供的运算过程示意图一；
图7为本申请实施例提供的运算模型示意图二；
图8为本申请实施例提供的运算过程示意图二；
图9为本申请实施例提供的PAM4信号示意图；
图10为本申请实施例提供的通信装置的结构示意图二。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。在本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，a-b，a-c，b-c或a-b-c，其中a、b和c可以是单个，也可以是多个。
本申请将围绕可包括多个设备、组件、模块等的系统来呈现各个方面、实施例或特征。应当理解和明白的是，各个系统可以包括另外的设备、组件、模块等，并且/或者可以并不包括结合附图讨论的所有设备、组件、模块等。此外，还可以使用这些方案的组合。
另外，在本申请实施例中，“示例地”、“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用示例的一词旨在以具体方式呈现概念。
图1为本申请实施例提供的重传方法所适用的通信系统的架构示意图。为便于理解本申请实施例，首先以图1中示出的通信系统的架构为例详细说明适用于本申请实施例的通信系统的架构。通信系统包括第一设备和第二设备。其中，第二设备用于向第一设备发送信号，该信号用于传输第一数据块，第一设备用于接收第二设备发送的信号。第一设备和第二设备可以通过有线或无线的方式通信，第一设备和第二设备可以集成在一起，如可以通过背板互连，也可以单独设置。
其中，第二设备可以包括循环冗余校验CRC生成模块、前向纠错FEC编码模块、调制模块等。本申请不对第二设备包括的模块以及各模块的功能进行限定，具体实现方式可参照现有技术。
图2为本申请实施例提供的第一设备的结构示意图。第一设备可以包括数字信号处理(digital signal processing，DSP)模块、重传逻辑(retry logic)模块。可选地，第一设备还可以包括前向纠错FEC模块和/或循环冗余校验CRC模块。
其中，数字信号处理模块应用于物理层，数字信号处理模块可以包括模拟数字转换器(analog to digital converter，ADC)、前馈均衡器(feed forward equalizer，FFE)、判决反馈 均衡器(decision feedback equalizer，DFE)、突发错误结尾检测(end of burst error detection，EoBD)器等。或者，数字信号处理模块可以包括7电平判决器、1/(1+D)解码器。其中，7电平判决器和1/(1+D)解码器可以替代上述判决反馈均衡器，从而形成两种不同的方案。
模拟数字转换器ADC，用于将接收的模拟信号转换成数字信号。
前馈均衡器FFE，用于对信号进行滤波，消除码间串扰信号。
判决反馈均衡器DFE，用于对接收到的信号进行解码，获得解码后的信号的幅值，将解码后的信号的幅值进行判决，还用于确定信号是否发生错误，若发生错误，则向EoBD发送错误指示信息。
7电平判决器，用于对接收到的信号进行判决。
1/(1+D)解码器，用于对信号进行解码，如根据当前解码输入信号的幅值与前一解码输出信号的幅值的差，确定当前解码输出信号的幅值，还用于确定信号是否发生错误，若发生错误，则向EoBD发送错误指示信息。
突发错误结尾检测EoBD器，用于根据上述判决反馈均衡器DFE或1/(1+D)解码器发送的错误指示信息，确定接收来自第二设备的信号发生错误的个数，若发生错误的个数大于第一设备的纠错能力，则向下述重传逻辑模块发送信号发生错误的个数大于第一设备的纠错能力的信息。
前向纠错FEC模块，用于对第一数据块进行译码，若译码失败，则向下述重传逻辑模块发送译码失败信息，若译码成功，则向下述重传逻辑模块发送译码成功信息。
循环冗余校验CRC模块，用于对第一数据块进行循环冗余校验，若校验失败，则向下述重传逻辑模块发送校验失败信息，若校验成功，则向下述重传逻辑模块发送校验成功信息。
重传逻辑模块，用于接收上述突发错误结尾检测EoBD器、前向纠错FEC模块、循环冗余校验CRC模块发送的信息，还用于根据上述突发错误结尾检测器、前向纠错FEC模块、循环冗余校验CRC模块发送的信息，确定是否请求第二设备重新发送第一数据块。
需要说明的是，本申请实施例提供的重传方法，可以适用于图1所示的第一设备与第二设备之间的通信。应理解，图1仅为便于理解而示例的简化示意图，该通信系统中还可以包括其他设备，图1中未予以画出。图2中示出的第一设备的结构并不构成对该第一设备的限定，实际的第一设备可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置。
图3为可用于执行本申请实施例提供的重传方法的一种通信装置300的结构示意图。通信装置300可以是图1中所示出的第一设备，也可以是应用于第一设备中的芯片(系统)或者其他部件或组件。如图3所示，通信装置300可以包括处理器301。通信装置300还可以包括存储器302和收发器303。其中，处理器301与存储器302和收发器303耦合，如可以通过通信总线连接。
下面结合图3对通信装置300的各个构成部件进行具体的介绍：
处理器301是通信装置300的控制中心，可以是一个处理器，也可以是多个处理元件的统称。例如，处理器301是一个或多个中央处理器(central processing unit，CPU)，也可以是特定集成电路(application specific integrated circuit，ASIC)，或者是被配置成实施 本申请实施例的一个或多个集成电路，例如：一个或多个微处理器(digital signal processor，DSP)，或，一个或者多个现场可编程门阵列(field programmable gate array，FPGA)。
可选地，处理器301可以通过运行或执行存储在存储器302内的软件程序，以及调用存储在存储器302内的数据，执行通信装置300的各种功能。
在具体的实现中，作为一种实施例，处理器301可以包括一个或多个CPU，例如图3中所示的CPU0和CPU1。
在具体实现中，作为一种实施例，通信装置300也可以包括多个处理器，例如图3中所示的处理器301和处理器304。这些处理器中的每一个可以是一个单核处理器(single-CPU)，也可以是一个多核处理器(multi-CPU)。这里的处理器可以指一个或多个通信设备、电路、和/或用于处理数据(例如计算机程序指令)的处理核。
可选地，存储器302可以是只读存储器(read-only memory，ROM)或可存储静态信息和指令的其他类型的静态存储通信设备，随机存取存储器(random access memory，RAM)或者可存储信息和指令的其他类型的动态存储通信设备，也可以是电可擦可编程只读存储器(electrically erasable programmable read-only memory，EEPROM)、只读光盘(compact disc read-only memory，CD-ROM)或其他光盘存储、光碟存储(包括压缩光碟、激光碟、光碟、数字通用光碟、蓝光光碟等)、磁盘存储介质或者其他磁存储通信设备、或者能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质，但不限于此。存储器302可以和处理器301集成在一起，也可以独立存在，并通过通信装置300的输入/输出端口(图3中未示出)与处理器301耦合，本申请实施例对此不作具体限定。
其中，所述存储器302用于存储执行本申请方案的软件程序，并由处理器301来控制执行。上述具体实现方式可以参考下述方法实施例，此处不再赘述。
收发器303，用于与其他通信装置之间的通信。例如，通信装置300为第一设备，收发器303可以用于与第二设备通信。此外，收发器303可以包括接收器和发送器(图3中未单独示出)。其中，接收器用于实现接收功能，发送器用于实现发送功能。收发器303可以和处理器301集成在一起，也可以独立存在，并通过通信装置300的输入/输出端口(图3中未示出)与处理器301耦合，本申请实施例对此不作具体限定。
需要说明的是，图3中示出的通信装置300的结构并不构成对该通信装置的限定，实际的通信装置可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置。
下面将结合图4-图9对本申请实施例提供的重传方法进行具体阐述。
图4为本申请实施例提供的重传方法的流程示意图一。该重传方法可以适用于图2所示的第一设备包括的各个模块/器件之间的通信。
如图4所示，该重传方法包括如下步骤：
S401，第一设备接收来自第二设备的信号。
其中，第一设备可以为信号的接收设备，第二设备可以为信号的发送设备，第二设备可以向第一设备发送信号，该信号用于传输第一数据块。
可选地，信号的幅度阈值可以包括第一幅度阈值、第二幅度阈值、第三幅度阈值和第四幅度阈值，第一幅度阈值小于第二幅度阈值，第二幅度阈值小于第三幅度阈值，第三 幅度阈值小于第四幅度阈值。
示例性地，信号可以为四电平脉冲幅度调制信号(4 pulse amplitude modulation，PAM4)。其中，PAM4信号采用4个不同的信号电平进行信号传输，如-3,-1,1,3，每个信号符号周期可以表示2个比特的逻辑信息(0,1,2,3)。也就是说，-3,-1,1,3这四个信号电平可以分别用于传输数据0,1,2,3，PAM4信号的第一幅度阈值可以为-3,-1,1,3中的-3或0,1,2,3中的0，第二幅度阈值可以为-3,-1,1,3中的-1或0,1,2,3中的1，第三幅度阈值可以为-3,-1,1,3中的1或0,1,2,3中的2，第四幅度阈值可以为-3,-1,1,3中的3或0,1,2,3中的3。
可选地，第一数据块可以包括：FEC码字或CRC帧、或以太网帧、或指定比特集合。其中，CRC帧是由有效数据和冗余校验比特构成的数据单元，通常一个CRC帧可以包括一个或多个FEC码字，指定比特集合也可以是指定比特序列。
图5为本申请实施例提供的运算模型示意图一。以第二设备发送PAM4信号经过1+a*D(0<a≤1)信道为例。
如图5所示，PAM4信号依次经过第二设备的1/(1+D)编码器(encoder)、1+a*D(0<a≤1)信道(channel)，叠加噪声后到达第一设备。第一设备接收到信号后，通过判决反馈均衡器DFE对信号进行第一解码和判决，然后通过(1+D)解码器(decoder)对信号进行第二解码，若第一设备包括FEC模块和/或CRC模块(图5中未示出)，可以将信号输入FEC模块和/或CRC模块。
在上述S401前，第二设备可以对信号进行编码调制等操作，然后信号通过1+a*D(0<a≤1)信道，叠加噪声后到达第一设备，下面结合图5和图6，以a＝1的1+a*D信道为例进行阐述。
步骤一，通过1/(1+D)编码器对信号进行编码，获得编码输出信号。
示例性地，编码过程可以包括：当前编码输出信号的幅值＝(当前编码输入信号的幅值-前一编码输出信号的幅值)mod4，其中，mod为取模运算。
结合图6，以PAM4信号的第一幅度阈值为或0,1,2,3中的0，第二幅度阈值为0,1,2,3中的1，第三幅度阈值为0,1,2,3中的2，第四幅度阈值为0,1,2,3中的3为例，假设第二设备的1/(1+D)编码器的在符号标识(symbol identity)1至20的输入信号分别为1,0,1,3,3,0,3,2,0,1,3,3,0,3,2,1,1,0,3,3。
符号标识1处的编码输出信号的幅值＝(符号标识1处的编码输入信号的幅值1-前一编码输出信号的幅值0)mod4＝1。其中，不存在符号标识1处编码输入信号的前一编码输出信号，可以视为前一编码输出信号的幅值为0。
符号标识2处的编码输出信号的幅值＝(符号标识2处的输入信号的幅值0-符号标识1处的编码输出信号的幅值1)mod4＝3。
符号标识3处的编码输出信号的幅值＝(符号标识3处的编码输入信号的幅值1-符号标识2处的编码输出信号的幅值3)mod4＝2。
类似地，采用上述编码过程，获得符号标识4至20处的编码输出信号的幅值(如图6所示)，具体运算过程此处不再赘述。
步骤二，编码输出信号作为信道输入信号，经过1+D信道，获得信道输出信号。
结合图5，当前信道输出信号的幅值等于当前信道输入信号的幅值加前一信道输入信号的幅值。
结合图6，符号标识1处的信道输出信号的幅值＝符号标识1处的信道输入信号的幅值1+前一编信道输入信号的幅值0＝1。其中，不存在符号标识1处的信道输出信号的前一信道输入信号，可以视为前一编信道输入信号的幅值为0。
符号标识2处的信道输出信号的幅值＝符号标识2处的信道输入信号的幅值3+符号标识1处的信道输入信号的幅值1＝4。
符号标识3处的信道输出信号的幅值＝符号标识3处的信道输入信号的幅值2+符号标识2处的信道输入信号的幅值3＝5。
类似地，采用上述信道处理过程，获得符号标识4至20处的信道输出信号的幅值(如图6所示)，具体运算过程此处不再赘述。
步骤三，将信道输出信号与噪声叠加，获得DFE输入信号，也可以称为第一解码输入信号。
需要说明的是，信道输出信号与噪声叠加后，得到的DFE输入信号不一定是图6所示的整数，还可以是小数，图6中的DFE输入信号均为整数，只是一个示例。
结合图6，符号标识1处的信道输出信号的幅值1与噪声叠加后为1，则符号标识1处的DFE输入信号的幅值为1。
符号标识2处的信道输出信号的幅值4与噪声叠加后为4，则符号标识2处的DFE输入信号的幅值为4。
符号标识3处的信道输出信号的幅值5与噪声叠加后为4，则符号标识3处的DFE输入信号的幅值为4，若没有噪声影响，符号标识3处的DFE输入信号的幅值应等于符号标识3处的信道输出信号的幅值5，所以此处产生了错误。
类似地，将信道输出信号与噪声叠加，获得符号标识4至20处的DFE输入信号的幅值(如图6所示)，具体过程此处不再赘述。受噪声影响，符号标识4至20处的DFE输入信号的幅值可能会产生错误，本申请实施例以符号标识4至20处的DFE输入信号的幅值未引入错误为例进行阐述。
图7为本申请实施例提供的运算模型示意图二，图7所示的运算模型的示意图仅适用于1+D信道场景。下面以第二设备发送PAM4信号经过1+D信道为例进行阐述。
如图7所示，随机4电平信号依次经过第二设备的1/(1+D)编码器、1+D信道，叠加噪声后到达第一设备。第一设备接收到信号后，通过7电平判决器(7level slicer)对信号进行判决，通过1/(1+D)解码器对信号进行第一解码，然后通过(1+D)解码器对信号进行第二解码，若第一设备包括FEC模块/或CRC模块(图7中未示出)，可以将信号输入FEC模块和/或CRC模块。
在上述S401前，第二设备可以对信号进行编码等操作，然后信号通过1+D信道，叠加噪声后到达第一设备，下面结合图7和图8进行阐述。
步骤四，通过1/(1+D)编码器对信号进行编码，获得编码输出信号。
结合图8，以PAM4信号的第一幅度阈值为或0,1,2,3中的0，第二幅度阈值为0,1,2,3中的1，第三幅度阈值为0,1,2,3中的2，第四幅度阈值为0,1,2,3中的3为例，假设第二设备的1/(1+D)编码器的在符号标识1至20的输入信号分别为1,0,1,3,3,0,3,2,0,1,3,3,0,3,2,1,1,0,3,3。获得的编码输出信号可参考图8，具体实现方式可参照上述步骤一，此处不再赘述。
步骤五，编码输出信号作为信道输入信号，经过1+D信道，获得信道输出信号。
获得的信道输出信号的阈值可参考图8，具体实现方式可参照上述步骤二，此处不再赘述。
步骤六，将信道输出信号与噪声叠加，获得7电平判决器输入信号，也就是第一设备的输入信号。
结合图8，符号标识1处的信道输出信号的幅值1与噪声叠加后为1，则符号标识1处的7电平判决器输入信号的幅值为1。
符号标识2处的信道输出信号的幅值4与噪声叠加后为4，则符号标识2处的7电平判决器输入信号的幅值为4。
符号标识3处的信道输出信号的幅值5与噪声叠加后为4，则符号标识3处的7电平判决器输入信号的幅值为4，若没有噪声影响，符号标识3处的7电平判决器输入信号的幅值应等于符号标识3处的信道输出信号的幅值5，所以此处产生了错误。
类似地，将信道输出信号与噪声叠加，获得符号标识4至20处的7电平判决器输入信号的幅值(如图8所示)，具体过程此处不再赘述。受噪声影响，符号标识4至20处的7电平判决器输入信号的幅值可能会产生错误，本申请实施例以符号标识4至20处的7电平判决器输入信号的幅值未引入错误为例进行阐述。
S402，第一设备对信号进行第一解码，获得第一解码输出信号的幅值。
示例性地，对第一数据块的物理层信号进行第一解码，获得第一解码输出信号的幅值。
例如，结合图5，对信号进行第一解码，可以包括：采用判决反馈均衡器DFE对信号进行解码，获得第一解码输出信号，该第一解码输出信号可以作为DFE的判决(slicer)模块的输入信号。
又例如，结合图7，对信号进行第一解码，可以包括：采用1/(1+D)解码器对信号进行解码，获得第一解码输出信号，该第一解码输出信号可以为1/(1+D)解码器输出信号。
可选地，当前第一解码输出信号的幅值是根据当前第一解码输入信号的幅值和前一第一解码输出信号的幅值确定的。
在一些实施例中，根据当前第一解码输入信号的幅值和前一第一解码输出信号的幅值确定当前第一解码输出信号的幅值，可以包括：当前第一解码输出信号的幅值＝当前第一解码输入信号的幅值-a*前一DFE输出信号的幅值。其中，a为因子，如a为判决反馈均衡器DFE的抽头系数，0<a≤1，DFE输出信号是根据第一解码输出信号确定的。
结合图5，DFE输出信号是DFE的判决模块对第一解码输出信号进行判决后的信号，第一解码输入信号为DFE输入信号，第一解码输出信号为DFE的判决模块的输入信号。
在另一些实施例中，根据当前第一解码输入信号的幅值和前一第一解码输出信号的幅值确定当前第一解码输出信号的幅值，可以包括：当前第一解码输出信号的幅值＝当前第一解码输入信号的幅值-前一第一解码输出信号的幅值。
结合图7，第一解码输入信号为7电平判决器输出信号，第一解码输出信号为1/(1+D)解码器输出信号。
在一种可能的设计方案中，在上述S402后，本申请实施例的重传方法，还可以包括：根据第一解码输出信号的幅值与信号的幅度阈值之间的幅值间隔，确定信号的幅值。
图9为本申请实施例提供的PAM4信号示意图。如图9所示，横坐标表示信号的幅值x，纵坐标表示信号幅值的概率密度f，PAM4信号的第一幅度阈值为-3，第二幅度阈值为-1，第三幅度阈值为1，第四幅度阈值为3，d1为相邻幅度阈值之间的幅值间隔2，N为第一边界值，K为第二边界值。或者，PAM4信号的第一幅度阈值可以为0，第二幅度阈值可以为1，第三幅度阈值可以为2，第四幅度阈值可以为3(图9中未示出)，d1为相邻幅度阈值之间的幅值间隔1。
在一些实施例中，上述第一边界值N可以满足下述公式：N＝M-a*d1。其中，a为因子，如a为判决反馈均衡器DFE的抽头系数，0＜a≤1，d1为相邻幅度阈值之间的幅值间隔，M为第一幅度阈值。
上述第二边界值K可以满足下述公式：K＝P+a*d1。其中，a为因子，如a为判决反馈均衡器DFE的抽头系数，0＜a≤1，d1为相邻幅度阈值之间的幅值间隔，P为第四幅度阈值。
在另一些实施例中，第一边界值N可以满足下述公式：N＝M-b*a*d1。其中，b为经验值，0＜b≤1，a为因子，如a为判决反馈均衡器DFE的抽头系数，0＜a≤1，d1为相邻幅度阈值之间的幅值间隔，M为第一幅度阈值。
上述第二边界值K可以满足下述公式：K＝P+b*a*d1。其中，b为经验值，0＜b≤1，a为因子，如a为判决反馈均衡器DFE的抽头系数，0＜a≤1，d1为相邻幅度阈值之间的幅值间隔，P为第四幅度阈值。也就是说，可以根据经验对信号的第一边界值和第二边界值进行设置。
需要说明的是，本申请实施例只是以四电平脉冲幅度调制信号为例，不对信号的电平数进行限定，当信号包括的幅度阈值大于4个幅度阈值，或信号包括的幅度阈值小于4个幅度阈值时，第一幅度阈值可以为信号包括的幅度阈值中最小的幅度阈值，第四幅度阈值可以为信号包括的幅度阈值中最大的幅度阈值。
在一些实施例中，上述根据第一解码输出信号的幅值与信号的幅度阈值之间的幅值间隔，确定信号的幅值，可以包括：将信号的幅值确定为与第一解码输出信号的幅值间隔的幅值最小的幅度阈值。
结合图9，当第一解码输出信号的幅值为-3.5时，幅值-3.5与幅度阈值-3的幅值间隔为0.5，幅值-3.5与幅度阈值-1的幅值间隔为2.5，幅值-3.5与幅度阈值1的幅值间隔为4.5，幅值-3.5与幅度阈值3的幅值间隔为6.5，幅值-3.5与幅度阈值-3的幅值间隔最小，则可以将信号的幅值确定为-3。
在另一些实施例中，上述根据第一解码输出信号的幅值与信号的幅度阈值之间的幅值间隔，确定信号的幅值，可以包括：按照判决规则确定信号的幅值。
示例性地，判决规则可以包括：若第一边界值≤Q＜(第一幅度阈值+0.5*d1)，则可以将信号的幅值确定为第一幅度阈值；若(第一幅度阈值+0.5*d1)≤Q＜(第二幅度阈值+0.5*d1)，则可以将信号的幅值确定为第二幅度阈值；若(第二幅度阈值+0.5*d1)≤Q＜(第三幅度阈值+0.5*d1)，则可以将信号的幅值确定为第三幅度阈值；若(第三幅度阈值+0.5*d1)≤Q≤第二边界值，则可以将信号的幅值确定为第四幅度阈值。其中，Q为第 一解码输出信号的幅值，d1为相邻幅度阈值之间的幅值间隔。
结合图9，第一幅度阈值为-3，第二幅度阈值为-1，第三幅度阈值为1，第四幅度阈值为3，若第一解码输出信号的幅值为-3.5，且a＝1，b＝0.55，第一边界值N＝-3-0.55*1*2＝-4.1，第一幅度阈值+0.5*d1＝-3+0.5*2＝-2，-4.1＜-3.5＜-2，则可以将信号的幅值确定为-3。
假设PAM4信号的第一幅度阈值为0，第二幅度阈值为1，第三幅度阈值为2，第四幅度阈值为3，若第一解码输出信号的幅值为3.5，且a＝1，b＝0.55，第二边界值K＝3+0.55*1*1＝3.55，第三幅度阈值+0.5*d1＝2+0.5*1＝2.5，2.5＜3.5＜3.55，则可以将信号的幅值确定为3。
再一些实施例中，上述根据第一解码输出信号的幅值与信号的幅度阈值之间的幅值间隔，确定信号的幅值，可以包括：若第一解码输出信号的幅值小于第一边界值，则将信号的幅值确定为第一幅度阈值；若第一解码输出信号的幅值大于第二边界值，则将信号的幅值确定为第四幅度阈值。
结合图9，第一幅度阈值为-3，第二幅度阈值为-1，第三幅度阈值为1，第四幅度阈值为3，若第一解码输出信号的幅值为-5，且a＝1，b＝0.55，第一边界值N＝-3-0.55*1*2＝-4.1，-5＞-4.1，则可以将信号的幅值确定为-3。
假设PAM4信号的第一幅度阈值为0，第二幅度阈值为1，第三幅度阈值为2，第四幅度阈值为3，若第一解码输出信号的幅值为4，且a＝1，b＝0.55，第二边界值K＝3+0.55*1*1＝3.55，4大于3.55，则可以将信号的幅值确定为3。
示例性地，承接上述步骤三，结合图5和图6，以a＝1，1+D信道为例，对获得第一解码输出信号的幅值，以及根据第一解码输出信号的幅值与信号的幅度阈值之间的幅值间隔确定信号的幅值进行阐述，具体实现方式参照下述步骤七至步骤八。
步骤七，对第一解码输入信号进行第一解码，获得第一解码输出信号。
第一解码过程可以包括：当前第一解码输出信号(DFE判决器输入信号)的幅值＝当前第一解码输入信号的幅值-前一DFE输出信号的幅值。其中，第一解码输出信号为图6中的DFE判决器输入信号，DFE输出信号的幅值的实现方式可参照下述步骤九。
结合图5和图6，符号标识1处的第一解码输出信号的幅值＝符号标识1处第一解码输入信号的幅值1-前一DFE输出信号的幅值0＝1。其中，不存在符号标识1处的第一解码输出信号的前一DFE输出信号的幅值，可以视为前一DFE输出信号的幅值为0。
符号标识2处的第一解码输出信号的幅值＝符号标识2处第一解码输入信号的幅值4-符号标识1处DFE输出信号的幅值1＝3。
符号标识3处的第一解码输出信号的幅值＝符号标识3处第一解码输入信号的幅值4-符号标识2处DFE输出信号的幅值3＝1。
类似地，采用上述第一解码过程，获得符号标识4至20处的第一解码输出信号的幅值(如图6所示)，具体运算过程此处不再赘述。
步骤八，根据第一解码输出信号的幅值与信号的幅度阈值之间的幅值间隔，获得DFE输出信号。
例如，将符号标识1处的第一解码输出信号的幅值1确定为幅度阈值1，则符号标识1处DFE输出信号的幅值为1。
将符号标识2处的第一解码输出信号的幅值3判决为幅度阈值3，则符号标识2处的DFE输出信号的幅值为3。
类似地，采用上述判决过程，获得符号标识3至17、19、20处的DFE输出信号的幅值(如图6所示)，具体运算过程此处不再赘述。由于在上述步骤三，符号标识3处，由于噪声引入了错误，使第一解码输出信号的幅值在符号标识3处开始产生错误，进而使得上述得出的符号标识3处的DFE输出信号的幅值产生错误，受DFE结构的影响，错误传递至符号标识17处。
符号标识18处的第一解码输出信号的幅值4，第二边界值K＝3+0.55*1*1＝3.55，4大于3.55，将符号标识18处的第一解码输出信号的幅值4判决为幅度阈值3，则符号标识18处的DFE输出信号的幅值为3，纠正了DFE输出信号的幅值，信号的错误传递终止，从而符号标识19、20处的DFE输出信号的幅值是正确的。
示例性地，承接上述步骤六，结合图7和图8，对获得第一解码输出信号的幅值，以及根据第一解码输出信号的幅值与信号的幅度阈值之间的幅值间隔确定信号的幅值进行阐述。具体实现方式参照下述步骤九至步骤十。
步骤九，对第一解码输入信号进行第一解码，获得第一解码输出信号。
第一解码过程可以包括：当前第一解码输出信号的幅值＝当前第一解码输入信号的幅值-前一1/(1+D)解码器输出信号的幅值。其中，第一解码输入信号的幅值为图8中的7电平判决器输出信号的幅值，第一解码输出信号的幅值为图8中的1/(1+D)解码器输出信号的幅值。
结合图7和图8，符号标识1处的第一解码输出信号的幅值＝符号标识1处第一解码输入信号的幅值1-前一1/(1+D)解码器输出信号的幅值0＝1。其中，不存在符号标识1处的第一解码输出信号的前一1/(1+D)解码器输出信号的幅值，可以视为前一1/(1+D)解码器输出信号的幅值为0。
符号标识2处的第一解码输出信号的幅值＝符号标识2处第一解码输入信号的幅值4-符号标识1处1/(1+D)解码器输出信号的幅值1＝3。
类似地，采用上述第一解码过程，获得符号标识3至18、20处的第一解码输出信号的幅值(如图8所示)，具体运算过程此处不再赘述。
符号标识19处的第一解码输出信号的幅值＝符号标识19处第一解码输入信号的幅值3-符号标识18处1/(1+D)解码器判决输出信号的幅值3＝0。1/(1+D)解码器判决输出信号的幅值的实现方式可参照下述步骤十，此处不再赘述。
步骤十，根据第一解码输出信号的幅值与信号的幅度阈值之间的幅值间隔，获得1/(1+D)解码器判决输出信号。
例如，将符号标识1处的第一解码输出信号的幅值1确定为幅度阈值1，则符号标识1处1/(1+D)解码器判决输出信号的幅值为1。
类似地，采用上述判决过程，获得符号标识2至17、19、20处的1/(1+D)解码器判决输出信号的幅值(如图8所示)，具体运算过程此处不再赘述。由于在上述步骤六，符号标识3处，由于噪声引入了错误，使第一解码输出信号的幅值在符号标识3处开始产生错误，进而使得上述得出的符号标识3处的1/(1+D)解码器判决输出信号的幅值产生错误，受1/(1+D)解码器的影响，错误传递至符号标识17处。
其中，符号标识18处的第一解码输出信号的幅值4，第二边界值K＝3+0.55*1*1＝3.55，4大于3.55，将符号标识18处的第一解码输出信号的幅值4确定为幅度阈值3， 则符号标识18处的1/(1+D)解码器判决输出信号的幅值为3，纠正了符号标识18处的第一解码输出信号的幅值，信号的错误传递终止。
S403，第一设备确定信号是否发生错误。
在一种可能的设计方案中，确定信号发生错误，可以包括：若第一解码输出信号的幅值小于第一边界值或大于第二边界值，则信号发生错误。
示例性地，第一解码输出信号可以是第一数据块的物理层传输信号。
其中，第二边界值大于第一边界值。关于第一边界值和第二边界值的具体实现方式可参照上述S402，此处不再赘述。
结合图9，假设a＝1，b＝0.55，第一边界值N＝-3-0.55*1*2＝-4.1，第二边界值K＝3+0.55*1*2＝4.1，若第一解码输出信号的幅值为5，5大于4.1，则信号发生错误。
假设PAM4信号的第一幅度阈值为0，第二幅度阈值为1，第三幅度阈值为2，第四幅度阈值为3，若第一解码输出信号的幅值为4，且a＝1，b＝0.55，第二边界值K＝3+0.55*1*1＝3.55，4大于3.55，则信号发生错误。
示例性地，承接上述步骤八，结合图5和图6，以a＝1，1+D信道为例，对确定信号是否发生错误进行阐述。具体实现方式参照下述步骤十一。
步骤十一，确定第一解码输出信号是否发生错误。
结合图6，第一幅度阈值为0，第二幅度阈值为1，第三幅度阈值为2，第四幅度阈值为3，假设a＝1，b＝0.55，则第一边界值N＝0-0.55*1*1＝-0.55，第二边界值K＝3+0.55*1*1＝3.55，若第一解码输出信号的幅值小于-0.55或大于3.55，则信号发生错误。
符号标识1-17处、符号标识19处、符号标识20处的第一解码输出信号的幅值均在-0.55至3.55之间，符号标识18处的第一解码输出信号的幅值(图6中DFE判决器输入信号的幅值)大于第二边界值3.55，则确定信号发生错误。
示例性地，承接上述步骤八，结合图7和图8，对确定信号是否发生错误进行阐述。具体实现方式参照下述步骤十二。
步骤十二，确定第一解码输出信号是否发生错误。
若第一解码输出信号的幅值小于第一边界值或大于第二边界值，则信号发生错误，否则，信号未发生错误。具体实现方式可参照上述步骤十一，此处不再赘述。
S404，第一设备确定第一数量。
其中，第一数量为接收来自第二设备的信号发生错误的个数。
具体地，第一设备可以根据上述S403，第一设备确定信号是否发生错误的结果，统计信号发生错误的个数。
可选地，第一设备可以以FEC码字、或CRC帧、或以太网帧、或指定比特集合为基本粒度，确定第一数量。也就是说，第一数量可以为特定长度的信号中，信号发生错误的个数。
如图6或图8所示，EoBD确定接收来自第二设备的信号发生错误的个数，在符号标识18处检测出信号发生错误，EoBD置为1。
可选地，第一设备可以对信号进行第二解码，下面结合图5和图6进行阐述。
步骤十三，通过(1+D)解码器对信号进行解码，获得(1+D)解码器输出信号。
示例性地，第二解码过程可以包括：当前(1+D)解码器输出信号的幅值＝(当前(1+D)解码器输入信号的幅值+前一(1+D)解码器输入信号的幅值)mod4，其中，mod为取模运算。
结合图6，(1+D)解码器输入信号为DFE输出信号。符号标识1处的(1+D)解码器输出信号的幅值＝(符号标识1处的(1+D)解码器输入信号的幅值1+前一(1+D)解码器输入信号的幅值0)mod4＝1。其中，不存在符号标识1处的编码输入信号的前一(1+D)解码器输入信号，可以视为前一(1+D)解码器输入信号的幅值为0。
符号标识2处的(1+D)解码器输出信号的幅值＝(符号标识2处的(1+D)解码器输入信号的幅值3+符号标识1处的(1+D)解码器输入信号的幅值1)mod4＝0。
符号标识3处的(1+D)解码器输出信号的幅值＝(符号标识3处的(1+D)解码器输入信号的幅值1+符号标识2处的(1+D)解码器输入信号的幅值3)mod4＝0。
类似地，采用上述第二解码过程，获得符号标识4至17处的(1+D)解码器输出信号的幅值(如图6所示)，具体运算过程此处不再赘述。
由于在符号标识18处检测出第一解码输出信号发生错误，符号标识18处的(1+D)解码器输出信号的幅值＝(符号标识18处的第一解码输出信号的幅值4+符号标识17处的(1+D)解码器输入信号的幅值0)mod4＝0，其中，第一解码输出信号为图6中的DFE判决器输入信号。
符号标识19处的(1+D)解码器输出信号的幅值＝(符号标识19处的(1+D)解码器输入信号的幅值0+符号标识18处的(1+D)解码器输入信号的幅值3)mod4＝3。
符号标识20处的(1+D)解码器输出信号的幅值＝(符号标识20处的(1+D)解码器输入信号的幅值3+符号标识19处的(1+D)解码器输入信号的幅值0)mod4＝3。
结合图6，第二解码后，符号标识3处的(1+D)解码器输出信号的幅值0，与符号标识3处的1/(1+D)编码器输入信号的幅值1，不相同，符号标识3处的信号出现错误。其它符号标识处的(1+D)解码器输出信号的幅值，与1/(1+D)编码器输入信号的幅值对应相同。
下面结合图7和图8对第二解码进行阐述。
步骤十四，通过(1+D)解码器对信号进行解码，获得(1+D)解码器输出信号。
示例性地，第二解码过程可以包括：当前(1+D)解码器输出信号的幅值＝(当前(1+D)解码器输入信号的幅值+前一(1+D)解码器输入信号的幅值)mod4，其中，mod为取模符号。
结合图8，(1+D)解码器输入信号为1/(1+D)解码器判决输出信号。具体实现方式可参照上述步骤十三，此处不再赘述。
S405，第一设备根据第一数量与第一阈值的关系，确定是否请求第二设备发送第一数据块。
在一种可能的设计方案中，上述第一设备根据第一数量与第一阈值的关系，确定是否请求第二设备发送第一数据块，可以包括：若第一数量大于第一阈值，则第一设备可以执行下述S406。
其中，第一阈值可以为第一设备对第一数据块进行译码时所能纠正的错误的最大数量。
可选地，第一数据块进行译码时所能纠正的错误的最大数量可以指FEC模块的纠错能力。当第一设备不包括FEC模块时，第一阈值可以为0。
示例性地，FEC模块的纠错能力t可以为：一个RS码字能够成功纠正的、允许出错的最多符号个数。FEC模块的纠错能力t可以满足下述公式t＝(N-K)/2，其中，N为RS码字长度，K为RS码字信息长度。
例如，RS(528,514)，528为RS码字长度，514为RS码字信息长度，则纠错能力t＝(528-514)/2＝7。
又例如，对于RS(544,514)，544为RS码字长度，514为RS码字信息长度，纠错能力t＝(544-514)/2＝15。
在一种可能的设计方案中，所述重传方法还可以包括：对第一数据块进行译码和/或对第一数据块进行循环冗余校验。也就是说，在物理层确定信号是否发生错误的方案可以与FEC技术和/或CRC技术结合使用，以进一步降低错误漏检发生的概率，提高数据传输的可靠性。
例如，第一设备可以以FEC码字长度为基本粒度，对第一数据块进行译码，和/或第一设备可以以CRC帧长度为基本粒度，对第一数据块进行循环冗余校验。
进一步地，在一些实施例中，若满足第二条件，则第一设备可以执行下述S406。
其中，第二条件可以包括第一数量大于第一阈值、对第一数据块译码失败、对第一数据块校验失败中的一项或多项。也就是说，当满足第二条件包括的条件中的任一条件或多个条件时，第一设备均可以请求第二设备重新发送第一数据块，从而可以提高数据传输的可靠性。
在另一些实施例中，若第一数量大于第一阈值且满足第三条件，则第一设备可以执行下述S406。
其中，第三条件可以包括对第一数据块译码成功和/或对第一数据块校验成功。如此，可以解决在对第一数据块译码的过程中，发生误纠，数据传输可靠性低的问题。也就是说，当确定第一数量大于第一阈值时，译码成功，可能是因为发生了误纠，实际未将错误数据纠正，则第一设备可以请求重传第一数据块，以提高数据传输的可靠性。
再一些实施例中，若第一数量小于或等于第一阈值且满足第一条件，则第一设备可以执行下述S406。
其中，第一条件可以包括对第一数据块译码失败和/或对第一数据块校验失败。也就是说，第一数量小于或等于第一阈值时，可以采用FEC技术和CRC技术，降低错误漏检发生的概率，提高数据传输的可靠性。
S406，第一设备请求第二设备发送第一数据块。
可选地，第一设备请求第二设备发送第一数据块，可以包括：向第二设备发送第一请求。其中，第一请求可以用于请求第二设备发送第一数据块。
基于图4所示的重传方法，第一设备可以统计接收来自第二设备的第一数据块对应的物理层信号发生错误的个数，根据信号发生错误的个数与第一设备的译码纠错能力，如第一设备进行译码时所能纠正的错误的最大数量，确定是否请求第二设备重新发送该第一数据块。如此，在对第一数据块进行译码和校验前，从物理层信号提取错误信息，能够降低数据传输延时、提高第一设备的检错能力，从而可以提高数据传输的效率和数据传输的可靠性。
以上结合图4-图9详细说明了本申请实施例提供的重传方法。以下结合图10详细说 明本申请实施例提供的通信装置。
图10是本申请实施例提供的通信装置的结构示意图二。该通信装置可适用于图1所示出的通信系统中，执行图4所示的重传方法中第一设备的功能。为了便于说明，图10仅示出了该通信装置的主要部件。
如图10所示，该通信装置1000包括：收发模块1001和处理模块1002。
其中，处理模块1002，用于确定第一数量。其中，第一数量为接收来自第二设备的信号发生错误的个数，信号用于传输第一数据块；
处理模块1002，还用于根据第一数量与第一阈值的关系，确定是否控制收发模块1001请求第二设备发送第一数据块。其中，第一阈值为处理模块1002对第一数据块进行译码时所能纠正的错误的最大数量。
可选地，信号发生错误，可以包括：第一解码输出信号的幅值小于第一边界值或大于第二边界值。其中，第二边界值大于第一边界值，第一解码输出信号的幅值是根据当前第一解码输入信号的幅值和前一第一解码输出信号的幅值确定的。
可选地，信号的幅度阈值包括第一幅度阈值、第二幅度阈值、第三幅度阈值和第四幅度阈值，第一幅度阈值小于第二幅度阈值，第二幅度阈值小于第三幅度阈值，第三幅度阈值小于第四幅度阈值。第一边界值N为：N＝M-a*d1。其中，a为因子，0＜a≤1，d1为相邻幅度阈值之间的幅值间隔，M为第一幅度阈值。第二边界值K为：K＝P+a*d1。其中，a为因子，0＜a≤1，d1为相邻幅度阈值之间的幅值间隔，P为第四幅度阈值。
在一种可能的设计方案中，处理模块1002，还用于根据第一解码输出信号的幅值与信号的幅度阈值之间的幅值间隔，确定信号的幅值。
在一种可能的设计方案中，处理模块1002，还用于若第一解码输出信号的幅值小于第一边界值，则将信号的幅值确定为第一幅度阈值。处理模块1002，还用于若第一解码输出信号的幅值大于第二边界值，则将信号的幅值确定为第四幅度阈值。
在一种可能的设计方案中，处理模块1002，还用于若第一数量大于第一阈值，则控制收发模块1001请求第二设备发送第一数据块。
在一种可能的设计方案中，处理模块1002，还用于对第一数据块进行译码和/或，处理模块1002，还用于对第一数据块进行循环冗余校验。
在一种可能的设计方案中，处理模块1002，还用于若第一数量小于或等于第一阈值且满足第一条件，则控制收发模块1001请求第二设备发送第一数据块。其中，第一条件包括对第一数据块译码失败和/或对第一数据块校验失败。
在另一种可能的设计方案中，处理模块1002，还用于若满足第二条件，则控制收发模块1001请求第二设备发送第一数据块。其中，第二条件包括第一数量大于第一阈值、对第一数据块译码失败、对第一数据块校验失败中的一项或多项。
再一种可能的设计方案中，处理模块1002，还用于若第一数量大于第一阈值且满足第三条件，则控制收发模块1001请求第二设备发送第一数据块。其中，第三条件包括对第一数据块译码成功和/或对第一数据块校验成功。
可选地，第一数据块包括：FEC码字或CRC帧、或以太网帧、或指定比特集合。
需要说明的是，收发模块1001可以包括接收模块和发送模块(图10中未示出)。其中，接收模块用于接收来自第二设备的数据和/或信令；发送模块用于向第二设备 发送第一请求，第一请求用于请求第二设备发送第一数据块，或用于向第二设备发送其它数据和/或信令。本申请对于收发模块1001的具体实现方式，不做具体限定。
可选地，通信装置1000还可以包括存储模块(图10中未示出)，该存储模块存储有程序或指令。当处理模块1002执行该程序或指令时，使得通信装置1000可以执行图4所示的重传方法中第一设备的功能。
需要说明的是，通信装置1000可以是图1所示的第一设备或图3所示的通信装置300，也可以是可设置于第一设备或通信装置300的芯片(系统)或其他部件或组件，本申请对此不做限定。
此外，通信装置1000的技术效果可以参考图4所示的重传方法的技术效果，此处不再赘述。
本申请实施例提供一种通信系统。该系统包括第一设备和第二设备。
本申请实施例提供一种计算机可读存储介质，该计算机可读存储介质包括计算机程序或指令；当该计算机程序或指令在计算机上运行时，使得该计算机执行上述方法实施例所述的重传方法。
本申请实施例提供一种计算机程序产品，包括计算机程序或指令，当该计算机程序或指令在计算机上运行时，使得该计算机执行上述方法实施例所述的重传方法。
应理解，在本申请实施例中的处理器可以是中央处理单元(central processing unit，CPU)，该处理器还可以是其他通用处理器、数字信号处理器(digital signal processor，DSP)、专用集成电路(application specific integrated circuit，ASIC)、现成可编程门阵列(field programmable gate array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
还应理解，本申请实施例中的存储器可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(read-only memory，ROM)、可编程只读存储器(programmable ROM，PROM)、可擦除可编程只读存储器(erasable PROM，EPROM)、电可擦除可编程只读存储器(electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(random access memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的随机存取存储器(random access memory，RAM)可用，例如静态随机存取存储器(static RAM，SRAM)、动态随机存取存储器(DRAM)、同步动态随机存取存储器(synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(double data rate SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(synchlink DRAM，SLDRAM)和直接内存总线随机存取存储器(direct rambus RAM，DR RAM)。
上述实施例，可以全部或部分地通过软件、硬件(如电路)、固件或其他任意组合来实现。当使用软件实现时，上述实施例可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令或计算机程序。在计算机上加载或执行所述计算机指令或计算机程序时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以为通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计 算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集合的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质。半导体介质可以是固态硬盘。
应理解，本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况，其中A,B可以是单数或者复数。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系，但也可能表示的是一种“和/或”的关系，具体可参考前后文进行理解。
本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a,b,或c中的至少一项(个)，可以表示：a,b,c,a-b,a-c,b-c,或a-b-c，其中a,b,c可以是单个，也可以是多个。
应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元或模块及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元或模块的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，上述单元或模块的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或模块可以结合或者可以集成到另一个系统，或一些单元或模块可以忽略，或其对应的功能不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元/模块的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元/模块可以是或者也可以不是物理上分开的，作为单元/模块显示的部件可以是或者也可以不是物理单元/模块，即可以位于一个地方，或者也可以分布到多个网络单元/模块上。可以根据实际的需要选择其中的部分或者全部单元/模块来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元/模块可以集成在一个处理单元/模块中，也可以是各个单元/模块单独物理存在，也可以两个或两个以上单元/模块集成在一个单元/模块中。
所述功能如果以软件功能单元/模块的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说 对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(read-only memory，ROM)、随机存取存储器(random access memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (21)

  1. 一种重传方法，其特征在于，所述方法包括：
    第一设备确定第一数量；其中，所述第一数量为接收来自第二设备的信号发生错误的个数，所述信号用于传输第一数据块；
    所述第一设备根据所述第一数量与第一阈值的关系，确定是否请求所述第二设备发送所述第一数据块；其中，所述第一阈值为所述第一设备对所述第一数据块进行译码时所能纠正的错误的最大数量。
  2. 根据权利要求1所述的重传方法，其特征在于，所述信号发生错误，包括：第一解码输出信号的幅值小于第一边界值或大于第二边界值；其中，所述第二边界值大于所述第一边界值，所述第一解码输出信号的幅值是根据当前第一解码输入信号的幅值和前一第一解码输出信号的幅值确定的。
  3. 根据权利要求1或2所述的重传方法，其特征在于，所述信号的幅度阈值包括第一幅度阈值、第二幅度阈值、第三幅度阈值和第四幅度阈值，所述第一幅度阈值小于所述第二幅度阈值，所述第二幅度阈值小于所述第三幅度阈值，所述第三幅度阈值小于所述第四幅度阈值；
    第一边界值N为：N＝M-a*d1；其中，a为因子，0＜a≤1，d1为相邻幅度阈值之间的幅值间隔，M为所述第一幅度阈值；
    第二边界值K为：K＝P+a*d1；其中，a为因子，0＜a≤1，d1为相邻幅度阈值之间的幅值间隔，P为所述第四幅度阈值。
  4. 根据权利要求3所述的重传方法，其特征在于，所述方法还包括：
    所述第一设备根据所述第一解码输出信号的幅值与所述信号的幅度阈值之间的幅值间隔，确定所述信号的幅值。
  5. 根据权利要求4所述的重传方法，其特征在于，所述第一设备根据所述第一解码输出信号的幅值与所述信号的幅度阈值之间的幅值间隔，确定所述信号的幅值，包括：
    若所述第一解码输出信号的幅值小于所述第一边界值，则所述第一设备将所述信号的幅值确定为所述第一幅度阈值；
    若所述第一解码输出信号的幅值大于所述第二边界值，则所述第一设备将所述信号的幅值确定为所述第四幅度阈值。
  6. 根据权利要求1-5中任一项所述的重传方法，其特征在于，所述第一设备根据所述第一数量与第一阈值的关系，确定是否请求所述第二设备发送所述第一数据块，包括：
    若所述第一数量大于所述第一阈值，则所述第一设备请求所述第二设备发送所述第一数据块。
  7. 根据权利要求1-6中任一项所述的重传方法，其特征在于，所述方法还包括：
    所述第一设备对所述第一数据块进行译码，和/或，对所述第一数据块进行循环冗余校验。
  8. 根据权利要求1-7中任一项所述的重传方法，其特征在于，所述方法还包括：
    若所述第一数量小于或等于所述第一阈值且满足第一条件，则所述第一设备请求 所述第二设备发送所述第一数据块；其中，所述第一条件包括对所述第一数据块译码失败和/或对所述第一数据块校验失败；或者，
    若满足第二条件，则所述第一设备请求所述第二设备发送所述第一数据块；其中，所述第二条件包括所述第一数量大于所述第一阈值、对所述第一数据块译码失败、对所述第一数据块校验失败中的一项或多项；或者，
    若所述第一数量大于所述第一阈值且满足第三条件，则所述第一设备请求所述第二设备发送所述第一数据块；其中，所述第三条件包括对所述第一数据块译码成功和/或对所述第一数据块校验成功。
  9. 根据权利要求1-8中任一项所述的重传方法，其特征在于，所述第一数据块包括：FEC码字或CRC帧、或以太网帧、或指定比特集合。
  10. 一种通信装置，其特征在于，所述装置包括：收发模块和处理模块；
    所述处理模块，用于确定第一数量；其中，所述第一数量为接收来自第二设备的信号发生错误的个数，所述信号用于传输第一数据块；
    所述处理模块，还用于根据所述第一数量与第一阈值的关系，确定是否控制所述收发模块请求所述第二设备发送所述第一数据块；其中，所述第一阈值为所述处理模块对所述第一数据块进行译码时所能纠正的错误的最大数量。
  11. 根据权利要求10所述的通信装置，其特征在于，所述信号发生错误，包括：第一解码输出信号的幅值小于第一边界值或大于第二边界值；其中，所述第二边界值大于所述第一边界值，所述第一解码输出信号的幅值是根据当前第一解码输入信号的幅值和前一第一解码输出信号的幅值确定的。
  12. 根据权利要求10或11所述的通信装置，其特征在于，所述信号的幅度阈值包括第一幅度阈值、第二幅度阈值、第三幅度阈值和第四幅度阈值，所述第一幅度阈值小于所述第二幅度阈值，所述第二幅度阈值小于所述第三幅度阈值，所述第三幅度阈值小于所述第四幅度阈值；
    第一边界值N为：N＝M-a*d1；其中，a为因子，0＜a≤1，d1为相邻幅度阈值之间的幅值间隔，M为所述第一幅度阈值；
    第二边界值K为：K＝P+a*d1；其中，a为因子，0＜a≤1，d1为相邻幅度阈值之间的幅值间隔，P为所述第四幅度阈值。
  13. 根据权利要求12所述的通信装置，其特征在于，
    所述处理模块，还用于根据所述第一解码输出信号的幅值与所述信号的幅度阈值之间的幅值间隔，确定所述信号的幅值。
  14. 根据权利要求13所述的通信装置，其特征在于，
    所述处理模块，还用于若所述第一解码输出信号的幅值小于所述第一边界值，则将所述信号的幅值确定为所述第一幅度阈值；
    所述处理模块，还用于若所述第一解码输出信号的幅值大于所述第二边界值，则将所述信号的幅值确定为所述第四幅度阈值。
  15. 根据权利要求10-14中任一项所述的通信装置，其特征在于，
    所述处理模块，还用于若所述第一数量大于所述第一阈值，则控制所述收发模块请求所述第二设备发送所述第一数据块。
  16. 根据权利要求10-15中任一项所述的通信装置，其特征在于，
    所述处理模块，还用于对所述第一数据块进行译码；和/或，
    所述处理模块，还用于对所述第一数据块进行循环冗余校验。
  17. 根据权利要求10-16中任一项所述的通信装置，其特征在于，
    所述处理模块，还用于若所述第一数量小于或等于所述第一阈值且满足第一条件，则控制所述收发模块请求所述第二设备发送所述第一数据块；其中，所述第一条件包括对所述第一数据块译码失败和/或对所述第一数据块校验失败；或者，
    所述处理模块，还用于若满足第二条件，则控制所述收发模块请求所述第二设备发送所述第一数据块；其中，所述第二条件包括所述第一数量大于所述第一阈值、对所述第一数据块译码失败、对所述第一数据块校验失败中的一项或多项；或者，
    所述处理模块，还用于若所述第一数量大于所述第一阈值且满足第三条件，则控制所述收发模块请求所述第二设备发送所述第一数据块；其中，所述第三条件包括对所述第一数据块译码成功和/或对所述第一数据块校验成功。
  18. 根据权利要求10-17中任一项所述的通信装置，其特征在于，所述第一数据块包括：FEC码字或CRC帧、或以太网帧、或指定比特集合。
  19. 一种通信装置，其特征在于，所述通信装置包括：处理器，所述处理器与存储器耦合；
    所述存储器，用于存储计算机程序；
    所述处理器，用于执行所述存储器中存储的所述计算机程序，以使得所述通信装置执行如权利要求1-9中任一项所述的重传方法。
  20. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质包括计算机程序或指令，当所述计算机程序或指令在计算机上运行时，使得所述计算机执行如权利要求1-9中任一项所述的重传方法。
  21. 一种计算机程序产品，其特征在于，所述计算机程序产品包括：计算机程序或指令，当所述计算机程序或指令在计算机上运行时，使得所述计算机执行如权利要求1-9中任一项所述的重传方法。
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