WO2022001519A1 - Dispositif à semi-conducteur et son procédé de fabrication - Google Patents

Dispositif à semi-conducteur et son procédé de fabrication Download PDF

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Publication number
WO2022001519A1
WO2022001519A1 PCT/CN2021/096329 CN2021096329W WO2022001519A1 WO 2022001519 A1 WO2022001519 A1 WO 2022001519A1 CN 2021096329 W CN2021096329 W CN 2021096329W WO 2022001519 A1 WO2022001519 A1 WO 2022001519A1
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WIPO (PCT)
Prior art keywords
layer
modified
thickness
insulating
layers
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PCT/CN2021/096329
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English (en)
Chinese (zh)
Inventor
缪海生
张建栋
冯冰
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无锡华润上华科技有限公司
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Publication of WO2022001519A1 publication Critical patent/WO2022001519A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N97/00—Electric solid-state thin-film or thick-film devices, not otherwise provided for

Definitions

  • the present invention relates to the technical field of semiconductors, and in particular, to a semiconductor device and a manufacturing method thereof.
  • MIM metal/insulator/metal
  • MIM capacitors The manufacturing process of MIM capacitors is generally to deposit a metal layer on the silicon round substrate as the lower plate, then grow a dielectric film as the insulating layer, and then deposit a metal layer as the upper plate, and finally lithography and engraving Etching defines MIM capacitors, whose dielectric layer generally uses silicon nitride (SIN) as an intermediate insulating layer.
  • SIN silicon nitride
  • the electrical properties of MIM capacitors mainly relate to leakage and breakdown voltage (BV).
  • a method for fabricating a semiconductor device which includes:
  • the dielectric layer includes an insulating layer and a modified layer arranged in layers, the modified layer is located between the adjacent insulating layers, and the thickness of the insulating layer is greater than that of the modified layer.
  • Another aspect of the present invention provides a semiconductor device comprising:
  • a dielectric layer is formed on the underlying metal layer, the dielectric layer includes an insulating layer and a modified layer arranged in layers, the modified layer is located between the adjacent insulating layers, and the insulating layer is The thickness is greater than the thickness of the modified layer;
  • the present invention further provides a semiconductor device, including a MIM capacitor, wherein a dielectric layer of the MIM capacitor includes a stacked insulating layer and a modified layer, the modified layer is located between the adjacent insulating layers, and the The thickness of the insulating layer is greater than the thickness of the modified layer.
  • the present invention also provides an electronic device, which includes a MIM capacitor and an electronic component connected to the MIM capacitor.
  • the dielectric layer of the MIM capacitor includes a stacked insulating layer and a modified layer, and the modified layer is located adjacent to the MIM capacitor. between the insulating layers, and the thickness of the insulating layer is greater than the thickness of the modified layer.
  • FIG. 1 shows a schematic flow chart of a current method for manufacturing an MIM capacitor
  • FIG. 2 shows a schematic flowchart of a method for manufacturing a MIM capacitor according to an embodiment of the present invention
  • FIG. 3A to FIG. 3H are schematic structural diagrams of devices obtained by sequentially performing various steps in a method for manufacturing an MIM capacitor according to an embodiment of the present invention
  • FIG. 4 is a schematic structural diagram of a MIM capacitor according to an embodiment of the present invention.
  • Spatial relational terms such as “under”, “below”, “below”, “under”, “above”, “above”, etc., may be used herein for convenience of description This describes the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, then elements or features described as “below” or “beneath” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
  • the current high-K materials mainly include HfO 2 /ZrO 2 and the combination of HfO 2 /ZrO 2 and so on.
  • both of the above two methods have certain disadvantages or problems.
  • For the first method since it increases the electrical performance by increasing the area of the upper plate of the MIM capacitor and the thickness of the dielectric layer, increasing the area of the upper plate of the MIM capacitor will inevitably reduce the competitiveness of the chip (the increase of the chip area, cost increase), and at the same time increasing the thickness of the dielectric layer also increases the cost and efficiency of the process; for the second method, since high-K materials are used, and Hf/Zr is a ferroelectric material, how to solve the high-K MIM capacitance stability Sex is the focus and difficulty of current research.
  • MIM capacitors have the characteristics of parallel plate capacitance.
  • the capacitance value of the MIM capacitor can be increased, but the leakage current of the MIM capacitor may increase, and the BV (breakdown voltage) will become smaller; when the dielectric thickness d is increased, the capacitance of the MIM capacitor will be reduced. value, but the electrical performance of the MIM capacitor will be improved (leakage decreases, BV increases).
  • the purpose of the present invention is to improve its electrical performance (reduce leakage and increase BV) under the condition that the thickness d of the dielectric layer remains unchanged (reach a constant capacitance value), and can work stably at a higher voltage for a long time.
  • the current manufacturing method of the MIM capacitor includes: step 101, forming a bottom metal layer on the substrate, the bottom metal layer is, for example, a three-layer structure, including Ti/TiN, AlCu and TiTiN; step 102, on the bottom layer A dielectric layer is formed on the metal layer, for example, silicon nitride (SiN) is used for the dielectric layer; step 103, a top metal layer, such as TiN, is formed on the dielectric layer; step 104, a patterned photoresist layer is formed on the top metal layer, The MIM capacitor region is defined; in step 105, the top metal layer is etched using the patterned photoresist layer as a mask, and the top metal layer outside the MIM capacitor region is removed.
  • step 101 forming a bottom metal layer on the substrate, the bottom metal layer is, for example, a three-layer structure, including Ti/TiN, AlCu and TiTiN
  • step 102 on the bottom layer
  • a dielectric layer is formed on the metal
  • the present invention improves its electrical performance (reduces leakage and increases BV) under the condition that the thickness of the MIM capacitor dielectric layer remains unchanged (reaches a constant capacitance value), and can work stably at a higher voltage for a long time.
  • FIG. 2 shows a schematic flow chart of a method for fabricating a MIM capacitor according to an embodiment of the present invention
  • FIGS. 3A to 3H illustrate the structure of a device obtained by sequentially implementing each step of the method for fabricating an MIM capacitor according to an embodiment of the present invention Schematic. The manufacturing method of the MIM capacitor according to the embodiment of the present invention will be described in detail below with reference to FIG. 2 and FIGS. 3A to 3H .
  • the manufacturing method of the MIM capacitor of this embodiment includes:
  • step 201 as shown in FIG. 3A , a semiconductor substrate 300 is provided, and an underlying metal layer 301 is formed on the semiconductor substrate 300 .
  • the semiconductor substrate 300 can be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III/V compound semiconductors, and also includes many of these semiconductors. Layer structure, etc., or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator
  • SOI silicon-on-insulator
  • SSOI silicon-on-insulator
  • SiGeOI silicon-germanium-on-insulator
  • the semiconductor substrate 300 may also have conductive members formed therein, and the conductive members may be gates, sources or drains of transistors, and may also be metal interconnect structures electrically connected to the transistors, and so on.
  • an isolation structure such as STI (Shallow Trench Isolation Structure) may also be formed on the semiconductor substrate 300 .
  • the constituent material of the semiconductor substrate 300 is single crystal silicon.
  • the bottom metal layer 301 may include one or more metal layers, which may be made of common metal layer materials, and the selection of the metal material is based on the design requirements of the MIM capacitor.
  • the underlying metal layer 301 has a three-layer structure, the first metal layer is Ti or TiN, the second metal layer is aluminum copper alloy (AlCu), wherein the copper content is less, and the third layer is The metal layer adopts Ti or TiN.
  • the underlying metal layer 301 may be formed by various suitable processes, such as PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition), or ALD (Atomic Layer Deposition), wherein the first metal layer serves as an adhesion layer, and the second metal layer serves as an adhesion layer.
  • the first metal layer serves as the main body of the bottom metal layer, and the third metal layer serves as the anti-reflection layer.
  • the thickness of the underlying metal layer 301 is It should be understood that in other embodiments, the underlying metal layer 301 may adopt other suitable materials, structures and thicknesses, and this embodiment is only an example.
  • a dielectric layer 302 will be formed on the underlying metal layer 301.
  • the dielectric layer 302 is a stacked structure. The following describes the formation of the dielectric layer 302 with reference to FIG. 2 and FIGS. 3B to 3E. process is described.
  • Step 202 as shown in FIG. 3B , an insulating layer 3020 is formed on the underlying metal layer 301 .
  • the insulating layer 3020 is made of a material suitable for the MIM capacitor medium, for example, in this embodiment, the insulating layer 3020 is made of silicon nitride.
  • the insulating layer 3020 may be formed by various suitable processes such as PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition), or ALD (Atomic Layer Deposition).
  • the thickness of the insulating layer 3020 depends on the total thickness of the dielectric layer 302, the number of layers of the insulating layer 3020, and the thickness and number of the modified layers, which will be described later.
  • Step 203 as shown in FIG. 3C , a modified layer 3021 is formed on the insulating layer 3020 .
  • the modified layer 3021 adopts a material that can interact with the insulating layer 3020 to increase the electrical properties of the insulating layer 3020 .
  • the insulating layer 3020 is made of silicon nitride
  • the modified layer 3021 is made of amorphous silicon.
  • the modified layer 3021 may be formed by plasma treatment of a silicon-containing gas.
  • SiH 4 can be replaced with other suitable silicon sources, and He can also be replaced with other inert gases.
  • step 204 as shown in FIG. 3D, steps 202 to 203 are repeated to form the insulating layer 3020 and the modification layer 3021 in a stacked arrangement.
  • steps 202 to 203 are performed according to the specific structural design of the dielectric layer, which may be performed only once, or may be performed twice or more.
  • Step 205 as shown in FIG. 3E , an insulating layer 3020 is formed on the uppermost modified layer 3021 .
  • the dielectric layer 302 includes an insulating layer 3020 and a modified layer 3021 arranged in layers, and the modified layer 3021 is located between the adjacent insulating layers 3020 , in other words, the same as the previous Compared with a single dielectric layer, in this embodiment, the dielectric layer 302 is equivalent to inserting multiple thin modified layers 3021 into the insulating layer 3020 to transform it into a laminated structure of the insulating layer 3020 and the modified layer 3021 , and the electrical properties of the insulating layer 3020 are increased through the interaction between the modified layer 3021 and the insulating layer 3020 .
  • the insulating layer 3020 is silicon nitride
  • the modification layer 3021 is an amorphous silicon layer. Inserting an amorphous silicon layer into the silicon nitride layer can achieve the following functions: 1) Amorphous silicon has more dangling bonds, which makes it have excellent performance of trapping charges, thereby improving the leakage and breakdown voltage performance of MIM capacitors; 2) The existence of amorphous silicon will not affect the adhesion between its upper and lower dielectrics. At the same time, amorphous silicon breaks the formation of the original SI-N bond of SiN and acts as a barrier for the passage of charges, thereby improving the MIM capacitance. 3) The thin amorphous silicon in the SiNSiSiNSi ⁇ SiN structure has little effect on the dielectric constant of its dielectric layer, so a constant capacitance value ( Same capacitance value as SiN MIM capacitors of the same thickness).
  • the thickness of the insulating layer 3020 is greater than the thickness of the modified layer 3021, and the thickness of the modified layer 3021 is smaller, for example, less than or equal to
  • the thickness of each insulating layer 3020 (the total thickness d of the dielectric layer 302 ⁇ the total thickness of the modified layer 3021)/the number of insulating layers 3020, so that the total thickness d of the dielectric layer 302 remains unchanged
  • the total thickness of the modified layer 3021 is equal to the thickness of the modified layer*the number of layers of the modified layer.
  • the stacking result of silicon nitride and amorphous silicon is used as the dielectric layer, in other embodiments, other suitable materials can also be used, not limited to silicon nitride and amorphous silicon The combination.
  • Step 206 as shown in FIG. 3F , a top metal layer 303 is formed on the dielectric layer 302 .
  • the top metal layer 303 can be made of various suitable upper plate materials.
  • the top metal layer 303 is Ti or TiN, which can be processed by various suitable processes, such as PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Deposition), etc. form.
  • PVD Physical Vapor Deposition
  • CVD Chemical Vapor Deposition
  • ALD Atomic Layer Deposition
  • the thickness of the top metal layer 303 is
  • a patterned photoresist layer 304 is formed on the top metal layer 303 to define the MIM capacitor.
  • the photoresist layer 304 can be made of commonly used positive or negative photoresist materials, and is patterned through operations such as exposure and development, so as to define the regions of the MIM capacitors, that is, in which regions the MIM capacitors are formed.
  • the area shielded by the photoresist layer 304 is the area where the MIM capacitor is formed.
  • Step 208 as shown in FIG. 3H, etching the top metal layer 303 by using the patterned photoresist layer 304 as a mask to form the upper plate 305 of the MIM capacitor.
  • the top metal layer 303 is etched through a suitable dry etching process or wet etching process to remove the top metal layer outside the MIM capacitor region, and the top metal layer in the MIM capacitor region is retained as the upper plate 305.
  • the shape and area of the top plate 305 are defined to define the plate area of the MIM capacitor (the plate area of the MIM capacitor depends on the top plate area).
  • the wet etching process includes wet etching processes such as hydrofluoric acid, phosphoric acid, hydrogen peroxide, etc.
  • the dry etching process includes but is not limited to: reactive ion etching (RIE), ion beam etching, plasma etching or laser etching cut.
  • a dry etching process is used to perform the etching, and as an example, in this embodiment, the etching is dry etching, and the process parameters of the dry etching include: an etching gas Including Cl 2 and other gases, the flow rate is 50sccm ⁇ 500sccm, 10sccm ⁇ 100sccm, and the pressure is 2mTorr ⁇ 50mTorr, where sccm represents cubic centimeters per minute, mTorr represents micrometer mercury column.
  • an etching gas Including Cl 2 and other gases the flow rate is 50sccm ⁇ 500sccm, 10sccm ⁇ 100sccm
  • the pressure is 2mTorr ⁇ 50mTorr, where sccm represents cubic centimeters per minute, mTorr represents micrometer mercury column.
  • the process steps implemented by the method according to the embodiment of the present invention are completed. It can be understood that the method for fabricating a semiconductor device in this embodiment not only includes the above steps, but may also include other required steps before, during or after the above steps. For example, after step 208, etching steps such as interconnect layers may also be included, and in these steps, the dielectric layer 302 and the underlying metal layer 301 will be etched at the same time.
  • the dielectric layer is formed into a laminated structure of the insulating layer and the modified layer, that is, at least one thin modified layer is inserted into the insulating layer, and by modifying the The function of the dielectric layer is used to increase the electrical properties of the dielectric layer, so that the electrical properties of the MIM capacitor can be improved under the condition of keeping the thickness of the dielectric layer unchanged, so that it can work stably at a higher voltage for a long time.
  • FIG. 4 Another aspect of the present invention further provides a semiconductor device, as shown in FIG. 4 , comprising: an underlying metal layer 401 formed on the semiconductor substrate 400; a dielectric layer 402 formed on the underlying metal layer 401,
  • the dielectric layer 402 includes a stacked insulating layer 4020 and a modified layer 4021, the modified layer 4021 is located between the adjacent insulating layers 4020, and the thickness of the insulating layer 4020 is greater than that of the modified layer The thickness of 4021; the top metal layer 403, which is formed on the dielectric layer 402.
  • the insulating layer 4020 includes a silicon nitride layer
  • the modified layer 4021 includes an amorphous silicon layer
  • the thickness of the amorphous silicon layer is less than or equal to
  • the dielectric layer of the MIM capacitor includes a laminated structure of an insulating layer and a modified layer, that is, at least one thin modified layer is inserted into the insulating layer, and the modified layer is used to increase the
  • the electrical properties of the dielectric layer can improve the electrical properties of the MIM capacitor under the condition of keeping the thickness of the dielectric layer unchanged, so that it can work stably at a higher voltage for a long time.
  • the semiconductor device includes: a bottom metal layer, which is formed on a semiconductor substrate; a dielectric layer, which is formed on the bottom metal layer, and the dielectric layer includes a stacked insulating layer and a modified layer, and the modified layer is The insulating layer is located between the adjacent insulating layers, and the thickness of the insulating layer is greater than the thickness of the modified layer; the top metal layer is formed on the dielectric layer.
  • the insulating layer includes a silicon nitride layer
  • the modified layer includes an amorphous silicon layer
  • the thickness of the amorphous silicon layer is less than or equal to
  • the electronic component can be any electronic component such as a discrete device, an integrated circuit, or the like.
  • the electronic device can improve the electrical performance of the MIM capacitor under the condition that the thickness of the dielectric layer is kept constant due to the semiconductor device included, so that it can work stably at a higher voltage for a long time. Therefore, the electronic device also has similar advantages.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Dispositif à semi-conducteur et son procédé de fabrication. Le procédé de fabrication de dispositif à semi-conducteur consiste à : fournir un substrat semi-conducteur (300), et former une couche métallique sous-jacente (301) sur le substrat semi-conducteur (300) ; former une couche diélectrique (302) sur la couche métallique sous-jacente (301) ; former une couche métallique supérieure (303) sur la couche diélectrique (302) ; et former des motifs sur la couche métallique supérieure (303) pour retirer la couche métallique supérieure (303) non dans une région de condensateur, de manière à former une plaque polaire supérieure (305). La couche diélectrique (302) comprend des couches d'isolation (3020) et des couches de modification (3021) empilées, une couche de modification (3021) étant située entre des couches d'isolation (3020) adjacentes, et les couches d'isolation (3020) étant plus épaisses que les couches de modification (3021).
PCT/CN2021/096329 2020-07-02 2021-05-27 Dispositif à semi-conducteur et son procédé de fabrication WO2022001519A1 (fr)

Applications Claiming Priority (2)

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CN202010634353.2 2020-07-02
CN202010634353.2A CN113889572A (zh) 2020-07-02 2020-07-02 半导体器件及其制作方法

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6341056B1 (en) * 2000-05-17 2002-01-22 Lsi Logic Corporation Capacitor with multiple-component dielectric and method of fabricating same
CN101783286A (zh) * 2009-01-20 2010-07-21 中芯国际集成电路制造(上海)有限公司 结构为金属-绝缘体-金属的电容器制造方法
CN103247698A (zh) * 2012-02-06 2013-08-14 台湾积体电路制造股份有限公司 电容器结构及其形成方法
CN104465608A (zh) * 2013-09-23 2015-03-25 中芯国际集成电路制造(上海)有限公司 Mim电容器及其制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6341056B1 (en) * 2000-05-17 2002-01-22 Lsi Logic Corporation Capacitor with multiple-component dielectric and method of fabricating same
CN101783286A (zh) * 2009-01-20 2010-07-21 中芯国际集成电路制造(上海)有限公司 结构为金属-绝缘体-金属的电容器制造方法
CN103247698A (zh) * 2012-02-06 2013-08-14 台湾积体电路制造股份有限公司 电容器结构及其形成方法
CN104465608A (zh) * 2013-09-23 2015-03-25 中芯国际集成电路制造(上海)有限公司 Mim电容器及其制造方法

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