WO2022001007A1 - 芯片测试模组 - Google Patents

芯片测试模组 Download PDF

Info

Publication number
WO2022001007A1
WO2022001007A1 PCT/CN2020/134978 CN2020134978W WO2022001007A1 WO 2022001007 A1 WO2022001007 A1 WO 2022001007A1 CN 2020134978 W CN2020134978 W CN 2020134978W WO 2022001007 A1 WO2022001007 A1 WO 2022001007A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
carrier board
test
tested
inner carrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2020/134978
Other languages
English (en)
French (fr)
Inventor
吴佳瑜
巨涛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SZ DJI Technology Co Ltd
Original Assignee
SZ DJI Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SZ DJI Technology Co Ltd filed Critical SZ DJI Technology Co Ltd
Publication of WO2022001007A1 publication Critical patent/WO2022001007A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/04—Housings; Supporting members; Arrangements of terminals
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer

Definitions

  • the present application relates to the technical field of chip testing, and in particular, to a chip testing module.
  • the chip to be tested is usually installed in the chip test module, the test chip is mounted on the surface of the test carrier, and is connected to the chip to be tested through wiring, and the test carrier is connected to the packaged chip to be tested and the test carrier.
  • Automated testing machine detects whether the function and performance of the chip to be tested are normal through the test carrier board, and rejects the chips that do not meet the requirements.
  • more and more signal integrity problems are encountered by the test carrier during chip testing, such as reflection, loss and crosstalk, which can no longer meet the needs of chip testing.
  • the present application provides a chip testing module.
  • the chip test module includes: a mounting seat for mounting a chip to be tested; and an inner carrier board assembly assembled with the mounting seat, the inner carrier board assembly including an inner carrier board, a first pin carrier board, a first pin carrier board, a second A two-pin carrier board, the inner carrier board is installed between the first pin carrier board and the second pin carrier board, and the first pin carrier board is provided with an electrical connection with the chip to be tested and the inner carrier board.
  • a first conductive element connected, the second pin carrier board is provided with a second conductive element electrically connected to the inner carrier board and a communication interface electrically connected to the second conductive element, the inner carrier board is used for A test chip is installed, wherein the test chip is electrically connected to the chip to be tested through the inner carrier board and the first conductive element, for testing the chip to be tested, and to the test chip through the communication interface Test result output.
  • the mounting base includes a base body and a cover body fitted with the base body, the chip to be tested is arranged between the base body and the cover body, and the base body is provided with the first A channel through which a conductive element passes.
  • the cover body is rotatably mounted on the base body.
  • the mounting base further includes a knob and a pressing block matched with the knob. By rotating the knob, the pressing block can press the chip to be tested.
  • the base body, the first needle carrier and the second needle carrier are fixedly connected.
  • the chip test module further includes a test carrier, and the base, the first pin carrier, the second pin carrier and the test carrier are fixedly connected by fasteners.
  • the inner carrier plate is mounted on the second needle carrier plate, and the second needle carrier plate is provided with a limiting column for defining the inner carrier plate.
  • the first conductive element includes one of the following conductive elements: a metal probe and a copper post;
  • the second conductive element includes one of the following conductive elements: a metal probe and a copper post.
  • the inner carrier board is made by using an HDI process or a substrate process.
  • the chip to be tested includes: SoC, CPU and FPGA.
  • an inner carrier board for installing the test chip is arranged between the first pin carrier board and the second pin carrier board, so that the distance between the test chip and the chip to be tested is close, and the test chip can be effectively
  • the problem of signal loss and crosstalk is reduced, and the thickness of the inner carrier board is small, so that the distance between the test chips arranged on the upper and lower surfaces of the inner carrier board is short, and the influence of signal reflection can be reduced.
  • FIG. 1 is an exploded schematic view of the chip test module of the present application.
  • FIG. 2 is an assembly diagram of the chip test module shown in FIG. 1 .
  • FIG. 3 is an assembly view of the chip test module shown in FIG. 1 , wherein the cover is in an open state.
  • an embodiment of the present application provides a chip test module 100 , which is used for FT (Final Test, final test) mass production testing of the chip to be tested, so as to detect whether the function and performance of the chip to be tested are normal, and Eliminate the chips to be tested whose indicators do not meet the requirements.
  • FT Fluor Test, final test
  • the chips to be tested include digital chips with high-speed memory interfaces, such as: SoC (System on Chip, system on chip), CPU (Center Process Unit, central processing unit), FPGA (Field Programmable Gate Array, field programmable gate array), etc. chip, but not limited to this.
  • SoC System on Chip, system on chip
  • CPU Center Process Unit, central processing unit
  • FPGA Field Programmable Gate Array, field programmable gate array
  • the chip test module 100 includes a mounting base 10 and an inner carrier board assembly.
  • the mounting seat 10 is used for mounting the chip to be tested.
  • the inner carrier board assembly is assembled with the mounting seat 10 , and specifically, the inner carrier board assembly is mounted under the mounting seat 10 .
  • the inner carrier board assembly includes an inner carrier board 21 , a first needle carrier board 22 and a second pin carrier board 23 .
  • the inner carrier board 21 is mounted between the first pin carrier board 22 and the second pin carrier board 23 .
  • the first pin carrier 22 is provided with a first conductive element 221 electrically connected to the chip to be tested and the inner carrier
  • the second pin carrier 23 is provided with the inner carrier 21
  • a second conductive element (not shown) electrically connected and a communication interface electrically connected with the second conductive element
  • the inner carrier board 21 is used for mounting the test chip 24 .
  • the test chip 24 is electrically connected to the chip to be tested through the inner carrier board 21 and the first conductive element 221 for testing the chip to be tested, and to test the chip to be tested through the communication interface result output.
  • the test chip 24 is a memory chip.
  • the signal for completing the wiring on the inner carrier board 21 is a memory high-speed interface signal.
  • the test chip 24 may also be other chips that are difficult to achieve high-speed operation due to signal integrity reasons.
  • an inner carrier board 21 for mounting the test chip 24 is arranged between the first pin carrier board 22 and the second pin carrier board 23 , so that the distance between the test chip 24 and the chip to be tested is relatively close , can effectively reduce signal loss and crosstalk problems, and the thickness of the inner carrier board 21 is small, so that the distance between the test chips 24 arranged on the upper and lower surfaces of the inner carrier board 21 is short, which can reduce the influence of signal reflection, so, The signal integrity problem between the test chip 24 and the chip to be tested is solved; in addition, for the test requirements of different types of test chips, different inner carrier boards 21 can be replaced, thereby reducing costs, and the inner carrier board 21 can be Upgraded with the advancement of printed circuit board technology.
  • the mounting base 10 includes a base body 11 and a cover body 12 fitted with the base body, the chip to be tested is disposed between the base body 11 and the cover body 12 , and the base body 12
  • the body 11 is provided with passages through which the first conductive elements 221 pass.
  • the chip to be tested can be defined more conveniently and reliably.
  • the cover body 12 is first opened, then the chip to be tested is placed on the seat body 11 , and then the cover body 12 is closed. In this way, the chip to be tested can be placed on the mounting seat 10 .
  • the chip to be tested is disposed on the seat body 11 .
  • the chip to be tested may also be disposed on the cover body 12 .
  • the cover body 12 is rotatably mounted on the base body 11 . In this way, by rotating the cover body 12, the cover body 12 can be urged to switch between the open state and the closed state.
  • the cover body 12 When it is necessary to set the chip to be tested on the mounting base 10, firstly rotate the cover body 12 so that the cover body 12 is turned to the open state (refer to FIG. 3), then place the chip to be tested on the base body 11, and then reversely rotate the cover body 12 , so that the cover body 12 is switched to the closed state (refer to FIG. 2 ). At this time, the chip to be tested is confined between the base body 11 and the cover body 12 .
  • the cover body 12 and the base body 11 can be fixedly fixed by means of a snap or the like.
  • the cover body 12 can also be detachably mounted on the base body 11 .
  • the cover body 12 is first disassembled, and then the The measuring chip is arranged on the base body 11 , and then the cover body 12 is installed on the base body 11 .
  • the above are just some examples and are not limited to the above examples.
  • the mounting base 10 further includes a knob 13 and a pressing block 14 matched with the knob 13 .
  • the pressing block 14 can be pressed against the chip to be tested. In this way, by adjusting the knob 13 , the pressing block 14 presses the chip under test, so that the chip under test and the first conductive element 221 maintain a stable and good electrical connection.
  • the knob 13 and the pressing block 14 are connected by screws, and the pressing block 14 cooperates with the cover body 12 to limit the position. In this way, when the knob 13 is rotated, the pressing block can be urged. 14 moves in the up and down direction, and presses the chip to be tested by the pressing block 14 .
  • the mounting seat 10 includes an elastic element that presses against the chip to be tested, the elastic element is disposed between the cover 12 and the chip to be tested, and is pressed by the elastic element on the chip under test, so as to press the chip under test tightly, so that the chip under test and the first conductive element 221 maintain a stable and good electrical connection.
  • the elastic element that presses against the chip to be tested
  • the elastic element is disposed between the cover 12 and the chip to be tested, and is pressed by the elastic element on the chip under test, so as to press the chip under test tightly, so that the chip under test and the first conductive element 221 maintain a stable and good electrical connection.
  • the base body 11 , the first needle carrier plate 22 and the second needle carrier plate 23 are fixedly connected. That is, the mounting base 10 and the inner carrier board assembly are fixed together. In other embodiments, the mounting base 10 and the inner carrier board assembly can also be detachably mounted together.
  • the chip test module 100 further includes a test carrier, which is a circuit board for connecting the packaged chip to be tested and an automated testing machine.
  • the base body 11 , the first needle carrier 22 , the second needle carrier 23 and the test carrier are fixedly connected by fasteners. In this way, the fixing method is convenient and reliable.
  • the fasteners are bolts, and the bolts pass through the base body 11 , the first needle carrier plate 22 , the second needle carrier plate 23 and the test carrier plate in sequence and then cooperate with nuts to be fixed.
  • the socket body 11 , the first needle carrier board 22 , the second needle carrier board 23 and the test carrier board are respectively square, and the socket body 11 , the first needle carrier board 22 , the second needle carrier board 23 and the test carrier board are respectively square.
  • Four corners of the carrier plate are respectively provided with through holes for bolts to pass through.
  • the base body 11 , the first needle carrier board 22 , the second needle carrier board 23 and the test carrier board can also be fixed together by means of snaps, gluing, or the like.
  • the inner carrier plate 21 is mounted on the second needle carrier plate 23 , and the second needle carrier plate 23 is provided with a limiting column 231 for defining the inner carrier plate 21 .
  • the limiting post 231 may be made of nylon or other materials. In this way, by arranging the limiting posts 231 on the second needle carrier 23, the inner carrier 21 can be conveniently and reliably limited, and the inner carrier 21 can be easily replaced according to testing needs.
  • the limit posts 231 are arranged in two rows, the inner carrier plate 21 is defined between the two rows of limit posts 231 , and each row of the limit posts 231 is set to two or more.
  • the first conductive element 221 includes one of the following conductive elements: a metal probe and a copper post; the second conductive element includes one of the following conductive elements: a metal probe and a copper post.
  • the first conductive element 221 is a metal probe, and the second conductive element is a metal probe.
  • the first conductive element 221 is a copper pillar, and the second conductive element is a copper pillar.
  • the inner carrier board 21 adopts an HDI (High Density Interconnection, high density interconnection) process. Since the inner carrier board 21 adopts the HDI process, it has the following advantages: 1. The inner carrier board 21 is thin, the distance between the test chips 24 arranged on the upper and lower surfaces of the inner carrier board 21 is short, and the influence of signal reflection is small; 2. The inner carrier board 21 adopts the blind buried hole process, the via holes do not generate stubs, and the amount of signal reflection is small; 3. The test chip 24 is placed close to the chip to be tested, which can solve the problem of signal loss and crosstalk 4.
  • HDI High Density Interconnection, high density interconnection
  • different inner carrier boards 21 can be replaced without the need to replace the test carrier board, so that the cost can be reduced, and the inner carrier board 21 can be upgraded with the progress of the printed circuit board technology. . It can be seen that, because the inner carrier board 21 adopts the HDI process, it has good signal integrity, solves the problem of yield loss caused by the signal integrity problem, and saves costs.
  • the inner carrier board 21 may also be fabricated by a packaging substrate process, but is not limited thereto.
  • the chip to be tested is tested by the chip test module 100 of the present application, the chip to be tested is electrically connected to the inner carrier board 21 through the first conductive element 221 of the first pin carrier board 22, so that the chip to be tested and the test chip 24 are electrically connected.
  • the high-speed signal is transmitted between the test chip and the test chip 24, and the test chip 24 will judge whether the signal transmission is normal; then the test chip 24 will pass the judgment result through the inner carrier board 21, the second conductive element on the second needle carrier board 23 and the communication
  • the interface is transmitted to the test carrier board 30 through a low-speed signal, and the test carrier board 30 then transmits the above judgment result to the automatic testing machine (not shown in the figure), and the automatic testing machine can determine whether the function and performance of the chip to be tested are normal according to the received information. , so that the chips to be tested that do not meet the requirements can be eliminated.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

一种芯片测试模组（100），包括：安装座（10），用于安装待测芯片；及内载板组件，与安装座（10）装配在一起，内载板组件包括内载板（21）、第一针载板（22）、第二针载板（23），内载板（21）安装于第一针载板（22）和第二针载板（23）之间，第一针载板（22）设有与待测芯片和内载板（21）电连接的第一导电元件（221），第二针载板（23）设有与内载板（21）电连接的第二导电元件和通信接口，内载板（21）用于安装测试芯片（24），测试芯片（24）通过内载板（21）、第一导电元件（221）与待测芯片电连接，用于对待测芯片进行测试，并通过通信接口将测试结果输出。芯片测试模组（100）解决了测试芯片（24）和待测芯片之间的信号完整性问题。

Description

芯片测试模组 技术领域
本申请涉及芯片测试技术领域，尤其涉及一种芯片测试模组。
背景技术
当芯片制造完成之后，必须将芯片进行测试，以确保芯片功能的正确性。在传统芯片测试方法中，通常将待测芯片安装于芯片测试模组内，测试芯片贴装于测试载板表面，通过走线与待测芯片相连，测试载板连接封装完的待测芯片和自动化测试机。自动化测试机通过测试载板检测待测芯片功能、性能是否正常，并剔除指标不符合要求的芯片。然而，随着待测芯片的速率日益提升，在芯片测试时测试载板遇到的信号完整性问题越来越多，例如：反射、损耗和串扰，已无法满足芯片测试需要。
发明内容
本申请提供一种芯片测试模组。该芯片测试模组包括：安装座，用于安装待测芯片；及内载板组件，与所述安装座装配在一起，所述内载板组件包括内载板、第一针载板、第二针载板，所述内载板安装于所述第一针载板和第二针载板之间，所述第一针载板设有与所述待测芯片和所述内载板电连接的第一导电元件，所述第二针载板设有与所述内载板电连接的第二导电元件以及与所述第二导电元件电连接的通信接口，所述内载板用于安装测试芯片，其中，所述测试芯片通过所述内载板以及所述第一导电元件与所述待测芯片电连接，用于对所述待测芯片进行测试，并通过所述通信接口将测试结果输出。
可选地，所述安装座包括座体和与所述座体配合安装的盖体，所述待测芯片设置于所述座体和盖体之间，所述座体设有供所述第一导电元件通过的通道。
可选地，所述盖体以可转动的方式安装于所述座体。
可选地，所述安装座还包括旋钮和与所述旋钮配合的压块，通过转动所述旋钮，能够使得所述压块压紧所述待测芯片。
可选地，所述座体、第一针载板和第二针载板固定连接。
可选地，所述芯片测试模组还包括测试载板，所述座体、第一针载板、第二针载 板和测试载板通过紧固件固定连接。
可选地，所述内载板安装于所述第二针载板，所述第二针载板设有用于限定所述内载板的限位柱。
可选地，所述第一导电元件包括下列导电元件其中之一：金属探针、铜柱；所述第二导电元件包括下列导电元件其中之一：金属探针、铜柱。
可选地，所述内载板采用HDI工艺或者基板工艺制成。
可选地，所述待测芯片包括：SoC、CPU和FPGA。
本申请提供的芯片测试模组，在第一针载板和第二针载板之间设置用于安装测试芯片的内载板，使得测试芯片和待测芯片之间距离较近，能够有效地减少信号的损耗和串扰问题，并且内载板厚度小，使得设置于内载板上下两个表面的测试芯片的距离短，能够减少信号反射带来的影响，如此，解决了现有技术中测试芯片和待测芯片之间的信号完整性问题；另外，对于不同型号测试芯片的测试需求，可以更换不同的内载板，从而能够降低成本，并且内载板能够随着印刷电路板工艺的进步而升级。
附图说明
图1是本申请芯片测试模组的分解示意图。
图2是图1所示的芯片测试模组的组装图。
图3是图1所示的芯片测试模组的组装图，其中盖体处于打开状态。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本申请相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置和方法的例子。
在本申请使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本申请。在本申请和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
下面结合附图，对本申请的芯片测试模组进行详细说明。在不冲突的情况下，下述的实施例及实施方式中的特征可以相互组合。
请参阅图1至图3，本申请实施例提供一种芯片测试模组100，用于对待测芯片FT(Final Test，最终测试)量产测试，以检测待测芯片功能、性能是否正常，并剔除指标不符合要求的待测芯片。
待测芯片包括带有高速内存接口的数字芯片，例如：SoC(System on Chip，片上系统)、CPU(Center Process Unit，中央处理器)、FPGA(Field Programmable Gate Array，现场可编程门阵列)等芯片，但不限于此。
芯片测试模组100包括安装座10和内载板组件。所述安装座10用于安装待测芯片。所述内载板组件与所述安装座10装配在一起，具体地，所述内载板组件安装于所述安装座10下方。
所述内载板组件包括内载板21、第一针载板22、第二针载板23，所述内载板21安装于所述第一针载板22和第二针载板23之间，所述第一针载板22设有与所述待测芯片和所述内载板电连接的第一导电元件221，所述第二针载板23设有与所述内载板21电连接的第二导电元件(图未示)以及与所述第二导电元件电连接的通信接口，所述内载板21用于安装测试芯片24。其中，所述测试芯片24通过所述内载板21以及所述第一导电元件221与所述待测芯片电连接，用于对所述待测芯片进行测试，并通过所述通信接口将测试结果输出。
在一个实施例中，所述测试芯片24为内存芯片，相应的，所述内载板21上完成布线的信号为内存高速接口信号。在另一个实施例中，所述测试芯片24也可以为其他由于信号完整性原因难以实现高速率工作的芯片。
本申请芯片测试模组100，在第一针载板22和第二针载板23之间设置用于安装测试芯片24的内载板21，使得测试芯片24和待测芯片之间距离较近，能够有效地减少信号的损耗和串扰问题，并且内载板21厚度小，使得设置于内载板21上下两个表面的测试芯片24的距离短，能够减少信号反射带来的影响，如此，解决了测试芯片24和待测芯片之间的信号完整性问题；另外，对于不同型号测试芯片的测试需求，可以更换不同的内载板21，从而能够降低成本，并且内载板21能够随着印刷电路板工艺的进步而升级。
在一个实施例中，所述安装座10包括座体11和与所述座体配合安装的盖体12， 所述待测芯片设置于所述座体11和盖体12之间，所述座体11设有供所述第一导电元件221通过的通道。如此，通过座体11和盖体12配合，能够更加方便可靠地对待测芯片进行限定。在使用时，先将所述盖体12打开，然后将待测芯片置于所述座体11，再将所述盖体12合上，如此，即可将待测芯片设置于安装座10。在一个实施例中，所述待测芯片设置于所述座体11。在另一个实施例中，所述待测芯片也可以设置于所述盖体12。
在图示实施例中，所述盖体12以可转动的方式安装于所述座体11。如此，通过转动盖体12，即可促使盖体12在打开状态和闭合状态之间切换。在需要将待测芯片设置于安装座10时，先转动盖体12，使得盖体12转动至打开状态(参图3)，然后将待测芯片置于座体11，然后反向转动盖体12，使得盖体12切换至闭合状态(参图2)，此时待测芯片被限定于座体11和盖体12之间。当盖体12处于闭合状态时，盖体12和座体11可以通过卡扣等方式配合固定。
在其他实施例中，所述盖体12也可以通过可拆卸的方式安装于所述座体11，在需要将待测芯片设置于安装座10时，先将盖体12拆卸下来，再将待测芯片设置于座体11，然后将盖体12安装于座体11。以上只是一些例子，并不限于上述例子。
所述安装座10还包括旋钮13和与所述旋钮13配合的压块14，通过转动所述旋钮13，能够使得所述压块14压紧所述待测芯片。如此，通过调节旋钮13使得压块14压紧待测芯片，进而使得待测芯片与第一导电元件221保持稳定良好的电连接。
在图示实施例中，所述旋钮13和所述压块14之间通过螺纹连接，所述压块14与所述盖体12配合限位，如此，当转动旋钮13时，能够促使压块14沿上下方向移动，通过压块14将待测芯片压紧。
在另一个实施例中，所述安装座10包括抵压于所述待测芯片的弹性元件，所述弹性元件设置于所述盖体12和待测芯片之间，通过所述弹性元件抵压于待测芯片，从而将待测芯片压紧，使得待测芯片与第一导电元件221保持稳定良好的电连接。以上只是一些例子，并不限于上述例子。
在图示实施例中，所述座体11、第一针载板22和第二针载板23固定连接。也就是说，所述安装座10和内载板组件固定在一起。在其他实施例中，所述安装座10和内载板组件也可以可拆卸地安装在一起。
所述芯片测试模组100还包括测试载板，所述测试载板是用于连接封装完的待测 芯片和自动化测试机的电路板。所述座体11、第一针载板22、第二针载板23和测试载板通过紧固件固定连接。如此，固定方式方便可靠。
在图示实施例中，所述紧固件为螺栓，螺栓依次穿过座体11、第一针载板22、第二针载板23和测试载板后与螺母配合固定。在该实施例中，座体11、第一针载板22、第二针载板23和测试载板分别呈方形，且座体11、第一针载板22、第二针载板23和测试载板的四个角处分别设有供螺栓穿过的通孔。在其他实施例中，所述座体11、第一针载板22、第二针载板23和测试载板之间还可以通过卡扣、胶粘等方式固定在一起。
所述内载板21安装于所述第二针载板23，所述第二针载板23设有用于限定所述内载板21的限位柱231。所述限位柱231可以为尼龙材质或者其他材质。如此，通过在第二针载板23设置限位柱231，能够方便、可靠地对内载板21进行限位，并且能够方便地根据检测需要对内载板21进行更换。在图示实施例中，所述限位柱231设为两排，所述内载板21限定于两排限位柱231之间，每排限位柱231设为两个或者两个以上。
所述第一导电元件221包括下列导电元件其中之一：金属探针、铜柱；所述第二导电元件包括下列导电元件其中之一：金属探针、铜柱。在图示实施例中，所述第一导电元件221为金属探针，所述第二导电元件为金属探针。在另一个实施例中，所述第一导电元件221为铜柱，所述第二导电元件为铜柱。以上只是一些例子，并不限于上述例子。
在一个优选实施例中，所述内载板21采用HDI(High Density Interconnection，高密度互联)工艺。由于内载板21采用HDI工艺，具有如下优点：1、内载板21薄，设置于内载板21上、下两个表面的测试芯片24之间距离短，信号反射带来的影响小；2、内载板21采用盲埋孔工艺，过孔不产生Stub(残桩)，信号反射的量较小；3、测试芯片24摆放位置靠近待测芯片，能够解决信号的损耗和串扰问题；4、对于不同型号测试芯片的测试需求，可以更换不同的内载板21，而不需要更换测试载板，从而能够降低成本，并且内载板21能够随着印刷电路板工艺的进步而升级。由此可见，由于内载板21采用HDI工艺，从而具备良好的信号完整性，解决了由信号完整性问题造成的良率损失问题，节省成本。
在其他实施例中，所述内载板21也可以采用封装基板工艺制成，且不限于此。
通过本申请的芯片测试模组100对待测芯片进行测试时，待测芯片通过第一针载板22的第一导电元件221与内载板21形成电连接，从而在待测芯片和测试芯片24之 间传递高速信号，待测芯片会判断与测试芯片24之间的信号传递是否正常；然后测试芯片24将判断结果通过内载板21、第二针载板23上的第二导电元件和通信接口通过低速信号传递给测试载板30，测试载板30再将上述判断结果传递给自动化测试机(图未示)，自动化测试机根据接收到的信息能够确定待测芯片的功能、性能是否正常，从而能够剔除不符合要求的待测芯片。
以上所述仅是本申请的较佳实施例而已，并非对本申请做任何形式上的限制，虽然本申请已以较佳实施例揭露如上，然而并非用以限定本申请，任何熟悉本专业的技术人员，在不脱离本申请技术方案的范围内，当可利用上述揭示的技术内容做出些许更动或修饰为等同变化的等效实施例，但凡是未脱离本申请技术方案的内容，依据本申请的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本申请技术方案的范围内。
本申请文件披露的内容包含受版权保护的材料。该版权为版权所有人所有。版权所有人不反对任何人复制专利与商标局的官方记录和档案中所存在的该申请文件或者该申请披露。

Claims (10)

  1. 一种芯片测试模组，其特征在于，包括：
    安装座(10)，用于安装待测芯片；及
    内载板组件，与所述安装座(10)装配在一起，所述内载板组件包括内载板(21)、第一针载板(22)、第二针载板(23)，所述内载板(21)安装于所述第一针载板(22)和第二针载板(23)之间，所述第一针载板(22)设有与所述待测芯片和所述内载板电连接的第一导电元件(221)，所述第二针载板(23)设有与所述内载板(21)电连接的第二导电元件以及与所述第二导电元件电连接的通信接口，所述内载板(21)用于安装测试芯片(24)，
    其中，所述测试芯片通过所述内载板(21)以及所述第一导电元件(221)与所述待测芯片电连接，用于对所述待测芯片进行测试，并通过所述通信接口将测试结果输出。
  2. 如权利要求1所述的芯片测试模组，其特征在于，所述安装座(10)包括座体(11)和与所述座体配合安装的盖体(12)，所述待测芯片设置于所述座体和盖体之间，所述座体设有供所述第一导电元件通过的通道。
  3. 如权利要求2所述的芯片测试模组，其特征在于，所述盖体以可转动的方式安装于所述座体。
  4. 如权利要求2所述的芯片测试模组，其特征在于，所述安装座还包括旋钮(13)和与所述旋钮(13)配合的压块(14)，通过转动所述旋钮，能够使得所述压块压紧所述待测芯片。
  5. 如权利要求2所述的芯片测试模组，其特征在于，所述座体、第一针载板和第二针载板固定连接。
  6. 如权利要求5所述的芯片测试模组，其特征在于，所述芯片测试模组还包括测试载板，所述座体、第一针载板、第二针载板和测试载板通过紧固件固定连接。
  7. 如权利要求1所述的芯片测试模组，其特征在于，所述内载板(21)安装于所述第二针载板(23)，所述第二针载板设有用于限定所述内载板的限位柱(231)。
  8. 如权利要求1所述的芯片测试模组，其特征在于，所述第一导电元件包括下列导电元件其中之一：金属探针、铜柱；所述第二导电元件包括下列导电元件其中之一：金属探针、铜柱。
  9. 如权利要求1所述的芯片测试模组，其特征在于，所述内载板采用HDI工艺或者基板工艺制成。
  10. 如权利要求1所述的芯片测试模组，其特征在于，所述待测芯片包括：SoC、CPU和FPGA。
PCT/CN2020/134978 2020-06-28 2020-12-09 芯片测试模组 Ceased WO2022001007A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202021223303.7U CN212781099U (zh) 2020-06-28 2020-06-28 芯片测试模组
CN202021223303.7 2020-06-28

Publications (1)

Publication Number Publication Date
WO2022001007A1 true WO2022001007A1 (zh) 2022-01-06

Family

ID=75087000

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/134978 Ceased WO2022001007A1 (zh) 2020-06-28 2020-12-09 芯片测试模组

Country Status (2)

Country Link
CN (1) CN212781099U (zh)
WO (1) WO2022001007A1 (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115267501A (zh) * 2022-07-29 2022-11-01 河北新华北集成电路有限公司 一种功率芯片测试装置
CN116298776A (zh) * 2023-02-03 2023-06-23 上海华岭集成电路技术股份有限公司 一种带光源的ate cis测试夹具及其测试方法
CN117054859A (zh) * 2023-10-11 2023-11-14 苏州朗之睿电子科技有限公司 一种芯片加热测试装置及其测试方法
CN119805171A (zh) * 2025-03-12 2025-04-11 深圳市昂科技术有限公司 一种便于取放的芯片测试设备
CN120314756A (zh) * 2025-04-29 2025-07-15 燕麦(杭州)智能制造有限公司 一种柔性印刷电路组件的compass测试设备

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113466664A (zh) * 2021-07-02 2021-10-01 深圳市宏旺微电子有限公司 一种ddr芯片测试方法、装置、终端设备及存储介质

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080020623A1 (en) * 2006-07-21 2008-01-24 Protos Electronics Test socket-lid assembly
CN102788947A (zh) * 2011-05-17 2012-11-21 联咏科技股份有限公司 测试芯片及其芯片测试系统
CN204389644U (zh) * 2015-02-11 2015-06-10 中芯国际集成电路制造(北京)有限公司 测试板装置
CN105959067A (zh) * 2016-04-22 2016-09-21 北京联盛德微电子有限责任公司 一种发射机芯片的校准方法和装置
CN207557414U (zh) * 2016-12-28 2018-06-29 上海捷策创电子科技有限公司 一种晶圆级测试装置
CN210668281U (zh) * 2019-12-06 2020-06-02 加特兰微电子科技(上海)有限公司 一种芯片测试装置及天线封装芯片

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080020623A1 (en) * 2006-07-21 2008-01-24 Protos Electronics Test socket-lid assembly
CN102788947A (zh) * 2011-05-17 2012-11-21 联咏科技股份有限公司 测试芯片及其芯片测试系统
CN204389644U (zh) * 2015-02-11 2015-06-10 中芯国际集成电路制造(北京)有限公司 测试板装置
CN105959067A (zh) * 2016-04-22 2016-09-21 北京联盛德微电子有限责任公司 一种发射机芯片的校准方法和装置
CN207557414U (zh) * 2016-12-28 2018-06-29 上海捷策创电子科技有限公司 一种晶圆级测试装置
CN210668281U (zh) * 2019-12-06 2020-06-02 加特兰微电子科技(上海)有限公司 一种芯片测试装置及天线封装芯片

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115267501A (zh) * 2022-07-29 2022-11-01 河北新华北集成电路有限公司 一种功率芯片测试装置
CN116298776A (zh) * 2023-02-03 2023-06-23 上海华岭集成电路技术股份有限公司 一种带光源的ate cis测试夹具及其测试方法
CN117054859A (zh) * 2023-10-11 2023-11-14 苏州朗之睿电子科技有限公司 一种芯片加热测试装置及其测试方法
CN117054859B (zh) * 2023-10-11 2023-12-29 苏州朗之睿电子科技有限公司 一种芯片加热测试装置及其测试方法
CN119805171A (zh) * 2025-03-12 2025-04-11 深圳市昂科技术有限公司 一种便于取放的芯片测试设备
CN120314756A (zh) * 2025-04-29 2025-07-15 燕麦(杭州)智能制造有限公司 一种柔性印刷电路组件的compass测试设备

Also Published As

Publication number Publication date
CN212781099U (zh) 2021-03-23

Similar Documents

Publication Publication Date Title
CN212781099U (zh) 芯片测试模组
EP0259163A2 (en) Semiconductor wafer probe
CN206193044U (zh) 平行四边形翻转式光学芯片模组测试插座
TW200305024A (en) Flexible test head internal interface
CN213780291U (zh) 一种新型测试治具
US8217674B2 (en) Systems and methods to test integrated circuits
CN103913689A (zh) 测试装置及测试方法
CN207923948U (zh) 一种高频测试插座
CN116027078A (zh) 一种探针卡对齐装置
CN201047867Y (zh) Ic测试载板免焊接组装结构
CN213181797U (zh) 一种上下针模测试fpc双面金手指结构
TWI858429B (zh) 高頻測試用探針卡
US6980015B2 (en) Back side probing method and assembly
CN201837697U (zh) 用于测试载板的模拟测试装置
CN217112612U (zh) 一种智能手表主板测试装置
CN211785661U (zh) 一种可拆卸式量子点材料测试治具
CN212207665U (zh) 一种tr组件参数测试夹具
JP3586330B2 (ja) デバイス間接触不良結線検出方法
CN113484608A (zh) 一种摄像头模组点胶及阻抗测试治具
CN212723212U (zh) 芯片模组的测试工装及测试系统
CN207380094U (zh) 电子模块测试连接装置
CN207730846U (zh) 智能周转柜通用主控板测试工装
CN222050413U (zh) 用于同轴测试插座的探针短路测试仪及测试系统
CN219201689U (zh) 一种测试模组夹具和测试系统
CN223092025U (zh) 一种针模性能检测工装

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20943033

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20943033

Country of ref document: EP

Kind code of ref document: A1