WO2021258910A1 - Substrat d'affichage et appareil d'affichage - Google Patents

Substrat d'affichage et appareil d'affichage Download PDF

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Publication number
WO2021258910A1
WO2021258910A1 PCT/CN2021/094030 CN2021094030W WO2021258910A1 WO 2021258910 A1 WO2021258910 A1 WO 2021258910A1 CN 2021094030 W CN2021094030 W CN 2021094030W WO 2021258910 A1 WO2021258910 A1 WO 2021258910A1
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WO
WIPO (PCT)
Prior art keywords
light
display area
emitting element
insulating layer
layer
Prior art date
Application number
PCT/CN2021/094030
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English (en)
Chinese (zh)
Inventor
吴超
龙跃
魏锋
刘聪
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to JP2022532839A priority Critical patent/JP2023531340A/ja
Priority to EP21830053.1A priority patent/EP4068384A4/fr
Priority to KR1020227016393A priority patent/KR20230026978A/ko
Priority to US17/789,405 priority patent/US20230045968A1/en
Publication of WO2021258910A1 publication Critical patent/WO2021258910A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors

Definitions

  • the embodiment of the present disclosure relates to a display substrate and a display device.
  • Organic Light-Emitting Diode (OLED) display devices have the characteristics of wide viewing angle, high contrast, fast response speed, wide color gamut, high screen-to-body ratio, self-luminous, thin and light. Due to the above-mentioned characteristics and advantages, organic light-emitting diode (OLED) display devices have gradually received widespread attention and can be applied to mobile phones, displays, notebook computers, smart watches, digital cameras, instrumentation, flexible wearable devices and other display functions. Device. With the further development of display technology, display devices with a high screen-to-body ratio can no longer meet people's needs, and display devices with a full screen have become the development trend of display technology in the future.
  • At least one embodiment of the present disclosure provides a display substrate including a display area; wherein the display area includes a first display area and a second display area that do not overlap each other, and the second display area at least partially surrounds the first display area.
  • Display area the light transmittance of the first display area is greater than the light transmittance of the second display area;
  • the first display area includes at least one first light-emitting element, and the second display area includes at least one first A pixel circuit;
  • the display area further includes at least one first connection line, the first connection line includes a first end located in the first display area and a second end located in the second display area;
  • the at least One first light-emitting element includes a first sub-light-emitting element, the at least one first pixel circuit includes a first sub-pixel circuit, and the first end of the first connection line is electrically connected to the anode of the first sub-light-emitting element, The second end of the first connection line is electrically connected to the first sub-pixel circuit;
  • the first via hole of the layer is electrically connected to the first connection line;
  • the cross-sectional shape of the first via hole in a plane perpendicular to the display substrate is an inverted boss shape, and in the first via hole,
  • the opening diameter of the second insulating layer is larger than the opening diameter of the first insulating layer;
  • the anode of the first sub-light-emitting element includes a first groove structure, and the first groove structure is located in the first via hole Inside, and the bottom of the first groove structure is in contact with the first connecting line to achieve electrical connection.
  • the display area further includes at least one second connecting line, and the second connecting line includes a first end located in the first display area and a first end located in the first display area.
  • the at least one first light-emitting element further includes a second sub-light-emitting element
  • the at least one first pixel circuit further includes a second sub-pixel circuit
  • the first end of the second connecting line Is electrically connected to the anode of the second sub-light-emitting element
  • the second end of the second connection line is electrically connected to the second sub-pixel circuit
  • the display substrate further includes a second connection layer, the second connection Layer is located between the first insulating layer and the second insulating layer, the second connecting line is located on the second connecting layer;
  • the anode of the second sub-light emitting element is located on the anode layer, and the first The anode of the two sub-light-emitting elements is electrically connected to the second connecting line through a
  • the surface of the first groove structure away from the first connection layer is curved
  • the surface of the second groove structure away from the second connection layer is Surface
  • each of the first sub-pixel circuit and the second sub-pixel circuit includes a first switching transistor, and the first switching transistor includes a gate, a second One electrode and a second electrode;
  • the display substrate further includes a source and drain metal layer and a third insulating layer, the third insulating layer is located on the source and drain metal layer, and the first connection layer is located on the first On the three insulating layer, the first electrode and the second electrode of the first switch transistor are located in the source and drain metal layer; the second end of the first connecting line passes through the third insulating layer
  • the hole is electrically connected to the first electrode or the second electrode of the first switching transistor of the first sub-pixel circuit; the second end of the second connecting line passes through the third insulating layer and the first insulating layer
  • the fourth via hole is electrically connected to the first pole or the second pole of the first switch transistor of the second sub-pixel circuit.
  • the cross-sectional shape of the fourth via in a plane perpendicular to the display substrate is an inverted boss shape, and in the fourth via, the The opening diameter of the first insulating layer is larger than the opening diameter of the third insulating layer.
  • the second connection line is electrically connected to the transition metal layer, and the transition metal layer is connected to the second sub-pixel circuit.
  • the first electrode or the second electrode of the first switching transistor is electrically connected in contact, and the transition metal layer and the first connection layer are formed in the same process.
  • the second display area further includes at least one second light-emitting element and at least one second pixel circuit, and the second light-emitting element and the second pixel circuit are electrically connected to each other.
  • the second pixel circuit includes a second switching transistor, the second switching transistor includes a gate, a first pole, and a second pole, the first pole and the second pole of the second switching transistor are located at the source Drain metal layer; the anode of the second light-emitting element is located in the anode layer, the anode of the second light-emitting element passes through the first insulating layer, the second insulating layer and the third insulating layer
  • the fifth via hole is electrically connected to the first pole or the second pole of the second switching transistor; the cross-sectional shape of the fifth via hole in a plane perpendicular to the display substrate is an inverted boss shape.
  • the opening diameter of the first insulating layer is larger than the opening diameter of the third insulating layer.
  • the opening diameter of the second insulating layer is equal to or larger than the opening diameter of the first insulating layer.
  • the anode of the second light-emitting element includes a third groove structure, the third groove structure is located in the fifth via, and the third groove The bottom of the groove structure is in contact with the first pole or the second pole of the second switch transistor to achieve electrical connection.
  • the display area further includes a third display area, the third display area at least partially surrounds the second display area, and the third display area is connected to the third display area.
  • the first display area and the second display area do not overlap;
  • the third display area includes at least one third light-emitting element and at least one third pixel circuit, the third light-emitting element and the third pixel circuit are electrically connected
  • the third pixel circuit includes a third switching transistor, the third switching transistor includes a gate, a first pole, and a second pole, and the first pole and the second pole of the third switching transistor are located in the source and drain Polar metal layer;
  • the anode of the third light-emitting element is located in the anode layer, the anode of the third light-emitting element passes through the first insulating layer, the second insulating layer and the third insulating layer
  • the six via holes are electrically connected to the first pole or the second pole of the third switching transistor; the cross-sectional shape of the sixth via hole
  • the opening diameter of the second insulating layer is equal to or larger than the opening diameter of the first insulating layer.
  • the anode of the third light-emitting element includes a fourth groove structure, the fourth groove structure is located in the sixth via, and the fourth groove The bottom of the groove structure is in contact with the first pole or the second pole of the third switch transistor to achieve electrical connection.
  • the first connection line and the second connection line respectively include transparent conductive traces.
  • the at least one first light-emitting element includes a plurality of first light-emitting elements, the plurality of first light-emitting elements are arranged in an array, and the first connecting line and The second connecting lines all extend along the row direction of the array composed of the plurality of first light-emitting elements.
  • the first light-emitting element, the second light-emitting element, and the third light-emitting element each include an organic light-emitting diode.
  • the at least one first light-emitting element includes a plurality of first light-emitting elements
  • the at least one second light-emitting element includes a plurality of second light-emitting elements
  • the at least one The third light-emitting element includes a plurality of third light-emitting elements; the distribution density per unit area of the plurality of first light-emitting elements in the first display area is less than or equal to that of the plurality of second light-emitting elements in the second display area.
  • a distribution density per unit area in the region, where the distribution density per unit area of the plurality of second light-emitting elements in the second display region is smaller than the distribution density per unit area of the plurality of third light-emitting elements in the third display region density.
  • At least one embodiment of the present disclosure further provides a display device, including the display substrate according to any embodiment of the present disclosure.
  • the display device provided by an embodiment of the present disclosure further includes a sensor, wherein the display substrate has a first side for display and a second side opposite to the first side, and the first display area allows The light on the first side is at least partially transmitted to the second side, the sensor is disposed on the second side of the display substrate, and the sensor is configured to receive the light from the first side.
  • the orthographic projection of the sensor on the display substrate at least partially overlaps the first display area.
  • FIG. 1 is a schematic plan view of a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 2 is a schematic plan view of a first display area and a second display area of the display substrate shown in FIG. 1;
  • FIG. 3 is an example of the first display area and the second display area of the display substrate shown in FIG. 2;
  • FIG. 4 is an enlarged view of a partial area REG1 in FIG. 3;
  • FIG. 5A is an enlarged view of a partial area REG2 in FIG. 3;
  • FIG. 5B is an enlarged view of the area in FIG. 5A that includes only one column of first pixel circuits, one column of first light-emitting elements, one column of second pixel circuits, and one column of second light-emitting elements;
  • Fig. 6A is a schematic cross-sectional view taken along the line A-A' in Fig. 5B;
  • FIG. 6B is an enlarged view of the first via hole H1 in FIG. 6A;
  • 6C is a schematic layout of the area corresponding to the first via H1 and the connected anode in FIG. 6A;
  • 6D is a schematic layout of the area corresponding to the third via H3 and the connected source and drain metal layers in FIG. 6A;
  • Fig. 7A is a schematic cross-sectional view taken along the line B-B' in Fig. 5B;
  • FIG. 7B is an enlarged view of the second via hole H2 in FIG. 7A;
  • FIG. 7C is a schematic layout of the area corresponding to the second via H2 and the connected anode in FIG. 7A;
  • FIG. 7D is a schematic diagram of another structure of the fourth via H4;
  • FIG. 7E is a schematic layout of the area corresponding to the fourth via H4 and the connected source and drain metal layers in FIG. 7A;
  • Fig. 8A is a schematic cross-sectional view taken along the line C-C' in Fig. 5B;
  • FIG. 8B is an enlarged view of the fifth via H5 in FIG. 8A;
  • FIG. 8C is a schematic layout of the area corresponding to the fifth via hole H5 and the connected anode and source and drain metal layers in FIG. 8A; FIG.
  • FIG. 9 is an enlarged view of a partial area REG3 of the third display area of the display substrate shown in FIG. 1;
  • Fig. 10A is a schematic cross-sectional view taken along the line D-D' in Fig. 9;
  • FIG. 10B is an enlarged view of the sixth via hole H6 in FIG. 10A;
  • FIG. 11A is a schematic layout corresponding to a partial area REG4 in FIG. 4; FIG.
  • FIG. 11B is a schematic layout showing only the first connecting line in FIG. 11A;
  • FIG. 11C is a schematic layout showing only the second connecting line in FIG. 11A;
  • Fig. 11D is a schematic cross-sectional view taken along the line E-E' in Fig. 11A;
  • 12A is one of the schematic layouts corresponding to the second light-emitting element in the second display area of the display substrate provided by some embodiments of the present disclosure
  • 12B is the second schematic layout corresponding to the second light-emitting element in the second display area of the display substrate provided by some embodiments of the present disclosure
  • FIG. 13A is a schematic structural diagram of a 7T1C pixel circuit
  • FIG. 13B is a driving timing diagram of the 7T1C pixel circuit shown in FIG. 13A;
  • FIG. 14 is a schematic block diagram of a display device provided by at least one embodiment of the present disclosure.
  • FIG. 15 is a schematic diagram of a laminated structure of a display device provided by at least one embodiment of the present disclosure.
  • the distribution density per unit area (PPI) of the element may be smaller than the distribution density per unit area of light-emitting elements in other display regions of the display substrate.
  • the arrangement of the light-emitting elements and corresponding pixel circuits in different areas is different, so that the wiring mode and layout design of the display substrate are different from the usual ones with uniform distribution.
  • the display substrate of the light-emitting element is different. This leads to the need to provide more via holes on the display substrate to achieve electrical connection between the film layers.
  • the presence of more vias on the display substrate affects the stability of the electrical connection, and makes the uniformity of the transmitted light poor, which affects the performance of the under-screen sensor (such as a camera). The sensing effect reduces the performance of the display device using the display substrate.
  • At least one embodiment of the present disclosure provides a display substrate and a display device.
  • the display substrate can reduce the difficulty of processing, improve the reliability of electrical connections, improve the uniformity of transmitted light, and help improve the sensitivity of under-screen sensors (such as cameras). Test effect.
  • At least one embodiment of the present disclosure provides a display substrate including a display area.
  • the display area includes a first display area and a second display area that do not overlap each other, the second display area at least partially surrounds the first display area, and the light transmittance of the first display area is greater than the light transmittance of the second display area.
  • the first display area includes at least one first light-emitting element, and the second display area includes at least one first pixel circuit.
  • the display area further includes at least one first connection line, and the first connection line includes a first end located in the first display area and a second end located in the second display area.
  • At least one first light-emitting element includes a first sub-light-emitting element
  • at least one first pixel circuit includes a first sub-pixel circuit
  • the first end of the first connecting line is electrically connected to the anode of the first sub-light-emitting element.
  • the second end is electrically connected to the first sub-pixel circuit.
  • the display substrate includes a first connection layer, a first insulating layer, a second insulating layer, and an anode layer that are sequentially stacked.
  • the first connection line is located in the first connection layer, the anode of the first sub-light-emitting element is located in the anode layer, and the anode of the first sub-light-emitting element is electrically connected to the first connection line through the first via hole penetrating the first insulating layer and the second insulating layer. connect.
  • the cross-sectional shape of the first via hole in a plane perpendicular to the display substrate is an inverted boss shape.
  • the opening diameter of the second insulating layer is larger than the opening diameter of the first insulating layer.
  • the anode of the first sub-light-emitting element includes a first groove structure, the first groove structure is located in the first via hole, and the bottom of the first groove structure is in contact with the first connecting line to achieve electrical connection.
  • FIG. 1 is a schematic plan view of a display substrate provided by at least one embodiment of the present disclosure.
  • the display substrate 01 includes a display area 10, and the display area 10 includes a first display area 11, a second display area 12 and a third display area 13.
  • the first display area 11, the second display area 12, and the third display area 13 do not overlap each other.
  • the third display area 13 at least partially surrounds (eg, partially surrounds) the second display area 12, and the second display area 12 at least partially surrounds (eg, completely surrounds) the first display area 11.
  • the display substrate 01 may further include a peripheral area that at least partially surrounds the third display area 13.
  • the light transmittance of the first display area 11 is greater than the light transmittance of the second display area 12.
  • at least the first display area 11 allows light to pass through.
  • the display substrate 01 has a first side for display and a second side opposite to the first side.
  • the first side is the front side of the display substrate 01 (that is, the plane shown in FIG. 1 )
  • the second side is the back side of the display substrate 01.
  • a sensor may be provided at a position corresponding to the first display area 11 on the second side of the display substrate 01, and the sensor may be, for example, an image sensor or an infrared sensor.
  • the sensor is configured to receive light from the first side of the display substrate 01, so that it can perform image shooting, distance sensing, light intensity sensing, and other operations. For example, the light passes through the first display area 11 and then irradiates the sensor, thereby being affected by the sensor. Sensing.
  • FIG. 2 is a schematic plan view of a first display area and a second display area of the display substrate shown in FIG. 1.
  • the second display area 12 at least partially surrounds (for example, completely surrounds) the first display area 11.
  • the shape of the first display area 11 may be a circle or an ellipse, and the shape of the second display area 12 may be a rectangle, but the embodiment of the present disclosure is not limited thereto.
  • the shapes of the first display area 11 and the second display area 12 may both be rectangles or other suitable shapes.
  • FIG. 3 is an example of the first display area and the second display area of the display substrate shown in FIG. 2.
  • 4 is an enlarged view of a partial area REG1 in FIG. 3
  • FIG. 5A is an enlarged view of a partial area REG2 in FIG.
  • FIG. 5B shows that the adjacent first pixel circuit and the first light-emitting element are connected to each other.
  • FIGS. 3, 4 and 4 5A it can be understood that the left side of the first light-emitting element in FIG. 5B may also be provided with other first light-emitting elements not shown, and the right side of the first pixel circuit may also be provided with other first pixel circuits not shown.
  • the first display area 11 includes at least one (for example, multiple) first light-emitting elements 411.
  • the first display area 11 includes a plurality of first light emitting elements 411 arranged in an array, and the first light emitting elements 411 are configured to emit light.
  • the pixel circuit for driving the first light-emitting element 411 is arranged in the second display area 12, thereby reducing the metal coverage area of the first display area 11 and increasing the first display area 11. Therefore, the light transmittance of the first display area 11 is greater than the light transmittance of the second display area 12.
  • the plurality of first light-emitting elements 411 may be arranged in a plurality of light-emitting units, and these light-emitting units are arranged in an array.
  • each light emitting unit may include one or more first light emitting elements 411.
  • the multiple first light-emitting elements 411 may emit light of the same color or light of different colors, for example, may emit white light, red light, blue light, green light, etc., which may be determined according to actual needs. No restrictions.
  • the arrangement of the plurality of first light-emitting elements 411 can refer to the conventional arrangement of pixel units, such as GGRB, RGBG, RGB, etc., which is not limited in the embodiment of the present disclosure.
  • the first display area 11 allows light from the first side of the display substrate 01 to be at least partially transmitted to the second side of the display substrate 01.
  • a sensor on the second side of the display substrate 01 and corresponding to the position of the first display area 11. Strong perception and other operations.
  • the second display area 12 includes at least one (for example, a plurality of) first pixel circuits 412.
  • the first light-emitting elements 411 and the first pixel circuits 412 are electrically connected in a one-to-one correspondence, and the plurality of first pixel circuits 412 are used to drive the plurality of first light-emitting elements 411 in a one-to-one correspondence.
  • the rectangular frame shown in FIG. 5B (the black frame and white filled area indicated by reference numeral 412) represents the first pixel driving unit, and each first pixel driving unit includes a first pixel circuit 412.
  • the first pixel circuit 412 is configured to drive a plurality of first light-emitting elements 411 to emit light in a one-to-one correspondence. That is, one first pixel circuit 412 drives one corresponding first light-emitting element 411, and different first pixel circuits 412 drive different first light-emitting elements 411.
  • the first pixel driving unit may include one or more first pixel circuits 412.
  • the first pixel driving unit also includes a first pixel circuit 412.
  • the first pixel driving unit also includes a plurality of first pixel circuits 412, and the number of first light-emitting elements 411 in each light-emitting unit is, for example, It is equal to the number of first pixel circuits 412 in each first pixel driving unit, thereby achieving one-to-one corresponding driving.
  • the plurality of first light-emitting elements 411 are arranged in an array, and the plurality of first pixel circuits 412 are also arranged in an array.
  • array arrangement may refer to multiple devices being arranged in a group and multiple sets of device arrays, or it may refer to multiple devices themselves being arrayed, which is not limited in the embodiments of the present disclosure.
  • FIG. 3, FIG. 4, FIG. 5A, and FIG. The four first pixel circuits 412 form a group, and the multiple groups of first pixel circuits 412 are arranged in an array.
  • each first pixel driving unit includes four first pixel circuits 412.
  • the display area 10 further includes at least one first connection line 110 and at least one second connection line 120.
  • the first connecting line 110 includes a first end located in the first display area 11 and a second end located in the second display area 12, that is, the first connecting line 110 extends from the first display area 11 to the second display area 12.
  • the second connecting line 120 includes a first end located in the first display area 11 and a second end located in the second display area 12, that is, the second connecting line 120 extends from the first display area 11 to the second end. Display area 12.
  • the first light-emitting element 411 includes a first sub-light-emitting element 411a and a second sub-light-emitting element 411b
  • the first pixel circuit 412 includes a first sub-pixel circuit 412a and a second sub-pixel circuit 412b.
  • the first end of the first connection line 110 is electrically connected to the anode of the first sub-light emitting element 411a
  • the second end of the first connection line 110 is electrically connected to the first sub-pixel circuit 412a
  • the first connection line 110 is configured to connect the first
  • the electrical signal provided by the sub-pixel circuit 412a is transmitted to the anode of the first sub-light-emitting element 411a, thereby driving the first sub-light-emitting element 411a to emit light.
  • the first end of the second connecting line 120 is electrically connected to the anode of the second sub-light-emitting element 411b
  • the second end of the second connecting line 120 is electrically connected to the second sub-pixel circuit 412b
  • the second connecting line 120 is configured to connect the second
  • the electrical signal provided by the sub-pixel circuit 412b is transmitted to the anode of the second sub-light-emitting element 411b, thereby driving the second sub-light-emitting element 411b to emit light.
  • a part of the first light-emitting elements 411 (for example, the first sub-light-emitting element 411a) is electrically connected to the first connection line 110, and the other part of the first light-emitting elements 411 (For example, the second sub-light-emitting element 411b) is electrically connected to the second connection line 120, so that all the first light-emitting elements 411 are electrically connected to the corresponding first pixel circuit 412 through the corresponding connection line, thereby realizing the first light emission Component 411 is driven.
  • the first connection line 110 and the second connection line 120 are located in different film layers of the display substrate 01, that is, the first connection line 110 and the second connection line 120 are located in two different film layers. Due to the different film layers, the orthographic projection of the first connecting line 110 on the display substrate 01 and the orthographic projection of the second connecting line 120 on the display substrate 01 can overlap, so that the wiring space can be effectively used, and the wiring is convenient, so that the first All the first light-emitting elements 411 in a display area 11 are electrically connected to corresponding connecting lines. Even if the number of first light-emitting elements 411 is large and the corresponding connection lines are large, the display substrate 01 can provide sufficient wiring space.
  • different film layers are insulated from each other at positions where no vias are provided.
  • the wires located in different film layers can be electrically connected by providing vias.
  • these different film layers are prepared in different processes.
  • the first process is used to prepare one of these different film layers, and then the second process is used to prepare the other of these different film layers.
  • a third process can also be used to prepare an insulating layer. Insulate each other.
  • the first process, the second process, and the third process may be the same or different.
  • the display substrate 01 includes a base substrate
  • different film layers have different distances from the base substrate. That is, among the different film layers, one film layer is closer to the base substrate, and the other film layer is farther from the base substrate.
  • the meaning of the different film layers can be referred to the above description, and will not be repeated.
  • the connecting line used to realize the electrical connection between the first light-emitting element 411 and the first pixel circuit 412 is not limited to being located in two different film layers, and may also be located in three different film layers.
  • Layer, 4 film layers or any number of film layers, that is, these connecting lines are not limited to the first connecting line 110 and the second connecting line 120 described above, and may also include the first connecting line 110 and the second connecting line 110 and the second connecting line 120 described above.
  • the connecting line 120 is located on other connecting lines of different film layers, which is not limited in the embodiment of the present disclosure.
  • a plurality of first connection lines 110 and a plurality of second connection lines 120 form a connection line array, and each connection line in the connection line array (the connection line may be the first connection line 110 or The second connecting line 120) electrically connects one first light-emitting element 411 and one first pixel circuit 412 correspondingly.
  • the distance between the correspondingly connected first light-emitting element 411 and the first pixel circuit 412 may be substantially similar during the wiring design. .
  • a plurality of pixel circuits (including a first pixel circuit 412 and a second pixel circuit 422) are arranged in an array, and a plurality of first light-emitting elements 411 are also arranged in an array.
  • the first pixel circuit 412 in the (P-1)th column and the first light-emitting element 411 in the W-th column pass through a connecting line (which can be the first connecting line 110 or The second connecting line 120) is electrically connected, and the length of the connecting line is, for example, about S1; the first pixel circuit 412 in the (P+1)th column and the first light-emitting element 411 in the (W+1)th column pass through the connecting line ( It may be the electrical connection of the first connecting wire 110 or the second connecting wire 120), and the length of the connecting wire is about S2, for example.
  • the difference between S1 and S2 is within a certain range and should not be too large.
  • the specific value of the difference range of S1 and S2 may be determined according to actual requirements, which is not limited in the embodiment of the present disclosure.
  • the first pixel circuit 412 and the first light-emitting element 411 located in the (Q-1)th row and the (Q-2)th row may adopt a similar wiring manner.
  • the embodiment of the present disclosure is not limited to the situation shown in FIG. 5A.
  • the distribution positions of the first pixel circuit 412 and the first light-emitting element 411 connected by the connecting line may also be other positions, which may be determined according to actual needs. The disclosed embodiment does not limit this.
  • the distribution mode and positional relationship of the plurality of first connection lines 110 and the plurality of second connection lines 120 in a plane parallel to the display substrate 01 are not limited, which can be determined according to actual wiring requirements.
  • the first connecting lines 110 and the second connecting lines 120 may be arranged at intervals one by one, or may be arranged at intervals in groups, or may be randomly distributed. This is the case in the embodiments of the present disclosure. No restrictions.
  • the first sub-light-emitting element 411a and the second sub-light-emitting element 411b may have no difference in structure and function.
  • the first sub-pixel circuit 412a and the second sub-pixel circuit 412b are in structure and function. There may be no difference in function. They are called “first” and “second”, just to distinguish the connection lines (that is, the first connection line 110 and the second connection line 120) connected to these light-emitting elements and the pixel circuit. ), which does not constitute a limitation to the embodiments of the present disclosure.
  • FIG. 6A is a schematic cross-sectional view along the line AA' in FIG. 5B
  • FIG. 6B is an enlarged view of the first via H1 in FIG. 6A
  • FIG. 6C is a diagram corresponding to the first via H1 and the connected anode in FIG. 6A
  • the schematic layout of the region FIG. 6D is a schematic layout of the region corresponding to the third via H3 and the connected source and drain metal layers in FIG. 6A.
  • the display substrate 01 includes a third insulating layer 33, a first connection layer 21, a first insulating layer 31, a second insulating layer 32, and an anode layer 40 that are sequentially stacked.
  • the first sub-light-emitting element 411a includes an anode 4111, a cathode 4113, and a light-emitting layer 4112 located between the anode 4111 and the cathode 4113.
  • the first connection line 110 is located on the first connection layer 21, and the anode 4111 of the first sub-light-emitting element 411 a is located on the anode layer 40.
  • the anode 4111 of the first sub-light emitting element 411a is electrically connected to the first connection line 110 through the first via hole H1 penetrating the first insulating layer 31 and the second insulating layer 32.
  • the cross-sectional shape of the first via hole H1 in a plane perpendicular to the display substrate 01 is an inverted boss shape.
  • the inverted boss shape can be regarded as a shape formed by joining two rectangles of different sizes. The upper rectangle is larger, and the lower rectangle is larger. Therefore, a step is formed on at least one side surface of the inverted boss shape, for example, steps are formed on two side surfaces; for example, the orthographic projection of the part corresponding to the rectangle located below on the base substrate 74 is completely on the rectangle located above The corresponding part is inside the orthographic projection on the base substrate 74.
  • each edge of the orthographic projection on the base substrate 74 and the part corresponding to the upper rectangle are on the substrate.
  • the edges of the orthographic projection on the substrate 74 are spaced apart from each other.
  • the opening diameter L2 of the second insulating layer 32 is larger than the opening diameter L1 of the first insulating layer 31.
  • the opening diameter L2 of the second insulating layer 32 may be 6 ⁇ m ⁇ 6 ⁇ m, or the opening diameter L1 of the first insulating layer 31 may be 6 ⁇ m ⁇ 6 ⁇ m. Since the first via hole H1 needs to penetrate through two insulating layers, the depth of the first via hole H1 is relatively large.
  • the difficulty of processing the first via hole H1 can be reduced, and it is convenient
  • a conductive material (for example, the material of the anode 4111) is deposited in the first via hole H1, thereby improving the reliability of the electrical connection.
  • the anode 4111 of the first sub-light-emitting element 411a includes a first groove structure GR1, the first groove structure GR1 is located in the first via H1, and the bottom of the first groove structure GR1 is in contact with the first connecting line 110 to Realize electrical connection.
  • the thickness of this part can be reduced, so that the thickness of this part is not much different from the thickness of other parts of the anode 4111, thereby improving the overall
  • the uniformity of the transmitted light ensures that there is no obvious difference in brightness in different areas, and the first display area 11 has better light transmittance, which in turn helps to improve the sensing effect of the under-screen sensor (such as a camera), such as imaging clearer.
  • the first via hole H1 is in the shape of an inverted boss, when preparing the anode 4111, it is advantageous to form the groove structure, and the process difficulty can be reduced.
  • the surface of the first groove structure GR1 away from the first connection layer 21 is a curved surface.
  • the light intensity of the transmitted light can be continuously changed to avoid sudden changes in the light intensity at a local position, thereby further improving the uniformity of the transmitted light.
  • the embodiment of the present disclosure is not limited to this.
  • the surface of the first groove structure GR1 away from the first connection layer 21 may also be a flat surface, an inclined surface, etc., which may be determined according to actual requirements.
  • the anode 4111 may include multiple anode sub-layers, for example, a three-layer structure of ITO/Ag/ITO (not labeled in the figure), etc.
  • the specific form of the anode 4111 is not limited in the embodiment of the present disclosure.
  • the cathode 4113 may be a structure formed on the entire surface of the display substrate 01, and the cathode 4113 may include, for example, metal materials such as lithium (Li), aluminum (Al), magnesium (Mg), and silver (Ag).
  • the cathode 4113 can be formed as a very thin layer, the cathode 4113 has good light transmittance.
  • the anode 4111 includes an ITO/Ag/ITO three-layer structure, its thickness may be 86/1000/86A.
  • the second connecting line 120 is located in a different film layer from the first connecting line 110 (the film layer where the second connecting line 120 is located and the corresponding cross-sectional structure will be described later). Description), and the second connection line 120 and the anode 4111 of the first sub-light-emitting element 411a are also located in different layers. Therefore, although the contour of the second connection line 120 overlaps with the anode 4111 of the first sub-light-emitting element 411a, However, the second connection line 120 is not electrically connected to the anode 4111 of the first sub-light-emitting element 411a.
  • the first sub-pixel circuit 412a includes a first switching transistor (for example, a switching thin film transistor 412T) and a storage capacitor 412C.
  • the switching thin film transistor 412T includes a gate 4121, an active layer 4122, a first electrode 4123, and a second electrode 4124.
  • the first electrode 4123 may be a source or a drain
  • the second electrode 4124 may be a drain or a source.
  • the storage capacitor 412C includes a first capacitor plate 4125 and a second capacitor plate 4126.
  • the active layer 4121 is disposed on the base substrate 74, and the first gate insulating layer 741 is disposed on the side of the active layer 4121 away from the base substrate 74.
  • the gate 4122 and the first capacitor plate 4125 are arranged in the same layer and are located on the side of the first gate insulating layer 741 away from the base substrate 74.
  • a second gate insulating layer 742 is provided on the side.
  • the second capacitor plate 4126 is disposed on the side of the second gate insulating layer 742 away from the base substrate 74, and the side of the second capacitor plate 4126 away from the base substrate 74 is provided with an interlayer insulating layer 743.
  • the first electrode 4123 and the second electrode 4124 are arranged on the side of the interlayer insulating layer 743 away from the base substrate 74, and pass through the first gate insulating layer 741, the second gate insulating layer 742, and the side of the interlayer insulating layer 743.
  • the via hole in the interlayer insulating layer 743 is electrically connected to the active layer 4121.
  • the first electrode 4123 and the second electrode 4124 are both located on the source and drain metal layer SD, the third insulating layer 33 is located on the source and drain metal layer SD, and the first connection layer 21 is located on the third insulating layer 33.
  • the third insulating layer 33 can not only play a role of insulation, but also play a role of planarization.
  • the second end of the first connection line 110 is electrically connected to the second electrode 4124 of the first switching transistor (for example, the switching thin film transistor 412T) included in the first sub-pixel circuit 412a through the third via hole H3 penetrating the third insulating layer 33. connect.
  • the embodiment of the present disclosure is not limited to this.
  • the second end of the first connection line 110 may also be electrically connected to the first electrode 4123 of the switching thin film transistor 412T included in the first sub-pixel circuit 412a.
  • the cross-sectional size of the third via hole H3 in a plane parallel to the display substrate 01 may be 4 ⁇ m ⁇ 4 ⁇ m.
  • the first display area 11 further includes a transparent support layer 78 on the base substrate 74, and the first sub-light-emitting element 411 a is located on the side of the transparent support layer 78 away from the base substrate 74. Therefore, with respect to the base substrate 74, the first sub-light-emitting element 411a in the first display area 11 can be combined with light-emitting elements in other display areas (for example, the second light-emitting element in the second display area 12 described later).
  • the element 421 and the third light-emitting element 431 in the third display area 13 are at substantially the same height, so that the display effect of the display substrate 01 can be improved.
  • the display substrate 01 may also include a pixel defining layer 746, an encapsulation layer 747 and other structures.
  • the pixel defining layer 746 is disposed on the anode 4111 (for example, a partial structure of the anode 4111), and includes a plurality of openings to define different pixels or sub-pixels, and the light emitting layer 4112 is formed in the openings of the pixel defining layer 746.
  • the horizontal distance between the opening of the pixel defining layer 746 and the first via hole H1 may be 4.6 ⁇ m.
  • the encapsulation layer 747 may include a single-layer or multi-layer encapsulation structure, for example, the multilayer encapsulation structure includes a stack of an inorganic encapsulation layer and an organic encapsulation layer, thereby improving the encapsulation effect on the display substrate 01.
  • the pixel defining layers 746 in the first display area 11, the second display area 12, and the third display area 13 are arranged in the same layer, and the pixel defining layers 746 in the first display area 11, the second display area 12 and the third display area 13 are
  • the encapsulation layer 747 is provided in the same layer, and in some embodiments is still integrally connected, which is not limited in the embodiments of the present disclosure.
  • the base substrate 74 may be a glass substrate, a quartz substrate, a metal substrate, or a resin substrate, etc., and may be a rigid substrate or a flexible substrate, which is not limited in the embodiments of the present disclosure.
  • the first gate insulating layer 741, the second gate insulating layer 742, the interlayer insulating layer 743, the first insulating layer 31, the second insulating layer 32, the third insulating layer 33, the pixel defining layer 746, and the encapsulation layer 747 It may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, or may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenol resin.
  • the embodiments of the present disclosure do not specifically limit the materials of the above-mentioned functional layers.
  • the thicknesses of the first insulating layer 31, the second insulating layer 32, and the third insulating layer 33 may be 10000-15000A, respectively.
  • the material of the active layer 4121 may include semiconductor materials such as polysilicon or oxide semiconductor (for example, indium gallium zinc oxide).
  • the part of the active layer 4121 may be conductive through a conductive process such as doping, so as to have higher conductivity.
  • the materials of the gate 4122, the first capacitor plate 4125, and the second capacitor plate 4126 may include metal materials or alloy materials, such as molybdenum, aluminum, and titanium.
  • the material of the first pole 4123 and the second pole 4124 may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed of molybdenum, aluminum, titanium, etc.
  • the multi-layer structure is a multi-metal laminated layer , Such as titanium, aluminum, titanium three-layer metal laminate (Ti/Al/Ti) and so on.
  • the display substrate 01 provided by the embodiment of the present disclosure may be an organic light emitting diode (OLED) display substrate or a quantum dot light emitting diode (QLED) display substrate, etc.
  • OLED organic light emitting diode
  • QLED quantum dot light emitting diode
  • the embodiment of the present disclosure does not limit the specific type of the display substrate.
  • the light-emitting layer (for example, the aforementioned light-emitting layer 4112) may include small molecular organic materials or polymer molecular organic materials, may be fluorescent light-emitting materials or phosphorescent light-emitting materials, and may be light-emitting Red light, green light, blue light, or white light.
  • the light-emitting layer may further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.
  • the light-emitting layer may include quantum dot materials, such as silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, Cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, lead selenide quantum dots, indium phosphide quantum dots and indium arsenide quantum dots, etc.
  • the particle size of the quantum dots is, for example, 2nm ⁇ 20nm.
  • FIG. 7A is a schematic cross-sectional view taken along the line BB' in Fig. 5B
  • Fig. 7B is an enlarged view of the second via H2 in Fig. 7A
  • Fig. 7C is a diagram corresponding to the second via H2 and the connected anode in Fig. 7A
  • FIG. 7D is a schematic diagram of another structure of the fourth via H4
  • FIG. 7E is a schematic layout of the area corresponding to the fourth via H4 and the connected source and drain metal layers in FIG. 7A.
  • the display substrate 01 further includes a second connecting layer 22, the second connecting layer 22 is located between the first insulating layer 31 and the second insulating layer 32, and the second connecting line 120 is located at the second connecting layer.
  • the arrangement of the second sub-light-emitting element 411b is similar to that of the first sub-light-emitting element 411a.
  • the arrangement of the first switching transistor (for example, the switching thin film transistor 412T) and the storage capacitor 412C included in the second sub-pixel circuit 412b is the same as that of the first sub-pixel circuit 412b.
  • the arrangement of the first switch transistor and the storage capacitor 412C in the sub-pixel circuit 412a is similar. For related description, please refer to the description of FIGS. 6A-6D above, which will not be repeated here.
  • the anode 4111 of the second sub-light-emitting element 411b is located on the anode layer 40, and the anode 4111 of the second sub-light-emitting element 411b is electrically connected to the second connection line 120 through the second via H2 penetrating the second insulating layer 32.
  • the anode 4111 of the second sub-light-emitting element 411b includes a second groove structure GR2, the second groove structure GR2 is located in the second via H2, and the bottom of the second groove structure GR2 is in contact with the second connecting line 120 to Realize electrical connection.
  • the part of the anode 4111 deposited in the second via hole H2 as a groove structure, the thickness of this part can be reduced, so that the thickness of this part is not much different from the thickness of other parts of the anode 4111, thereby improving the overall Uniformity of transmitted light.
  • the surface of the second groove structure GR2 away from the second connection layer 22 is a curved surface.
  • the light intensity of the transmitted light can be continuously changed to avoid sudden changes in the light intensity at a local position, thereby further improving the uniformity of the transmitted light.
  • the embodiment of the present disclosure is not limited to this.
  • the surface of the second groove structure GR2 away from the second connection layer 22 may also be a flat surface, an inclined surface, etc., which may be determined according to actual requirements.
  • the second end of the second connection line 120 passes through the fourth via hole H4 passing through the third insulating layer 33 and the first insulating layer 31 and the first switching transistor (for example, the switching thin film transistor 412T) of the second sub-pixel circuit 412b.
  • the second pole 4124 is electrically connected.
  • the embodiment of the present disclosure is not limited to this.
  • the second terminal of the second connecting line 120 may also be electrically connected to the first pole 4123 of the switching thin film transistor 412T included in the second sub-pixel circuit 412b.
  • the cross-sectional shape of the fourth via hole H4 in a plane perpendicular to the display substrate 01 is an inverted boss shape.
  • the opening diameter of the first insulating layer 31 is larger than the opening diameter of the third insulating layer 33. Since the fourth via H4 needs to penetrate through two insulating layers, the depth of the fourth via H4 is relatively large.
  • a conductive material (for example, the material of the second connection line 120) is deposited in the fourth via hole H4, thereby improving the reliability of the electrical connection.
  • the first connection line 110 is located in a different film layer from the second connection line 120, and the anode 4111 of the first connection line 110 and the second sub-light-emitting element 411b are also located Different film layers, therefore, although the outline of the first connection line 110 overlaps with the anode 4111 of the second sub-light-emitting element 411b, the first connection line 110 is not electrically connected to the anode 4111 of the second sub-light-emitting element 411b.
  • connection manner between the second connection line 120 and the first switching transistor is not limited to the manner shown in FIG. Difficulty.
  • the second connection line 120 is electrically connected to the transition metal layer 23, and the transition metal layer 23 is electrically connected to the first sub-pixel circuit 412b.
  • the first pole 4123 or the second pole 4124 of the switching transistor is electrically connected, thereby realizing the electrical connection between the second connection line 120 and the switching thin film transistor 412T.
  • the transition metal layer 23 and the first connection layer 21 are formed in the same process, that is, the transition metal layer 23 and the first connection layer 21 can be the same film layer, in which a part of the structure forms the first connection line 110. Another part of the structure is used to electrically connect the second connection line 120 and the switching thin film transistor 412T of the second sub-pixel circuit 412b.
  • the second display area 12 further includes at least one (for example, multiple) second light-emitting elements 421 and at least one (for example, multiple) second pixel circuits 422.
  • the second light-emitting element 421 is electrically connected to the second pixel circuit 422 in a one-to-one correspondence, and the second pixel circuit 422 is used to drive the second light-emitting element 421 to emit light.
  • the rectangular frame indicated by the reference number 422 in FIG. 5B is only used to show the approximate position of the second pixel circuit 422, and does not indicate the specific shape of the second pixel circuit 422 and the specific boundary of the second pixel circuit 422.
  • at least one second light-emitting element 421 and its corresponding second pixel circuit 422 constitute a second pixel driving unit 42.
  • the second pixel driving unit 42 may include a second pixel circuit 422 and a second light-emitting element 421, or may include a plurality of second pixel circuits 422 and a plurality of second light-emitting elements 421.
  • the second pixel driving unit 42 includes a plurality of second pixel circuits 422 and a plurality of second light-emitting elements 421
  • the number of second pixel circuits 422 in each second pixel driving unit 42 is, for example, equal to that of the second light-emitting elements 421. Quantity, which realizes one-to-one correspondence drive.
  • a plurality of second light emitting elements 421 are arranged in an array, and a plurality of second pixel circuits 422 are also arranged in an array.
  • array arrangement may refer to multiple devices being arranged in a group and multiple sets of device arrays, or it may refer to multiple devices themselves being arrayed, which is not limited in the embodiments of the present disclosure.
  • every four second light-emitting elements 421 form a group, and multiple groups of second light-emitting elements 421 are arranged in an array.
  • every four second pixel circuits 422 are one group. Groups, multiple groups of second pixel circuits 422 are arranged in an array.
  • each second pixel driving unit 42 includes four second pixel circuits 422 and four second light-emitting elements 421.
  • Fig. 8A is a schematic cross-sectional view taken along the line CC' in Fig. 5B
  • Fig. 8B is an enlarged view of the fifth via H5 in Fig. 8A
  • Fig. 8C is corresponding to the fifth via H5 and the connected anode and Schematic layout of the area of the source and drain metal layers.
  • the second pixel circuit 422 includes a second switching transistor (for example, a switching thin film transistor 422T) and a storage capacitor 422C.
  • the switching thin film transistor 422T includes a gate 4221, an active layer 4222, a first electrode 4223, and a second electrode 4224.
  • the first electrode 4223 may be a source or a drain
  • the second electrode 4224 may be a drain or a source.
  • the storage capacitor 422C includes a first capacitor plate 4225 and a second capacitor plate 4226.
  • the active layer 4221 is disposed on the base substrate 74, and the first gate insulating layer 741 is disposed on the side of the active layer 4221 away from the base substrate 74.
  • the gate 4222 and the first capacitor plate 4225 are arranged in the same layer, and are located on the side of the first gate insulating layer 741 away from the base substrate 74.
  • a second gate insulating layer 742 is provided on the side.
  • the second capacitor plate 4226 is disposed on the side of the second gate insulating layer 742 away from the base substrate 74, and the side of the second capacitor plate 4226 away from the base substrate 74 is provided with an interlayer insulating layer 743.
  • the first electrode 4223 and the second electrode 4224 are disposed on the side of the interlayer insulating layer 743 away from the base substrate 74, and pass through the first gate insulating layer 741, the second gate insulating layer 742, and the interlayer insulating layer 743.
  • the via hole in the interlayer insulating layer 743 is electrically connected to the active layer 4221.
  • the first electrode 4223 and the second electrode 4224 are both located on the source and drain metal layer SD, and the third insulating layer 33 is located on the source and drain metal layer SD.
  • the third insulating layer 33 can not only play a role of insulation, but also play a role of planarization.
  • the second light-emitting element 421 includes an anode 4211, a cathode 4213, and a light-emitting layer 4212 located between the anode 4211 and the cathode 4213, and the anode 4211 is located at the anode layer 40.
  • the anode 4211 of the second light-emitting element 421 passes through the fifth via hole H5 penetrating the first insulating layer 31, the second insulating layer 32, and the third insulating layer 33 and the first electrode 4223 of the second switching transistor (for example, the switching thin film transistor 42T). Or the second pole 4224 is electrically connected.
  • the cross-sectional shape of the fifth via H5 in a plane perpendicular to the display substrate 01 is an inverted boss shape.
  • the opening diameter L3 of the first insulating layer 31 is larger than the opening diameter L4 of the third insulating layer 33. Since the fifth via hole H5 needs to penetrate through three insulating layers, the depth of the fifth via hole H5 is relatively large.
  • a conductive material for example, the material of the anode 4211
  • the opening diameter of the second insulating layer 32 is equal to or larger than the opening diameter of the first insulating layer 31.
  • the opening diameter of the second insulating layer 32 is equal to the opening diameter of the first insulating layer 31, that is, both are equal to L3, so that the same mask can be used to prepare the first insulating layer.
  • the openings of an insulating layer 31 and a second insulating layer 32 reduce the number of masks required and reduce the production cost.
  • the opening diameter of the second insulating layer 32 may be larger than the opening diameter of the first insulating layer 31, so that the fifth via H5 can be formed in a three-stage stepped shape to further reduce the processing difficulty and facilitate A conductive material (for example, the material of the anode 4211) is deposited in the fifth via hole H5 to further improve the reliability of the electrical connection.
  • a conductive material for example, the material of the anode 4211
  • the anode 4211 of the second light-emitting element 421 includes a third groove structure GR3, the third groove structure GR3 is located in the fifth via H5, and the bottom of the third groove structure GR3 is connected to the second switching transistor (such as a switching thin film transistor).
  • the first pole 4223 or the second pole 4224 of 422T) contact to achieve electrical connection.
  • the fifth via hole H5 is in the shape of an inverted boss, when preparing the anode 4211, it is advantageous to form the groove structure, and the process difficulty can be reduced.
  • the surface of the third groove structure GR3 away from the source and drain metal layer SD may be a curved surface, a flat surface, an inclined surface, etc., which is not limited in the embodiment of the present disclosure.
  • FIG. 9 is an enlarged view of a partial area REG3 of the third display area of the display substrate shown in FIG. 1.
  • the third display area 13 includes at least one (for example, multiple) third light-emitting elements 431 and at least one (for example, multiple) third pixel circuits 432.
  • the third light-emitting element 431 is electrically connected to the third pixel circuit 432 in a one-to-one correspondence, and the third pixel circuit 432 is used to drive the third light-emitting element 431 to emit light.
  • At least one third light-emitting element 431 and its corresponding third pixel circuit 432 constitute a third pixel driving unit 43.
  • the third pixel driving unit 43 may include a third pixel circuit 432 and a third light-emitting element 431, or may include a plurality of third pixel circuits 432 and a plurality of third light-emitting elements 431.
  • the third pixel driving unit 43 includes a plurality of third pixel circuits 432 and a plurality of third light-emitting elements 431
  • the number of third pixel circuits 432 in each third pixel driving unit 43 is, for example, equal to that of the third light-emitting element 431. Quantity, which realizes one-to-one correspondence drive.
  • a plurality of third light emitting elements 431 are arranged in an array, and a plurality of third pixel circuits 432 are also arranged in an array.
  • array arrangement may refer to multiple devices being arranged in a group and multiple sets of device arrays, or it may refer to multiple devices themselves being arrayed, which is not limited in the embodiments of the present disclosure.
  • every four third light-emitting elements 431 form a group, and multiple groups of third light-emitting elements 431 are arranged in an array.
  • every four third pixel circuits 432 are one group. Groups of third pixel circuits 432 are arranged in an array.
  • each third pixel driving unit 43 includes four third pixel circuits 432 and four third light-emitting elements 431.
  • Fig. 10A is a schematic cross-sectional view taken along the line D-D' in Fig. 9 and Fig. 10B is an enlarged view of the sixth via H6 in Fig. 10A.
  • the third pixel circuit 432 includes a third switching transistor (for example, a switching thin film transistor 432T) and a storage capacitor 432C.
  • the switching thin film transistor 432T includes a gate 4321, an active layer 4322, a first electrode 4323, and a second electrode 4324.
  • the first electrode 4323 may be a source or a drain
  • the second electrode 4324 may be a drain or a source.
  • the storage capacitor 432C includes a first capacitor plate 4325 and a second capacitor plate 4326.
  • the active layer 4321 is disposed on the base substrate 74, and the first gate insulating layer 741 is disposed on the side of the active layer 4321 away from the base substrate 74.
  • the gate 4322 and the first capacitor plate 4325 are arranged in the same layer and are located on the side of the first gate insulating layer 741 away from the base substrate 74.
  • a second gate insulating layer 742 is provided on the side.
  • the second capacitor plate 4326 is disposed on the side of the second gate insulating layer 742 away from the base substrate 74, and the side of the second capacitor plate 4326 away from the base substrate 74 is provided with an interlayer insulating layer 743.
  • the first electrode 4323 and the second electrode 4324 are arranged on the side of the interlayer insulating layer 743 away from the base substrate 74, and pass through the first gate insulating layer 741, the second gate insulating layer 742, and the interlayer insulating layer 743.
  • the via hole in the interlayer insulating layer 743 is electrically connected to the active layer 4321.
  • the first electrode 4323 and the second electrode 4324 are both located on the source and drain metal layer SD, and the third insulating layer 33 is located on the source and drain metal layer SD.
  • the third insulating layer 33 can not only play a role of insulation, but also play a role of planarization.
  • the third light-emitting element 431 includes an anode 4311, a cathode 4313, and a light-emitting layer 4312 located between the anode 4311 and the cathode 4313, and the anode 4311 is located at the anode layer 40.
  • the anode 4311 of the third light-emitting element 431 passes through the sixth via hole H6 penetrating the first insulating layer 31, the second insulating layer 32, and the third insulating layer 33 and the first electrode 4323 of the third switching transistor (for example, the switching thin film transistor 432T). Or the second pole 4324 is electrically connected.
  • the cross-sectional shape of the sixth via hole H6 in a plane perpendicular to the display substrate 01 is an inverted boss shape.
  • the opening diameter L5 of the first insulating layer 31 is larger than the opening diameter L6 of the third insulating layer 33. Since the sixth via hole H6 needs to penetrate through three insulating layers, the depth of the sixth via hole H6 is relatively large.
  • a conductive material for example, the material of the anode 4311
  • the opening diameter of the second insulating layer 32 is equal to or larger than the opening diameter of the first insulating layer 31.
  • the opening diameter of the second insulating layer 32 is equal to the opening diameter of the first insulating layer 31, that is, both are equal to L5, so that the same mask can be used to prepare the first insulating layer.
  • the openings of an insulating layer 31 and a second insulating layer 32 reduce the number of masks required and reduce the production cost.
  • the opening diameter of the second insulating layer 32 may be larger than the opening diameter of the first insulating layer 31, so that the sixth via hole H6 can be formed in a three-stage step shape to further reduce the processing difficulty and facilitate A conductive material (for example, the material of the anode 4311) is deposited in the sixth via hole H6 to further improve the reliability of the electrical connection.
  • a conductive material for example, the material of the anode 4311
  • the anode 4311 of the third light-emitting element 431 includes a fourth groove structure GR4, the fourth groove structure GR4 is located in the sixth via H6, and the bottom of the fourth groove structure GR4 is connected to the third switching transistor (such as a switching thin film transistor).
  • the sixth via hole H6 is in the shape of an inverted boss, when preparing the anode 4311, it is advantageous to form the groove structure, and the process difficulty can be reduced.
  • the surface of the fourth groove structure GR4 away from the source and drain metal layer SD may be a curved surface, a flat surface, an inclined surface, etc., which is not limited in the embodiment of the present disclosure.
  • FIG. 11A is a schematic layout corresponding to the partial area REG4 in FIG. 4
  • FIG. 11B is a schematic layout showing only the first connecting line in FIG. 11A
  • FIG. 11C is a schematic layout showing only the second connecting line in FIG. 11A
  • FIG. 11D is a schematic cross-sectional view along the line E-E' in FIG. 11A.
  • the first connection line 110 and the second connection line 120 extend in respective extending directions, for example, the first connection line 110
  • the extending direction of and the extending direction of the second connecting line 120 may be the same or different.
  • the third insulating layer 33, the first connecting line 110 (that is, the first connecting layer 21), the first insulating layer 31, the second connecting line 120 (that is, the second connecting layer 22), the second The insulating layer 32 and the pixel defining layer 746 are stacked in sequence. Since the first insulating layer 31 is provided, the first connection line 110 and the second connection line 120 are insulated from each other and will not be short-circuited.
  • FIG. 11D refer to the foregoing content, which is not shown in FIG. 11D.
  • FIG. 12A is one of the schematic layouts corresponding to the second light-emitting element in the second display area of a display substrate provided by some embodiments of the present disclosure
  • FIG. 12B is a second display area of a display substrate provided by some embodiments of the present disclosure Schematic layout of the second light-emitting element corresponding to the second. For example, as shown in FIGS.
  • the first connection line 110 and the second connection line 120 are separated from the anode 4211 of the second light-emitting element 421.
  • the bottom side (that is, the side where the anode 4211 is close to the base substrate 74) passes through and is insulated from the anode 4211 of the second light-emitting element 421.
  • the first connection line 110 and the second connection line 120 may respectively include transparent conductive traces, and the transparent conductive traces are made of, for example, indium tin oxide (ITO). Setting the first connecting line 110 and the second connecting line 120 as transparent conductive traces can increase the light transmittance of the display substrate 01.
  • ITO indium tin oxide
  • the plurality of first light-emitting elements 411 are arranged in an array, and the first connection line 110 and the second connection line 120 both extend along the row direction of the array composed of the plurality of first light-emitting elements 411.
  • the embodiment of the present disclosure is not limited to this, and the extending direction of the first connection line 110 and the second connection line 120 may also be any other direction, which is not limited by the embodiment of the present disclosure.
  • the extension direction of the first connection line 110 and the extension direction of the second connection line 120 may be the same or different.
  • the first light emitting element 411, the second light emitting element 421, and the third light emitting element 431 may each include an organic light emitting diode (OLED).
  • OLED organic light emitting diode
  • the embodiments of the present disclosure are not limited thereto.
  • the first light-emitting element 411, the second light-emitting element 421, and the third light-emitting element 431 may also be quantum dot light-emitting diodes (QLEDs) or other applicable light-emitting devices. There is no restriction on this.
  • the distribution density per unit area of the plurality of first light-emitting elements 411 in the first display area 11 is smaller than the distribution density per unit area of the plurality of second light-emitting elements 421 in the second display area 12, and the plurality of second light-emitting elements 421 are
  • the distribution density per unit area in the second display area 12 is smaller than the distribution density per unit area of the plurality of third light-emitting elements 431 in the third display area 13.
  • the first display area 11 and the second display area 12 may be referred to as a low-resolution area of the display substrate 01, and correspondingly, the third display area 13 may be referred to as a high-resolution area of the display substrate 01.
  • the sum of the pixel light-emitting area of the second display area 12 and the first display area 11 may be 1/8 to 1/2 of the pixel light-emitting area of the third display area 13.
  • the distribution density per unit area of the plurality of first light-emitting elements 411 in the first display region 11 may also be equal to the unit area distribution density of the plurality of second light-emitting elements 421 in the second display region 12 Density, which can be determined according to actual requirements, and the embodiment of the present disclosure does not limit this.
  • the display substrate 01 By increasing the distribution density per unit area of the light-emitting elements in the first display area 11, the second display area 12, and the third display area 13, it is possible to facilitate the display substrate 01 while ensuring that the three display areas emit light normally to display images.
  • the light on the first side of the first display area 11 passes through the first display area 11 to reach the second side, thereby facilitating the sensor provided on the second side of the display substrate 01 to sense the light.
  • the display substrate 01 may also include other structures or components, and is not limited to the structures and components described above.
  • the display substrate 01 may further include one or more barrier layers, buffer layers, etc., which are not limited in the embodiments of the present disclosure.
  • FIG. 13A is a schematic structural diagram of a 7T1C pixel circuit.
  • the aforementioned first pixel circuit 412 for example, the first sub-pixel circuit 412a and the second sub-pixel circuit 412b
  • the second pixel circuit 422 and the third pixel circuit 432 can all adopt the 7T1C pixel circuit.
  • the 7T1C pixel circuit 100 includes a first transistor CT1, a second transistor CT2, a third transistor CT3, a fourth transistor CT4, a fifth transistor CT5, a sixth transistor CT6, a seventh transistor CT7, and a memory Capacitance Cst.
  • the first transistor CT1 to the seventh transistor CT7 are all P-type transistors.
  • the first terminal of the storage capacitor Cst is connected to the first power supply voltage terminal VDD to receive the first power supply voltage V1
  • the second terminal of the storage capacitor Cst is connected to the first node N1.
  • the first end of the light emitting element EL is connected to the fourth node N4, and the second end of the light emitting element EL is connected to the second power supply voltage terminal VSS to receive the second power supply voltage V2.
  • the control terminal of the first transistor CT1 is connected to the first node N1, the first terminal of the first transistor CT1 is connected to the second node N2, and the second terminal of the first transistor CT1 is connected to the third node N3.
  • the first terminal of the second transistor CT2 is connected to the second node N2, and the second terminal of the second transistor CT2 is connected to the data signal terminal DAT to receive a data signal (for example, a data voltage) Vdata.
  • the first terminal of the third transistor CT3 is connected to the first node N1, and the second terminal of the third transistor CT3 is connected to the third node N3.
  • the first terminal of the fourth transistor CT4 is connected to the first node N1, and the second terminal of the fourth transistor CT4 is connected to the first reset signal terminal Init1 to receive the first reset signal Vinit1 provided by the first reset signal terminal Init1.
  • the first terminal of the fifth transistor CT5 is connected to the first power supply voltage terminal VDD, and the first terminal of the fifth transistor CT5 is connected to the second node N2.
  • the first terminal of the sixth transistor CT6 is connected to the fourth node N4, and the second terminal of the sixth transistor CT6 is connected to the second reset signal terminal Init2 to receive the second reset signal Vinit2.
  • the first terminal of the seventh transistor CT7 is connected to the third node N3, and the second terminal of the seventh transistor CT7 is connected to the fourth node N4.
  • control terminal GAT1 of the second transistor CT2 and the control terminal GAT2 of the third transistor CT3 are both connected to the scan signal terminal GAT (not shown in the figure)
  • the control terminal EM1 of the fifth transistor CT5 and the control terminal of the seventh transistor CT7 EM2 are all connected to the light-emitting control terminal EM (not shown in the figure)
  • the control terminal of the fourth transistor CT4 is configured to be connected to the first reset control terminal RST1
  • the control terminal of the sixth transistor CT6 is configured to be connected to the second reset control terminal RST2.
  • FIG. 13A also shows the first node N1, the second node N2, the third node N3, the fourth node N4, and the light emitting element EL.
  • FIG. 13B is a driving timing diagram of the 7T1C pixel circuit shown in FIG. 13A. As shown in FIG. 13B, each driving cycle of the 7T1C pixel circuit 100 includes a first phase t1, a second phase t2, and a third phase t3.
  • the first reset control terminal RST1 receives an active level
  • the scan signal terminal GAT, the second reset control terminal RST2 and the light emission control terminal EM all receive an invalid level.
  • the fourth transistor CT4 is turned on, the second transistor CT2, the third transistor CT3, the fifth transistor CT5, the sixth transistor CT6, and the seventh transistor CT7 are turned off; the fourth transistor CT4 is configured to receive the first reset signal (for example , Reset voltage) Vinit1, and write the first reset signal Vinit1 to the storage capacitor Cst to reset the storage capacitor Cst; the voltage of the first node N1 is Vinit1, and Vinit1 is, for example, a negative value.
  • the first transistor CT1 is turned on.
  • the scan signal terminal GAT and the second reset control terminal RST2 receive the valid level
  • the first reset control terminal RST1 and the light-emitting control terminal EM receive the invalid level
  • the first transistor CT1 to the third transistor CT3 and the sixth transistor CT6 are turned on
  • the fourth transistor CT4, the fifth transistor CT5, and the seventh transistor CT7 are turned off
  • the second transistor CT2 receives the data signal Vdata
  • the data signal Vdata is turned on
  • the first transistor CT1 and the third transistor CT3 are written to the control terminal of the first transistor CT1, and the storage capacitor Cst stores the data signal Vdata written to the control terminal of the first transistor CT1 at the control terminal of the first transistor CT1.
  • the voltage of a node N1 is Vdata+Vth; the sixth transistor CT6 is configured to receive a second reset signal (for example, a reset voltage) Vinit2, and write the second reset signal Vinit2 to the first end of the light-emitting element EL to emit light
  • a second reset signal for example, a reset voltage
  • Vinit2 The first terminal of the element EL is reset
  • Vinit2 Vinit2
  • Vinit2 is, for example, a negative value.
  • the light-emitting control terminal EM receives the valid level, and the first reset control terminal RST1, the scan signal terminal GAT, and the second reset control terminal RST2 receive the invalid level;
  • the first transistor CT1, the fifth transistor CT5, and the seventh transistor CT7 are turned on, the second transistor CT2, the third transistor CT3, the fourth transistor CT4, and the sixth transistor CT6 are turned off;
  • the first transistor CT1 is configured to be based on storage
  • the data signal for example, the data voltage
  • Vdata in the storage capacitor Cst and the received first power supply voltage V1 are controlled to flow through the first transistor CT1 and from the first power supply voltage terminal VDD to the light-emitting element EL for driving the light-emitting element
  • the driving current of EL; the voltage of the first node N1 is Vdata+Vth, and the voltage of the second node N2 is VDD;
  • the driving current Id can be expressed by the following formula:
  • k ⁇ Cox ⁇ W/L; ⁇ is the mobility of carriers in the first transistor CT1, Cox is the capacitance of the gate oxide layer of the first transistor CT1, and W/L is the channel of the first transistor CT1.
  • the width-to-length ratio of the channel Vth is the threshold voltage of the first transistor CT1, Vth is the gate-source voltage of the first transistor CT1, Vg is the gate voltage of the first transistor CT1, and Vs is the source voltage of the first transistor CT1.
  • the 7T1C pixel circuit 100 shown in FIGS. 13A and 13B has a threshold compensation function.
  • the first pixel circuit 412 (for example, the first sub-pixel circuit 412a and the second sub-pixel circuit 412b), the second pixel circuit 422, and the third pixel circuit 432 are not limited to the above 7T1C.
  • the pixel circuit may also adopt other applicable pixel circuits, which are not limited in the embodiments of the present disclosure.
  • the specific circuit structures of the first pixel circuit 412, the second pixel circuit 422, and the third pixel circuit 432 may be the same or different from each other, which may be determined according to actual requirements, which is not limited in the embodiment of the present disclosure.
  • the first switching transistor in the first pixel circuit 412, the second switching transistor in the second pixel circuit 422, and the third switching transistor in the third pixel circuit 432 may all be the seventh transistor CT7 in FIG. 13A.
  • the seventh transistor CT7 supplies an electric signal to the anode of the corresponding light emitting element EL.
  • the first light-emitting element 411 (for example, the first sub-light-emitting element 411a and the second sub-light-emitting element 411b), the second light-emitting element 421, and the third light-emitting element 431 may all be the light-emitting element EL in FIG. 13A. It can be an organic light emitting diode (OLED) or a quantum dot light emitting diode (QLED).
  • At least one embodiment of the present disclosure further provides a display device, which includes the display substrate provided by any embodiment of the present disclosure.
  • the display device can reduce the processing difficulty, improve the reliability of the electrical connection, improve the uniformity of transmitted light, and help improve the sensing effect of the under-screen sensor (such as a camera).
  • FIG. 14 is a schematic block diagram of a display device provided by at least one embodiment of the present disclosure.
  • the display device 20 includes a display substrate 210, which is a display substrate provided by any embodiment of the present disclosure, such as the aforementioned display substrate 01.
  • the display device 20 can be any electronic device with a display function, such as a smart phone, a notebook computer, a tablet computer, a TV, and the like.
  • the smart phone or tablet computer may have a full-screen design, that is, there is no peripheral area surrounding the third display area 13.
  • the smart phone or tablet computer also has an under-screen sensor (such as a camera, an infrared sensor, etc.), which can perform operations such as image shooting, distance sensing, and light intensity sensing.
  • an under-screen sensor such as a camera, an infrared sensor, etc.
  • FIG. 15 is a schematic diagram of a laminated structure of a display device provided by at least one embodiment of the present disclosure.
  • the display device 20 includes a display substrate 210, and the display substrate 210 is a display substrate provided by any embodiment of the present disclosure, such as the aforementioned display substrate 01.
  • the display device 20 further includes a sensor 220.
  • the display substrate 01 has a first side F1 for display and a second side F2 opposite to the first side F1. That is, the first side F1 is the display side, and the second side F2 is the non-display side.
  • the display substrate 01 is configured to perform a display operation on the first side F1, that is, the first side F1 of the display substrate 01 is the light emitting side of the display substrate 01, and the first side F1 faces the user.
  • the first side F1 and the second side F2 are opposed to each other in the normal direction of the display surface of the display substrate 01.
  • the sensor 220 is disposed on the second side F2 of the display substrate 01, and the sensor 220 is configured to receive light from the first side F1.
  • the sensor 220 and the first display area 11 overlap in the normal direction of the display surface of the display substrate 01 (for example, the direction perpendicular to the display substrate 01), and the sensor 220 may receive and process the data passing through the first display area 11.
  • the optical signal may be visible light, infrared light, etc.
  • the first display area 11 allows light from the first side F1 to be at least partially transmitted to the second side F2.
  • the first display area 11 is not provided with a pixel circuit. In this case, the light transmittance of the first display area 11 can be improved.
  • the orthographic projection of the sensor 220 on the display substrate 01 at least partially overlaps the first display area 11.
  • the orthographic projection of the sensor 220 on the display substrate 01 is located in the first display area 11.
  • the orthographic projection of the sensor 220 on the display substrate 01 is similar to the first display. Area 11 partially overlaps. At this time, since the light can propagate to the sensor 220 laterally, it is not necessary that the sensor 220 is completely located at a position corresponding to the first display area 11.
  • the first display area 11 can be reduced.
  • the element in the shielding of the light signal incident to the first display area 11 and irradiated to the sensor 220 can improve the signal-to-noise ratio of the image output by the sensor 220.
  • the first display area 11 may be referred to as a high light transmission area of a low resolution area of the display substrate 01
  • the second display area 12 may be referred to as a transition area.
  • the senor 220 may be an image sensor, which may be used to collect an image of the external environment facing the light-collecting surface of the sensor 220, and may be, for example, a CMOS image sensor or a CCD image sensor.
  • the sensor 220 may also be an infrared sensor, a distance sensor, or the like.
  • the sensor 220 may be implemented as a camera of a mobile terminal such as a mobile phone, a notebook, etc., and may also include, for example, a lens, a mirror, or an optical waveguide as required.
  • Optical devices to modulate the optical path may be implemented as a camera of a mobile terminal such as a mobile phone, a notebook, etc., and may also include, for example, a lens, a mirror, or an optical waveguide as required. Optical devices to modulate the optical path.
  • the senor 220 may include photosensitive pixels arranged in an array.
  • each photosensitive pixel may include a photosensitive detector (for example, a photodiode, a phototransistor) and a switching transistor (for example, a switching thin film transistor).
  • the photodiode can convert the light signal irradiated on it into an electrical signal
  • the switching transistor can be electrically connected with the photodiode to control whether the photodiode is in the state of collecting the light signal and the time for collecting the light signal.
  • the anode of the first light-emitting element 411 adopts a stacked structure of ITO/Ag/ITO.
  • the first display area 11 only the anode of the first light-emitting element 411 does not transmit light, that is, it is used for
  • the traces for driving the first light-emitting element 411 are configured as transparent conductive traces. In this case, not only can the light transmittance of the first display area 11 be further improved, but also the diffraction and reflection caused by various elements in the first display area 11 can be reduced.
  • the display device 20 may further include more components and structures, which are not limited in the embodiments of the present disclosure.
  • the technical effects and detailed description of the display device 20 reference may be made to the above description of the display substrate 01, which will not be repeated here.

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Abstract

Sont décrits ici un substrat d'affichage et un appareil d'affichage. Le substrat d'affichage (01) comprend une zone d'affichage (10). La zone d'affichage (10) comprend une première zone d'affichage (11), une seconde zone d'affichage (12) et une première ligne de connexion (110). La première zone d'affichage (11) comprend un premier élément électroluminescent (411). La seconde zone d'affichage (12) comprend un premier circuit de pixel (412). La première ligne de connexion (110) est connectée électriquement à un premier circuit de sous-pixel (412a) et à une anode d'un premier sous-élément électroluminescent (411a). La première ligne de connexion (110) est située au niveau d'une première couche de connexion (21), et l'anode du premier sous-élément électroluminescent (411a) est connectée électriquement à la première ligne de connexion (110) au moyen d'un premier trou d'interconnexion (H1) qui pénètre dans une première couche isolante (31) et une seconde couche isolante (32). La forme en coupe transversale du premier trou d'interconnexion (H1) dans un plan perpendiculaire au substrat d'affichage (01) est une forme de bossage inversé, et dans le premier trou d'interconnexion (H1), l'orifice d'ouverture de la seconde couche isolante (32) est plus grand qu'un orifice d'ouverture de la première couche isolante (31). L'anode du premier sous-élément électroluminescent (411a) comprend une première structure de rainure (GR1) située dans le premier trou d'interconnexion (H1), le fond de la première structure de rainure (GR1) étant en contact avec la première ligne de connexion (110), de façon à réaliser une connexion électrique. Selon le substrat d'affichage (01), la difficulté de traitement peut être réduite, et la fiabilité de connexion électrique et l'uniformité de la lumière transmise sont améliorées.
PCT/CN2021/094030 2020-06-23 2021-05-17 Substrat d'affichage et appareil d'affichage WO2021258910A1 (fr)

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KR1020227016393A KR20230026978A (ko) 2020-06-23 2021-05-17 디스플레이 기판 및 디스플레이 장치
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US20230045968A1 (en) 2023-02-16
KR20230026978A (ko) 2023-02-27
CN113838888A (zh) 2021-12-24

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