WO2021258305A1 - 一种铁电存储器及存储设备 - Google Patents

一种铁电存储器及存储设备 Download PDF

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Publication number
WO2021258305A1
WO2021258305A1 PCT/CN2020/097809 CN2020097809W WO2021258305A1 WO 2021258305 A1 WO2021258305 A1 WO 2021258305A1 CN 2020097809 W CN2020097809 W CN 2020097809W WO 2021258305 A1 WO2021258305 A1 WO 2021258305A1
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Prior art keywords
voltage
ferroelectric
semiconductor layer
memory
electrode
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PCT/CN2020/097809
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English (en)
French (fr)
Inventor
许俊豪
卜思童
侯朝昭
张瑜
张燕燕
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华为技术有限公司
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Priority to CN202080101670.6A priority Critical patent/CN115699181A/zh
Priority to PCT/CN2020/097809 priority patent/WO2021258305A1/zh
Publication of WO2021258305A1 publication Critical patent/WO2021258305A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors

Definitions

  • This application relates to the field of data storage technology, and in particular to a ferroelectric memory and storage device.
  • DRAM dynamic random access memory
  • FRAM ferroelectric random access memory
  • Ferroelectric random access memory can also be called ferroelectric memory. It is a kind of production based on the principle that the polarization direction of ferroelectric materials changes under the action of an electric field. The memory has the advantages of fast reading and writing speed, low power consumption and small area.
  • the memory cell in a ferroelectric memory is usually a ferroelectric field-effect transistor (ferroelectric field-effect transistor) based on a metal-ferroelectrics-insulator-semiconductor (MFIS) structure.
  • FeFET ferroelectric field-effect transistor
  • the ferroelectric memory based on the FeFET structure has an interface between the ferroelectric layer and the insulating layer that is easy to trap charges, which causes defects in the interface, which in turn leads to poor durability of the ferroelectric memory.
  • the present application provides a ferroelectric memory and a storage device, which are used to reduce interface defects in the ferroelectric memory and improve the durability of the ferroelectric memory.
  • a ferroelectric memory includes at least one memory cell.
  • Each memory cell includes: a first electrode, a second electrode, a third electrode, a ferroelectric layer, and a first semiconductor layered Layer, the second semiconductor layer and the third semiconductor layer, the semiconductor material of each semiconductor layer may be silicon or silicon germanium, etc.; wherein, one of the first semiconductor layer and the second semiconductor layer is an N-type semiconductor, and the other is a P Type semiconductor (for example, the first semiconductor layer is an N-type semiconductor and the second semiconductor layer is a P-type semiconductor; or, the first semiconductor layer is a P-type semiconductor and the second semiconductor layer is an N-type semiconductor), so that the first semiconductor layer and A PN junction is formed between the second semiconductor layers; in addition, a first electrode is provided on the side of the first semiconductor layer away from the second semiconductor layer, and a third electrode is provided on the side of the third semiconductor layer away from the second semiconductor layer.
  • the electrode material of the electrode and the third electrode can be a compound of silicon and metal, such as titanium silicide, zirconium silicide, tantalum silicide, tungsten silicide, etc.; the ferroelectric layer surrounds all or part of the side surfaces of the third semiconductor layer, and the third semiconductor layer
  • the side surface can refer to the surface parallel to the depth direction (or axis direction) of the third semiconductor layer, or refer to the circumference of the third semiconductor layer, the second electrode surrounds the ferroelectric layer, and the electrode material of the second electrode can be metal Materials such as aluminum (Al), copper (Cu), tungsten (W), and tungsten nitride (WN), etc.
  • each memory cell can be equivalent to a memory cell with a metal-ferroelectrics-semiconductor (MFS) structure controlled by the polarization of the ferroelectric layer.
  • MFS metal-ferroelectrics-semiconductor
  • the ferroelectric layer only surrounds all or part of the side surface of the third semiconductor layer, but does not surround the first semiconductor layer and the second semiconductor layer, so that when writing data to the memory cell subsequently, you can The influence of the first electrode on the polarization state of the ferroelectric material is reduced, thereby reducing the risk of miswriting of the ferroelectric memory.
  • the third semiconductor layer is intrinsic semiconductor, for example, the third semiconductor layer is intrinsic Si.
  • the third semiconductor layer is a P-type semiconductor; or, when the second semiconductor layer is an N-type semiconductor, the third semiconductor layer It is an N-type semiconductor.
  • the production of the second semiconductor layer and the third semiconductor layer can be achieved in one step, thereby simplifying the iron
  • the second semiconductor layer and the third semiconductor layer are both P-type semiconductor or N-type semiconductor, which also reduces the contact resistance of the third electrode; at the same time, the carriers originally distributed on the surface of the third semiconductor layer It can be distributed in the bulk of the third semiconductor layer, so that the interaction between the carriers and the traps in the ferroelectric layer can be reduced, and the durability of the ferroelectric memory can be improved.
  • the first electrode is a bottom electrode
  • the second electrode is a gate electrode
  • the third electrode is a top electrode
  • the ferroelectric layer is a ferroelectric material or an antiferroelectric material.
  • the ferroelectric material may be hafnium zirconate (HfZrO 2 ), and the antiferroelectric material may be zirconium. Acid (ZrO 2 ).
  • HfZrO 2 hafnium zirconate
  • ZrO 2 zirconium. Acid
  • the polarization state, the positive residual polarization state with different polarization intensities can also be obtained to meet different design requirements and improve the design flexibility of the ferroelectric memory; in addition, when the ferroelectric layer is an antiferroelectric material , Due to the high stability of the antiferroelectric material, the durability of the ferroelectric memory will be further improved.
  • the absolute value of the voltage difference between the second electrode and the third electrode is set to the first voltage, and the first voltage is greater than or equal to the specified voltage
  • the specified voltage may refer to the critical voltage at which the polarization direction of the ferroelectric layer is reversed; when reading data to the memory cell, the voltage difference between the first electrode and the third electrode is set to the second voltage, the second voltage Less than the specified voltage.
  • the ferroelectric memory includes a memory cell array with m rows and n columns, m first voltage lines, m second voltage lines, and n third voltage lines, and the memory cell array It includes a plurality of memory cells, where m and n are positive integers; wherein, the first electrodes of n memory cells belonging to the same row in the memory cell array are connected to one of the m first voltage lines, and the The first electrodes of the memory cells are connected to different first voltage lines, so that m rows are correspondingly connected to m first voltage lines; the second electrodes of n memory cells belonging to the same row in the memory cell array are connected to m second voltage lines In one of the second voltage lines, the second electrodes of memory cells in different rows are connected to different second voltage lines, so m rows are correspondingly connected to m second voltage lines; m memory cells belonging to the same column in the memory cell array The third electrode of is connected to one of the n third voltage lines, and the third electrodes of the memory cells in different columns
  • the ferroelectric memory can realize the area of a single memory cell based on the MFS structure of 4F 2 through the memory cell array, which is compared with the area of 8F 2 of a single memory cell based on the capacitor structure in the prior art DRAM.
  • the area of the ferroelectric memory can be greatly reduced.
  • the first voltage line is the source line SL
  • the second voltage line is the word line WL
  • the third voltage line is the bit line BL, that is, in the memory cell array, they belong to the same row.
  • the first electrodes of the n memory cells are connected to the same SL
  • the second electrodes of the n memory cells belonging to the same row are connected to the same WL
  • the third electrodes of the m memory cells belonging to the same column are connected to the same BL.
  • the voltage of the first voltage line when writing data to a memory cell in the memory cell array, is set to the first voltage, and the first voltage is greater than or equal to the specified voltage.
  • setting the voltage of the first voltage line to the first voltage can ensure that all memory cells in the memory cell array are in a zero bias or reverse bias state, so as to reduce leakage current when writing data.
  • the second voltage line connected to the n memory cells included in the first row when writing data to n memory cells included in the first row of the memory cell array in parallel, the second voltage line connected to the n memory cells included in the first row The voltage of is set to zero or the first voltage, the voltage of the second voltage line connected to the memory cells included in the remaining rows except the first row in m rows is set to one-half of the first voltage, and the first row is m For any of the rows, the first voltage is greater than or equal to the specified voltage.
  • parallel data writing of multiple memory cells included in the same row in the memory cell array can be implemented, thereby greatly improving the read and write efficiency of the ferroelectric memory.
  • the second voltage line connected to the n memory cells included in the first row The voltage of is set to zero or four-thirds of the first voltage, and the voltage of the second voltage line connected to the memory cells included in the remaining rows except the first row in m rows is set to two-thirds of the first voltage ,
  • the first row is any row of m rows, and the first voltage is greater than or equal to the specified voltage.
  • the voltage of the first voltage line connected to the n memory cells included in the first row is The voltage is set to zero, the voltage of the first voltage line connected to the memory cells included in the remaining rows except the first row in m rows is set to the second voltage, the voltage of the second voltage line is set to zero, and the third voltage line The voltage of is set to the second voltage, and the second voltage is less than the specified voltage.
  • a storage device in a second aspect, includes: a circuit board, and a ferroelectric memory connected to the circuit board, the ferroelectric memory is provided by the first aspect or any one of the possible implementation manners of the first aspect Ferroelectric memory.
  • a storage device in a third aspect, includes a controller and a ferroelectric memory, the controller is used to control the reading and writing of the ferroelectric memory, the ferroelectric memory is the first aspect or any one of the first aspect Possible implementations of the ferroelectric memory provided.
  • a non-transitory computer-readable storage medium for use with a computer.
  • the computer has software for designing integrated circuits, and one or more computer-readable data structures are stored on the computer-readable storage medium.
  • the or multiple computer-readable data structures include photomask data used to manufacture the above-mentioned first aspect or the ferroelectric memory provided by any possible implementation of the first aspect.
  • any of the storage devices provided above and the non-transitory computer-readable storage medium used with a computer include the same or corresponding features of the ferroelectric memory provided above.
  • the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding integrated circuits provided above, which will not be repeated here.
  • FIG. 1 is a schematic structural diagram of a storage device provided by an embodiment of the application.
  • FIG. 2 is a schematic diagram of a ferroelectric memory provided by an embodiment of the application.
  • FIG. 3 is a schematic diagram of a storage unit provided by an embodiment of the application.
  • FIG. 4 is a cross-sectional view of a storage unit provided by an embodiment of the application.
  • FIG. 5 is a cross-sectional view of another storage unit provided by an embodiment of the application.
  • FIG. 6 is a cross-sectional view of another storage unit provided by an embodiment of the application.
  • FIG. 7 is a schematic diagram of a read current provided by an embodiment of the application.
  • FIG. 8 is a schematic diagram of yet another ferroelectric memory provided by an embodiment of the application.
  • FIG. 9 is a schematic diagram of another ferroelectric memory provided by an embodiment of the application.
  • FIG. 10 is a schematic diagram of a P-V curve provided by an embodiment of this application.
  • FIG. 11 is a schematic diagram of yet another ferroelectric memory provided by an embodiment of the application.
  • circuits/components used with the term “for” include hardware, such as circuits that perform operations, and the like.
  • At least one of a, b, or c can mean: a, b, c, a and b, a and c, b and c or a, b and c, where a, b, and c can be It can be single or multiple.
  • words such as “first” and “second” do not limit the quantity and order.
  • FIG. 1 is a schematic structural diagram of a storage system provided by an embodiment of the application.
  • the storage system may include a ferroelectric memory; optionally, the storage system may also include a CPU, a cache, and a controller. Wait. Wherein, the CPU, the buffer, the controller, and the ferroelectric memory can be integrated together, and the ferroelectric memory can be coupled with the buffer through the controller, and coupled with the CPU through the buffer.
  • the ferroelectric memory includes a memory cell array with m rows and n columns, m first voltage lines, m second voltage lines, and n third voltage lines.
  • Voltage line the memory cell array includes a plurality of memory cells, m and n are positive integers.
  • the values of m and n are both equal to 3 as an example for illustration.
  • the first voltage line may be a source line (SL)
  • the second voltage line may be a word line (WL)
  • the third voltage line may be a bit line (BL).
  • n memory cells belonging to the same row can be connected to one SL in m SLs and one WL in m WLs.
  • Memory cells in different rows are connected to different SLs and WLs, which belong to the same column.
  • the m memory cells can be connected to one BL of the m BLs, and memory cells in different columns are connected to different BLs.
  • the following takes a memory cell in the memory cell array of the ferroelectric memory as an example to describe the structure of the memory cell in detail.
  • FIG. 3 is a schematic structural diagram of a storage unit provided by an embodiment of the application.
  • (a) in FIG. 3 is a perspective view of the storage unit
  • (b) in FIG. 3 is a perspective view as shown in (a) in FIG. 3 A three-dimensional view taken vertically downward along the line HH'.
  • the memory cell includes: a first electrode 1, a second electrode 2, a third electrode 3, a ferroelectric layer 4, and a first semiconductor layer 10, a second semiconductor layer 20, and a third semiconductor layer 30 that are stacked. .
  • one of the first semiconductor layer 10 and the second semiconductor layer 20 is an N-type semiconductor, and the other is a P-type semiconductor, that is, a PN junction is formed between the first semiconductor layer 10 and the second semiconductor layer 20.
  • the first semiconductor layer 10 is an N-type semiconductor
  • the second semiconductor layer 20 is a P-type semiconductor
  • the first semiconductor layer 10 is a P-type semiconductor
  • the second semiconductor layer 20 is an N-type semiconductor.
  • the semiconductor material in the first semiconductor layer 10 and the second semiconductor layer 20 may be silicon (Si), silicon germanium (SiGe), or the like.
  • the first semiconductor layer 10 is P-type Si (P-type Si) and the second semiconductor layer 20 is N-type Si (N-type Si) as an example for description.
  • a first electrode 1 is provided on the side of the first semiconductor layer 10 away from the second semiconductor layer 20, and the axis distance of the first electrode 1 may be equal to or smaller than that of the first semiconductor layer 10.
  • the third semiconductor layer 30 A third electrode 3 is provided on the side away from the second semiconductor layer 20, and the axis distance of the third electrode 3 may be equal to or smaller than the axis distance of the third semiconductor layer 30.
  • the electrode materials of the first electrode 1 and the third electrode 3 may be a compound of silicon and metal, such as titanium silicide, zirconium silicide, tantalum silicide, and tungsten silicide.
  • the ferroelectric layer 4 surrounds all or part of the side surface of the third semiconductor layer 30, and the second electrode 2 surrounds the ferroelectric layer 4, where the side surface of the third semiconductor layer 30 may refer to the depth of the third semiconductor layer 30. A surface whose direction (or axis direction) is parallel, or refers to the circumference of the third semiconductor layer 30.
  • the ferroelectric layer 4 may surround all sides of the third semiconductor layer 30, or may only surround part of the sides of the third semiconductor layer 30. In FIG. 3, the ferroelectric layer 4 surrounds all the sides of the third semiconductor layer 30 as an example for illustration. In FIG. 4, the ferroelectric layer 4 surrounds a part of the side surface of the third semiconductor layer 30 as an example for description.
  • the ferroelectric layer 4 here can be a ferroelectric material or an antiferroelectric material.
  • the ferroelectric material can be hafnium zirconate (HfZrO 2 ), and the antiferroelectric material can be zirconate (ZrO 2 ).
  • Films formed with ferroelectric materials can be called ferroelectric films, and films formed with antiferroelectric materials can be called antiferroelectric films.
  • ferroelectric films and antiferroelectric films can be collectively referred to as ferroelectric layers ( It can also be called a ferroelectric thin film).
  • the electrode material of the second electrode 2 here may be a metal material, such as aluminum (Al), copper (Cu), tungsten (W), tungsten nitride (WN), and the like.
  • each memory cell can be equivalent to a memory cell with a metal-ferroelectrics-semiconductor (MFS) structure controlled by the polarization of the ferroelectric layer 4 Therefore, there is no interface between the ferroelectric layer and the insulating layer that is easy to trap charges in the memory cell, thereby reducing interface defects and improving the durability of the ferroelectric memory.
  • MFS metal-ferroelectrics-semiconductor
  • the ferroelectric layer 4 only surrounds all or part of the side surface of the third semiconductor layer 30, but does not surround the first semiconductor layer 10 and the second semiconductor layer 20, so that subsequent writing to the memory cell During data data, the influence of the first electrode 1 on the polarization state of the ferroelectric material can be reduced, thereby reducing the risk of miswriting of the ferroelectric memory.
  • the ferroelectric layer 4 is made of ferroelectric material or antiferroelectric material, by changing the direction of the built-in electric field introduced into the ferroelectric material or antiferroelectric material, a negative remanent polarization state with different polarization intensities can be obtained. It is also possible to obtain positive residual polarization states with different polarization intensities to meet different design requirements and improve the design flexibility of the ferroelectric memory.
  • the first semiconductor layer 10, the second semiconductor layer 20, and the third semiconductor layer 30 may be columnar, and the cross section of the columnar may be any of closed figures such as a circle, an ellipse, or a polygon, for example,
  • the polygon may be a triangle, a quadrilateral, a pentagon, a hexagon, etc., which is not specifically limited in the embodiment of the present application.
  • the cylindrical cross-section is circular as an example for description.
  • the third semiconductor layer 30 is intrinsic semiconductor.
  • the third semiconductor layer 30 is intrinsic Si.
  • the third semiconductor layer 30 is a P-type semiconductor, for example, the second semiconductor layer 20 and the third semiconductor layer 30 are both P-type Si; or
  • the second semiconductor layer 20 is an N-type semiconductor, the third semiconductor layer 30 is an N-type semiconductor.
  • the second semiconductor layer 20 and the third semiconductor layer 30 are both N-type Si.
  • the production of the second semiconductor layer 20 and the third semiconductor layer 30 can be realized in one step, thereby simplifying the ferroelectric memory The production steps.
  • the second semiconductor layer 20 and the third semiconductor layer 30 are both P-type semiconductor or N-type semiconductor, which can also reduce the contact resistance of the third electrode 3; at the same time, the carriers originally distributed on the surface of the third semiconductor layer 30 can be Distributed in the bulk of the third semiconductor layer 30, the interaction between the carriers and the traps in the ferroelectric layer 4 can be reduced, and the durability of the ferroelectric memory can be improved.
  • the first semiconductor layer 10 is P-type Si
  • the second semiconductor layer 20 and the third semiconductor layer 30 are both N-type Si as an example for description.
  • (A) in FIG. 4 is a perspective view of the storage unit, and (b) in FIG. 4 is a perspective view after the perspective view shown in (a) in FIG. 4 is cut vertically downward along the line HH' direction.
  • the first electrode 1 may be a bottom electrode
  • the second electrode 2 may be a gate electrode
  • the third electrode 3 may be a top electrode.
  • FIG. 5 is a cross-sectional view of the memory cell shown in (a) of FIG. 3 after being cut vertically downward along the line HH'.
  • the first electrode 1 and the third electrode 3 can be grounded, and a negative bias voltage can be applied to the second electrode 2.
  • V W the voltage difference obtained by subtracting the voltage of the second electrode 2 from the voltage of the third electrode 3 is the first voltage V W.
  • the ferroelectric layer 4 is negatived, and a large amount of positive With charge, the contact barrier between the third semiconductor layer 30 and the ferroelectric layer 4 is lowered, so that the memory cell is written in a low resistance state, that is, data "0" is written.
  • the first electrode 1 and the third electrode 3 can be grounded, and a positive bias voltage V W can be applied to the second electrode 2 to The voltage difference obtained by subtracting the voltage of the third electrode 3 from the voltage of the second electrode 2 is the first voltage V W.
  • the contact barrier between the semiconductor layer 30 and the ferroelectric layer 4 is increased, so that the memory cell is written in a high resistance state, that is, data "1" is written.
  • P in FIG. 5 represents the polarization direction of the ferroelectric layer 4.
  • the data “0” corresponds to the low resistance state and the data “1” corresponds to the high resistance state as an example for description.
  • the data “0” can also correspond to the high resistance state
  • data "1” corresponds to the low resistance state, which is not limited in the embodiment of the present application.
  • FIG. 6 is a cross-sectional view of the storage unit shown in (a) of FIG. 3 after being cut vertically downward along the line HH'.
  • the storage unit when reading data to the storage unit may be a third electrode to the first electrode 3 between the second voltage V R, and reads the third electrode of the current I R 3; FIG. 6 (a), when the value of the I R is larger than the threshold, the data can be determined that the memory cell is "0" (in this case labeled I R I R_0), because it is written in the memory cell is the data "0", the memory cell is low resistance state, so that the current phase of the read current is large, "1" is written to the data; in FIG.
  • I R when the I R is When the value is less than the above threshold, it can be determined that the data in the memory cell is "1" (I R at this time is marked as I R_1 ), because when the memory cell is written with data "1", the memory cell It is a high-impedance state, so the read current is smaller than the current when data "0" is written. 7 is shown in FIG. "1"
  • a current I R of the read time may be schematic data "0" is written and the data storage unit, particularly when the second voltage V R at about [-2V, 0.4 when V] interval, current I R V R increases as the second voltage decreases, when the second voltage V R at about [0.4V, 2V] interval, a second voltage as the current I R V R Increase with the increase.
  • connection relationship between the memory cell array in the ferroelectric memory shown in FIG. 2 and m first voltage lines, m second voltage lines, and n third voltage lines is specifically As described below.
  • the first electrodes 1 of n memory cells belonging to the same row in the memory cell array are connected to the same first voltage line, and the first electrodes 1 of memory cells in different rows are connected to different first voltage lines, so that m rows correspond to Connect m first voltage lines.
  • the second electrodes of n memory cells belonging to the same row are connected to the same second voltage line, and the second electrodes 2 of memory cells in different rows are connected to different second voltage lines, so that m rows are correspondingly connected to m The second voltage line.
  • the third electrodes 3 of m memory cells belonging to the same column are connected to the same third voltage line, and the third electrodes 3 of memory cells in different columns are connected to different third voltage lines, so that n columns are correspondingly connected to n A third voltage line.
  • the first voltage line is parallel to the second voltage line
  • the third voltage line is perpendicular to both the first voltage line and the second voltage line.
  • the first voltage line may be a source line (SL)
  • the second voltage line may be a word line (WL)
  • the third voltage line may be a bit line (BL). That is, in the memory cell array, the first electrodes 1 of n memory cells belonging to the same row are connected to the same SL, the second electrodes 2 of n memory cells belonging to the same row are connected to the same WL, and m memory cells belonging to the same column are connected to the same SL.
  • the third electrode 3 of the unit is connected to the same BL.
  • the ferroelectric memory shown in Figure 2 by applying different voltages on m first voltage lines, m second voltage lines, and n third voltage lines, it is possible to read the memory cells in the ferroelectric memory.
  • Write that is, write data or read data to the storage unit in the ferroelectric memory.
  • the voltage applied to m first voltage lines, m second voltage lines, and n third voltage lines can be controlled by the controller.
  • the first voltage line is SL
  • the second voltage line is WL
  • the third voltage line is BL as an example.
  • the first voltage is greater than or equal to the specified voltage
  • the second voltage is less than the specified voltage.
  • the specified voltage of may refer to the critical voltage at which the polarization direction of the ferroelectric layer 4 is reversed, and the first row in the memory cell array may refer to any row of m rows. In the following Figure 8, Figure 9, and Figure 11, the row where the five-pointed star is located represents the first row.
  • the voltages of the m SLs can be set to the first voltage V W , and the first voltage V W is greater than or equal to the specified voltage In this way, it can be ensured that all memory cells in the memory cell array are in a zero-bias or reverse-bias state, so as to reduce the leakage current when writing data.
  • the writing of data "0" and "1" is realized by setting the voltage difference between the WL and BL connected to the memory cell in the memory cell array.
  • the memory cell when the voltage difference between WL and BL connected to a memory cell is set to a negative first voltage -V W , the memory cell is written as data "0"; when a memory cell is connected When the voltage difference between WL and BL is set to a positive first voltage V W , the memory cell is written as data "1"; when a memory cell is connected to the voltage difference between WL and BL is set to When one half of the first voltage is 1/2V W , the state of the memory cell remains unchanged.
  • the voltage of the WL connected to the n memory cells included in the first row may be set to zero. Or the first voltage V W.
  • the memory cell connected to the BL is written as data "1"
  • the state of the memory cell connected to the BL remains unchanged.
  • the voltage of the WL corresponding to the first row is set to the first voltage V W
  • the memory cell connected to the BL is written as data "0”
  • the voltage of a BL is set to zero, the state of the memory cell connected to the BL remains unchanged.
  • the voltage of the WL connected to the memory cells in the remaining rows except the first row included in the m rows of the memory cell array can be set to one-half of the first voltage 1/2V W , that is, unselected Connect WL to 1/2V W so that the operating voltage of the unselected memory cell is 0, 1/2V W or -1/2V W.
  • the method of writing data described in FIG. 8 can be referred to as the V/2 method.
  • the voltage of the WL connected to the n memory cells included in the first row may be set to zero. Or four-thirds of the first voltage 4/3V W. Among them, when the voltage of the WL corresponding to the first row is set to 4/3V W , if the voltage of a certain BL is set to one-third of the first voltage 1/3V W , then the memory cell connected to the BL It is written as data "1". If the voltage of a certain BL is set to the first voltage V W , the state of the memory cell connected to the BL remains unchanged.
  • the voltage of the WL corresponding to the first row is set to zero, if the voltage of a certain BL is set to the first voltage V W , the memory cell connected to the BL is written as data "1", if a certain BL The voltage of is set to one third of the first voltage 1/3V W , then the state of the memory cell connected to the BL remains unchanged.
  • the voltage of the WL connected to the memory cells included in the remaining rows except the first row in the m rows of the memory cell array can be set to two-thirds of the first voltage 2/3V W , that is, unselected Connect WL to 2/3V W , so that the operating voltage of the unselected memory cell is 1/3V W or -1/3V W.
  • the method of writing data described in FIG. 9 can be referred to as the V/3 method.
  • data can also be written to m memory cells included in a certain column in the memory cell array in parallel.
  • the specific process is the same as the process in FIG. 8 or FIG. Similarly, the embodiments of the present application will not be repeated here.
  • the ferroelectric layer 4 in the memory cell is made of antiferroelectric material
  • the relationship between the polarization P of the ferroelectric layer 4 and the applied voltage V is shown in (c) and (d) in Figure 10, at this time
  • the selected memory cell is written with data "0" when the first voltage V W with a positive voltage V is applied, and the data "0" is written with the selected memory cell when the first voltage -V W with a negative voltage is applied.
  • the unselected memory cells retain the original data "0" or "1".
  • the applied voltage V in FIG. 10 may refer to the voltage applied between the second electrode 2 and the third electrode 3.
  • the voltage of the SL connected to the n memory cells included in the first row may be set to zero.
  • the voltage of the SL connected to the memory cells included in the remaining rows except the first row in the m rows of the memory cell array can be set to the second voltage V R , and the voltages of all WLs are set to zero, All voltages BL are set equal to the second voltage V R, at this time, the first electrode comprises a first row of n memory cells is the voltage difference between V R is set to 1 and the third electrode 3, so as to read
  • the current corresponding to the output data "0" or "1” the voltage difference between the first electrode 1 and the third electrode 3 of the memory cells included in the remaining rows other than the first row is set to zero, so that no Leakage current.
  • the reading and writing methods described in FIGS. 8 to 11 can realize parallel read and write of the same WL or the same BL in the memory cell array, that is, the same row or the same row Multiple storage units in the column write data or read data in parallel, thereby greatly improving the read and write efficiency of the ferroelectric memory.
  • an embodiment of the present application further provides a storage device, which includes a circuit board and a ferroelectric memory connected to the circuit board.
  • the ferroelectric memory may be any of the ferroelectric memories provided above.
  • the circuit board may be a printed circuit board (PCB), of course, the circuit board may also be a flexible circuit board (FPC), etc., and the circuit board is not limited in this embodiment.
  • the storage device is different types of user equipment or terminal devices such as computers, mobile phones, tablet computers, wearable devices, and in-vehicle devices; the storage devices may also be network devices such as base stations.
  • the storage device further includes a packaging substrate, the packaging substrate is fixed on the printed circuit board PCB by solder balls, and the ferroelectric memory is fixed on the packaging substrate by solder balls.
  • an embodiment of the present application also provides a storage device that includes a controller and a ferroelectric memory, and the controller is used to control reading and writing in the ferroelectric memory, and the ferroelectric memory may be the one provided above Any kind of ferroelectric memory.
  • a non-transitory computer-readable storage medium for use with a computer, the computer has software for designing integrated circuits, and the computer-readable storage medium stores one or more Computer-readable data structure, one or more computer-readable data structures include photomask data used to manufacture any of the ferroelectric memories provided above.

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Abstract

一种铁电存储器，该铁电存储器包括至少一个存储单元，每个存储单元包括：第一电极（1），第二电极（2），第三电极（3），铁电层（4），以及层叠设置的第一半导体层（10）、第二半导体层（20）和第三半导体层（30）；其中，第一半导体层（10）和第二半导体层（20）之间形成PN结，第一半导体层（10）远离第二半导体层（20）的一侧设置有第一电极（1），第三半导体层（30）远离第二半导体层（20）的一侧设置有第三电极（3），铁电层（4）包围第三半导体层（30）的全部侧面或者部分侧面，第二电极（2）包围铁电层（4）。这样后续在向该存储单元读写数据时，可以降低铁电层（4）的极化对于第一半导体层（10）和第二半导体层（20）形成的PN结的影响，从而有利于提升该铁电存储器的耐久性。

Description

一种铁电存储器及存储设备 技术领域
本申请涉及数据存储技术领域，尤其涉及一种铁电存储器及存储设备。
背景技术
目前，动态随机存取存储器(dynamic random access memory，DRAM)已成为高性能运算不可或缺的主要存储器，每年市场对于DRAM的容量需求都呈指数增长。但是，DRAM在工艺上只能实现14nm节点的微缩，对于更大容量的存储需求，只能使用多个DRAM芯片的叠加来实现，这样会造成整个存储器的面积、成本和功耗都较大的问题。因此，铁电随机存储器(ferroelectric random access memory，FRAM)应用而生，铁电随机存储器也可称为铁电存储器，是利用铁电材料在电场作用下极化方向发生改变的原理制作的一种存储器，具有读写速率快、功耗低和面积小等优点。
现有技术中，铁电存储器中的存储单元通常是基于金属-铁电层-绝缘层-半导体层(metal-ferroelectrics-insulator-semiconductor，MFIS)结构的铁电场效应晶体管(ferroelectric field-effect transistor，FeFET)。但是，这种基于FeFET结构的铁电存储器，由于存在容易俘获电荷的铁电层-绝缘层的界面，从而会使该界面产生缺陷，进而导致铁电存储器的耐久性较差。
发明内容
本申请提供一种铁电存储器及存储设备，用于减小铁电存储器中的界面缺陷，提高该铁电存储器的耐久性。
为达到上述目的，本申请采用如下技术方案：
第一方面，提供一种铁电存储器，该铁电存储器包括至少一个存储单元，每个存储单元包括：第一电极，第二电极，第三电极，铁电层，以及层叠设置的第一半导体层、第二半导体层和第三半导体层，每个半导体层的半导体材料可以为硅或者硅锗等；其中，第一半导体层和第二半导体层中的一个为N型半导体、另一个为P型半导体(比如，第一半导体层为N型半导体，第二半导体层为P型半导体；或者，第一半导体层为P型半导体，第二半导体层为N型半导体)，这样第一半导体层和第二半导体层之间形成PN结；另外，第一半导体层远离第二半导体层的一侧设置有第一电极，第三半导体层远离第二半导体层的一侧设置有第三电极，第一电极和第三电极的电极材料可以是硅和金属的化合物，比如，硅化钛、硅化锆、硅化钽和硅化钨等；铁电层包围第三半导体层的全部侧面或者部分侧面，第三半导体层的侧面可以是是指与第三半导体层的深度方向(或者轴线方向)平行的表面，或者是指第三半导体层的四周，第二电极包围铁电层，第二电极的电极材料可以为金属材料，比如，铝(Al)、铜(Cu)、钨(W)和氮化钨(WN)等。
上述技术方案提供的铁电存储器中，每个存储单元可以等效为一个由铁电层极化控制的金属-铁电层-半导体层(metal-ferroelectrics-semiconductor，MFS)结构的存储单元，该存储单元中不存在容易俘获电荷的铁电层-绝缘层的界面，从而会减小界面缺 陷，提高该铁电存储器的耐久性。同时，在每个存储单元中，铁电层仅包围第三半导体层的全部侧面或者部分侧面，而未包围第一半导体层和第二半导体层，这样后续在向该存储单元写数据时，可以降低第一电极对铁电材料极化状态的影响，进而降低铁电存储器误写的风险。
在第一方面的一种可能的实现方式中，第三半导体层为本征半导体，比如，第三半导体层为本征Si。
在第一方面的一种可能的实现方式中，当第二半导体层为P型半导体时，第三半导体层为P型半导体；或者，当第二半导体层为N型半导体时，第三半导体层为N型半导体。上述可能的实现方式中，当第二半导体层和第三半导体层同为P型半导体或者N型半导体时，通过一个步骤即可实现第二半导体层和第三半导体层的制作，从而简化该铁电存储器的制作步骤；此外，第二半导体层和第三半导体层同为P型半导体或者N型半导体还降低第三电极的接触电阻；同时，原先分布在第三半导体层表面处的载流子可以在第三半导体层的体中分布，从而可以降低该载流子与铁电层中的陷阱的相互作用，提高该铁电存储器的耐久性。
在第一方面的一种可能的实现方式中，第一电极为底电极，第二电极为栅电极，第三电极为顶电极。
在第一方面的一种可能的实现方式中，铁电层为铁电材料或者反铁电材料，比如，该铁电材料可以为锆酸铪(HfZrO 2)，该反铁电材料可以为锆酸(ZrO 2)。上述可能的实现方式中，当铁电层为铁电材料或者反铁电材料时，通过改变引入铁电材料或者反铁电材料中的内建电场方向，可以得到极化强度不同的负向剩余极化状态，也可以得到极化强度不同的正向剩余极化状态，以此来满足不同的设计需求，提高该铁电存储器的设计灵活性；此外，当铁电层为反铁电材料时，由于反铁电材料的稳定性较高，还会进一步提高该铁电存储器的耐久性。
在第一方面的一种可能的实现方式中，当向存储单元写数据时，第二电极与第三电极之间的电压差的绝对值设置为第一电压，第一电压大于或等于指定电压，该指定电压可以是指使铁电层的极化方向发生反转的临界电压；当向存储单元读数据时，第一电极与第三电极之间的电压差设置为第二电压，第二电压小于该指定电压。上述可能的实现方式中，通过在第一电极、第二电极和第三电极施加不同的电压，即可实现对该存储单元的读写，且读写的速率较快。
在第一方面的一种可能的实现方式中，铁电存储器包括m行n列的存储单元阵列、m条第一电压线、m条第二电压线和n条第三电压线，存储单元阵列包括多个存储单元，m和n为正整数；其中，该存储单元阵列中属于同一行的n个存储单元的第一电极连接m条第一电压线中的一条第一电压线，不同行的存储单元的第一电极连接不同的第一电压线，从而m行对应连接m条第一电压线；该存储单元阵列中属于同一行的n个存储单元的第二电极连接m条第二电压线中的一条第二电压线，不同行的存储单元的第二电极连接不同的第二电压线，从而m行对应连接m条第二电压线；该存储单元阵列中属于同一列的m个存储单元的第三电极连接n条第三电压线中的一条第三电压线，不同列的存储单元的第三电极连接不同的第三电压线，从而n列对应连接n条第三电压线。可选的，第一电压线与第二电压线平行，第三电压线与第一电压线和第二电压线均垂直。 上述可能的实现方式中，铁电存储器通过该存储单元阵列可以实现基于MFS结构的单个存储单元的面积为4F 2，与现有技术DRAM中基于电容结构的单个存储单元的面积8F 2相比，可以大大降低该铁电存储器的面积。
在第一方面的一种可能的实现方式中，第一电压线为源线SL，第二电压线为字线WL，第三电压线为位线BL，即在存储单元阵列中，属于同一行的n个存储单元的第一电极连接同一个SL，属于同一行的n个存储单元的第二电极连接同一个WL，属于同一列的m个存储单元的第三电极连接同一个BL。
在第一方面的一种可能的实现方式中，当向存储单元阵列中的一个存储单元写数据时，第一电压线的电压设置为第一电压，第一电压大于或等于指定电压。上述可能的实现方式中，将第一电压线的电压设置为第一电压，可以保证该存储单元阵列中的所有存储单元均处于零偏或者反偏状态，以降低写数据时的泄漏电流。
在第一方面的一种可能的实现方式中，当向存储单元阵列中的第一行包括的n个存储单元并行写数据时，第一行包括的n个存储单元所连接的第二电压线的电压设置为零或者第一电压，m行中除第一行之外的其余行包括的存储单元所连接的第二电压线的电压设置为第一电压的二分之一，第一行为m行中的任一行，第一电压大于或等于指定电压。上述可能的实现方式中，可以实现该存储单元阵列中同一行包括的多个存储单元的并行写数据，从而大大提高该铁电存储器的读写效率。
在第一方面的一种可能的实现方式中，当向存储单元阵列中的第一行包括的n个存储单元并行写数据时，第一行包括的n个存储单元所连接的第二电压线的电压设置为零或者第一电压的三分之四，m行中除第一行之外的其余行包括的存储单元所连接的第二电压线的电压设置为第一电压的三分之二，第一行为m行中的任一行，第一电压大于或等于指定电压。上述可能的实现方式中，可以实现该存储单元阵列中同一行包括的多个存储单元的并行写数据，从而大大提高该铁电存储器的读写效率。
在第一方面的一种可能的实现方式中，当向存储单元阵列中的第一行包括的n个存储单元读数据时，第一行包括的n个存储单元所连接的第一电压线的电压设置为零，m行中除第一行之外的其余行包括的存储单元所连接的第一电压线的电压设置为第二电压，第二电压线的电压设置为零，第三电压线的电压设置为第二电压，第二电压小于指定电压。上述可能的实现方式中，可以实现该存储单元阵列中同一行包括的多个存储单元的并行读数据，从而大大提高该铁电存储器的读写效率。
第二方面，提供一种存储设备，该存储设备包括：电路板、以及与电路板连接的铁电存储器，铁电存储器为第一方面或者第一方面的任一项可能的实现方式所提供的铁电存储器。
第三方面，提供一种存储设备，该存储设备包括控制器和铁电存储器，该控制器用于控制该铁电存储器的读写，该铁电存储器为第一方面或者第一方面的任一项可能的实现方式所提供的铁电存储器。
第四方面，提供一种与计算机一起使用的非瞬时性计算机可读存储介质，计算机具有用于设计集成电路的软件，计算机可读存储介质上存储有一个或多个计算机可读数据结构，一个或多个计算机可读数据结构包括用于制造上述第一方面或者第一方面的任一种可能的实现方式所提供的铁电存储器的光掩膜数据。
可以理解地是，上述提供的任一种存储设备和与计算机一起使用的非瞬时性计算机可读存储介质等包含了上文所提供的铁电存储器的相同或相对应的特征，因此，其所能达到的有益效果可参考上文所提供的对应的集成电路中的有益效果，此处不再赘述。
附图说明
图1为本申请实施例提供的一种存储装置的结构示意图；
图2为本申请实施例提供的一种铁电存储器的示意图；
图3为本申请实施例提供的一种存储单元的示意图；
图4为本申请实施例提供的一种存储单元的剖面图；
图5为本申请实施例提供的另一种存储单元的剖面图；
图6为本申请实施例提供的又一种存储单元的剖面图；
图7为本申请实施例提供的一种读电流的示意图；
图8为本申请实施例提供的又一种铁电存储器的示意图；
图9为本申请实施例提供的另一种铁电存储器的示意图；
图10为本申请实施例提供的一种P-V曲线示意图；
图11为本申请实施例提供的又一种铁电存储器的示意图。
具体实施方式
下文将详细论述各实施例的制作和使用。但应了解，本申请提供的许多适用发明概念可实施在多种具体环境中。所论述的具体实施例仅仅说明用以实施和使用本说明和本技术的具体方式，而不限制本申请的范围。
除非另有定义，否则本文所用的所有科技术语都具有与本领域普通技术人员公知的含义相同的含义。
各电路或其它组件可描述为或称为“用于”执行一项或多项任务。在这种情况下，“用于”用来通过指示电路/组件包括在操作期间执行一项或多项任务的结构(例如电路系统)来暗指结构。因此，即使当指定的电路/组件当前不可操作(例如未打开)时，该电路/组件也可以称为用于执行该任务。与“用于”措辞一起使用的电路/组件包括硬件，例如执行操作的电路等。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。在本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，a和b，a和c，b和c或a、b和c，其中a、b和c可以是单个，也可以是多个。另外，在本申请的实施例中，“第一”、“第二”等字样并不对数量和次序进行限定。
需要说明的是，本申请中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的” 或者“例如”等词旨在以具体方式呈现相关概念。
本申请的技术方案可以应用于采用铁电存储器的各种存储系统中，比如，本申请的技术方案可以应用于计算机中，还可以应用于包括存储器的存储系统中、或者包括处理器和存储器的存储系统中，该处理器可以为中央处理器(central processing unit，CPU)、人工智能(artificial intelligence，AI)处理器、数字信号处理器(digital signal processor)和神经网络处理器等。示例性的，图1为本申请实施例提供的一种存储系统的结构示意图，该存储系统可以包括铁电存储器；可选的，该存储系统还可以包括CPU、缓存器(cache)和控制器等。其中，该CPU、缓存器、控制器和铁电存储器可以集成在一起，铁电存储器可以通过控制器与该缓存器耦合，以及通过该缓存器和该CPU相耦合。
图2为本申请实施例提供的一种铁电存储器的结构示意图，该铁电存储器包括m行n列的存储单元阵列、m条第一电压线、m条第二电压线和n条第三电压线，该存储单元阵列包括多个存储单元，m和n为正整数。图2中以m和n的值均等于3为例进行说明。在实际应用中，第一电压线可以为源线(source line，SL)，第二电压线可以为字线(word line，WL)，第三电压线可以为位线(bit line，BL)。在该铁电存储器中，属于同一行的n个存储单元可以连接m条SL中的一条SL、以及连接m条WL中一条WL，不同行的存储单元连接的SL和WL不同，属于同一列的m个存储单元可以连接m条BL中的一条BL，不同列的存储单元连接的BL不同。
下面以该铁电存储器的存储单元阵列中的一个存储单元为例，对该存储单元的结构进行详细说明。
图3为本申请实施例提供的一种存储单元的结构示意图，图3中的(a)为该存储单元的立体图，图3中的(b)为图3中的(a)所示的立体图沿着直线HH’方向垂直向下剖开之后的立体图。参见图3，该存储单元包括：第一电极1，第二电极2，第三电极3，铁电层4，以及层叠设置的第一半导体层10、第二半导体层20和第三半导体层30。
其中，第一半导体层10和第二半导体层20中的一个为N型半导体、另一个为P型半导体，即第一半导体层10和第二半导体层20之间形成PN结。比如，第一半导体层10为N型半导体，第二半导体层20为P型半导体；或者，第一半导体层10为P型半导体，第二半导体层20为N型半导体。第一半导体层10和第二半导体层20中的半导体材料可以是硅(Si)或者硅锗(SiGe)等。图3中以第一半导体层10为P型Si(P-type Si)、第二半导体层20为N型Si(N-type Si)为例进行说明。
另外，第一半导体层10远离第二半导体层20的一侧设置有第一电极1，第一电极1的轴边距可以等于或小于第一半导体层10的轴边距，第三半导体层30远离第二半导体层20的一侧设置有第三电极3，第三电极3的轴边距可以等于或小于第三半导体层30的轴边距。这里的第一电极1和第三电极3的电极材料可以是硅和金属的化合物，比如，硅化钛、硅化锆、硅化钽和硅化钨等。
再者，铁电层4包围第三半导体层30的全部侧面或者部分侧面，第二电极2包围铁电层4，这里的第三半导体层30的侧面可以是指与第三半导体层30的深度方向(或者轴线方向)平行的表面，或者是指第三半导体层30的四周。铁电层4可以包围第三 半导体层30的全部侧面，也可以仅包围第三半导体层30的部分侧面，图3中以铁电层4包围第三半导体层30的全部侧面为例进行说明，图4中以铁电层4包围第三半导体层30的部分侧面为例进行说明。这里的铁电层4可以为铁电材料或者反铁电材料，比如，该铁电材料可以为锆酸铪(HfZrO 2)，该反铁电材料可以为锆酸(ZrO 2)。以铁电材料形成的薄膜可以称为铁电薄膜，以反铁电材料形成的薄膜可以称为反铁电薄膜，在本申请中可以将铁电薄膜和反铁电薄膜统称为铁电层(也可以称为铁电性薄膜)。这里的第二电极2的电极材料可以为金属材料，比如，铝(Al)、铜(Cu)、钨(W)和氮化钨(WN)等。
本申请实施例提供的铁电存储器中，每个存储单元可以等效为一个由铁电层4极化控制的金属-铁电层-半导体层(metal-ferroelectrics-semiconductor，MFS)结构的存储单元，该存储单元中不存在容易俘获电荷的铁电层-绝缘层的界面，从而会减小界面缺陷，提高该铁电存储器的耐久性。同时，在每个存储单元中，铁电层4仅包围第三半导体层30的全部侧面或者部分侧面，而未包围第一半导体层10和第二半导体层20，这样后续在向该存储单元写数据时，可以降低第一电极1对铁电材料极化状态的影响，进而降低铁电存储器误写的风险。此外，当铁电层4为铁电材料或者反铁电材料时，通过改变引入铁电材料或者反铁电材料中的内建电场方向，可以得到极化强度不同的负向剩余极化状态，也可以得到极化强度不同的正向剩余极化状态，以此来满足不同的设计需求，提高该铁电存储器的设计灵活性。
可选的，第一半导体层10、第二半导体层20和第三半导体层30可以呈柱状，该柱状的横截面可以呈圆形、椭圆形或者多边形等闭合图形中的任一种，比如，该多边形可以为三角形、四边形、五边形、六边形等，本申请实施例对此不作具体限制。图3中以该柱状的横截面呈圆形为例进行说明。
在一种实施例中，第三半导体层30为本征半导体，比如，如图3所示，第三半导体层30为本征Si。在另一种实施例中，当第二半导体层20为P型半导体时，第三半导体层30为P型半导体，比如，第二半导体层20和第三半导体层30均为P型Si；或者，当第二半导体层20为N型半导体时，第三半导体层30为N型半导体，比如，第二半导体层20和第三半导体层30均为N型Si。当第二半导体层20和第三半导体层30同为P型半导体或者N型半导体时，可以通过一个步骤即可实现第二半导体层20和第三半导体层30的制作，从而简化该铁电存储器的制作步骤。此外，第二半导体层20和第三半导体层30同为P型半导体或者N型半导体还可以降低第三电极3的接触电阻；同时，原先分布在第三半导体层30表面处的载流子可以在第三半导体层30的体中分布，从而可以降低该载流子与铁电层4中的陷阱的相互作用，提高该铁电存储器的耐久性。比如，图4中以第一半导体层10为P型Si、第二半导体层20和第三半导体层30均为N型Si为例进行说明。图4中的(a)为该存储单元的立体图，图4中的(b)为图4中的(a)所示的立体图沿着直线HH’方向垂直向下剖开之后的立体图。
在实际应用中，第一电极1可以为底电极，第二电极2可以为栅电极，第三电极3可以为顶电极。通过在第一电极1、第二电极2和第三电极3施加不同的电压，可以实现对该存储单元的读写，即向该存储单元写数据或者读数据。其中，可以由控制器 控制施加在第一电极1、第二电极2和第三电极3的电压。
如图5所示，当向该存储单元写数据时，可以在第二电极2和第三电极3之间施加电压，以将第二电极2与第三电极3之间的电压差的绝对值(即二者之差的绝对值)设置为第一电压V W，第一电压V W大于或等于指定电压，这里的指定电压可以是指使铁电层4的极化方向发生反转的临界电压。图5为图3中的(a)所示的该存储单元沿着直线HH’垂直向下剖开之后的剖面图。
具体的，如图5中的(a)所示，当向该存储单元写入数据“0”时，可以将第一电极1和第三电极3接地、对第二电极2施加负偏压-V W，以使第三电极3的电压减去第二电极2的电压得到的电压差为第一电压V W，此时，铁电层4负极化，第三半导体层30的表面出现大量正电荷，第三半导体层30与铁电层4之间的接触势垒降低，从而该存储单元被写为低阻状态，即写入数据“0”。如图5中的(b)所示，当向该存储单元写入数据“1”时，可以将第一电极1和第三电极3接地、对第二电极2施加正偏压V W，以使第二电极2的电压减去第三电极3的电压得到的电压差为第一电压V W，此时，铁电层4正极化，第三半导体层30的表面出现大量负电荷，第三半导体层30与铁电层4之间的接触势垒增大，从而该存储单元被写为高阻状态，即写入数据“1”。图5中的P表示铁电层4的极化方向。
需要说明的是，本申请实施例中以数据“0”对应低阻状态、数据“1”对应高阻状态为例进行说明，在实际应用中，数据“0”也可以对应高阻状态、数据“1”对应低阻状态，本申请实施例对此不作具有限制。
如图6所示，当向该存储单元读数据时，可以在第一电极1和第三电极3之间施加电压，以将第一电极1与第三电极3之间的电压差设置为第二电压V R，第二电压V R小于指定电压，这里的指定电压可以是指使铁电层4的极化方向发生反转的临界电压。图6为图3中的(a)所示的该存储单元沿着直线HH’垂直向下剖开之后的剖视图。
具体的，当向该存储单元读取数据时，可以在第一电极1于第三电极3之间施加第二电压V R，并读取第三电极3的电流I R；如图6中的(a)所示，当该I R的值大于阈值时，即可确定该存储单元中的数据为“0”(此时的I R标记为I R_0)，这是因为在该存储单元被写入数据“0”时，该存储单元为低阻状态，从而读取的电流相对于写入数据“1”时的电流较大；如图6中的(b)所示，当该I R的值小于上述阈值时，即可确定该存储单元中的数据为“1”(此时的I R标记为I R_1)，这是因为在该存储单元被写入数据“1”时，该存储单元为高阻状态，从而读取的电流相对于写入数据“0”时的电流较小。图7中示出了存储单元中写入数据“0”和写入数据“1”时读取的电流I R的一种可能的示意图，具体当第二电压V R大约处于[-2V，0.4V]的区间时，电流I R随着第二电压V R的增加而减小，当第二电压V R大约处于[0.4V，2V]的区间时，电流I R随着第二电压V R的增加而增加。在图7中，当第二电压V R的取值大约为1V时，数据“0”对应读取的电流I R_0的取值大约为10 -5A，数据“1”对应读取的电流I R_1的取值大约为10 -12A。
进一步的，结合上述存储单元的相关描述，上述图2所示的铁电存储器中的存储单元阵列与m条第一电压线、m条第二电压线和n条第三电压线的连接关系具体如下所 述。
其中，该存储单元阵列中属于同一行的n个存储单元的第一电极1连接同一个第一电压线，不同行的存储单元的第一电极1连接不同的第一电压线，从而m行对应连接m条第一电压线。该存储单元阵列中属于同一行的n个存储单元的第二电极连接同一个第二电压线，不同行的存储单元的第二电极2连接不同的第二电压线，从而m行对应连接m条第二电压线。该存储单元阵列中属于同一列的m个存储单元的第三电极3连接同一个第三电压线，不同列的存储单元的第三电极3连接不同的第三电压线，从而n列对应连接n条第三电压线。可选的，第一电压线与第二电压线平行，第三电压线与第一电压线和第二电压线均垂直。上述铁电存储器通过该存储单元阵列可以实现基于MFS结构的单个存储单元的面积为4F 2(feature size，特征尺寸)，与现有技术DRAM中基于电容结构的单个存储单元的面积8F 2相比，可以大大降低该铁电存储器的面积。
在实际应用中，第一电压线可以为源线(source line，SL)，第二电压线可以为字线(word line，WL)，第三电压线可以为位线(bit line，BL)，即在存储单元阵列中，属于同一行的n个存储单元的第一电极1连接同一个SL，属于同一行的n个存储单元的第二电极2连接同一个WL，属于同一列的m个存储单元的第三电极3连接同一个BL。
对于图2所示的铁电存储器，通过在m条第一电压线、m条第二电压线和n条第三电压线上施加不同的电压，可以实现对该铁电存储器中存储单元的读写，即向该铁电存储器中的存储单元写数据或者读数据。其中，可以由控制器控制施加在m条第一电压线、m条第二电压线和n条第三电压线的电压。下面以第一电压线为SL、第二电压线为WL、第三电压线为BL为例进行说明，且下文中的第一电压均大于或等于指定电压，第二电压均小于指定电压，这里的指定电压可以是指使铁电层4的极化方向发生反转的临界电压，该存储单元阵列中的第一行可以是指m行中的任一行。下述图8、图9和图11中以五角星所在的一行表示第一行。
具体的，如图8所示，当向该存储单元阵列中的一个存储单元写数据时，可以将m条SL的电压均设置为第一电压V W，第一电压V W大于或等于指定电压，这样可以保证该存储单元阵列中的所有存储单元均处于零偏或者反偏状态，以降低写数据时的泄漏电流。同时通过该存储单元阵列中的设置存储单元所连接的WL与BL之间的电压差来实现数据“0”和“1”的写入。比如，当某一存储单元所连接的WL与BL之间的电压差被设置为负的第一电压-V W时，该存储单元被写为数据“0”；当某一存储单元所连接的WL与BL之间的电压差被设置为正的第一电压V W时，该存储单元被写为数据“1”；当某一存储单元所连接的WL与BL之间的电压差被设置为二分之一的第一电压1/2V W时，该存储单元的状态保持不变。
或者，如图8所示，当向该存储单元阵列中的第一行包括的n个存储单元并行写数据时，可以将第一行包括的n个存储单元所连接的WL的电压设置为零或者第一电压V W。其中，当第一行对应的WL的电压被设置为零时，若某一BL的电压被设置为零，则该BL所连接的存储单元被写为数据“1”，若某一BL的电压被设置为第一电压V W，则该BL所连接的存储单元的状态保持不变。当第一行对应的WL的电压被设置为第一电压V W时，若某一BL的电压被设置为第一电压V W，则该BL所连接的存储单元被写为数据“0”，若某一BL的电压被设置为零，则该BL所连接的存储单元的状态保 持不变。此外，该存储单元阵列包括的m行中除第一行之外的其余行包括的存储单元所连接的WL的电压可以被设置为二分之一的第一电压1/2V W，即未选中的WL接1/2V W，这样未选中的存储单元的操作电压为0、1/2V W或-1/2V W。图8所描述的写数据的方法可以称为V/2法。
或者，如图9所示，当向该存储单元阵列中的第一行包括的n个存储单元并行写数据时，可以将第一行包括的n个存储单元所连接的WL的电压设置为零或者三分之四的第一电压4/3V W。其中，当第一行对应的WL的电压被设置为4/3V W时，若某一BL的电压被设置为三分之一的第一电压1/3V W，则该BL所连接的存储单元被写为数据“1”，若某一BL的电压被设置为第一电压V W，则该BL所连接的存储单元的状态保持不变。当第一行对应的WL的电压被设置为零时，若某一BL的电压被设置为第一电压V W，则该BL所连接的存储单元被写为数据“1”，若某一BL的电压被设置为三分之一的第一电压1/3V W，则该BL所连接的存储单元的状态保持不变。此外，该存储单元阵列包括的m行中除第一行之外的其余行包括的存储单元所连接的WL的电压可以被设置为三分之二的第一电压2/3V W，即未选中的WL接2/3V W，这样未选中的存储单元的操作电压为1/3V W或-1/3V W。图9所描述的写数据的方法可以称为V/3法。
同理，按照上述图8或图9所描述的写数据的方法，也可以向该存储单元阵列中的某一列包括的m个存储单元并行写数据，具体过程与上述图8或图9的过程类似，本申请实施例在此不再赘述。
在上述几种不同的写数据方法中，当存储单元中的铁电层4为铁电材料时，铁电层4的极化强度P与外加电压V之间的关系如图10中的(a)和(b)所示，此时选中存储单元在外加电压V为负的第一电压-V W时被写入数据“0”，选中的存储单元在外加电压为正的第一电压V W时被写入数据“1”，未选中的存储单元保持原有的数据“0”或“1”。当存储单元中的铁电层4为反铁电材料时，铁电层4的极化强度P与外加电压V之间的关系如图10中的(c)和(d)所示，此时选中的存储单元在外加电压V为正的第一电压V W时被写入数据“0”，选中的存储单元在外加电压为负的第一电压-V W时被写入数据“0”，未选中的存储单元保持原有的数据“0”或“1”。图10中的外加电压V可以是指施加在第二电极2与第三电极3之间的电压。
具体的，如图11所示，当向该存储单元阵列中的第一行包括的n个存储单元读数据时，第一行包括的n个存储单元所连接的SL的电压可以被设置为零，该存储单元阵列包括的m行中除第一行之外的其余行包括的存储单元所连接的SL的电压可以被设置为第二电压V R，所有的WL的电压均被设置为零，所有的BL的电压均被设置为第二电压V R，此时，第一行包括的n个存储单元的第一电极1和第三电极3之间的电压差被设置为V R，从而读出的数据“0”或“1”对应的电流，第一行之外的其余行包括的存储单元的第一电极1和第三电极3之间的电压差被设置为零，从而不会产生泄露电流。
上述对该存储单元阵列中的存储单元进行读写方法中，图8至图11所描述的读写方法可以实现该存储单元阵列中同WL或者同BL的并行读写，即对同一行或者同一列的多个存储单元并行的写数据或读数据，从而可以大大提高该铁电存储器的读写效率。
基于此，本申请实施例还提供一种存储设备，该存储设备包括电路板、以及与电路板连接的铁电存储器，该铁电存储器可以为上文所提供的任一种铁电存储器。其中， 该电路板可以为印制电路板(printed circuit board，PCB)，当然电路板还可以为柔性电路板(FPC)等，本实施例对电路板不作限制。可选的，该存储设备为计算机、手机、平板电脑、可穿戴设备和车载设备等不同类型的用户设备或者终端设备；该存储设备还可以为基站等网络设备。
可选的，该存储设备还包括封装基板，该封装基板通过焊球固定于印刷电路板PCB上，该铁电存储器通过焊球固定于封装基板上。
基于此，本申请实施例还提供一种存储设备，该存储设备包括控制器和铁电存储器，该控制器用于控制该铁电存储器中的读写，该铁电存储器可以为上文所提供的任一种铁电存储器。
需要说明的是，关于三维铁电存储器的相关描述，具体可以参见上述图2-图11中关于铁电存储器的描述，本申请实施例在此不再赘述。
在本申请的另一方面，还提供一种与计算机一起使用的非瞬时性计算机可读存储介质，该计算机具有用于设计集成电路的软件，该计算机可读存储介质上存储有一个或多个计算机可读数据结构，一个或多个计算机可读数据结构包括用于制造上文所提供的任意一个铁电存储器的光掩膜数据。
最后应说明的是：以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (14)

  1. 一种铁电存储器，其特征在于，所述铁电存储器包括至少一个存储单元，每个所述存储单元包括：第一电极，第二电极，第三电极，铁电层，以及层叠设置的第一半导体层、第二半导体层和第三半导体层；
    其中，所述第一半导体层和所述第二半导体层中的一个为N型半导体、另一个为P型半导体，所述第一半导体层远离所述第二半导体层的一侧设置有所述第一电极，所述第三半导体层远离所述第二半导体层的一侧设置有所述第三电极，所述铁电层包围所述第三半导体层的全部侧面或者部分侧面，所述第二电极包围所述铁电层。
  2. 根据权利要求1所述的铁电存储器，其特征在于，所述第三半导体层为本征半导体。
  3. 根据权利要求1所述的铁电存储器，其特征在于，当所述第二半导体层为P型半导体时，所述第三半导体层为P型半导体；或者，当所述第二半导体层为N型半导体时，所述第三半导体层为N型半导体。
  4. 根据权利要求1-3任一项所述的铁电存储器，其特征在于，所述第一电极为底电极，所述第二电极为栅电极，所述第三电极为顶电极。
  5. 根据权利要求1-4任一项所述的铁电存储器，其特征在于，所述铁电层为铁电材料或者反铁电材料。
  6. 根据权利要求1-5任一项所述的铁电存储器，其特征在于，当向所述存储单元写数据时，所述第二电极与所述第三电极之间的电压差的绝对值设置为第一电压，所述第一电压大于或等于指定电压；
    当向所述存储单元读数据时，所述第一电极与所述第三电极之间的电压差设置为第二电压，所述第二电压小于所述指定电压。
  7. 根据权利要求1-6任一项所述的铁电存储器，其特征在于，所述铁电存储器包括m行n列的存储单元阵列、m条源线SL、m条字线WL和n条位线BL，所述存储单元阵列包括多个所述存储单元，m和n为正整数；
    其中，所述存储单元阵列中属于同一行的n个存储单元的第一电极连接所述m条SL中的一条SL，所述存储单元阵列中属于同一行的n个存储单元的第二电极连接所述m条WL中的一条WL，所述存储单元阵列中属于同一列的m个存储单元的第三电极连接所述n条BL中的一条BL。
  8. 根据权利要求7所述的铁电存储器，其特征在于，所述m条SL与所述m条WL平行，所述n条BL与所述m条SL和所述m条WL均垂直。
  9. 根据权利要求7或8所述的铁电存储器，其特征在于，当向所述存储单元阵列中的一个存储单元写数据时，所述m条SL的电压设置为第一电压，所述第一电压大于或等于指定电压。
  10. 根据权利要求7或8所述的铁电存储器，其特征在于，当向所述存储单元阵列中的第一行包括的n个存储单元并行写数据时，所述第一行包括的n个存储单元所连接的所述WL的电压设置为零或者第一电压，所述m行中除所述第一行之外的其余行包括的存储单元所连接的所述WL的电压设置为所述第一电压的二分之一，所述第一行为 所述m行中的任一行，所述第一电压大于或等于指定电压。
  11. 根据权利要求7或8所述的铁电存储器，其特征在于，当向所述存储单元阵列中的第一行包括的n个存储单元并行写数据时，所述第一行包括的n个存储单元所连接的所述WL的电压设置为零或者第一电压的三分之四，所述m行中除所述第一行之外的其余行包括的存储单元所连接的所述WL的电压设置为所述第一电压的三分之二，所述第一行为所述m行中的任一行，所述第一电压大于或等于指定电压。
  12. 根据权利要求7-11任一项所述的铁电存储器，其特征在于，当向所述存储单元阵列中的第一行包括的n个存储单元读数据时，所述第一行包括的n个存储单元所连接的所述SL的电压设置为零，所述m行中除所述第一行之外的其余行包括的存储单元所连接的所述SL的电压设置为第二电压，所述WL的电压设置为零，所述BL的电压设置为所述第二电压，所述第二电压小于指定电压。
  13. 一种存储设备，其特征在于，所述存储设备包括：电路板、以及与所述电路板连接的铁电存储器，所述铁电存储器为权利要求1-12任一项所述的铁电存储器。
  14. 一种存储设备，其特征在于，所述存储设备包括控制器和铁电存储器，所述控制器用于控制所述铁电存储器的读写，所述铁电存储器为权利要求1-12任一项所述的铁电存储器。
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