WO2021254207A1 - 发送数据帧的方法、接收数据帧的方法及通信装置 - Google Patents

发送数据帧的方法、接收数据帧的方法及通信装置 Download PDF

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Publication number
WO2021254207A1
WO2021254207A1 PCT/CN2021/098776 CN2021098776W WO2021254207A1 WO 2021254207 A1 WO2021254207 A1 WO 2021254207A1 CN 2021098776 W CN2021098776 W CN 2021098776W WO 2021254207 A1 WO2021254207 A1 WO 2021254207A1
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information
chip
interleaver
sub
chips
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PCT/CN2021/098776
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English (en)
French (fr)
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刘辰辰
梁丹丹
淦明
张美红
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华为技术有限公司
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Priority to EP21826672.4A priority Critical patent/EP4156568A4/en
Publication of WO2021254207A1 publication Critical patent/WO2021254207A1/zh
Priority to US18/068,274 priority patent/US20230118836A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/003—Arrangements for allocating sub-channels of the transmission path
    • H04L5/0044—Arrangements for allocating sub-channels of the transmission path allocation of payload
    • H04L5/0046—Determination of how many bits are transmitted on different sub-channels
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0059—Convolutional codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0067—Rate matching
    • H04L1/0068—Rate matching by puncturing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/0001—Arrangements for dividing the transmission path
    • H04L5/0003—Two-dimensional division
    • H04L5/0005—Time-frequency
    • H04L5/0007—Time-frequency the frequencies being orthogonal, e.g. OFDM(A), DMT
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/003—Arrangements for allocating sub-channels of the transmission path
    • H04L5/0044—Arrangements for allocating sub-channels of the transmission path allocation of payload
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W16/00—Network planning, e.g. coverage or traffic planning tools; Network deployment, e.g. resource partitioning or cells structures
    • H04W16/02—Resource partitioning among network components, e.g. reuse partitioning
    • H04W16/06—Hybrid resource partitioning, e.g. channel borrowing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W16/00—Network planning, e.g. coverage or traffic planning tools; Network deployment, e.g. resource partitioning or cells structures
    • H04W16/14—Spectrum sharing arrangements between different networks

Definitions

  • the embodiments of the present application relate to the field of communications, and more specifically, to a method for sending a data frame, a method for receiving a data frame, and a communication device.
  • WLAN wireless local area network, wireless local area network
  • the maximum channel bandwidth supported by each generation of standards has gradually increased through the channel bonding mechanism, from the 20MHz channel bandwidth supported by the 802.11a/g standard to the 802.11n standard
  • future standards for example, 802.11be
  • the continuous channel bonding mechanism also has drawbacks.
  • the sender when a narrowband subordinate channel in the bonded channel is busy, the sender will not be able to use a larger subordinate channel. Taking an 80MHz channel as an example, if the slave 20MHz channel is busy, even if the slave 40MHz channel is idle, the sender can only use the bandwidth of the master 20MHz channel, which wastes the air interface resources of the slave 40MHz channel.
  • the 802.11ax standard in addition to supporting continuous channel bonding like the 802.11ac standard, also introduces a preamble puncturing mechanism to further improve the spectrum utilization.
  • Preamble puncturing was called non-contiguous channel bonding (NCB) at the beginning of the discussion.
  • NCB non-contiguous channel bonding
  • An example of a preamble puncturing pattern is shown in Figure 1.
  • HE-SIG B high efficient signal field B
  • the 802.11ax standard introduced the concept of content channel (CC).
  • CC content channel
  • the bandwidth of the information carried by HE-SIG-B is 20MHz
  • HE-SIG-B includes one content channel, and one content channel corresponds to one sub-channel
  • HE-SIG-B carries
  • HE-SIG-B includes two content channels, denoted as: CC1 and CC2, where CC1 corresponds to one subchannel, and this CC2 corresponds to one subchannel
  • CC1 corresponds to one subchannel
  • this CC2 corresponds to one subchannel
  • the data message bandwidth is 80MHz
  • HE- SIG-B includes two content channels.
  • the two content channels correspond to the 4 sub-channels in the specified order, that is, the order of CC1, CC2, CC1, and CC2; when the data message bandwidth is 160MHz, the Based on further expansion, HE-SIG-B includes two content channels, and the two content channels correspond to 8 sub-channels in a specified order, that is, the order of CC1, CC2, CC1, CC2, CC1, and CC2.
  • the receiving end must receive at least one CC1 and at least one CC2 to fully recover the information carried by the content channel. Therefore, the robustness of communication is poor, and the supported puncturing mode is limited. For example, it does not support the mode in which the 20M where two CC1 or two CC2 are located is punctured at the same time.
  • the present application provides a method for sending a data frame, a method for receiving a data frame, and a communication device, which can improve the robustness of communication and the flexibility of puncturing.
  • a method for sending a data frame is provided, which is executed in a communication system in which a channel is divided into N sub-channels, N ⁇ 2, and the method includes: a transmitting end device encodes first information based on a first encoder, To generate the first chip and the second chip, the first encoder includes a 1/2 convolutional code encoder, and the first information includes part or all of the information corresponding to the preamble field of the data frame; based on M
  • the interleaver performs interleaving processing on the first information to generate M pieces of information, where the M pieces of information correspond to the M pieces of interleaver one-to-one, and the m-th piece of information in the M pieces of information is based on Generated by the interleaving process of the m-th interleaver in the M interleavers, the m-th information corresponds to the m-th interleaver, m ⁇ [2, M+1], M ⁇ 1; based on the An encoder performs encoding processing
  • the target information to be sent is interleaved on the sending end based on multiple interleavers, and the interleaved information is further coded, and the coded information is sent through multiple sub-channels.
  • the receiving end can recover the target information according to the information on any two of the multiple channels and the interleaver information corresponding to the two channels, thereby improving the flexibility of puncturing for the multiple channels. , And improve the robustness of communication.
  • M 1.
  • the bandwidth of the channel used by the communication system of this application is 80Mhz
  • the bandwidth of the channel used by the communication system of this application is 160Mhz
  • One of the sub-channels within the 80Mhz bandwidth includes 4 sub-channels (the bandwidth of each sub-channel is 20 MHz). Thereafter, the 4 chips corresponding to the 80Mhz bandwidth can be copied, and the copied 4 chips can be respectively carried on the 4 sub-channels in the other 80Mhz bandwidth of the 160Mhz channel.
  • the bandwidth of the channel used by the communication system of this application is Q ⁇ 80Mhz
  • the 4 chips corresponding to the 80Mhz bandwidth can be copied Q times, and the copied Q ⁇ 4 chips can be respectively carried in the other (Q-1) ⁇ 80Mhz bandwidth of the 160Mhz channel ( Q-1) 4 sub-channels.
  • the value of M is the result of rounding up N/2 and subtracting 1.
  • the size of a chip corresponds to a 20MHz sub-channel, that is, when the value of M is the result of rounding up to N/2 and subtracting 1,
  • the bandwidth of the channel used by the communication system of the present application is 80Mhz
  • the value of N is 4, and 4 chips are generated according to the solution of the present application, and each chip corresponds to a sub-channel.
  • the bandwidth of the channel used by the communication system of this application is 160Mhz
  • the value of N is 8.
  • the value of M is N/2 rounded up and then subtracted by 1 (in this case, it is 3), according to this application
  • the scheme generates 8 chips, and each chip corresponds to a sub-channel.
  • the method further includes: determining the M interleavers according to a first mapping relationship, where the first mapping relationship includes interleaver corresponding information for each of the N subchannels, where ,
  • the m-th interleaver is an interleaver corresponding to the 2m+1-th sub-channel and the 2nd (m+1)-th sub-channel, and the 2m+1-th sub-channel is used to transmit the 2m+1-th chip, so
  • the second (m+1)th subchannel is used to transmit the second (m+1)th chip.
  • a method for sending a data frame is provided, which is executed in a communication system in which a channel is divided into N sub-channels, N ⁇ 2, and the method includes: a sending end device generates a first chip according to the first information, so The first information includes part or all of the information corresponding to the preamble field of the data frame; based on M interleavers, the first information is interleaved to generate M information, where the M information and the M There is a one-to-one correspondence between each interleaver, wherein the m-th information in the M information is generated based on the interleaving processing of the m-th interleaver in the M interleavers, and the m-th information is interleaved with the m-th interleaver.
  • the M information is encoded based on the first encoder to generate M chips, and the first encoder includes a recursive systematic convolutional code Encoder; generates a data frame, the data frame includes N chips, the N chips correspond to the N sub-channels one-to-one, and each sub-channel is used to carry the corresponding chip, the N codes
  • a chip includes the first chip and all or part of the M chips; the data frame is transmitted through at least two subchannels of the N subchannels.
  • the target information to be sent is interleaved on the sending end based on multiple interleavers, and the interleaved information is further coded, and the coded information is sent through multiple sub-channels.
  • the receiving end can recover the target information according to the information on any two of the multiple channels and the interleaver information corresponding to the two channels, thereby improving the flexibility of puncturing for the multiple channels, and Improve the robustness of communication.
  • M 3.
  • the value of N can be 8.
  • the 4 chips corresponding to the 80Mhz bandwidth can be copied, and the copied 4 chips can be respectively carried on the 4 sub-channels in the other 80Mhz bandwidth of the 160Mhz channel.
  • each code A slice corresponds to a sub-channel in a bandwidth of 80Mhz, where the bandwidth of 80Mhz includes 4 sub-channels (the bandwidth of each sub-channel is 20 MHz).
  • the 4 chips corresponding to the 80Mhz bandwidth can be copied Q times, and the copied Q ⁇ 4 chips can be respectively carried in the other (Q-1) ⁇ 80Mhz bandwidth of the 160Mhz channel ( Q-1) 4 sub-channels.
  • M N-1.
  • the size of a chip corresponds to a 20MHz sub-channel, that is, when the value of M is the result of rounding up to N/2 and subtracting 1,
  • the bandwidth of the channel used by the communication system of this application is 80Mhz, the value of N is 4.
  • the bandwidth of the channel used by the communication system of this application is 160Mhz, the value of N is 8.
  • the method further includes: determining the M interleavers according to a first mapping relationship, where the first mapping relationship includes interleaver corresponding information for each of the N channels, where The m-th interleaver is an interleaver corresponding to the m-th subchannel, the m-th subchannel is used to transmit the m-th chip, and the m-th chip is generated after the m-th information is encoded Chip.
  • a method for receiving a data frame is provided, which is executed in a communication system in which a channel is divided into N subchannels, N ⁇ 2, and the method includes: receiving end equipment through K subchannels of the N subchannels.
  • the information is generated after the interleaving process of the k-th interleaver and the encoding process of the first encoder, or the chips carried by the k-th sub-channel in the K sub-channels are the first information after the first coding
  • the k-th interleaver is the interleaver corresponding to the k-th sub-channel, the first
  • the target information to be sent is interleaved on the sending end based on multiple interleavers, and the interleaved information is further coded, and the coded information is sent through multiple sub-channels.
  • the receiving end can recover the target information according to the information on any two of the multiple channels and the interleaver information corresponding to the two channels, thereby improving the flexibility of puncturing for the multiple channels, and Improve the robustness of communication.
  • the corresponding information of the interleaver and the first decoder according to each of the K sub-channels includes:
  • the first decoder includes a Viterbi decoder.
  • the method further includes: determining the interleaver corresponding information of each of the K subchannels according to a first mapping relationship, wherein the first mapping relationship includes each of the N channels Corresponding information for the interleaver of each channel.
  • a method for receiving a data frame is provided, characterized in that it is executed in a communication system in which a channel is divided into N sub-channels, N ⁇ 2, and the method includes: precoding first information according to a precoding matrix Processing to generate a first information matrix, the information matrix includes N rows, the precoding matrix includes N rows, the N rows of the precoding matrix correspond to the N channels in a one-to-one correspondence, and the Any T rows are linearly independent, T ⁇ 2; each row of the first information matrix is coded according to the first encoder to generate N chips, where the nth code among the N chips A slice is generated after encoding the nth row in the first matrix, n ⁇ [1, N]; a data frame is generated, the data frame includes N chips, and the N chips and the N The sub-channels have a one-to-one correspondence, and each sub-channel is used to carry a corresponding chip; the data frame is sent through at least two of the 2N channels.
  • the target information to be sent is pre-encoded based on the pre-encoding matrix at the transmitting end, and the pre-encoded information is further encoded, and the encoded information is sent through multiple sub-channels.
  • the receiving end can recover the target information according to the information on any two of the multiple channels and the precoding matrix, thereby improving the flexibility of puncturing for the multiple channels and improving the robustness of communication.
  • the performing precoding processing on the first information according to the precoding matrix includes: dividing the first information into T information segments; generating a second information matrix according to the T information segments, so The second information matrix includes T rows, and each row corresponds to one information segment; the precoding matrix and the second information matrix are multiplied to obtain the first information matrix, wherein the precoding matrix includes T List.
  • each element in the second matrix information matrix corresponds to a number on the first finite field, the size of the first finite field is 2 q , and the t th in the second information matrix
  • Each element in the row corresponds to the q bits of the t-th information segment in the T information segments, and the t-th row corresponds to the t-th information segment, t ⁇ [1, T] ,
  • each element in the second matrix information matrix is obtained after the corresponding q bits are converted, and any T rows in the precoding matrix are linearly independent on the first finite field.
  • the precoding matrix includes all or part of the rows of the following P matrix:
  • the method before encoding each row of the first information matrix according to the first encoder, the method further includes: adding a parity check bit to each row of the first information matrix.
  • a first mapping relationship is stored in the transmitting end device, and the first mapping relationship is used to indicate a one-to-one correspondence between N rows in the precoding matrix and the N channels.
  • a method for sending information is provided, which is executed in a communication system in which a channel is divided into N subchannels, N ⁇ 2, and the method includes: a receiving end device receives data through K subchannels of the N subchannels Frame, N ⁇ K ⁇ 2; according to the first decoder and the row in the precoding matrix corresponding to each of the K subchannels, the code carried in each of the at least two subchannels The chip is decoded to obtain the first information.
  • the first information includes part or all of the information corresponding to the preamble field of the data frame.
  • the chip carried by the kth subchannel in the K subchannels is the first
  • the k-th row element in the information matrix is generated after being encoded by the first encoder, and the first information matrix is generated by the precoding process of the precoding matrix for the first information, in the precoding matrix
  • the precoding matrix includes some or all rows of the following P matrix:
  • the method further includes: determining a row in a precoding matrix corresponding to each of the K subchannels according to a first mapping relationship, where the first mapping relationship is used to indicate the precoding matrix There is a one-to-one correspondence between the N rows in and the N channels.
  • a method for sending a data frame is provided, which is executed in a communication system in which a channel is divided into N sub-channels, N ⁇ 2, and the method includes: the transmitting end device divides the first information to generate the first code Chip and second chip; according to M interleaver groups, the first chip and the second chip are processed to obtain M chips, and the M chips are interleaved with the M
  • Each chip has a one-to-one correspondence, and each chip is obtained based on the corresponding interleaver group, where each interleaver group includes two interleavers, and the m-th chip among the M chips is the m_1-th sequence It is obtained by adding the m_2th sequence to the m_1th sequence.
  • the m_1th sequence is obtained after the first chip is interleaved by one of the m-th interleaver groups in the M interleaver groups.
  • the m_2th sequence is obtained after the second chip is interleaved by another interleaver in the m-th interleaver group, and the m-th chip corresponds to the m-th interleaver group, m ⁇ [3 , M+2], M ⁇ 1;
  • the data frame includes N chips, the N chips correspond to the N subchannels one-to-one, and each subchannel is used to carry the corresponding code Chip, the N chips include the first chip, the second chip, and all or part of the M chips; sending through at least two of the N subchannels The data frame.
  • the receiving end can be based on any two of the multiple channels.
  • the above information and the interleaver group corresponding to the channel recover the target information, so that the flexibility of puncturing for the multiple channels can be improved, and the robustness of communication can be improved.
  • M 2.
  • the bandwidth of the channel used by the communication system of this application is 160Mhz
  • One of the sub-channels within the 80Mhz bandwidth includes 4 sub-channels (the bandwidth of each sub-channel is 20 MHz). Thereafter, the 4 chips corresponding to the 80Mhz bandwidth can be copied, and the copied 4 chips can be respectively carried on the 4 sub-channels in the other 80Mhz bandwidth of the 160Mhz channel.
  • the bandwidth of the channel used by the communication system of this application is Q ⁇ 80Mhz
  • M N-2.
  • the bandwidth of the channel used by the communication system of this application is 80Mhz, the value of N is 4.
  • each code The slice corresponds to a sub-channel.
  • the bandwidth of the channel used by the communication system of this application is Q ⁇ 80Mhz
  • the value of N is Q ⁇ 4
  • M N-2 (Q ⁇ 4-2 in this case)
  • the scheme generates Q ⁇ 4 chips, and each chip corresponds to a sub-channel.
  • the m_1th sequence is the same as the first chip
  • the m_2th sequence is a sequence formed by cyclically shifting bits in the second chip by at least one (for example, m) bits.
  • the interleaver group of the present application can be easily realized.
  • the method further includes: determining the M interleaver groups according to a first mapping relationship, where the first mapping relationship includes interleaver group correspondence information for each of the N channels , Wherein the m-th interleaver is an interleaver corresponding to the m-th sub-channel, and the m-th sub-channel is used to transmit the m-th chip.
  • a method for receiving a data frame is provided, which is executed in a communication system in which a channel is divided into N sub-channels, N ⁇ 2, and the method includes: receiving end equipment through K sub-channels of the N sub-channels.
  • the first information includes part or all of the information corresponding to the preamble field of the data frame.
  • the first chip or the second chip obtained after the first information is divided, or the k-th chip is the first chip and the second chip that pass through the k-th sub-channel corresponding to the k interleaver group is obtained after processing, wherein each interleaver group includes two interleavers, the kth chip is obtained by adding the k_1th sequence and the k_2th sequence, and the k_1th sequence is the A chip is obtained after interleaving by one interleaver in the k-th interleaver group, and the k_2 sequence is obtained after the second chip is interleaved by another interleaver in the k-th interleaver group , K ⁇ [1, K].
  • the k_1th sequence is the same as the first chip, and the k_2th sequence is a sequence formed by cyclically shifting at least one (for example, k) bits in the second chip.
  • the method further includes: determining the interleaver group corresponding information of each of the K sub-channels according to a first mapping relationship, where the first mapping relationship includes Corresponding information of the interleaver group for each channel.
  • a communication device including various modules or units for executing any one of the first to seventh aspects and the method in any one of its possible implementation manners.
  • a communication device including a processor, which is coupled with a memory and can be used to execute any one of the first to seventh aspects and the method in a possible implementation manner.
  • the communication device further includes a memory.
  • the communication device further includes a communication interface, and the processor is coupled with the communication interface.
  • the communication device further includes a communication interface, and the processor is coupled with the communication interface.
  • the communication device is a device.
  • the communication interface may be a transceiver, or an input/output interface.
  • the communication device is a chip or a chip system.
  • the communication interface may be an input/output interface, interface circuit, output circuit, input circuit, pin or related circuit on the chip or chip system.
  • the processor may also be embodied as a processing circuit or a logic circuit.
  • a communication device including: an input circuit, an output circuit, and a processing circuit.
  • the processing circuit is configured to receive a signal through the input circuit and transmit a signal through the output circuit, so that the people in the first to seventh aspects are in one aspect and any one of the possible implementation manners of each aspect thereof The method is implemented.
  • the above-mentioned communication device may be a chip
  • the input circuit may be an input pin
  • the output circuit may be an output pin
  • the processing circuit may be a transistor, a gate circuit, a flip-flop, and various logic circuits.
  • the input signal received by the input circuit may be received and input by, for example, but not limited to, a receiver
  • the signal output by the output circuit may be, for example, but not limited to, output to the transmitter and transmitted by the transmitter
  • the circuit can be a different circuit or the same circuit. In this case, the circuit is used as an input circuit and an output circuit at different times.
  • the embodiments of the present application do not limit the specific implementation manners of the processor and various circuits.
  • a processing device including a processor and a memory.
  • the processor is used to read instructions stored in the memory, receive signals through a receiver, and transmit signals through a transmitter, so as to execute any one of the first to seventh aspects and various possible implementations. Methods.
  • processors there are one or more processors and one or more memories.
  • the memory may be integrated with the processor, or the memory and the processor may be provided separately.
  • the memory can be a non-transitory memory, such as a read only memory (ROM), which can be integrated with the processor on the same chip, or can be set on different chips.
  • ROM read only memory
  • the embodiment of the present application does not limit the type of the memory and the setting mode of the memory and the processor.
  • sending instruction information may be a process of outputting instruction information from the processor
  • receiving capability information may be a process of the processor receiving input capability information.
  • the processed output data may be output to the transmitter, and the input data received by the processor may come from the receiver.
  • the transmitter and receiver can be collectively referred to as a transceiver.
  • the processor in the above-mentioned eleventh aspect may be a chip, and the processor may be implemented by hardware or software.
  • the processor When implemented by hardware, the processor may be a logic circuit, an integrated circuit, etc.; when implemented by software
  • the processor may be a general-purpose processor, which is implemented by reading software codes stored in the memory.
  • the memory may be integrated in the processor, may be located outside the processor, and exist independently.
  • a processing device including: a communication interface and a processing circuit, where the communication interface is used according to the first, second, fourth, or sixth aspect and any one of them
  • the method in the implementation manner sends a transmission frame, and the processing circuit is used to generate the transmission frame.
  • a processing device including: a communication interface and a processing circuit, the communication interface is used to obtain a transmission frame to be processed, and the processing circuit is used in accordance with the third, fifth, or The method in the seventh aspect and any one of its possible implementation manners processes the to-be-processed transmission frame.
  • a computer program product includes: a computer program (also called code, or instruction), which when the computer program is executed, causes a computer to execute the first aspect To any aspect of the seventh aspect and the method in any possible implementation manner of each aspect.
  • a computer program also called code, or instruction
  • a computer-readable medium stores a computer program (also called code, or instruction) when it runs on a computer, so that the computer executes the above-mentioned first Aspect to any one of the seventh aspect and the method in any one of the possible implementation manners of each aspect.
  • a computer program also called code, or instruction
  • a communication system which includes the aforementioned sender device and receiver device.
  • Fig. 1 is a schematic diagram of an example of a punching scheme.
  • Fig. 2 is a schematic diagram of an example of a content channel.
  • Fig. 3 is a schematic diagram of an example of the communication system of the present application.
  • Fig. 4 is an example of the channel allocation method of the present application.
  • Fig. 5 is a schematic diagram of an example of a data frame of the present application.
  • Fig. 6 is a schematic diagram of an example of the structure of HE-SIG-B.
  • FIG. 7 is a schematic diagram of an example of the chip generation method of the present application.
  • FIG. 8 is a schematic diagram of an example of the decoding process corresponding to the chip generation method shown in FIG. 7.
  • FIG. 9 is a schematic diagram of another example of the chip generation method of the present application.
  • FIG. 10 is a schematic diagram of an example of the decoding process corresponding to the chip generation method shown in FIG. 9.
  • FIG. 11 is a schematic diagram of another example of the chip generation method of the present application.
  • FIG. 12 is a schematic diagram of another example of the chip generation method of the present application.
  • FIG. 13 is a schematic diagram of an example of the decoding process corresponding to the chip generation methods shown in FIG. 11 and FIG. 12.
  • FIG. 14 is a schematic diagram of another example of the chip generation method of the present application.
  • FIG. 15 is a schematic diagram of another example of the chip generation method of the present application.
  • FIG. 16 is a schematic diagram of an example of the communication device of the present application.
  • FIG. 17 is a schematic diagram of another example of the communication device of the present application.
  • FIG. 18 is a schematic diagram of another example of the communication device of the present application.
  • FIG. 19 is a schematic diagram of an example of AP of the present application.
  • FIG. 20 is a schematic diagram of an example of STA of the present application.
  • WLAN wireless local area network
  • LTE long term evolution
  • UMTS universal mobile telecommunication system
  • WiMAX worldwide interoperability for microwave access
  • WLAN system is taken as an example to describe the application scenarios of the embodiments of the present application and the methods of the embodiments of the present application.
  • the embodiments of this application can be applied to a WLAN system, and the embodiments of this application can be applied to any one of the IEEE 802.11 series protocols currently adopted by the Institute of Electrical and Electronics Engineers (IEEE). .
  • IEEE Institute of Electrical and Electronics Engineers
  • the WLAN may include one or more basic service sets (BSS), and the network nodes in the basic service set include access points (AP) and stations (station, STA).
  • BSS basic service sets
  • One STA can only access one AP (that is, the STA is associated with the AP), and one AP can be associated with multiple STAs.
  • beam training is required to obtain the optimal receiving beam and/or the optimal transmitting beam between the STA and the AP.
  • IEEE 802.11ad introduced a personal basic service set (PBSS) and a personal basic service set control node (PBSS control point, PCP).
  • PBSS personal basic service set
  • PCP personal basic service set control node
  • Each personal basic service set can include one PCP/AP and multiple stations associated with the PCP/AP.
  • the user station (STA) in WLAN can be called system, user unit, access terminal, mobile station, mobile station, remote station, remote terminal, mobile device, user terminal, terminal, wireless communication device, user agent, user device or User equipment (user equipment, UE).
  • the STA can be a cellular phone, a cordless phone, a session initiation protocol (SIP) phone, a wireless local loop (WLL) station, a personal digital assistant (PDA), and a wireless local area network (such as Wi-Fi) communication-enabled handheld devices, wearable devices, computing devices, or other processing devices connected to wireless modems.
  • SIP session initiation protocol
  • WLL wireless local loop
  • PDA personal digital assistant
  • Wi-Fi wireless local area network
  • the PCP/AP in the WLAN can be used to communicate with the STA through a wireless local area network, and transmit data from the STA to the network side, or transmit data from the network side to the STA.
  • the scenario system shown in FIG. 1 may be a WLAN system
  • the WLAN system in FIG. 3 may include one or more APs and one or more STAs
  • FIG. 3 takes one AP and three STAs as an example.
  • Various standards can be used for wireless communication between AP and STA. For example, single-user multiple-input multiple-output (SU-MIMO) technology or multi-user multiple-input multiple-output (MU) technology can be used between AP and STA.
  • SU-MIMO single-user multiple-input multiple-output
  • MU multi-user multiple-input multiple-output
  • -MIMO technology for wireless communication.
  • APs are also called wireless access points or hotspots.
  • APs are the access points for mobile users to enter the wired network. They are mainly deployed in homes, buildings, and campuses, and they can also be deployed outdoors.
  • AP is equivalent to a bridge connecting wired and wireless networks, and its main function is to connect various wireless network clients together, and then connect the wireless network to the Ethernet.
  • the AP may be a terminal device or a network device with a wireless fidelity (wireless fidelity, WiFi) chip.
  • the AP may be a device supporting multiple WLAN standards such as 802.11.
  • WLAN starts from 802.11a/g, goes through 802.11n, 802.11ac, to 802.11ax and 802.11be, which are currently under discussion.
  • the allowable transmission bandwidth and the maximum transmission rate supported are shown in Table 1 below.
  • Figure 4 shows an example of channel allocation in this application. As shown in Figure 2, the entire channel is divided into a primary 20MHz channel (or primary channel for short, Primary 20MHz, P20), a secondary 20MHz channel (Secondary 20MHz, S20), and 40MHz channel (S40), from 80MHz (S80) channel. In addition, there are corresponding P40 and P80. As the bandwidth increases, the data rate of data transmission also increases. Therefore, in the next generation of standards, larger bandwidths greater than 160MHz (such as 240MHz, 320MHz) will be considered.
  • Orthogonal Frequency Division Multiplexing can be used to implement simultaneous multi-user transmission.
  • OFDM is a multi-carrier transmission technology that uses a large number of adjacent orthogonal subcarriers, and each subcarrier is modulated by traditional modulation techniques, making the technology capable of high-speed transmission while being effective against Frequency selective fading (frequency selective fading), so many wireless transmission protocols have adopted orthogonal frequency division multiplexing.
  • PHY Protocol Data Unit PHY Protocol Data Unit
  • HE MU High Efficient Multiple User
  • Fig. 5 shows an example of a data frame (taking HE MU PPDU as an example) of the present application.
  • the traditional short training sequence (legacy short training field, L-STF) contains 10 repetitive parts.
  • the receiving end uses the repetition characteristics to detect PPDUs, obtain frequency and time (or correct) (correction) ).
  • the "traditional short training sequence” can also be referred to as a traditional short training sequence field, and in this application, the "field” can also be referred to as a domain or part, and the description of the same or similar situations is omitted below.
  • L-LTF legacy long training field
  • SIGNAL NOISE RATIO SIGNAL NOISE RATIO
  • the legacy signaling field (L-SIG) is used to carry rate and length information, and indicates the duration of the PPDU. For traditional stations, the transmission needs to be delayed for at least the duration of the PPDU to prevent interference.
  • the non-HE part of the L-SIG can be decoded by the HE site and the traditional site at the same time, and corresponding information can be obtained to ensure backward compatibility.
  • the repeat legacy signal field (RL-SIG) is a copy of the L-SIG symbol, so it has all the characteristics of the L-SIG. Copying L-SIG has the following advantages:
  • MRC maximum ratio combining
  • the receiving end detects whether the L-SIG and the following symbol are similar, as one of the basis for identifying whether the received PPDU is an HE PPDU.
  • HESIG-A The information carried in the high efficient signal field A (HE-SIG-A) can help analyze the HE PPDU.
  • HESIG-A in the HE MU PPDU contains related instructions on the high efficient signal field A (HESIG-B), for example, the number of HESIG-B symbols or multiple user multiple input (multiple user multiple input).
  • MUMIMO Multiple output
  • HESIG-B coding and modulation strategy HESIG-B compression (indicating whether to compress)
  • the corresponding modulation and coding parameters of the data part are respectively indicated for different users in the HE-SIG-B.
  • HE-SIG-B provides resource allocation information for OFDMA and MU-MIMO.
  • Fig. 6 shows an example of the structure of HE-SIG-B carried on a 20 MHz sub-channel. As shown in Figure 6, the entire HE-SIG-B is divided into two parts.
  • User field by user According to the order of resource unit allocation, there are 1 to Y user fields. There are usually 2 user fields in one group (except the last one), and every two user fields are followed by a CRC field and a tail field; the last user field may consist of one or two user fields and one user field. It is composed of the CRC field and the tail field.
  • the method of the present application can be used to transmit the information in one or more fields in the aforementioned data frame, for example, the information in HESIG-B.
  • FIG. 7 shows a schematic diagram of an example of the encoding and sending process of the information #A1 by the transmitting end device (denoted as device #A1) in Embodiment 1.
  • the information #A1 may correspond to the above-mentioned HESIG-B Information.
  • the process of determining (or generating) the information #A1 by the device #A1 may be the same or similar to the prior art. In order to avoid redundant description, the detailed description is omitted here.
  • the device #A1 may be an AP, or the device #A1 may also be a STA, and this application is not particularly limited.
  • the channel between the device #A1 and the receiving end device of the data frame (for example, the device #A2 described later) can be reduced to N sub-channels, where N ⁇ 2.
  • device #A1 encodes information #A1 (that is, an example of the first information) through a 1/2 rate convolutional code encoder (Convolutional Code Encoder, CC encoder) to generate chip #A1 and code chip# A2.
  • a 1/2 rate convolutional code encoder Convolutional Code Encoder, CC encoder
  • the device #A1 can add W bits (ie, tail bits) to the information #A1, and input the 1/2 code rate convolutional code encoder, and the output two chips (ie, chip #A1 and code One chip in slice #A2) includes bits generated based on one convolution coefficient in a rate 1/2 convolutional code encoder.
  • the other chip includes bits generated based on another convolution coefficient in a rate 1/2 convolutional code encoder.
  • chip #A1 and chip #A2 have the same length, and chip# The lengths of A1 and chip #A2 are the same as the length of information #A1.
  • the number of W corresponds to the number of shift registers used in the 1/2 rate convolutional code encoder (for example, the same).
  • the length of the chip #A1 and chip #A2 may be the length corresponding to the 20 MHz sub-channel, that is, in this application, the size of a chip is sufficient to be able to transmit on a 20 MHz sub-channel. .
  • the device #A1 interleaves the information #A1 through the interleaver #A to generate the information #A2 (that is, an example of the second information).
  • Interleaving is a technology used for data processing in communication systems.
  • an interleaver is a device that achieves maximum change of information structure without changing information content.
  • the interleaver #A may include a regular interleaver.
  • a regular interleaver can also be called a packet interleaver, that is, an interleaver that reads rows in rows or rows out in columns.
  • a simple 3 x 3 interleaving matrix can include 32 interleaving methods, but these 32 types Although there are many differences in the form of the reading, but in terms of its essence, the characteristics shown are completely the same. So they can be summarized into four limited forms. We use L for left, R for right, T for up, and B for down. Then these four interleavers can be expressed in turn: LR/TB, LR/BT, RL /TB, RL/BT. LR means writing people from left to right, TB means reading from top to bottom, and so on for other representations.
  • the interleaver #A may include an irregular interleaver.
  • irregular interleaver is mostly derived from the above four group interleavers. At present, there are mainly diagonal interleaver, spiral interleaver, and odd-even interleaver.
  • the diagonal interleaver and the spiral interleaver both use line writing and diagonal reading.
  • the difference between the two is that the diagonal interleaver is line writing and then reads diagonally from the first element of the first line , And the spiral interleaver reads diagonally from the first element of the last row.
  • the parity interleaver is a method of adding constraints to the generation of the interleaver in conjunction with the puncturing technique.
  • the puncturing technology is actually sending information into the channel in the form of puncturing and puncturing short codes in the process of encoding and decoding, and the receiving end restores it by adding analog zeros.
  • the interleaver #A may include a random interleaver.
  • the random interleaver can also be called a pseudo-random interleaver, that is, an interleaving method with better performance generated by random selection in advance, and then stored in the form of a table for reading.
  • the random performance of the random interleaver mainly depends on the random number generation method, the main parameter S of the interleaver, and the selection of values. For example, it is possible to generate random numbers based on the beth-ram shuffling technique based on linear residuals and random sampling of the system clock.
  • the random interleaver for example, an S-random interleaver, a T-random interleaver, or a T-random interleaver can be cited.
  • the random number generation of the S-random interleaver is similar to other interleavers, except that it has an additional condition, requiring that the information bits of the information sequence length S before interleaving must be adjacent to more than S+1 units after interleaving , In fact, is to let the interleaver have the characteristics of the largest dispersion factor parameter.
  • T-random interleaver is a special random interleaver. It requires that the distance between any pair of adjacent information bits in the codeword after interleaving be greater than the constraint length of the entire code.
  • S-T-Random Interleaver This interleaver is actually a combination of the two generation conditions of S-random interleaver and T-random interleaver.
  • the device #A1 encodes the information #A2 through the 1/2 rate convolutional code encoder to generate chip #A3 and chip #A4.
  • the process is similar to that in S110, the device #A1 uses the 1/2 rate convolutional code encoder to encode the information #A1.
  • the device #A1 uses the 1/2 rate convolutional code encoder to encode the information #A1.
  • the S110 and S120 can be executed synchronously, or the S110 and S120 can also be executed asynchronously.
  • This application is not particularly limited, and when the S110 and S120 are executed asynchronously, the execution order can be set arbitrarily , This application is not particularly limited.
  • the device #A1 may generate a data frame #A, and the data frame #A may include multiple chips from the above-mentioned chip #A1 to chip #A4.
  • the number of sub-channels is less than 4, that is, N ⁇ 3.
  • device #A1 can select N chips from the above chip #A1 to chip #A4, and the device #A1 can perform interleaving and constellation mapping on each of the N chips, and then map each chip to a subchannel.
  • device #A1 can perform interleaving and constellation mapping on each of the N chips, and then One chip is mapped to one sub-channel.
  • the channel width is greater than 80MHz
  • the number of sub-channels is greater than 4, that is, N>4.
  • device #A1 can perform interleaving and constellation mapping on each of the aforementioned chip #A1 to chip #A4 , And then map each chip to 4 sub-channels in an 80 MHz bandwidth.
  • part or all of the content (or chips) on the 80 MHz bandwidth can be repeatedly sent on other bandwidths.
  • the channel width is 160Mhz
  • device #A1 can perform interleaving and constellation mapping on each of the aforementioned chip #A1 to chip #A4, Then, each chip is mapped to 4 sub-channels in an 80 MHz bandwidth (denoted as bandwidth a1). And, the content of the bandwidth a1 can be repeatedly sent on another 80MHz bandwidth.
  • the channel width is 240MHz
  • three 80Ms send the same content, and 4 different chips are sent on different 20Ms within each 80MHz.
  • the channel width is 320MHz
  • the content of 80MHz can be repeated 4 times.
  • the device #A1 and the device #A2 may also include a mapping relationship #A (that is, an example of the first mapping relationship), and the mapping relationship #A is used to indicate the status of each of the multiple sub-channels. Corresponding information of the interleaver.
  • a mapping relationship #A that is, an example of the first mapping relationship
  • mapping relationship #A may be specified by the communication system or communication protocol, or the mapping relationship #A may also be negotiated and determined by the device #A1 and the device #A2, which is not specifically limited in this application.
  • the interleaver corresponding information of a subchannel can be used to indicate whether the chip corresponding to the subchannel #A1 has undergone interleaving (for example, the above-mentioned interleaver #A).
  • the interleaver corresponding information of the subchannel #A1 may be used to indicate whether the chip corresponding to the subchannel #A1 is generated based on the above information #A1 or the above information #A2.
  • the device #A1 may map the chip generated as described above to the corresponding sub-channel according to the mapping relationship #A.
  • the device #A1 may send the aforementioned data frame #A through at least two of the N channels. For example, the device #A1 may puncture one or more of the N channels as required.
  • the channel bandwidth is less than or equal to 80MHz
  • when puncturing is performed it is only necessary to ensure that chips can be sent through at least two sub-channels within the 80Mhz bandwidth, that is, to ensure that at least two sub-channels can be transmitted. All sub-channels are not punctured.
  • FIG. 8 is a schematic diagram showing an example of the decoding process of the receiving end device (denoted as device #A2) in the first embodiment.
  • the device #A2 can be a STA or an AP.
  • the device #A2 can be a STA or an AP.
  • the device #A2 may receive chips from at least two sub-channels among the N sub-channels.
  • the device #A2 can determine the interleaver corresponding information of the sub-channel that carries the chip.
  • the device #A2 can determine the interleaver corresponding information of the subchannel #An according to the above mapping relationship #A, that is, whether the chip #An After the interleaving process of the above-mentioned interleaver #A.
  • the device #B1 can decode the at least two chips by, for example, a Viterbi decoder. Restore the message #A1.
  • the device #B1 can use, for example, turbo ) Iterative decoding decodes the at least two chips, and then information #A1 can be recovered.
  • the device #A2 determines the demodulation confidence of the corresponding chip of each subchannel according to the chip reception of each of the N subchannels, where the demodulation confidence is also It can be called confidence or log likelihood ratio (LLR), etc. For example, if a subchannel does not carry a chip (or the subchannel is punctured), the value of the chip corresponding to the subchannel is The demodulation confidence is set to zero.
  • LLR log likelihood ratio
  • the confidence of the chip can be The determination is based on the confidence level of any one of the multiple sub-channels, or the confidence level of the chip may be determined based on the average value of the confidence levels of the multiple sub-channels in the multiple sub-channels.
  • device #A2 can input the determined confidence of chip #A1 and chip #A2, for example, to a Viterbi decoder to obtain output result #A1, and pair it based on interleaver #A.
  • the output result #A1 is interleaved to obtain the output result #A2, and the confidence of the determined chip #A1 and the chip #A2 and the output result #A2 are input into the Viterbi decoder to obtain the output result #A3, and
  • the output result #A3 and the confidence of the determined chip #A1 and chip #A2 are input to the Viterbi decoder, and the output result is used as the decoding result, thereby restoring the information #A1.
  • FIG. 9 shows a schematic diagram of an example of the encoding and sending process of the information #B1 by the transmitting end device (denoted as device #B1) of the second embodiment.
  • the information #B1 may correspond to the above-mentioned HESIG-B Information.
  • the process of determining (or generating) the information #B1 by the device #B1 may be the same or similar to the prior art. In order to avoid repetitive descriptions, detailed descriptions are omitted here.
  • the device #B1 may be an AP, or the device #B1 may also be a STA, and this application is not particularly limited.
  • the channel between the device #B1 and the receiving end device of the data frame (for example, the device #B2 described later) can be reduced to N sub-channels, where N ⁇ 2.
  • the device #B1 encodes the information #B1 (that is, an example of the first information) by the 1/2 rate convolutional code encoder to generate chip #B1 and chip #B2.
  • the process may be similar to the process of S110 described above. Here, in order to avoid redundant description, the detailed description is omitted.
  • device #B1 interleaves information #B1 through M interleavers (denoted as, interleaver #B1 ⁇ interleaver #BM), respectively, to generate M pieces of information, (denoted as, information #B2 ⁇ information #BM) , That is, an example of the second information).
  • the M interleavers are different, or in other words, any two pieces of information (specifically, the bit sequence of the information) in the information #B2 to information #BM+1 are different.
  • the device #B1 encodes the information #B2 through the 1/2 rate convolutional code encoder to generate chip #B3 and chip #B4.
  • device #B1 encodes information #B3 through a rate 1/2 convolutional code encoder to generate chip #B5 and chip #B6, and analogously to device #B1 through a rate 1/2 convolutional code encoder
  • the information #BM is encoded to generate chip #B2M+1 and chip #B2(M+1).
  • device #B1 encodes information #BM+1 with a rate 1/2 convolutional code encoder to generate a chip, which can also be recorded as chip #BN-1 and chip# BN.
  • the device #B1 encodes the information #BM+1 with a rate 1/2 convolutional code encoder to generate a chip, which can also be recorded as chip #BN and chip #BN+1.
  • the S210 and S220 can be executed synchronously, or the S210 and S220 can also be executed asynchronously.
  • This application is not particularly limited, and when the S210 and S220 are executed asynchronously, the execution order can be set arbitrarily , This application is not particularly limited.
  • the device #B1 may generate a data frame #B, and the data frame #B may include N chips out of the above-mentioned chip #B1 to chip #B2 (M+1).
  • the device #B1 may perform interleaving and constellation mapping on each of the above N chips, and then map each chip to a subchannel.
  • the device #B1 and the device #B1 may also include a mapping relationship #B (that is, an example of the first mapping relationship), and the mapping relationship #B is used to indicate the status of each of the multiple sub-channels. Corresponding information of the interleaver.
  • a mapping relationship #B that is, an example of the first mapping relationship
  • mapping relationship #B may be specified by the communication system or communication protocol, or the mapping relationship #B may also be negotiated and determined by the device #B1 and the device #B2, which is not specifically limited in this application.
  • the interleaver corresponding information of a subchannel (for example, subchannel #B1) can be used to indicate whether the chip corresponding to the subchannel #B1 has been interleaved (for example, the above-mentioned interleaver #B1 ⁇ interleaver#
  • the interleaver corresponding information of the subchannel #B1 can be used to indicate whether the chip corresponding to the subchannel #B1 is generated based on the above information #B1 or based on the above information #B2 ⁇ Information #BM+1 generated.
  • the interleaver corresponding information of the subchannel #B1 indicates that the chip carried by the subchannel #B1 is a chip after the interleaving process
  • the interleaver corresponding information of the subchannel #B1 is also used to indicate the subchannel
  • the chip corresponding to #B1 is specifically processed by the interleaver of the above-mentioned interleaver #B1 ⁇ Interleaver #BM, or in other words, the interleaver corresponding information of the subchannel #B1 is also used to indicate the subchannel# The interleaver corresponding to B1.
  • the device #B1 may map the chip generated as described above to the corresponding sub-channel according to the mapping relationship #B.
  • the device #B1 may send the aforementioned data frame #B through at least two of the N channels. For example, the device #B1 may puncture one or more of the N channels as required.
  • FIG. 10 is a schematic diagram showing an example of the decoding process of the receiving end device (denoted as device #B2) of the second embodiment.
  • the device #B2 can be a STA or an AP.
  • the device #B2 can be a STA or an AP.
  • the device #B2 may receive chips from at least two sub-channels among the N sub-channels.
  • Device #B2 can determine the interleaver corresponding information of the sub-channel that carries the chip.
  • device #B2 can determine the interleaver corresponding information of subchannel #Bn according to the above mapping relationship #B, that is, whether chip #Bn is After the interleaving process of the above-mentioned interleaver #B.
  • the device #B1 can decode the at least two chips by, for example, a Viterbi decoder. Restore the message #B1.
  • the device #B1 can be iteratively translated by, for example, Topology After the code decodes the at least two chips, information #B1 can be recovered.
  • the device #B2 determines the demodulation confidence of the corresponding chip of each subchannel according to the chip reception of each of the N subchannels, where the demodulation confidence is also It can be called confidence or log likelihood ratio (LLR), etc. For example, if a subchannel does not carry a chip (or the subchannel is punctured), the value of the chip corresponding to the subchannel is The demodulation confidence is set to zero.
  • LLR log likelihood ratio
  • device #B2 can input the confidence of the determined chip #B1 and chip #B2 into, for example, a Viterbi decoder to obtain the output result #B1, and pair it based on the interleaver #B1
  • the output result #B1 is interleaved to obtain the output result #B2
  • the confidence of the determined chip #B1 and the chip #B2 and the output result #B2 are input into the Viterbi decoder to obtain the output result #B3, and based on Interleaver #B2 performs interleaving processing on output result #B3 to obtain output result #B4, and inputs the determined chip #B3 and chip #B4's confidence and output result #B5 into the Viterbi decoder to obtain the output result #B6.
  • device #B2 interleaves the input decoding result based on the interleaver corresponding to each sub-channel chip (or each sub-channel), and interleaves the interleaved result and the chip corresponding to the sub-channel.
  • the confidence is input into the Viterbi decoder, and the message #B1 is recovered after iterating in turn.
  • FIG. 11 shows a schematic diagram of an example of the encoding and sending process of the information #C1 by the sending end device (denoted as device #C1) of the third embodiment.
  • the information #C1 may correspond to the above-mentioned HESIG-B Information.
  • the process of determining (or generating) the information #C1 by the device #C1 may be the same or similar to that in the prior art. In order to avoid redundant description, the detailed description is omitted here.
  • the device #C1 may be an AP, or the device #C1 may also be a STA, and this application is not particularly limited.
  • the channel between the device #C1 and the receiving end device of the data frame (for example, the device #C2 described later) can be reduced to N sub-channels, where N ⁇ 2.
  • device #C1 can generate chip #C1 according to information #C1.
  • device #C1 can fill W stuffing bits after information #C1 to generate chip #C1.
  • the value of W corresponds to the number of shift registers used in the recursive system convolutional code encoder (for example, the same).
  • device #C1 interleaves information #C1 through 3 interleavers (denoted as, interleaver #C1 ⁇ interleaver #C3), respectively, to generate 3 pieces of information, (denoted as, information #C2 ⁇ #C4 , That is, an example of the second information).
  • the three interleavers are different, or in other words, any two pieces of information (specifically, the bit sequence of the information) in the information #C2 to information #C4 are different.
  • device #C1 encodes information #C2 to information #C4 through a recursive systematic convolutional code encoder (recursive systematic convolutional encoder, RSC encoder) to generate chip #C2 to chip #C4.
  • a recursive systematic convolutional code encoder recursive systematic convolutional encoder, RSC encoder
  • the device #C1 can add W bits (ie, tail bits) to the information #C2, and input the recursive system convolutional code encoder to output one chip (ie, chip #C2).
  • the lengths of chip #C1 to chip #C4 are the same.
  • the S310 and S320 can be executed synchronously, or the S310 and S320 can also be executed asynchronously.
  • This application is not particularly limited, and when the S310 and S320 are executed asynchronously, the execution order can be set arbitrarily , This application is not particularly limited.
  • the device #C1 may generate a data frame #C, and the data frame #C may include multiple chips from the above-mentioned chip #C1 to chip #C4.
  • the number of sub-channels is less than 4, that is, N ⁇ 3.
  • device #C1 can select N chips from the above-mentioned chips #C1 to chip #C4, and the device #C1 can perform interleaving and constellation mapping on each of the N chips, and then map each chip to a subchannel.
  • device #C1 can perform interleaving and constellation mapping on each of the N chips, and then One chip is mapped to one sub-channel.
  • the channel width is greater than 80MHz
  • the number of sub-channels is greater than 4, that is, N>4.
  • device #C1 can perform interleaving and constellation mapping on each of the above-mentioned chip #C1 to chip #C4 , And then map each chip to 4 sub-channels in an 80 MHz bandwidth.
  • part or all of the content (or chips) on the 80 MHz bandwidth can be repeatedly sent on other bandwidths.
  • the channel width is 160Mhz
  • device #C1 can perform interleaving and constellation mapping on each of the above-mentioned chip #C1 to chip #C4, Then map each chip to 4 sub-channels in an 80 MHz bandwidth (denoted as bandwidth c1). And, the content of bandwidth c1 can be repeatedly sent on another 80MHz bandwidth.
  • the channel width is 240MHz
  • three 80Ms send the same content, and 4 different chips are sent on different 20Ms within each 80MHz.
  • the channel width is 320MHz
  • the content of 80MHz can be repeated 4 times.
  • the device #C1 and the device #C2 may also include a mapping relationship #C (that is, an example of the first mapping relationship), and the mapping relationship #C is used to indicate the status of each of the multiple sub-channels. Corresponding information of the interleaver.
  • a mapping relationship #C that is, an example of the first mapping relationship
  • mapping relationship #C may be specified by the communication system or communication protocol, or the mapping relationship #C may also be negotiated and determined by the device #C1 and the device #C2, which is not specifically limited in this application.
  • the interleaver corresponding information of a subchannel (for example, subchannel #C1) can be used to indicate whether the chip corresponding to the subchannel #C1 has been interleaved (for example, the aforementioned interleaver #C1 ⁇ interleaver#
  • the interleaver corresponding information of the subchannel #C1 can be used to indicate whether the chip corresponding to the subchannel #C1 is generated based on the above information #C1 or based on the above information #C2 ⁇ #C4 generated.
  • the interleaver corresponding information of the subchannel #C1 indicates that the chip carried by the subchannel #C1 is a chip after the interleaving process
  • the interleaver corresponding information of the subchannel #C1 is also used to indicate the subchannel
  • the chip corresponding to #C1 is specifically processed by the interleaver of the above-mentioned interleaver #C1 ⁇ interleaver #C4, or in other words, the interleaver corresponding information of the subchannel #C1 is also used to indicate the subchannel# C1 corresponds to the interleaver.
  • the device #C1 may map the chip generated as described above to the corresponding sub-channel according to the mapping relationship #C.
  • the device #C1 may send the aforementioned data frame #C through at least one of the N channels.
  • the device #C1 may puncture one or more of the N channels as required.
  • FIG. 12 is a schematic diagram showing an example of the encoding and transmission process of the transmitting end device according to the fourth embodiment.
  • device #C1 interleaves information #C1 through N-1 interleavers (denoted as interleaver #C1 ⁇ interleaver #CN-1). , Generate N-1 pieces of information, (denoted as, information #C2 ⁇ information #CN, that is, an example of the second information).
  • the N interleavers are different, or in other words, any two pieces of information (specifically, the bit sequence of the information) in the information #C2 to information #CN are different.
  • the device #C1 respectively encodes the information #C2 to the information #CN through a Recursive Systematic Convolutional Encoder (Recursive Systematic Convolutional Encoder) to generate chip #C2 to chip #CN.
  • a Recursive Systematic Convolutional Encoder Recursive Systematic Convolutional Encoder
  • the data frame #C may include multiple chips among the above-mentioned chip #C1 to chip #CN-1.
  • FIG. 13 is a schematic diagram showing an example of the decoding process of the receiving end device (denoted as device #C2) in the third and fourth embodiments.
  • the device #C2 can be a STA or an AP.
  • the device #C2 can be a STA or an AP.
  • the device #C2 may receive a chip from at least one sub-channel among the N sub-channels.
  • the device #C2 may determine the interleaver corresponding information of the subchannel carrying the chip.
  • the device #C2 can determine the interleaver corresponding information of the subchannel #Cn according to the above mapping relationship #C, that is, whether the chip #Cn is After the interleaving process of the above-mentioned interleaver #C.
  • device #C2 can decode the interleaver-processed chip through, for example, a Viterbi decoder to recover Message #C1.
  • the device #C2 may determine the interleaver corresponding to the chip according to the above mapping relationship #C, and based on the interleaver and Viterbi translation After the decoder decodes, the message #C1 can be recovered.
  • the device #C2 can also decode the at least two chips through, for example, Topology iterative decoding, to recover the information #C1.
  • the device #C2 determines the demodulation confidence of the corresponding chip of each subchannel according to the chip reception of each of the N subchannels, where the demodulation confidence is also It can be called confidence or log likelihood ratio (LLR), etc. For example, if a subchannel does not carry a chip (or the subchannel is punctured), the value of the chip corresponding to the subchannel is The demodulation confidence is set to zero.
  • LLR log likelihood ratio
  • the device #C2 can input the confidence of the determined chip #C1 into the interleaver #C1, and obtain the output result #C1, and the confidence of the output result #C1 and the chip #C2
  • the Viterbi decoder obtains the output result #C2, and de-interleaves the output result #C2 based on the de-interleaver corresponding to the interleaver #C1 to obtain the output result #C3, which is paired based on the interleaver C#2
  • the output result #C3 is interleaved to obtain the output result C#4, and the confidence of the output result #C4 and chip #3 is input into the Viterbi decoder, and the output result C#5 is obtained, which corresponds to the interleaver #C2
  • the deinterleaver deinterleaves the output result to obtain output result #C6.
  • device #C2 interleaves the input decoding result based on the interleaver corresponding to each sub-channel chip (or each sub-channel), and interleaves the interleaved result and the chip corresponding to the sub-channel.
  • the confidence is input to the Viterbi decoder, the output result is de-interleaved on the de-interleaver corresponding to the sub-channel, and the information #C1 is recovered after successive loop iterations.
  • FIG. 14 shows a schematic diagram of an example of the encoding and sending process of the information #D1 by the transmitting end device (denoted as device #D1) according to Embodiment 5.
  • the information #D1 may correspond to the above-mentioned HESIG-B Information.
  • the process of determining (or generating) the information #D1 by the device #D1 may be the same as or similar to the prior art. In order to avoid repetition, the detailed description is omitted here.
  • the device #D1 may be an AP, or the device #D1 may also be a STA, and this application is not particularly limited.
  • the channel between the device #D1 and the receiving end device of the data frame (for example, the device #D2 described later) can be reduced to N sub-channels, where N ⁇ 2.
  • the device #D1 divides the information #D1 (specifically, the bit stream or bit sequence of the information #D1) into T segments, T ⁇ 2.
  • every q bits in each segment is converted into a number on the finite field GF(2 ⁇ q). If the length of the bit stream is not an integer multiple of q, it can be supplemented by 0 or by 1.
  • the numbers on the transformed finite field will be arranged into a T ⁇ L matrix, which is denoted as matrix #D below, where the value of L is related to the length of information #D1, the size of T, and the size of q .
  • the device #D1 multiplies the aforementioned matrix #D with a precoding matrix (denoted as matrix #P) to obtain a precoded matrix #PD.
  • matrix #P a precoding matrix
  • the matrix #P is an N ⁇ T matrix, and any T rows of the matrix #P are linearly independent on the finite field GF(2 ⁇ q).
  • the matrix P includes some or all of the rows in the following matrix:
  • device #D1 converts each row of matrix #PD into a binary bit stream, and compares it with a convolutional code encoder (for example, a 1/2 rate convolutional code encoder or a recursive system convolutional code encoder, etc.)
  • the special stream is coded to form coded chips.
  • the device #D1 may also add parity bits in each binary bit stream.
  • the device #C1 can generate a data frame #C, and the data frame #C can include the above-mentioned coded chips. Specifically, the device #C1 performs interleaving and constellation mapping on each chip to convert each chip Map to a sub-channel (for example, a 20 MHz sub-channel).
  • the device #D1 may send the aforementioned data frame #C through at least T of the N subchannels. For example, the device #D1 may puncture one or more of the N channels as required.
  • any precoding matrix P that satisfies any T row it is linearly independent on the finite field GF(2 ⁇ q). If the matrix R is full rank, then the matrix P and the matrix R are multiplied to obtain The matrix of is also a precoding matrix satisfying that any T rows are linearly independent on the finite field GF(2 ⁇ q).
  • the upper half of the selected matrix is the identity matrix, so that the first T rows of the encoded matrix PD directly correspond to the original source sequence. Therefore, even if the receiving end only receives some of the first T rows, it can still correctly decode part of the information.
  • the device #D2 can receive chips (K ⁇ T) from K of the N subchannels.
  • the device #D2 can determine the row in the precoding matrix P corresponding to each of the K subchannels.
  • the device #D2 may arbitrarily select T subchannels from the K subchannels, and determine the row in the precoding matrix P corresponding to each of the T subchannels.
  • the row of the precoding matrix corresponding to the subchannel carrying the chip Dt can be understood as the t-th row in the precoding matrix P.
  • the device #D2 may include a mapping relationship #D (that is, an example of the first mapping relationship), and the mapping relationship #D is used to indicate the precoding matrix corresponding to each of the multiple sub-channels, That is, the rows in the matrix P.
  • a mapping relationship #D that is, an example of the first mapping relationship
  • mapping relationship #D may be specified by the communication system or communication protocol, or the mapping relationship #D may also be negotiated and determined by the device #D1 and the device #D2, which is not specifically limited in this application.
  • device #D2 can decode the chips on the K sub-channels by, for example, a Viterbi decoder to obtain a decoding result matrix E.
  • the decoding result matrix E includes K rows, and the K The rows correspond to the K sub-channels one-to-one, and each row includes the decoding result of the corresponding sub-channel chips.
  • the device #D2 may use a row in the matrix P corresponding to each of the K sub-channels as a row in the decoding matrix U, thereby generating a decoding matrix U including K rows.
  • the device #D2 can determine the inverse matrix H of the decoding matrix U.
  • the device #D2 can multiply the matrix E by the matrix H, and use the result as the decoding result, thereby restoring the information #D1.
  • the device #D2 can decode the chips on any T sub-channels among the K sub-channels by, for example, a Viterbi decoder to obtain the decoding result matrix E', and the decoding result
  • the matrix E' includes T rows, the T rows correspond to the above T sub-channels one-to-one, and each row includes the decoding result of the corresponding sub-channel chip.
  • the device #D2 may use the row in the matrix P corresponding to each of the T sub-channels as the row in the decoding matrix U', thereby generating the decoding matrix U'including the T rows.
  • the device #D2 can determine the inverse matrix H'of the decoding matrix U'.
  • the device #D2 can multiply the matrix E'and the matrix H', and use the result as the decoding result, thereby restoring the information #D1.
  • the device #D1 is an AP
  • the device #D2 can be a STA or an AP.
  • the device #D2 can be a STA or an AP.
  • FIG. 15 shows a schematic diagram of an example of the encoding and sending process of the information #E1 by the transmitting end device (denoted as device #E1) of the sixth embodiment.
  • the information #E1 may correspond to the above-mentioned HESIG-B Information.
  • the process of determining (or generating) the information #E1 by the device #E1 may be the same as or similar to the prior art, and the detailed description is omitted here to avoid redundancy.
  • the device #E1 may be an AP, or the device #E1 may also be a STA, and this application is not particularly limited.
  • the channel between the device #E1 and the receiving end device of the data frame (for example, the device #E2 described later) can be reduced to N sub-channels, where N ⁇ 2.
  • the device #E1 can divide the information #E1 (specifically, the bit stream of the information #E1) into two sequences of equal length, which are recorded as the sequence #E1 and the sequence #E2.
  • padding bits for example, 0 or 1 can be added to the segmented sequence of the information #E1, thereby generating the sequence #E1 and the sequence #E2.
  • equipment #E1 passes through two interleaver groups (denoted as, interleaver group #E1 ⁇ interleaver group #E2), respectively interleaving sequence #E1 and sequence #E2 to generate 2 sequences, (denoted as, Sequence #E3 ⁇ Sequence #E4, that is, an example of the second information).
  • each interleaver group includes two interleavers.
  • the two pieces of information correspond to the two interleaver groups one-to-one.
  • sequence #E3 corresponds to the interleaver group #E1
  • generation process of the sequence #E3 is as follows:
  • sequence #E1 is interleaved by an interleaver in the interleaver group #E1 to obtain the sequence #E1';
  • sequence #E2 is interleaved by another interleaver in the interleaver group #E1 to obtain the sequence #E2';
  • sequence #E1' and the sequence #E2' are added (specifically, binary addition) to obtain the sequence #E3.
  • the two interleaver groups are different, or in other words, the sequence #E3 and the sequence #E4 are different.
  • two interleavers of the same interleaver group can meet the following conditions:
  • m can represent the sequence number of the interleaver group #Em in the multiple interleaver groups, or m can be combined with the interleaver group.
  • the index of the sub-channel corresponding to the device group #Em is related.
  • sequence processed by one interleaver in the interleaver group #Em is the same as the sequence #E1, that is, one interleaver in the interleaver group #Em does not make any changes to the sequence.
  • the sequence processed by another interleaver in the interleaver group #Em is cyclically shifted by m bits relative to the sequence #E2.
  • the device #E1 uses an encoder, such as a 1/2 rate convolutional code encoder or a recursive system convolutional code encoder, to respectively encode the sequence #E1 ⁇ sequence #E4 to generate chip #E1 ⁇ code Piece #E4.
  • an encoder such as a 1/2 rate convolutional code encoder or a recursive system convolutional code encoder
  • the device #E1 may generate a data frame #E, and the data frame #E may include multiple chips from the above-mentioned chip #E1 to chip #E4.
  • the number of sub-channels is less than 4, that is, N ⁇ 3.
  • device #E1 can select N chips from the above-mentioned chips #E1 to chip #E4, and the device #E1 can perform interleaving and constellation mapping on each of the N chips, and then map each chip to a subchannel.
  • device #E1 can perform interleaving and constellation mapping on each of the N chips, and then One chip is mapped to one sub-channel.
  • the channel width is greater than 80MHz
  • the number of subchannels is greater than 4, that is, N>4.
  • device #E1 can perform interleaving and constellation mapping on each of the above-mentioned chip #E1 to chip #E4 , And then map each chip to 4 sub-channels in an 80 MHz bandwidth.
  • part or all of the content (or chips) on the 80 MHz bandwidth can be repeatedly sent on other bandwidths.
  • the channel width is 160Mhz
  • device #E1 can perform interleaving and constellation mapping on each of the above-mentioned chip #E1 to chip #E4, Then map each chip to 4 sub-channels in an 80 MHz bandwidth (denoted as bandwidth e1). And, the content of bandwidth e1 can be repeatedly sent on another 80MHz bandwidth.
  • the channel width is 240MHz
  • three 80Ms send the same content, and 4 different chips are sent on different 20Ms within each 80MHz.
  • the channel width is 320MHz
  • the content of 80MHz can be repeated 4 times.
  • the device #E1 and the device #E2 may also include a mapping relationship #E (that is, an example of the first mapping relationship), and the mapping relationship #E is used to indicate the status of each of the multiple sub-channels. Interleaver group corresponding information.
  • a mapping relationship #E that is, an example of the first mapping relationship
  • mapping relationship #E may be specified by the communication system or communication protocol, or the mapping relationship #E may also be negotiated and determined by the device #E1 and the device #E2, which is not specifically limited in this application.
  • the interleaver group corresponding information of a subchannel (for example, subchannel #E1) can be used to indicate whether the chip corresponding to the subchannel #E1 has been interleaved (for example, the aforementioned interleaver group #E1 ⁇ interleaving
  • the corresponding information of the interleaver group of the subchannel #E1 can be used to indicate whether the chip corresponding to the subchannel #E1 is generated based on the above information #E1 or is based on The above information #E2 ⁇ information #E4 are generated.
  • the interleaver group corresponding information of the subchannel #E1 indicates that the chip carried by the subchannel #E1 is a chip after the interleaving process
  • the interleaver group corresponding information of the subchannel #E1 is also used to indicate the The chip corresponding to the subchannel #E1 is specifically processed by the interleaver group in the interleaver group #E1 to the interleaver group #E4, or in other words, the interleaver group corresponding information of the subchannel #E1 is also used To indicate the interleaver group corresponding to the subchannel #E1.
  • the device #E1 may map the chip generated as described above to the corresponding sub-channel according to the mapping relationship #E.
  • the device #E1 may send the aforementioned data frame #E through at least two of the N channels.
  • the device #E1 may perform puncturing on one or more of the N channels as required.
  • the device #E1 passes through N-2 interleaver groups (denoted as, interleaver group #E1 to interleaver group #EN-2), respectively, to sequence # E1 and sequence #E2 are interleaved to generate N-2 sequences (denoted as sequence #E3 to sequence #EN, that is, an example of the second information).
  • the N-2 interleavers are different, or in other words, any two pieces of information (specifically, the bit sequence of the information) in the sequence #E3 to information #EN are different.
  • the device #E1 respectively encodes the sequence #E1 to the information #EN by the encoder to generate the chip #E1 to the chip #EN.
  • the data frame #E may include multiple chips among the aforementioned chip #E1 to chip #EN.
  • device #E2 can receive chips from K sub-channels out of N sub-channels, K ⁇ 2.
  • the device #E2 can be a STA or an AP.
  • the device #E2 can be a STA or an AP.
  • the device #E2 can decode the chips carried on the K sub-channels through a decoder.
  • the device #E2 can determine the interleaver group corresponding information of the K subchannels.
  • the device #E2 can determine the interleaver corresponding information of the subchannel #Ek according to the above mapping relationship #E, that is, whether the chip #Ek is After the interleaving process of the above-mentioned interleaver group.
  • the device #E2 can directly recover the information #E1 through the two decoded chips.
  • the device #E2 can determine the interleaver group of the chip #E3 (or the sub-channel carrying the chip #E3) according to the above mapping relationship #E, and based on the decoded chip #E3, the interleaver group and the decoded chip #E3 Chip #E1 restores chip #E2, and then restores information #E1 based on chip #E2 and chip #E1.
  • device #E2 can determine chip #E3 ( Or the interleaver group that carries the subchannel of chip #E3) and the interleaver group of chip #E4 (or the subchannel that carries chip #E4), and is based on the decoded chip #E3, chip# E4
  • the interleaver group restores chip #E1 and chip #E2, and then restores information #E1 based on chip #E2 and chip #E1.
  • the embodiment of the present application provides a communication device.
  • the device is used to implement the steps or procedures corresponding to the receiving end in the foregoing method embodiments.
  • the device is used to implement the steps or procedures corresponding to the sending end in the foregoing method embodiments.
  • FIG. 16 is a schematic block diagram of a communication device provided by an embodiment of the present application.
  • the device 600 may include a communication unit 610 and a processing unit 620.
  • the communication unit 610 can communicate with the outside, and the processing unit 620 is used for data processing.
  • the communication unit 610 may also be referred to as a communication interface or a transceiving unit.
  • the apparatus 600 can implement the execution corresponding to the sending end device (for example, device #A1, device #B1, device #C1, device #D1, device #E1) in the above method embodiment. Steps or procedures, where the processing unit 620 is configured to perform processing-related operations of the sending-end device in the foregoing method embodiment, and the communication unit 610 is configured to perform sending-related operations of the sending-end device in the foregoing method embodiment.
  • the sending end device for example, device #A1, device #B1, device #C1, device #D1, device #E1
  • the processing unit 620 is configured to perform processing-related operations of the sending-end device in the foregoing method embodiment
  • the communication unit 610 is configured to perform sending-related operations of the sending-end device in the foregoing method embodiment.
  • the apparatus 600 can implement execution corresponding to the receiving end device in the above method embodiment (for example, device #A2, device #B2, device #C2, device #D2, device #E2).
  • the communication unit 610 is used to perform the receiving-related operations of the receiving end device in the above method embodiment
  • the processing unit 620 is used to perform the processing related operations of the receiving end device in the above method embodiment.
  • the device 600 here is embodied in the form of a functional unit.
  • the term "unit” here can refer to application specific integrated circuits (ASICs), electronic circuits, processors used to execute one or more software or firmware programs (such as shared processors, proprietary processors, or groups). Processor, etc.) and memory, merged logic circuits, and/or other suitable components that support the described functions.
  • ASICs application specific integrated circuits
  • the apparatus 600 may be specifically the sending-end device in the foregoing embodiment, and may be used to execute each process and/or step corresponding to the sending-end device in the foregoing method embodiment.
  • the apparatus 600 may be specifically the receiving end device in the foregoing embodiment, and may be used to execute various processes and/or steps corresponding to the receiving end device in the foregoing method embodiment. To avoid repetition, details are not described herein again.
  • the apparatus 600 of each of the foregoing solutions has the function of implementing the corresponding steps performed by the sending end device in the foregoing method, or the apparatus 600 of each of the foregoing solutions has the function of implementing corresponding steps performed by the receiving end device of the foregoing method.
  • the functions can be realized by hardware, or by hardware executing corresponding software.
  • the hardware or software includes one or more modules corresponding to the above functions; for example, the communication unit can be replaced by a transceiver (for example, the sending unit in the communication unit can be replaced by a transmitter, and the receiving unit in the communication unit can be replaced by a receiver. Machine replacement), other units, such as the processing unit, etc., can be replaced by a processor to perform the transceiver operations and related processing operations in each method embodiment respectively.
  • the aforementioned communication unit may also be a transceiver circuit (for example, it may include a receiving circuit and a transmitting circuit), and the processing unit may be a processing circuit.
  • the device in FIG. 16 may be the AP or STA in the foregoing embodiment, or may be a chip or a chip system, for example, a system on chip (SoC).
  • the communication unit may be an input/output circuit or a communication interface; the processing unit is a processor, microprocessor, or integrated circuit integrated on the chip. There is no limitation here.
  • FIG. 17 shows a communication device 700 provided by an embodiment of the present application.
  • the device 700 includes a processor 710 and a transceiver 720.
  • the processor 710 and the transceiver 720 communicate with each other through an internal connection path, and the processor 710 is used to execute instructions to control the transceiver 720 to send signals and/or receive signals.
  • the device 700 may further include a memory 730, and the memory 730, the processor 710, and the transceiver 720 communicate with each other through an internal connection path.
  • the memory 730 is used to store instructions, and the processor 710 can execute the instructions stored in the memory 730.
  • the apparatus 700 is used to implement each process corresponding to the sending end device (for example, device #A1, device #B1, device #C1, device #D1, device #E1) in the foregoing method embodiment. And steps.
  • the apparatus 700 is used to implement the receiving end devices (for example, device #A2, device #B2, device #C2, device #D2, device #E2) corresponding to each of the foregoing method embodiments. Process and steps.
  • the apparatus 700 may be specifically the AP or STA in the foregoing embodiment, or may be a chip or a chip system.
  • the transceiver 720 may be the transceiver circuit of the chip, which is not limited here.
  • the apparatus 700 may be used to execute various steps and/or procedures corresponding to the sending end or the receiving end in the foregoing method embodiments.
  • the memory 730 may include a read-only memory and a random access memory, and provide instructions and data to the processor. A part of the memory may also include a non-volatile random access memory.
  • the memory can also store device type information.
  • the processor 710 may be configured to execute instructions stored in the memory, and when the processor 710 executes the instructions stored in the memory, the processor 710 is configured to execute each step and/or of the above-mentioned method embodiment corresponding to the AP or STA Or process.
  • each step of the above method can be completed by an integrated logic circuit of hardware in the processor or instructions in the form of software.
  • the steps of the method disclosed in the embodiments of the present application may be directly embodied as being executed and completed by a hardware processor, or executed and completed by a combination of hardware and software modules in the processor.
  • the software module can be located in a mature storage medium in the field, such as random access memory, flash memory, read-only memory, programmable read-only memory, or electrically erasable programmable memory, registers.
  • the storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware. In order to avoid repetition, it will not be described in detail here.
  • the processor in the embodiment of the present application may be an integrated circuit chip with signal processing capability.
  • the steps of the foregoing method embodiments can be completed by hardware integrated logic circuits in the processor or instructions in the form of software.
  • the above-mentioned processor may be a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components .
  • the processors in the embodiments of the present application may implement or execute the methods, steps, and logical block diagrams disclosed in the embodiments of the present application.
  • the general-purpose processor may be a microprocessor or the processor may also be any conventional processor or the like.
  • the steps of the method disclosed in the embodiments of the present application may be directly embodied as being executed and completed by a hardware decoding processor, or executed and completed by a combination of hardware and software modules in the decoding processor.
  • the software module can be located in a mature storage medium in the field, such as random access memory, flash memory, read-only memory, programmable read-only memory, or electrically erasable programmable memory, registers.
  • the storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.
  • the memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory can be read-only memory (ROM), programmable read-only memory (programmable ROM, PROM), erasable programmable read-only memory (erasable PROM, EPROM), and electrically available Erase programmable read-only memory (electrically EPROM, EEPROM) or flash memory.
  • the volatile memory may be random access memory (RAM), which is used as an external cache.
  • RAM random access memory
  • static random access memory static random access memory
  • dynamic RAM dynamic RAM
  • DRAM dynamic random access memory
  • synchronous dynamic random access memory synchronous DRAM, SDRAM
  • double data rate synchronous dynamic random access memory double data rate SDRAM, DDR SDRAM
  • enhanced synchronous dynamic random access memory enhanced SDRAM, ESDRAM
  • synchronous connection dynamic random access memory serial DRAM, SLDRAM
  • direct rambus RAM direct rambus RAM
  • FIG. 18 shows a communication device 800 provided by an embodiment of the present application.
  • the device 800 includes a processing circuit 810 and a transceiver circuit 820.
  • the processing circuit 810 and the transceiver circuit 820 communicate with each other through an internal connection path, and the processing circuit 810 is used to execute instructions to control the transceiver circuit 820 to send signals and/or receive signals.
  • the device 800 may further include a storage medium 830, and the storage medium 830 communicates with the processing circuit 810 and the transceiver circuit 820 through internal connection paths.
  • the storage medium 830 is used to store instructions, and the processing circuit 810 can execute the instructions stored in the storage medium 830.
  • the apparatus 800 is used to implement each process corresponding to the sending end device (for example, device #A1, device #B1, device #C1, device #D1, device #E1) in the foregoing method embodiment And steps.
  • the apparatus 800 is used to implement each of the receiving end devices (for example, device #A2, device #B2, device #C2, device #D2, device #E2) in the foregoing method embodiment. Process and steps.
  • FIG 19 shows the internal structure diagram of the AP product.
  • the AP can be multi-antenna or single-antenna.
  • the AP includes a physical layer (PHY) processing circuit and a media access control (media access control, MAC) layer processing circuit.
  • the physical layer processing circuit can be used to process physical layer signals
  • the MAC layer processing circuit can be used For processing MAC layer signals.
  • FIG. 20 shows the internal structure diagram of STA products.
  • STA products are usually terminal products that support the 802.11 series of standards, such as mobile phones, laptops, etc.
  • Figure 20 shows the STA structure diagram of a single antenna.
  • STA It can also be multi-antenna, and it can be a device with more than two antennas.
  • the STA may include a PHY layer processing circuit and a MAC layer processing circuit.
  • the physical layer processing circuit may be used to process physical layer signals
  • the MAC layer processing circuit may be used to process MAC layer signals.
  • the present application also provides a computer program product, the computer program product includes: computer program code, when the computer program code runs on a computer, the computer executes the steps shown in FIGS. 7 to 15 The method in any embodiment shown.
  • the present application also provides a computer-readable medium that stores program code, and when the program code runs on a computer, the computer executes the steps shown in FIGS. 7 to 15 The method in any embodiment shown.
  • the present application also provides a system, which includes the aforementioned one or more stations and one or more access points.
  • the disclosed system, device, and method can be implemented in other ways.
  • the device embodiments described above are merely illustrative, for example, the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components can be combined or It can be integrated into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • the functional units in the various embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium.
  • the technical solution of this application essentially or the part that contributes to the existing technology or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (read-only memory, ROM), random access memory (random access memory, RAM), magnetic disk or optical disk and other media that can store program code .

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Abstract

本申请提供了发送数据帧的方法、接收数据帧的方法及通信装置，该发送数据帧的方法包括：基于第一编码器对第一信息进行编码，以生成第一码片和第二码片；基于M个交织器，对所述第一信息进行交织处理，生成M个信息，其中，所述M个信息与所述M个交织器一一对应；基于所述第一编码器对所述M个信息进行编码处理，以生成2M个码片；生成数据帧，所述数据帧包括N个码片，所述N个码片包括所述第一码片、所述第二码片和所述2M个码片中的全部或部分码片；通过所述N个子信道中的至少两个子信道发送所述数据帧。从而，接收端能够根据任意两个子信道的码片以及子信道对应的交织器信息恢复出第一信息，能够提高前导码打孔的灵活性和通信的鲁棒性。

Description

发送数据帧的方法、接收数据帧的方法及通信装置
本申请要求于2020年6月18日提交中国专利局、申请号为202010558954.X、申请名称为“发送数据帧的方法、接收数据帧的方法及通信装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及通信领域，并且更具体地，涉及发送数据帧的方法、接收数据帧的方法及通信装置。
背景技术
随着WLAN(wireless local area network，无线局域网)技术的发展，每一代标准所支持的最大信道带宽通过信道绑定机制逐渐增大，从802.11a/g标准支持的20MHz信道带宽，到802.11n标准支持的20MHz/40MHz信道带宽，再到802.11ac标准支持的20MHz/40MHz/80MHz/160MHz/80MHz+80MHz的信道带宽，未来的标准(例如，802.11be)能够支持240MHz、320MHz甚至更高带宽。
然而，连续的信道绑定机制也有弊端，在802.11ac标准中当绑定信道中某一个窄带从属信道为忙碌时，发送端将无法采用更大的从属信道。以80MHz信道为例，如果从属20MHz信道为忙碌时，即使从属40MHz信道空闲，发送端也只能使用主20MHz信道的带宽，浪费了从属40MHz信道的空口资源。
为了解决这一问题，802.11ax标准除了同802.11ac标准一样，支持连续信道绑定以外，还引入了前导码打孔机制进一步提高频谱利用率。前导码打孔在讨论初期，被称为非连续的信道绑定(non-contiguous channel bonding，NCB)。一个前导码打孔模式的示例如图1所示。
现有技术中，数据帧中的某些字段例如，高效信令字段B(high efficient signal field B，HE-SIG B)等，长度较大，因此，希望将该字段中的信息通过不同的子信道传输。
例如，在802.11ax标准引入了内容信道(content channel，CC)的概念。如图2所示，当HE-SIG-B承载的信息的带宽为20MHz时，HE-SIG-B包括1个内容信道，该1个内容信道对应一个子信道；当HE-SIG-B承载的信息的带宽为40MHz时，HE-SIG-B包括两个内容信道，记做：CC1和CC2，该CC1对应一个子信道，该CC2对应一个子信道；当数据报文带宽为80MHz时，HE-SIG-B包括两个内容信道，此时，该两个内容信道按照规定顺序，即CC1、CC2、CC1、CC2的顺序对应于在4个子信道；当数据报文带宽为160MHz时，在80MHz的基础上进一步扩展，HE-SIG-B包括两个内容信道，该两个内容信道按照规定顺序，即CC1、CC2、CC1、CC2、CC1、CC2、CC1、CC2的顺序对应于8个子信道。
并且，在现有技术中，接收端必须接收到至少一个CC1和至少一个CC2才能完整的 恢复出内容信道承载的信息，因此，通信的鲁棒性较差，并且，支持的打孔模式受限，例如，不支持两个CC1或两个CC2所在的20M同时被打孔的模式。
发明内容
本申请提供一种发送数据帧的方法、接收数据帧的方法及通信装置，能够提高通信的鲁棒性，提高打孔的灵活性。
第一方面，提供一种发送数据帧的方法，在信道划分为N个子信道的通信系统中执行，N≥2，所述方法包括：发送端设备基于第一编码器对第一信息进行编码，以生成第一码片和第二码片，所述第一编码器包括1/2卷积码编码器，所述第一信息包括数据帧的前导码字段对应的部分或全部信息；基于M个交织器，对所述第一信息进行交织处理，生成M个信息，其中，所述M个信息与所述M个交织器一一对应，其中，所述M个信息中的第m信息是基于所述M个交织器中的第m交织器的交织处理生成的，所述第m信息与所述第m交织器对应，m∈[2，M+1]，M≥1；基于所述第一编码器对所述M个信息进行编码处理，以生成2M个码片，其中，所述2M个码片中的第2m+1码片和第2(m+1)码片是所述第m信息经过编码处理后生成的；生成数据帧，所述数据帧包括N个码片，所述N个码片与所述N个子信道一一对应，每个子信道用于承载所对应的码片，所述N个码片包括所述第一码片、所述第二码片和所述2M个码片中的全部或部分码片；通过所述N个子信道中的至少两个子信道发送所述数据帧。
根据本申请提供的方案，通过在发送端基于多个交织器对待发送的目标信息分别进行交织处理，并进一步对经过交织处理后的信息进行编码，并通过多个子信道分别发送经过编码后的信息，接收端能够根据多个信道中的任意两个信道上的信息以及该两个信道对应的交织器信息，恢复出所述目标信息，从而，能够提高针对上述多个信道的打孔的灵活性，并提高通信的鲁棒性。
可选地，M＝1。
具体地说，在一种实施方式中，一个码片的大小对应一个20MHz的子信道，即，当M＝1时，根据本申请提供的方案生成4个码片，该4个码片分别对应于一个80Hz的带宽内的4个子信道(每个子信道的带宽为20MHz)。
此情况下，当本申请的通信系统使用的信道的带宽为80Mhz时，N的值为4，从而，当M＝1时，根据本申请的方案生成4个码片，每个码片对应一个子信道。
当本申请的通信系统使用的信道的带宽为160Mhz时，N的值可以为8，从而，当M＝1时，首先根据本申请的方案生成4个码片，每个码片对应80Mhz的带宽内的一个子信道，其中，80Mhz的带宽包括4个子信道(每个子信道的带宽为20MHz)。其后，可以将该80Mhz的带宽对应的4个码片进行复制，并将复制得到的4个码片分别承载于160Mhz信道的另外80Mhz的带宽内的4个子信道。
依次类推，当本申请的通信系统使用的信道的带宽为Q×80Mhz时，N的值可以为Q×4，从而，当M＝1时，首先根据本申请的方案生成4个码片，每个码片对应80Mhz的带宽内的一个子信道，其中，80Mhz的带宽包括4个子信道(每个子信道的带宽为20MHz)。其后，可以将该80Mhz的带宽对应的4个码片进行Q次复制，并将复制得到的Q×4个码片分别承载于160Mhz信道的另外(Q-1)×80Mhz的带宽内的(Q-1)4个子信道。
可选地，M的值为N/2向上取整后减1的结果。
具体地说，在一种实施方式中，一个码片的大小对应一个20MHz的子信道，即，当M的值为N/2向上取整后减1的结果时，
如果本申请的通信系统使用的信道的带宽为80Mhz，则N的值为4，根据本申请的方案生成4个码片，每个码片对应一个子信道。
如果本申请的通信系统使用的信道的带宽为160Mhz，则N的值为8，当M的值为N/2向上取整后减1的结果(此情况下为3)时，根据本申请的方案生成8个码片，每个码片对应一个子信道。
依次类推，当本申请的通信系统使用的信道的带宽为Q×80Mhz时，N的值为Q×4，当M的值为N/2向上取整后减1的结果(此情况下为Q×2-1)时根据本申请的方案生成Q×4个码片，每个码片对应一个子信道。
可选地，所述方法还包括：根据第一映射关系，确定所述M个交织器，其中，所述第一映射关系包括所述N个子信道中的每个子信道的交织器对应信息，其中，所述第m交织器是第2m+1子信道和第2(m+1)子信道对应的交织器，所述第2m+1子信道用于传输所述第2m+1码片，所述第2(m+1)子信道用于传输所述第2(m+1)码片。
第二方面，提供一种发送数据帧的方法，在信道划分为N个子信道的通信系统中执行，N≥2，所述方法包括：发送端设备根据第一信息，生成第一码片，所述第一信息包括数据帧的前导码字段对应的部分或全部信息；基于M个交织器，对所述第一信息进行交织处理，生成M个信息，其中，所述M个信息与所述M个交织器一一对应，其中，所述M个信息中的第m信息是基于所述M个交织器中的第m交织器的交织处理生成的，所述第m信息与所述第m交织器对应，m∈[2，M+1]，M≥1；基于第一编码器对所述M个信息进行编码，以生成M个码片，所述第一编码器包括递归系统卷积码编码器；生成数据帧，所述数据帧包括N个码片，所述N个码片与所述N个子信道一一对应，每个子信道用于承载所对应的码片，所述N个码片包括所述第一码片和所述M个码片中的全部或部分码片；通过所述N个子信道中的至少两个子信道发送所述数据帧。
根据本申请提供的方案，通过在发送端基于多个交织器对待发送的目标信息分别进行交织处理，并进一步对经过交织处理后的信息进行编码，并通过多个子信道分别发送经过编码后的信息，接收端能够根据多个信道中的任意两个信道上的信息以及该两个信道对应的交织器信息恢复出该目标信息，从而，能够提高针对上述多个信道的打孔的灵活性，并提高通信的鲁棒性。
可选地，M＝3。
具体地说，在一种实施方式中，一个码片的大小对应一个20MHz的子信道，即，当M＝3时，根据本申请提供的方案生成4个码片，该4个码片分别对应于一个80Hz的带宽内的4个子信道(每个子信道的带宽为20MHz)。
此情况下，当本申请的通信系统使用的信道的带宽为80Mhz时，N的值可以为4，当M＝3时，根据本申请的方案生成4个码片，每个码片对应一个子信道。
当本申请的通信系统使用的信道的带宽为160Mhz时，N的值可以为8，当M＝3时，首先根据本申请的方案生成4个码片，每个码片对应80Mhz的带宽内的一个子信道，其中，80Mhz的带宽包括4个子信道(每个子信道的带宽为20MHz)。其后，可以将该80Mhz 的带宽对应的4个码片进行复制，并将复制得到的4个码片分别承载于160Mhz信道的另外80Mhz的带宽内的4个子信道。
依次类推，当本申请的通信系统使用的信道的带宽为Q×80Mhz时，N的值可以为Q×4，当M＝3时，首先根据本申请的方案生成4个码片，每个码片对应80Mhz的带宽内的一个子信道，其中，80Mhz的带宽包括4个子信道(每个子信道的带宽为20MHz)。其后，可以将该80Mhz的带宽对应的4个码片进行Q次复制，并将复制得到的Q×4个码片分别承载于160Mhz信道的另外(Q-1)×80Mhz的带宽内的(Q-1)4个子信道。
可选地，M＝N-1。
具体地说，在一种实施方式中，一个码片的大小对应一个20MHz的子信道，即，当M的值为N/2向上取整后减1的结果时，
如果本申请的通信系统使用的信道的带宽为80Mhz，则N的值为4，当M＝N-1(此情况下为3)时，根据本申请的方案生成4个码片，每个码片对应一个子信道。
如果本申请的通信系统使用的信道的带宽为160Mhz，则N的值为8，当M＝N-1(此情况下为7)时，根据本申请的方案生成8个码片，每个码片对应一个子信道。
依次类推，当本申请的通信系统使用的信道的带宽为Q×80Mhz时，N的值为Q×4，当M＝N-1(此情况下为Q×4-1)时，根据本申请的方案生成Q×4个码片，每个码片对应一个子信道。
可选地，所述方法还包括：根据第一映射关系，确定所述M个交织器，其中，所述第一映射关系包括所述N个信道中的每个信道的交织器对应信息，其中，所述第m交织器是第m子信道对应的交织器，所述第m子信道用于传输所述第m码片，所述第m码片是所述第m信息经过编码后生成的码片。
第三方面，提供一种接收数据帧的方法，在信道划分为N个子信道的通信系统中执行，N≥2，所述方法包括：接收端设备通过所述N个子信道中的K个子信道接收数据帧，N≥K≥2；根据所述K个子信道中的每个子信道的交织器对应信息和第一译码器，对所述至少两个子信道中的每个子信道中承载的码片进行译码，以获取第一信息，所述第一信息包括数据帧的前导码字段对应的部分或全部信息，其中，所述K个子信道中的第k子信道承载的码片是所述第一信息经过第k交织器的交织处理和第一编码器的编码处理后生成的，或者，所述K个子信道中的第k子信道承载的码片是所述第一信息经过所述第一编码器的编码处理后生成的，所述第k交织器是所述第k子信道对应的交织器，所述第一译码器与所述第一编码器对应，所述第一编码器包括1/2卷积码编码器或递归系统卷积码编码器，k∈[1，K]。
根据本申请提供的方案，通过在发送端基于多个交织器对待发送的目标信息分别进行交织处理，并进一步对经过交织处理后的信息进行编码，并通过多个子信道分别发送经过编码后的信息，接收端能够根据多个信道中的任意两个信道上的信息以及该两个信道对应的交织器信息恢复出该目标信息，从而，能够提高针对上述多个信道的打孔的灵活性，并提高通信的鲁棒性。
可选地，所述根据所述K个子信道中的每个子信道的交织器对应信息和第一译码器，包括：
将所述N个子信道中除所述K个子信道以外的子信道承载的码片的对数似然比置零。
可选地，所述第一解码器包括维特比译码器。
可选地，所述方法还包括：根据第一映射关系，确定所述K个子信道中的每个子信道的交织器对应信息，其中，所述第一映射关系包括所述N个信道中的每个信道的交织器对应信息。
第四方面，提供一种接收数据帧的方法，其特征在于，在信道划分为N个子信道的通信系统中执行，N≥2，所述方法包括：根据预编码矩阵对第一信息进行预编码处理，生成第一信息矩阵，所述信息矩阵包括N行，所述预编码矩阵包括N行，所述预编码矩阵的N行与所述N个信道一一对应，所述预编码矩阵中的任意T行之间线性无关，T≥2；根据第一编码器对所述第一信息矩阵的每一行进行编码，以生成N个码片，其中，所述N个码片中的第n码片是所述第一矩阵中的第n行经过编码后生成的，n∈[1，N]；生成数据帧，所述数据帧包括N个码片，所述N个码片与所述N个子信道一一对应，每个子信道用于承载所对应的码片；通过所述2N个信道中的至少两个信道发送所述数据帧。
根据本申请提供的方案，通过在发送端基于预编码矩阵对待发送的目标信息分别进行预编码处理，并进一步对经过预编码处理后的信息进行编码，并通过多个子信道分别发送经过编码后的信息，接收端能够根据多个信道中的任意两个信道上的信息以及该预编码矩阵恢复出该目标信息，从而，能够提高针对上述多个信道的打孔的灵活性，并提高通信的鲁棒性。
可选地，所述根据预编码矩阵对第一信息进行预编码处理，包括：将所述第一信息划分为T个信息分段；根据所述T个信息分段生成第二信息矩阵，所述第二信息矩阵包括T行，每行对应一个信息分段；将所述预编码矩阵与所述第二信息矩阵相乘，获得所述第一信息矩阵，其中，所述预编码矩阵包括T列。
可选地，所述第二矩信息阵中的每个元素对应为第一有限域上的一个数字，所述第一有限域的大小为2 q，且所述第二信息矩阵中的第t行中的每个元素对应所述T个信息分段中的第t个信息分段的q个比特，所述第t行与所述第t个信息分段对应，t∈[1，T]，且所述第二矩信息阵中的每个元素是所对应的q个比特转换后获得的，以及所述预编码矩阵中的任意T行之间在所述第一有限域上线性无关。
可选地，当q＝2，T＝2时，所述预编码矩阵包括下述P矩阵的全部或部分行：
Figure PCTCN2021098776-appb-000001
可选地，在根据第一编码器对所述第一信息矩阵的每一行进行编码之前，所述方法还包括：在所述第一信息矩阵的每一行添加奇偶校验比特。
可选地，所述发送端设备中保存有第一映射关系，所述第一映射关系用于指示所述预编码矩阵中的N行与所述N个信道之间的一一对应关系。
第五方面，提供一种发送信息的方法，在信道划分为N个子信道的通信系统中执行，N≥2，所述方法包括：接收端设备通过所述N个子信道中的K个子信道接收数据帧，N ≥K≥2；根据第一译码器和所述K个子信道中的每个子信道对应的预编码矩阵中的行，对所述至少两个子信道中的每个子信道中承载的码片进行译码，以获取第一信息，所述第一信息包括数据帧的前导码字段对应的部分或全部信息，其中，所述K个子信道中的第k个子信道承载的码片是第一信息矩阵中的第k行元素经过第一编码器的编码后生成的，所述第一信息矩阵是所述第一信息经过所述预编码矩阵的预编码处理生成的，所述预编码矩阵中的任意T行之间线性无关，T≥2，所述第一译码器与所述第一编码器对应。
可选地，当q＝2，T＝2时，所述预编码矩阵包括以下P矩阵的部分或全部行：
Figure PCTCN2021098776-appb-000002
可选地，所述方法还包括：根据第一映射关系，确定所述K个子信道中的每个子信道对应的预编码矩阵中的行，所述第一映射关系用于指示所述预编码矩阵中的N行与所述N个信道之间的一一对应关系。
第六方面，提供一种发送数据帧的方法，在信道划分为N个子信道的通信系统中执行，N≥2，所述方法包括：发送端设备对第一信息进行划分，以生成第一码片和第二码片；根据M个交织器组，对所述第一码片和所述第二码片进行处理，以获得M个码片，所述M个码片与所述M个交织器组一一对应，每个码片是基于所对应的交织器组获得的，其中，每个交织器组包括两个交织器，所述M个码片中的第m码片是第m_1序列与第m_2序列相加后获得的，所述第m_1序列是所述第一码片经过所述M个交织器组中的第m交织器组中的一个交织器的交织后获得的，所述第m_2序列是所述第二码片经过所述第m交织器组中的另一个交织器的交织后获得的，所述第m码片与所述第m交织器组对应，m∈[3，M+2]，M≥1；生成数据帧，所述数据帧包括N个码片，所述N个码片与所述N个子信道一一对应，每个子信道用于承载所对应的码片，所述N个码片包括所述第一码片、所述第二码片和所述M个码片中的全部或部分码片；通过所述N个子信道中的至少两个子信道发送所述数据帧。
根据本申请提供的方案，通过在发送端基于交织器组对待发送的目标信息分别进行处理，并通过多个子信道分别发送经过处理后的信息，接收端能够根据多个信道中的任意两个信道上的信息以及该信道对应的交织器组恢复出该目标信息，从而，能够提高针对上述多个信道的打孔的灵活性，并提高通信的鲁棒性。
可选地，M＝2。
具体地说，在一种实施方式中，一个码片的大小对应一个20MHz的子信道，即，当M＝2时，根据本申请提供的方案生成4个码片，该4个码片分别对应于一个80Hz的带宽内的4个子信道(每个子信道的带宽为20MHz)。
此情况下，当本申请的通信系统使用的信道的带宽为80Mhz时，N的值为4，从而，当M＝2时，根据本申请的方案生成4个码片，每个码片对应一个子信道。
当本申请的通信系统使用的信道的带宽为160Mhz时，N的值可以为8，从而，当M＝2 时，首先根据本申请的方案生成4个码片，每个码片对应80Mhz的带宽内的一个子信道，其中，80Mhz的带宽包括4个子信道(每个子信道的带宽为20MHz)。其后，可以将该80Mhz的带宽对应的4个码片进行复制，并将复制得到的4个码片分别承载于160Mhz信道的另外80Mhz的带宽内的4个子信道。
依次类推，当本申请的通信系统使用的信道的带宽为Q×80Mhz时，N的值可以为Q×4，从而，当M＝2时，首先根据本申请的方案生成4个码片，每个码片对应80Mhz的带宽内的一个子信道，其中，80Mhz的带宽包括4个子信道(每个子信道的带宽为20MHz)。其后，可以将该80Mhz的带宽对应的4个码片进行Q次复制，并将复制得到的Q×4个码片分别承载于160Mhz信道的另外(Q-1)×80Mhz的带宽内的(Q-1)4个子信道。
可选地，M＝N-2。
具体地说，在一种实施方式中，一个码片的大小对应一个20MHz的子信道，即，当M＝N-2时，
如果本申请的通信系统使用的信道的带宽为80Mhz，则N的值为4，当M＝N-2(此情况下位2)时，根据本申请的方案生成4个码片，每个码片对应一个子信道。
如果本申请的通信系统使用的信道的带宽为160Mhz，则N的值为8，当M＝N-2(此情况下为6)时，根据本申请的方案生成8个码片，每个码片对应一个子信道。
依次类推，当本申请的通信系统使用的信道的带宽为Q×80Mhz时，N的值为Q×4，当M＝N-2(此情况下为Q×4-2)时根据本申请的方案生成Q×4个码片，每个码片对应一个子信道。
可选地，所述第m_1序列与所述第一码片相同，所述第m_2序列是所述第二码片中的比特循环移位至少一个(例如，m个)比特后形成的序列。
从而，能够容易地实现本申请的交织器组。
可选地，所述方法还包括：根据第一映射关系，确定所述M个交织器组，其中，所述第一映射关系包括所述N个信道中的每个信道的交织器组对应信息，其中，所述第m交织器是第m子信道对应的交织器，所述第m子信道用于传输所述第m码片。
第七方面，提供一种接收数据帧的方法，在信道划分为N个子信道的通信系统中执行，N≥2，所述方法包括：接收端设备通过所述N个子信道中的K个子信道接收数据帧，N≥K≥2；根据第一译码器和所述K个子信道中的每个子信道的交织器组对应信息，对所述至少两个子信道中的每个子信道中承载的码片进行译码，以获取第一信息，所述第一信息包括数据帧的前导码字段对应的部分或全部信息，其中，所述K个子信道中的第k子信道承载的第k码片是所述第一信息进行划分后获得的第一码片或第二码片，或者，所述第k码片是所述第一码片和所述第二码片经过所第k子信道对应的第k交织器组进行处理后获得的，其中，每个交织器组包括两个交织器，第k码片是第k_1序列与第k_2序列相加后获得的，所述第k_1序列是所述第一码片经过第k交织器组中的一个交织器的交织后获得的，所述第k_2序列是所述第二码片经过所述第k交织器组中的另一个交织器的交织后获得的，k∈[1，K]。
可选地，所述第k_1序列与所述第一码片相同，所述第k_2序列是所述第二码片中的比特循环移位至少一个(例如，k个)比特后形成的序列。
可选地，所述方法还包括：根据第一映射关系，确定所述K个子信道中的每个子信道 的交织器组对应信息，其中，所述第一映射关系包括所述N个信道中的每个信道的交织器组对应信息。
第八方面，提供了一种通信装置，包括用于执行第一方面至第七方面中的任一方面及其任一种可能实现方式中的方法的各个模块或单元。
第九方面，提供了一种通信设备，包括处理器，所述处理器与存储器耦合，可用于执行第一方面至第七方面中的任一方面及其可能实现方式中的方法。可选地，该通信设备还包括存储器。可选地，该通信设备还包括通信接口，处理器与通信接口耦合。可选地，该通信设备还包括通信接口，处理器与通信接口耦合。
在一种实现方式中，该通信设备为设备。此情况下，所述通信接口可以是收发器，或，输入/输出接口。在另一种实现方式中，该通信设备为芯片或芯片系统。此情况下，所述通信接口可以是该芯片或芯片系统上的输入/输出接口、接口电路、输出电路、输入电路、管脚或相关电路等。所述处理器也可以体现为处理电路或逻辑电路。
第十方面，提供了一种通信装置，包括：输入电路、输出电路和处理电路。所述处理电路用于通过所述输入电路接收信号，并通过所述输出电路发射信号，使得所述第一方面至第七方面中的人一方面及其各方面的任一种可能实现方式中的方法被实现。
在具体实现过程中，上述通信装置可以为芯片，输入电路可以为输入管脚，输出电路可以为输出管脚，处理电路可以为晶体管、门电路、触发器和各种逻辑电路等。输入电路所接收的输入的信号可以是由例如但不限于接收器接收并输入的，输出电路所输出的信号可以是例如但不限于输出给发射器并由发射器发射的，且输入电路和输出电路可以是不同的电路，也可以是同一电路，这种情况下该电路在不同的时刻分别用作输入电路和输出电路。本申请实施例对处理器及各种电路的具体实现方式不做限定。
第十一方面，提供了一种处理装置，包括处理器和存储器。该处理器用于读取存储器中存储的指令，并可通过接收器接收信号，通过发射器发射信号，以执行所述第一方面至第七方面中的任一方面及其各种可能实现方式中的方法。
可选地，所述处理器为一个或多个，所述存储器为一个或多个。
可选地，所述存储器可以与所述处理器集成在一起，或者所述存储器与处理器分离设置。
在具体实现中，存储器可以为非瞬时性(non-transitory)存储器，例如只读存储器(read only memory，ROM)，其可以与处理器集成在同一块芯片上，也可以分别设置在不同的芯片上，本申请实施例对存储器的类型以及存储器与处理器的设置方式不做限定。
应理解，相关的数据交互过程例如发送指示信息可以为从处理器输出指示信息的过程，接收能力信息可以为处理器接收输入能力信息的过程。具体地，处理输出的数据可以输出给发射器，处理器接收的输入数据可以来自接收器。其中，发射器和接收器可以统称为收发器。
上述第十一方面中的处理器可以是一个芯片，该处理器可以通过硬件来实现也可以通过软件来实现，当通过硬件实现时，该处理器可以是逻辑电路、集成电路等；当通过软件来实现时，该处理器可以是一个通用处理器，通过读取存储器中存储的软件代码来实现，该存储器可以集成在处理器中，可以位于该处理器之外，独立存在。
第十二方面，提供了一种处理装置，包括：通信接口和处理电路，所述通信接口用于 按照所述第一方面、第二方面、第四方面或第六方面及其任一种可能实现方式中的方法发送传输帧，所述处理电路用于产生所述传输帧。
第十三方面，提供了一种处理装置，包括：通信接口和处理电路，所述通信接口用于获取待处理的传输帧，所述处理电路用于按照所述第三方面、第五方面或第七方面及其任一种可能实现方式中的方法处理所述待处理的传输帧。
第十四方面，提供了一种计算机程序产品，所述计算机程序产品包括：计算机程序(也可以称为代码，或指令)，当所述计算机程序被运行时，使得计算机执行所述第一方面至第七方面中的任一方面及其各方面的任一种可能实现方式中的方法。
第十五方面，提供了一种计算机可读介质，所述计算机可读介质存储有计算机程序(也可以称为代码，或指令)当其在计算机上运行时，使得计算机执行上述所述第一方面至第七方面中的任一方面及其各方面的任一种可能实现方式中的方法。
第十六方面，提供了一种通信系统，包括前述的发送端设备和接收端设备。
附图说明
图1是打孔方案的一例的示意图。
图2是内容信道的一例的示意图。
图3是本申请的通信系统的一例的示意图。
图4是本申请的信道分配方式的一例。
图5是本申请的数据帧的一例的示意图。
图6是HE-SIG-B的结构的一例的示意图。
图7是本申请的码片生成方式的一例的示意图。
图8是图7所示码片生成方式对应的译码过程的一例的示意图。
图9是本申请的码片生成方式的另一例的示意图。
图10是图9所示码片生成方式对应的译码过程的一例的示意图。
图11是本申请的码片生成方式的再一例的示意图。
图12是本申请的码片生成方式的再一例的示意图。
图13是图11和图12所示码片生成方式对应的译码过程的一例的示意图。
图14是本申请的码片生成方式的再一例的示意图。
图15是本申请的码片生成方式的再一例的示意图。
图16是本申请的通信装置的一例的示意图。
图17是本申请的通信装置的另一例的示意图。
图18是本申请的通信装置的再一例的示意图。
图19是本申请的AP的一例的示意图。
图20是本申请的STA的一例的示意图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
本申请实施例的技术方案可以应用于各种通信系统，例如：无线局域网(wireless local area network，WLAN)通信系统、长期演进(long term evolution，LTE)系统、LTE频分 双工(frequency division duplex，FDD)系统、LTE时分双工(time division duplex，TDD)、通用移动通信系统(universal mobile telecommunication system，UMTS)、全球互联微波接入(worldwide interoperability for microwave access，WiMAX)通信系统、未来的第五代(5th generation，5G)系统或新无线(new radio，NR)等。
以下作为示例性说明，仅以WLAN系统为例，描述本申请实施例的应用场景以及本申请实施例的方法。
具体而言，本申请实施例可以应用于WLAN系统，并且本申请实施例可以适用于WLAN当前采用的电气与电子工程师协会(institute of electrical and electronics engineers，IEEE)802.11系列协议中的任意一种协议。
WLAN可以包括一个或多个基本服务集(basic service set，BSS)，基本服务集中的网络节点包括接入点(access point，AP)和站点(station，STA)。一个STA只能接入一个AP(即将STA与AP关联)，而一个AP下可以关联多个STA。STA和AP在进行数据传输之前，需要进行波束训练，获得该STA和AP之间的最优接收波束和/或最优发送波束。IEEE 802.11ad在原有的BSS基础上，引入了个人基本服务集(personal basic service set，PBSS)和个人基本服务集控制节点(PBSS control point，PCP)。每个个人基本服务集可以包含一个PCP/AP和多个关联于该PCP/AP的站点。
WLAN中的用户站点(STA)可以称为系统、用户单元、接入终端、移动站、移动台、远方站、远程终端、移动设备、用户终端、终端、无线通信设备、用户代理、用户装置或用户设备(user equipment，UE)。该STA可以是蜂窝电话、无绳电话、会话启动协议(session initiation protocol，SIP)电话、无线本地环路(wireless local loop，WLL)站、个人数字助理(personal digital assistant，PDA)、具有无线局域网(例如Wi-Fi)通信功能的手持设备、可穿戴设备、计算设备或连接到无线调制解调器的其它处理设备。
WLAN中的PCP/AP可用于与STA通过无线局域网进行通信，并将STA的数据传输至网络侧，或将来自网络侧的数据传输至STA。
为便于理解本申请实施例，首先以图3中示出的通信系统为例详细说明适用于本申请实施例的通信系统。如图1所示的场景系统可以是WLAN系统，图3的WLAN系统可以包括一个或者多个AP，和一个或者多个STA，图3以一个AP和三个STA为例。AP和STA之间可以通过各种标准进行无线通信。例如，AP和STA之间可以采用单用户多入多出(single-user multiple-input multiple-output，SU-MIMO)技术或多用户多入多出(multi-users multiple-input multiple-output，MU-MIMO)技术进行无线通信。
其中，AP也称为无线访问接入点或热点等。AP是移动用户进入有线网络的接入点，主要部署于家庭、大楼内部以及园区内部，也可以部署于户外。AP相当于一个连接有线网和无线网的桥梁，其主要作用是将各个无线网络客户端连接到一起，然后将无线网络接入以太网。具体地，AP可以是带有无线保真(wireless fidelity，WiFi)芯片的终端设备或者网络设备。可选地，AP可以为支持802.11等多种WLAN制式的设备。
WLAN从802.11a/g开始，历经802.11n、802.11ac,到现在正在讨论中的802.11ax和802.11be，其允许传输的带宽和支持的最大传输速率如下表1所示
表1
Figure PCTCN2021098776-appb-000003
Figure PCTCN2021098776-appb-000004
图4示出了本申请的信道分配的一例，如图2所示，整个信道被分为主20MHz信道(或简称主信道，Primary 20MHz，P20)，从20MHz信道(Secondary 20MHz,S20)，从40MHz信道(S40)，从80MHz(S80)信道。另外相对应的存在P40和P80。随着带宽增大，数据传输的数据速率也随之增加。因此在下一代标准，会考虑大于160MHz的更大带宽(如240MHz，320MHz)。
为了提高频谱利用效率，可以采用例如，正交频分复用(Orthogonal frequency division multiplexing，OFDM)实现多用户同时传输。
OFDM是一种多载波传输的技术，使用大量相邻的正交子载波(orthogonal subcarrier)，其中每个子载波采用传统的调制技术进行调制，使得该技术具备高速率传输的能力，同时能有效对抗频率选择性衰减(frequency selective fading)，因此许多无线传输协议都采用了正交频分复用。
作为多用户传输技术中使用的数据帧(或者说，传输帧)，可以列举，例如，物理层协议数据单元(PHY Protocol Data Unit，PPDU)或高效多用户(High Efficient Multiple User，HE MU)PPDU等帧结构。
图5示出了本申请的数据帧(以HE MU PPDU为例)的一例。如图5所示，传统短训练序列(legacy short training field，L-STF)包含10个重复的部分，接收端利用重复特性进行PPDU的检测、频率和时间的获取(或者说，纠正)(纠正)。
其中，“传统短训练序列”也可以称为传统短训练序列字段，并且，在本申请中，“字段”也可以称为域或部分，以下，省略对相同或相似情况的说明。
传统长训练序列(legacy long training field，L-LTF)包含2个3.2μs的重复部分和1个1.6μs的保护间隔。接收端利用L-LTF可以进行频率和时间的进一步获取(纠正)，并进行信道估计，例如，对信噪比(SIGNAL NOISE RATIO，SNR)的估计。
传统信令字段(legacy signal field，L-SIG)用于承载速率和长度信息，指示PPDU的时长，对于传统站点，需要延迟到至少为该PPDU时长的时间后再进行传输，防止造成干扰。此外，非HE部分的L-SIG可以同时由HE站点和传统站点解码，并获取相应信息，用来保证后向兼容性。
重复传统信令字段(repeat legacy signal field，RL-SIG)是L-SIG符号的复制，因此具备L-SIG的所有特性。对L-SIG进行复制有以下优点：
1.可靠性增强。对符号进行复制，接收端进行最大比合并(maximal ratio combining，MRC)，可以使得等效SNR提高3dB，用于增强HE PPDU的可靠性，尤其适用于室外场景。MRC是一种接收技术，通过在接收端使用某种算法来改善接收端的信号质量。
2.提供了自动检测功能，用于区别HE PPDU和其他PPDU。接收端通过检测L-SIG和后边的一个符号是否相似，作为识别接收到的PPDU是否是HE PPDU的依据之一。
高效信令字段A(high efficient signal field A，HE-SIG-A)携带的信息可以帮助解析 HE PPDU。HE MU PPDU中的HESIG-A包含了关于高效信令字段B(high efficient signal field A，HESIG-B)的相关指示，例如，HESIG-B的符号数或多用户多输入多输入(multiple usermultiple input multiple output，MUMIMO)的用户数、HESIG-B的编码与调制策略、HESIG-B的压缩(指示是否进行压缩)，具体结构见。而数据部分的相应调制编码参数，则在HE-SIG-B中针对不同的用户分别指示。
HE-SIG-B为OFDMA和MU-MIMO提供了资源分配信息。
图6示出了一个20MHz的子信道上承载的HE-SIG-B的结构的一例。如图6所示，整个HE-SIG-B分为两部分。
1.公共部分字段：包含1～X个资源单元分配子字段、当带宽大于等于80MHz时存在的中间26-tone资源单元指示字段、用于校验的循环冗余校验(cyclic redundancy check，CRC)子字段及用于循环解码的尾部子字段。这里的X和带宽有关，当带宽为20MHz和40MHz时X＝1，为80MHz时X＝2，为160MHz时X＝4。
2.逐个用户字段：按照资源单元分配的顺序，存在1～Y个用户字段。用户字段通常是2个为1组(最后1组除外)，每2个用户字段后跟着1个CRC字段和尾部字段；最后1组用户字段，可能是由1个或者2个用户字段、1个CRC字段和尾部字段组成的。
本申请的方法可以用于传输上述数据帧中的一个或多个字段中的信息，例如，HESIG-B中的信息。
以下，为了便于理解和说明，以HESIG-B对应的信息(或者说，需要承载于HESIG-B的信息)的传输过程为例，对本申请的通信过程进行详细说明。
实施方式1
图7示出了实施方式1的发送端设备(记做，设备#A1)对于信息#A1的编码和发送过程的一例的示意图，作为示例而非限定该信息#A1可以是上述HESIG-B对应的信息。其中，设备#A1确定(或者说，生成)该信息#A1的过程可以与现有技术相同或相似，这里为了避免赘述，省略其详细说明。
其中，设备#A1可以为AP，或者，该设备#A1也可以为STA本申请并未特别限定。
并且，设备#A1与数据帧的接收端设备(例如，后述设备#A2)之间的信道可以化为N个子信道，N≥2。
在S110，设备#A1通过1/2码率卷积码编码器(Convolutional Code Encoder，CC encoder)对信息#A1(即，第一信息的一例)进行编码，生成码片#A1和码片#A2。
例如，设备#A1可以在信息#A1中加入W个比特(即，尾比特)，并输入1/2码率卷积码编码器，输出的两个码片(即，码片#A1和码片#A2)中的一个码片包括基于1/2码率卷积码编码器中的一个卷积系数产生的比特。另一个码片包括基于1/2码率卷积码编码器中的另一个卷积系数产生的比特，在本申请中，码片#A1和码片#A2的长度相同，并且，码片#A1和码片#A2的长度与信息#A1的长度相同。
在本申请中，W的数量与1/2码率卷积码编码器中使用的移位寄存器的数量对应(例如，相同)。
需要说明的是，本申请的1/2码率卷积码编码器对信息的编码过程也可以与现有技术相同或相似。
在本申请中，该码片#A1和码片#A2的长度可以是与20MHz的子信道对应的长度， 即，在本申请中，一个码片的大小满足能够在一个20MHz的子信道上传输。
在S120，设备#A1通过交织器#A，对信息#A1进行交织，生成信息#A2(即，第二信息的一例)。
交织是通信系统中进行数据处理而采用的一种技术，交织器从其本质上来说就是一种实现最大限度的改变信息结构而不改变信息内容的器件。
例如，该交织器#A可以包括规则交织器。
规则交织器也可以称为分组交织器，即，行读列出或列读行出的交织器，例如，在一个简单的3 x 3交织矩阵可以包括32种交织方式的存在，然而这32种读法中虽然有许多在形式上不同，但就其本质来讲所表现的特性却是完全一致的。所以它们又可以归纳为有限的四种形式，我们用L代表左，R代表右，T代表上，B代表下，则这四种交织器依次可以表示成：LR/TB，LR/BT，RL/TB，RL/BT。其中LR表示由左至右写人，TB表示由上至下读出，其它的表示形式也依此类推。
再例如，该交织器#A可以包括不规则交织器。
不规则交织器的形式大部分是由上述4种分组交织器演变而来的，目前主要有对角交织器、螺旋交织器、奇偶交织器等形式。
对角交织器和螺旋交织器都是采用行写而对角读出的方式，两者不同是在于对角交织器是行写然后从第一行的第一个元素开始以对角方式读出，而螺旋交织器则是从最后一行的第一个元素开始以对角的方式读出。
奇偶交织器是配合删余技术在交织器生成时加上限制条件的一种方法。删余技术其实就是在编译码过程中将信息以删余截短码的形式送入信道，收端通过加入模拟零的方式加以恢复。
再例如，该交织器#A可以包括随机交织器。
随机交织器也可以称为伪随机交织器，即，事先经过随机选择而生成的一种性能较好的交织方式，然后将其做成表的形式存储起来而进行读取的。
随机交织器的随机性能主要取决于随机数的产生方式、交织器主要参数S、取值的选取等方面。例如，可以利用基于线性取余贝斯-拉姆洗牌技术以及对系统时钟进行随机抽样产生随机数。
作为示例而非限定，作为随机交织器，可以列举，例如，S-随机交织器、T-随机交织器或T-随机交织器。
S-随机交织器的随机数的产生与其它交织器类似，只不过它有一个附加条件，要求在交织前的信息序列长为S的各信息位在交织后必须相邻大于S+1个单位，其实也就是让交织器拥有最大分散因子参数的特性。
T-随机交织器是一种特殊的随机交织器，它要求码字中的任何一对相邻的信息位在交织后的距离要大于整个码的约束长度。
S-T-随机交织器此交织器其实是对S-随机交织器和T-随机交织器两种产生条件的综合。
在S122，设备#A1通过1/2码率卷积码编码器对信息#A2进行编码，生成码片#A3和码片#A4。并且，该过程与上述S110中设备#A1通过1/2码率卷积码编码器对信息#A1进行编码类似，这里，为了避免赘述，省略其详细说明。
需要说明的是，在本申请中，该S110和S120可以同步执行，或者，该S110和S120也可以异步执行本申请并未特别限定，并且当该S110和S120异步执行时，执行顺序可以任意设置，本申请并未特别限定。
在S130，设备#A1可以生成数据帧#A，该数据帧#A可以包括上述码片#A1～码片#A4中的多个码片。
例如，当信道宽度小于80MHz时，子信道的数量小于4，即，N≤3，此情况下设备#A1可以从上述码片#A1～码片#A4中选择N个码片，并且，设备#A1可以对该N个码片中的每个进行交织和星座映射，进而将该每个码片映射到一个子信道上。
再例如，当信道宽度等于80MHz时，子信道的数量等于4，即，N＝4，此情况下设备#A1可以对该N个码片中的每个进行交织和星座映射，进而将该每个码片映射到一个子信道上。
再例如，当信道宽度大于80MHz时，子信道的数量大于4，即，N＞4，此情况下设备#A1可以对上述码片#A1～码片#A4中的每个进行交织和星座映射，进而将该每个码片映射到一个80MHz带宽中的4个子信道上。并且，可以在其他带宽上重复发送该80MHz带宽上的部分或全部内容(或者说，码片)。
例如，当信道宽度为160Mhz时，子信道的数量为8，即，N＝8，此情况下设备#A1可以对上述码片#A1～码片#A4中的每个进行交织和星座映射，进而将该每个码片映射到一个80MHz带宽(记做带宽a1)中的4个子信道上。并且，可以在另外80MHz带宽上重复发送带宽a1的内容。
同理，信道宽度为240MHz时，3个80M发送同样的内容，其中每个80MHz内在不同的20M上发送4个不同码片。类似地，信道宽度为320MHz时，可以把80MHz的内容重复4次。
例如，在本申请中，设备#A1和设备#A2中还可以包括映射关系#A(即，第一映射关系的一例)，该映射关系#A用于指示多个子信道中的每个子信道的交织器对应信息。
并且，在本申请中，映射关系#A可以为通信系统或通信协议规定，或者，该映射关系#A也可以由设备#A1和设备#A2协商确定，本申请并未特别限定。
在本申请中，一个子信道(记做，子信道#A1)的交织器对应信息可以用于指示该子信道#A1所对应的码片是否经过交织(例如，上述交织器#A)的处理，或者说，子信道#A1的交织器对应信息可以用于指示该子信道#A1所对应的码片是基于上述信息#A1生成的还是基于上述信息#A2生成的。
此情况下，在S130，设备#A1可以根据该映射关系#A，将如上所述生成的码片映射至所对应的子信道上。
在S140，设备#A1可以通过N个信道中的至少两个信道发送上述数据帧#A，例如，设备#A1可以根据需要，对N个信道中的一个或多个信道进行打孔。
在一种实施方式中，当信道的带宽小于或等于80MHz时，在进行打孔处理时，只要确保能够通过该80Mhz的带宽内的至少两个子信道发送码片即可，即，只要确保至少两个子信道未被打孔即可。
在另一种实施方式中，当信道的带宽大于80MHz时，在进行打孔处理时，只要确保至少两个子信道承载有不同码片的子信道未被打孔即可。
图8示出了实施方式1的接收端设备(记做，设备#A2)的译码过程的一例的示意图。
其中，当设备#A1为AP时，该设备#A2可以为STA或AP。
当该设备#A1为STA时，该设备#A2可以为STA或AP。
在S150，设备#A2可以从N个子信道中的至少两个子信道接收码片。
并且，设备#A2可以确定承载有码片的子信道的交织器对应信息。
例如，假设设备#A2在子信道#An接收到码片#An，则设备#A2可以根据上述映射关系#A，确定该子信道#An的交织器对应信息，即，该码片#An是否经过上述交织器#A的交织处理。
例如，如果所接收到的至少两个码片未经过交织器#A的处理，则设备#B1可以通过例如，维特比(Viterbi)译码器对该至少两个码片进行过解码，即可恢复出信息#A1。
再例如，如果所接收到的至少两个码片中的一个码片经过交织器#A的处理另一个码片未经过交织器#A的处理，则设备#B1可以通过例如，拓博(turbo)迭代译码对该至少两个码片进行过解码，即可恢复出信息#A1。
在一种实施方式在中，设备#A2根据N个子信道中的每个子信道的码片接收情况，确定每个子信道的所对应的码片的解调置信度，其中，该解调置信度也可以称为置信度或对数似然比(log likelihood ratio，LLR)等，例如，如果某个子信道未承载码片(或者说，该子信道被打孔)则该子信道对应的码片的解调置信度被置零。
需要说明的是，当信道带宽大于80MHz时，如上所述，每8080MHz的带宽重复发送，因此，可能存在通过多个子信道接收到同一码片的情况，此情况下，该码片的置信度可以基于该多个子信道中的任意一个子信道的置信度确定，或者，该码片的置信度可以基于该多个子信道中的多个子信道的置信度的平均值确定。
如图8所示，在S160，设备#A2可以将所确定码片#A1和码片#A2的置信度输入例如，维特比译码器，得到输出结果#A1，并基于交织器#A对输出结果#A1进行交织处理，得到输出结果#A2，并将所确定码片#A1和码片#A2的置信度和输出结果#A2输入维特比译码器，得到输出结果#A3，并将输出结果#A3和所确定码片#A1和码片#A2的置信度输入维特比译码器，并将输出结果作为译码结果，从而恢复出信息#A1。
实施方式2
图9示出了实施方式2的发送端设备(记做，设备#B1)对于信息#B1的编码和发送过程的一例的示意图，作为示例而非限定该信息#B1可以是上述HESIG-B对应的信息。其中，设备#B1确定(或者说，生成)该信息#B1的过程可以与现有技术相同或相似，这里为了避免赘述，省略其详细说明。
其中，设备#B1可以为AP，或者，该设备#B1也可以为STA本申请并未特别限定。
并且，设备#B1与数据帧的接收端设备(例如，后述设备#B2)之间的信道可以化为N个子信道，N≥2。
在S210，设备#B1通过1/2码率卷积码编码器对信息#B1(即，第一信息的一例)进行编码，生成码片#B1和码片#B2。
该过程可以与上述S110的过程相似，这里，为了避免赘述，省略其详细说明。
在S220，设备#B1通过M个交织器(记做，交织器#B1～交织器#BM)，分别对信息#B1进行交织，生成M个信息，(记做，信息#B2～信息#BM，即，第二信息的一例)。
其中，
Figure PCTCN2021098776-appb-000005
表示向上取整运算。
需要说明的是在本申请中，该M个交织器不同，或者说，该信息#B2～信息#BM+1中的任意两个信息(具体地说，是信息的比特序列)不同。
在S222，设备#B1通过1/2码率卷积码编码器对信息#B2进行编码，生成码片#B3和码片#B4。并且，设备#B1通过1/2码率卷积码编码器对信息#B3进行编码，生成码片#B5和码片#B6，依次类推设备#B1通过1/2码率卷积码编码器对信息#BM进行编码，生成码片#B2M+1和码片#B2(M+1)。
另外，由于
Figure PCTCN2021098776-appb-000006
因此，当N为偶数时，设备#B1通过1/2码率卷积码编码器对信息#BM+1进行编码而生成码片，也可以记做，码片#BN-1和码片#BN。
当N为奇数时，设备#B1通过1/2码率卷积码编码器对信息#BM+1进行编码而生成码片，也可以记做，码片#BN和码片#BN+1。
该过程与上述S210中设备#B1通过1/2码率卷积码编码器对信息#B1进行编码类似，这里，为了避免赘述，省略其详细说明。
需要说明的是，在本申请中，该S210和S220可以同步执行，或者，该S210和S220也可以异步执行本申请并未特别限定，并且当该S210和S220异步执行时，执行顺序可以任意设置，本申请并未特别限定。
在S230，设备#B1可以生成数据帧#B，该数据帧#B可以包括上述码片#B1～码片#B2(M+1)中的N个码片。
例如，设备#B1可以对上述N个码片的每个进行交织和星座映射，进而将该每个码片映射到一个子信道上。
例如，在本申请中，设备#B1和设备#B1中还可以包括映射关系#B(即，第一映射关系的一例)，该映射关系#B用于指示多个子信道中的每个子信道的交织器对应信息。
并且，在本申请中，映射关系#B可以为通信系统或通信协议规定，或者，该映射关系#B也可以由设备#B1和设备#B2协商确定，本申请并未特别限定。
在本申请中，一个子信道(例如，子信道#B1)的交织器对应信息可以用于指示该子信道#B1所对应的码片是否经过交织(例如，上述交织器#B1～交织器#BM中的一个交织器)的处理，或者说，子信道#B1的交织器对应信息可以用于指示该子信道#B1所对应的码片是基于上述信息#B1生成的还是基于上述信息#B2～信息#BM+1生成的。
并且，当子信道#B1的交织器对应信息指示该子信道#B1所承载的码片是经过交织处理后的码片时，该子信道#B1的交织器对应信息还用于指示该子信道#B1所对应的码片是具体经过上述交织器#B1～交织器#BM中的那一个交织器处理的，或者说，该子信道#B1的交织器对应信息还用于指示该子信道#B1对应的交织器。
此情况下，在S330，设备#B1可以根据该映射关系#B，将如上所述生成的码片映射至所对应的子信道上。
在S340，设备#B1可以通过N个信道中的至少两个信道发送上述数据帧#B，例如，设备#B1可以根据需要，对N个信道中的一个或多个信道进行打孔。
在进行打孔处理时，只要确保能够通过至少两个子信道发送码片即可，即，只要确保 至少两个子信道未被打孔即可。
图10示出了实施方式2的接收端设备(记做，设备#B2)的译码过程的一例的示意图。
其中，当设备#B1为AP时，该设备#B2可以为STA或AP。
当该设备#B1为STA时，该设备#B2可以为STA或AP。
在S250，设备#B2可以从N个子信道中的至少两个子信道接收码片。
设备#B2可以确定承载有码片的子信道的交织器对应信息。
例如，假设设备#B2在子信道#Bn接收到码片#Bn，则设备#B2可以根据上述映射关系#B，确定该子信道#Bn的交织器对应信息，即，该码片#Bn是否经过上述交织器#B的交织处理。
例如，如果所接收到的至少两个码片未经过交织器#B的处理，则设备#B1可以通过例如，维特比(Viterbi)译码器对该至少两个码片进行过解码，即可恢复出信息#B1。
再例如，如果所接收到的至少两个码片中的一个码片经过交织器#B的处理另一个码片未经过交织器#B的处理，则设备#B1可以通过例如，拓博迭代译码对该至少两个码片进行过解码，即可恢复出信息#B1。
在一种实施方式在中，设备#B2根据N个子信道中的每个子信道的码片接收情况，确定每个子信道的所对应的码片的解调置信度，其中，该解调置信度也可以称为置信度或对数似然比(log likelihood ratio，LLR)等，例如，如果某个子信道未承载码片(或者说，该子信道被打孔)则该子信道对应的码片的解调置信度被置零。
如图10所示，在S260，设备#B2可以将所确定码片#B1和码片#B2的置信度输入例如，维特比译码器，得到输出结果#B1，并基于交织器#B1对输出结果#B1进行交织处理，得到输出结果#B2，并将所确定码片#B1和码片#B2的置信度和输出结果#B2输入维特比译码器，得到输出结果#B3，并基于交织器#B2对输出结果#B3进行交织处理，得到输出结果#B4，并将所确定码片#B3和码片#B4的置信度和输出结果#B5输入维特比译码器，得到输出结果#B6。依次类推，设备#B2基于每个子信道的码片(或者说，每个子信道)对应的交织器对所输入的译码结果进行交织，并将交织后的结果以及该子信道对应的码片的置信度输入维特比译码器，依次循环迭代后恢复出信息#B1。
实施方式3
图11示出了实施方式3的发送端设备(记做，设备#C1)对于信息#C1的编码和发送过程的一例的示意图，作为示例而非限定该信息#C1可以是上述HESIG-B对应的信息。其中，设备#C1确定(或者说，生成)该信息#C1的过程可以与现有技术相同或相似，这里为了避免赘述，省略其详细说明。
其中，设备#C1可以为AP，或者，该设备#C1也可以为STA本申请并未特别限定。
并且，设备#C1与数据帧的接收端设备(例如，后述设备#C2)之间的信道可以化为N个子信道，N≥2。
在S310，设备#C1可以根据信息#C1生成码片#C1，例如，设备#C1可以在信息#C1后填充W个填充比特，生成码片#C1。其中，W的值与递归系统卷积码编码器中使用的移位寄存器的数量对应(例如，相同)。
在S320，设备#C1通过3个交织器(记做，交织器#C1～交织器#C3)，分别对信息#C1进行交织，生成3个信息，(记做，信息#C2～信息#C4，即，第二信息的一例)。
需要说明的是在本申请中，该3个交织器不同，或者说，该信息#C2～信息#C4中的任意两个信息(具体地说，是信息的比特序列)不同。
在S322，设备#C1通过递归系统卷积码编码器(recursive systematic convolutional encoder，RSC encoder)分别对信息#C2～信息#C4进行编码，生成码片#C2～码片#C4。
例如，设备#C1可以在信息#C2中加入W个比特(即，尾比特)，并输入递归系统卷积码编码器，输出的一个码片(即，码片#C2)。
在本申请中，码片#C1～码片#C4的长度相同。
需要说明的是，本申请的递归系统卷积码编码器对信息的编码过程也可以与现有技术相同或相似。
需要说明的是，在本申请中，该S310和S320可以同步执行，或者，该S310和S320也可以异步执行本申请并未特别限定，并且当该S310和S320异步执行时，执行顺序可以任意设置，本申请并未特别限定。
在S330，设备#C1可以生成数据帧#C，该数据帧#C可以包括上述码片#C1～码片#C4中的多个码片。
例如，当信道宽度小于80MHz时，子信道的数量小于4，即，N≤3，此情况下设备#C1可以从上述码片#C1～码片#C4中选择N个码片，并且，设备#C1可以对该N个码片中的每个进行交织和星座映射，进而将该每个码片映射到一个子信道上。
再例如，当信道宽度等于80MHz时，子信道的数量等于4，即，N＝4，此情况下设备#C1可以对该N个码片中的每个进行交织和星座映射，进而将该每个码片映射到一个子信道上。
再例如，当信道宽度大于80MHz时，子信道的数量大于4，即，N＞4，此情况下设备#C1可以对上述码片#C1～码片#C4中的每个进行交织和星座映射，进而将该每个码片映射到一个80MHz带宽中的4个子信道上。并且，可以在其他带宽上重复发送该80MHz带宽上的部分或全部内容(或者说，码片)。
例如，当信道宽度为160Mhz时，子信道的数量为8，即，N＝8，此情况下设备#C1可以对上述码片#C1～码片#C4中的每个进行交织和星座映射，进而将该每个码片映射到一个80MHz带宽(记做带宽c1)中的4个子信道上。并且，可以在另外80MHz带宽上重复发送带宽c1的内容。
同理，信道宽度为240MHz时，3个80M发送同样的内容，其中每个80MHz内在不同的20M上发送4个不同码片。类似地，信道宽度为320MHz时，可以把80MHz的内容重复4次。
例如，在本申请中，设备#C1和设备#C2中还可以包括映射关系#C(即，第一映射关系的一例)，该映射关系#C用于指示多个子信道中的每个子信道的交织器对应信息。
并且，在本申请中，映射关系#C可以为通信系统或通信协议规定，或者，该映射关系#C也可以由设备#C1和设备#C2协商确定，本申请并未特别限定。
在本申请中，一个子信道(例如，子信道#C1)的交织器对应信息可以用于指示该子信道#C1所对应的码片是否经过交织(例如，上述交织器#C1～交织器#CM中的一个交织器)的处理，或者说，子信道#C1的交织器对应信息可以用于指示该子信道#C1所对应的码片是基于上述信息#C1生成的还是基于上述信息#C2～信息#C4生成的。
并且，当子信道#C1的交织器对应信息指示该子信道#C1所承载的码片是经过交织处理后的码片时，该子信道#C1的交织器对应信息还用于指示该子信道#C1所对应的码片是具体经过上述交织器#C1～交织器#C4中的那一个交织器处理的，或者说，该子信道#C1的交织器对应信息还用于指示该子信道#C1对应的交织器。
此情况下，在S330，设备#C1可以根据该映射关系#C，将如上所述生成的码片映射至所对应的子信道上。
在S340，设备#C1可以通过N个信道中的至少一个信道发送上述数据帧#C，例如，设备#C1可以根据需要，对N个信道中的一个或多个信道进行打孔。
在进行打孔处理时，只要确保至少一个子信道未被打孔即可。
实施方式4
图12示出了实施方式4的发送端设备的编码和发送过程的一例的示意图。
与图11所示过程不同的是，在实施方式4中，设备#C1通过N-1个交织器(记做，交织器#C1～交织器#CN-1)，分别对信息#C1进行交织，生成N-1个信息，(记做，信息#C2～信息#CN，即，第二信息的一例)。
需要说明的是在本申请中，该N个交织器不同，或者说，该信息#C2～信息#CN中的任意两个信息(具体地说，是信息的比特序列)不同。
并且，设备#C1通过递归系统卷积码编码器(Recursive Systematic Convolutional Encoder)分别对信息#C2～信息#CN进行编码，生成码片#C2～码片#CN。
此情况下，该数据帧#C可以包括上述码片#C1～码片#CN-1中的多个码片。
图13示出了实施方式3和实施方式4的接收端设备(记做，设备#C2)的译码过程的一例的示意图。
其中，当设备#C1为AP时，该设备#C2可以为STA或AP。
当该设备#C1为STA时，该设备#C2可以为STA或AP。
在S350，设备#C2可以从N个子信道中的至少一个子信道接收码片。
在S360，设备#C2可以确定承载有码片的子信道的交织器对应信息。
例如，假设设备#C2在子信道#Cn接收到码片#Cn，则设备#C2可以根据上述映射关系#C，确定该子信道#Cn的交织器对应信息，即，该码片#Cn是否经过上述交织器#C的交织处理。
例如，如果所接收到的至少一个码片包括未经过交织处理的码片，则设备#C2可以通过例如，维特比译码器对该经过交织器处理的码片进行过解码，即可恢复出信息#C1。
再例如，如果所接收到的至少一个码片包括经过交织器处理的码片，则设备#C2可以根据上述映射关系#C确定该码片对应的交织器，并基于该交织器和维特比译码器进行解码，即可恢复出信息#C1。
再例如，如果接收到至少两个码片，则设备#C2还可以通过例如，拓博迭代译码对该至少两个码片进行过解码，即可恢复出信息#C1。
在一种实施方式在中，设备#C2根据N个子信道中的每个子信道的码片接收情况，确定每个子信道的所对应的码片的解调置信度，其中，该解调置信度也可以称为置信度或对数似然比(log likelihood ratio，LLR)等，例如，如果某个子信道未承载码片(或者说，该子信道被打孔)则该子信道对应的码片的解调置信度被置零。
如图13所示，在S370，设备#C2可以将所确定码片#C1的置信度输入交织器#C1，并得到输出结果#C1，并将该输出结果#C1和码片#C2的置信度输入例如，维特比译码器，得到输出结果#C2，并基于交织器#C1对应的解交织器对输出结果#C2进行解交织，得到输出结果#C3，并基于交织器C#2对输出结果#C3进行交织，得到输出结果C#4，并将输出结果#C4和码片#3的置信度输入维特比译码器，得到输出结果C#5，并通过交织器#C2对应的解交织器对该输出结果进行解交织，得到输出结果#C6。依次类推，设备#C2基于每个子信道的码片(或者说，每个子信道)对应的交织器对所输入的译码结果进行交织，并将交织后的结果以及该子信道对应的码片的置信度输入维特比译码器，对基于该子信道对应的解交织器，对输出结果进行解交织，依次循环迭代后恢复出信息#C1。
实施方式5
图14示出了实施方式5的发送端设备(记做，设备#D1)对于信息#D1的编码和发送过程的一例的示意图，作为示例而非限定该信息#D1可以是上述HESIG-B对应的信息。其中，设备#D1确定(或者说，生成)该信息#D1的过程可以与现有技术相同或相似，这里为了避免赘述，省略其详细说明。
其中，设备#D1可以为AP，或者，该设备#D1也可以为STA本申请并未特别限定。
并且，设备#D1与数据帧的接收端设备(例如，后述设备#D2)之间的信道可以化为N个子信道，N≥2。
在S410，设备#D1将信息#D1(具体地说是信息#D1的比特流或者说比特序列)划分为T个分段，T≥2。
并且，将每个分段中的每q个比特转化为有限域GF(2^q)上的一个数字，如果比特流长度不是q整数倍，则可以补0，或者补1。
其后，将把转化后的有限域上的数字排成一个T×L的矩阵，以下，记做矩阵#D，其中，L的值与信息#D1的长度、T的大小以及q的大小有关。
在S420，设备#D1将上述矩阵#D与预编码矩阵(记做，矩阵#P)相乘，得到预编码后的矩阵#PD。
其中，该矩阵#P为N×T的矩阵，并且该矩阵#P的任意T行之间在有限域GF(2^q)上都是线性无关的。
根据有限域的理论我们知道预编码矩阵P的行数有如下限制：
Figure PCTCN2021098776-appb-000007
作为示例而非限定，以q＝2，T＝2为例，此时预编码矩阵的行数最大是5，此情况下，矩阵P包括以下矩阵中的部分或全部行：
Figure PCTCN2021098776-appb-000008
在S430，设备#D1将矩阵#PD的每一行转换为二进制比特流，并通过卷积码编码器 (例如，1/2码率卷积码编码器或递归系统卷积码编码器等)对比特流进行编码，形成编码后的码片。
作为示例而非限定，在编码之前，在设备#D1还可以在每个二进制比特流中添加奇偶校验比特。
并且，设备#C1可以生成数据帧#C，该数据帧#C可以包括上述编码后的码片，具体地说，设备#C1对每个码片进行交织和星座映射等以将每个码片映射到一个子信道(例如，20MHz的子信道)上。
在S440，设备#D1可以通过N个子信道中的至少T个子信道发送上述数据帧#C，例如，设备#D1可以根据需要，对N个信道中的一个或多个信道进行打孔。
在本申请中，对于任意一个预编码矩阵P满足任意T行在有限域GF(2^q)上都是线性无关的，如果矩阵R是满秩的话，则矩阵P与矩阵R相乘后得到的矩阵也是一个满足任意T行在有限域GF(2^q)上都是线性无关的预编码矩阵。
即，在本申请中，在选取矩阵P时，通过使所选取的矩阵的上半部分是单位矩阵，这样与编码后的矩阵PD的前T行直接对应着原始的信源序列。从而，即使接收端只接收到前T行中的某些行，其依然可以正确解码出部分信息。
因此，在进行打孔处理时，只要确保至少T个子信道未被打孔即可。
相对应地，在实施方式5中，接收端设备(记做，设备#D2)在译码过程中，设备#D2可以从N个子信道中的K个子信道接收码片(K≥T)。
其后，设备#D2可以确定K个子信道中的每个子信道对应的预编码矩阵P中的行。
或者，设备#D2可以从K个子信道中任意选择T个子信道，并确定该T个子信道中的每个子信道对应的预编码矩阵P中的行。
设码片#Dt是基于矩阵PD的第t行生成的，则承载该码片Dt的子信道对应的预编码矩阵的行可以理解为预编码矩阵P中的第t行。
例如，在本申请中，设备#D2中可以包括映射关系#D(即，第一映射关系的一例)，该映射关系#D用于指示多个子信道中的每个子信道对应的预编码矩阵，即，矩阵P中的行。
并且，在本申请中，映射关系#D可以为通信系统或通信协议规定，或者，该映射关系#D也可以由设备#D1和设备#D2协商确定，本申请并未特别限定。
在一种实施方式中，设备#D2可以通过例如维特比译码器对该K个子信道上的码片进行译码，得到译码结果矩阵E，该译码结果矩阵E包括K行，该K行与K个子信道一一对应，每行包括所对应的子信道的码片的译码结果。
并且，设备#D2可以将K个子信道中的每个子信道对应的矩阵P中的行作为译码矩阵U中的行，从而生成包括K行的译码矩阵U。
并且，设备#D2可以确定译码矩阵U的逆矩阵H。
其中，设备#D2可以将矩阵E与矩阵H相乘，并将结果作为译码结果，从而恢复出信息#D1。
在另一种实施方式中，设备#D2可以通过例如维特比译码器对该K个子信道中的任意T个子信道上的码片进行译码，得到译码结果矩阵E’，该译码结果矩阵E’包括T行，该T行与上述T个子信道一一对应，每行包括所对应的子信道的码片的译码结果。
并且，设备#D2可以将T个子信道中的每个子信道对应的矩阵P中的行作为译码矩阵U’中的行，从而生成包括T行的译码矩阵U’。
并且，设备#D2可以确定译码矩阵U’的逆矩阵H’。
其中，设备#D2可以将矩阵E’与矩阵H’相乘，并将结果作为译码结果，从而恢复出信息#D1。
需要说明的是，当设备#D1为AP时，该设备#D2可以为STA或AP。
当该设备#D1为STA时，该设备#D2可以为STA或AP。
实施方式6
图15示出了实施方式6的发送端设备(记做，设备#E1)对于信息#E1的编码和发送过程的一例的示意图，作为示例而非限定该信息#E1可以是上述HESIG-B对应的信息。其中，设备#E1确定(或者说，生成)该信息#E1的过程可以与现有技术相同或相似，这里为了避免赘述，省略其详细说明。
其中，设备#E1可以为AP，或者，该设备#E1也可以为STA本申请并未特别限定。
并且，设备#E1与数据帧的接收端设备(例如，后述设备#E2)之间的信道可以化为N个子信道，N≥2。
在S510，设备#E1可以将信息#E1(具体地说是信息#E1的比特流)分成两段等长的序列，记做，序列#E1和序列#E2。
设该序列#E1和序列#E2的长度为L。
其中，当信息#E1的一半的长度小于L时，可以在信息#E1分段后的序列中添加填充比特(例如，0或1)，从而生成该序列#E1和序列#E2。
在S520，设备#E1通过2个交织器组(记做，交织器组#E1～交织器组#E2)，分别对序列#E1和序列#E2进行交织，生成2个序列，(记做，序列#E3～序列#E4，即，第二信息的一例)。
具体地说，在本申请中，每个交织器组包括两个交织器。
并且，所述2个信息与所述2个交织器组一一对应。
设序列#E3同一交织器组#E1对应，则该序列#E3的生成过程如下：
通过交织器组#E1中的一个交织器对序列#E1进行交织处理，得到序列#E1’；
通过交织器组#E1中的另一个交织器对序列#E2进行交织处理，得到序列#E2’；
将序列#E1’与序列#E2’进行相加(具体地说，是二进制相加)，得到序列#E3。
需要说明的是在本申请中，该2个交织器组不同，或者说，该序列#E3和序列#E4不同。
作为示例而非限定，同一交织器组的两个交织器可以满足以下条件：
以多个交织器组中的交织器组#Em为例中的两个交织器为例进行说明，m可以表示交织器组#Em在多个交织器组中的序号，或者，m可以与交织器组#Em对应的子信道的索引相关。
即，经过交织器组#Em中的一个交织器处理后的序列与该序列#E1相同，即交织器组#Em中的一个交织器不对序列进行任何变更。
经过交织器组#Em中的另一个交织器处理后的序列相对于该序列#E2循环移位了m个比特位。
即，序列#E2中的第i个比特经过交织器的交织处理后的位置为
Figure PCTCN2021098776-appb-000009
在S522，设备#E1通过编码器，例如，1/2码率卷积码编码器或递归系统卷积码编码器，分别对序列#E1～序列#E4进行编码，生成码片#E1～码片#E4。
在S530，设备#E1可以生成数据帧#E，该数据帧#E可以包括上述码片#E1～码片#E4中的多个码片。
例如，当信道宽度小于80MHz时，子信道的数量小于4，即，N≤3，此情况下设备#E1可以从上述码片#E1～码片#E4中选择N个码片，并且，设备#E1可以对该N个码片中的每个进行交织和星座映射，进而将该每个码片映射到一个子信道上。
再例如，当信道宽度等于80MHz时，子信道的数量等于4，即，N＝4，此情况下设备#E1可以对该N个码片中的每个进行交织和星座映射，进而将该每个码片映射到一个子信道上。
再例如，当信道宽度大于80MHz时，子信道的数量大于4，即，N＞4，此情况下设备#E1可以对上述码片#E1～码片#E4中的每个进行交织和星座映射，进而将该每个码片映射到一个80MHz带宽中的4个子信道上。并且，可以在其他带宽上重复发送该80MHz带宽上的部分或全部内容(或者说，码片)。
例如，当信道宽度为160Mhz时，子信道的数量为8，即，N＝8，此情况下设备#E1可以对上述码片#E1～码片#E4中的每个进行交织和星座映射，进而将该每个码片映射到一个80MHz带宽(记做带宽e1)中的4个子信道上。并且，可以在另外80MHz带宽上重复发送带宽e1的内容。
同理，信道宽度为240MHz时，3个80M发送同样的内容，其中每个80MHz内在不同的20M上发送4个不同码片。类似地，信道宽度为320MHz时，可以把80MHz的内容重复4次。
例如，在本申请中，设备#E1和设备#E2中还可以包括映射关系#E(即，第一映射关系的一例)，该映射关系#E用于指示多个子信道中的每个子信道的交织器组对应信息。
并且，在本申请中，映射关系#E可以为通信系统或通信协议规定，或者，该映射关系#E也可以由设备#E1和设备#E2协商确定，本申请并未特别限定。
在本申请中，一个子信道(例如，子信道#E1)的交织器组对应信息可以用于指示该子信道#E1所对应的码片是否经过交织(例如，上述交织器组#E1～交织器组#E3中的一个交织器)的处理，或者说，子信道#E1的交织器组对应信息可以用于指示该子信道#E1所对应的码片是基于上述信息#E1生成的还是基于上述信息#E2～信息#E4生成的。
并且，当子信道#E1的交织器组对应信息指示该子信道#E1所承载的码片是经过交织处理后的码片时，该子信道#E1的交织器组对应信息还用于指示该子信道#E1所对应的码片是具体经过上述交织器组#E1～交织器组#E4中的那一个交织器组处理的，或者说，该子信道#E1的交织器组对应信息还用于指示该子信道#E1对应的交织器组。
此情况下，在S530，设备#E1可以根据该映射关系#E，将如上所述生成的码片映射至所对应的子信道上。
在S540，设备#E1可以通过N个信道中的至少两个信道发送上述数据帧#E，例如，设备#E1可以根据需要，对N个信道中的一个或多个信道进行打孔。
在进行打孔处理时，只要确保至少两个子信道未被打孔即可。
实施方式7
与图15所示过程不同的是，在实施方式7中，设备#E1通过N-2个交织器组(记做，交织器组#E1～交织器组#EN-2)，分别对序列#E1和序列#E2进行交织，生成N-2个序列，(记做，序列#E3～序列#EN，即，第二信息的一例)。
需要说明的是在本申请中，该N-2个交织器不同，或者说，该序列#E3～信息#EN中的任意两个信息(具体地说，是信息的比特序列)不同。
并且，设备#E1通过编码器分别对序列#E1～信息#EN进行编码，生成码片#E1～码片#EN。
此情况下，该数据帧#E可以包括上述码片#E1～码片#EN中的多个码片。
相对应地，在实施方式6和实施方式7中，接收端设备(记做，设备#E2)在译码过程中，设备#E2可以从N个子信道中的K个子信道接收码片，K≥2。
其中，当设备#E1为AP时，该设备#E2可以为STA或AP。
当该设备#E1为STA时，该设备#E2可以为STA或AP。
并且，设备#E2可以通过解码器对该K个子信道上承载的码片进行解码。
并且，设备#E2可以确定该K个子信道的交织器组对应信息。
例如，假设设备#E2在子信道#Ek接收到码片#Ek，则设备#E2可以根据上述映射关系#E，确定该子信道#Ek的交织器对应信息，即，该码片#Ek是否经过上述交织器组的交织处理。
例如，如果所接收到两个码片包括未经过交织器组的交织处理的码片，则设备#E2可以直接通过该两个解码后的码片，恢复出信息#E1。
再例如，如果所接收到一个未经过交织器组的交织处理的码片(例如：码片#E1)和至少一个经过交织器组的交织处理的码片(例如，码片#E3)，则设备#E2可以根据上述映射关系#E确定码片#E3(或者说承载码片#E3的子信道)的交织器组，并基于解码后的码片#E3、该交织器组和解码后的码片#E1恢复出码片#E2，进而根据码片#E2和码片#E1恢复出信息#E1。
再例如，如果所接收到两个经过交织器组的交织处理的码片(例如：码片#E3和码片#E4)，则设备#E2可以根据上述映射关系#E确定码片#E3(或者说承载码片#E3的子信道)的交织器组以及码片#E4(或者说承载码片#E4的子信道)的交织器组，并基于解码后的码片#E3、码片#E4该交织器组恢复出码片#E1和码片#E2，进而根据码片#E2和码片#E1恢复出信息#E1。
本申请实施例提供了一种通信装置。在一种可能的实现方式中，该装置用于实现上述方法实施例中的接收端对应的步骤或流程。在另一种可能的实现方式中，该装置用于实现上述方法实施例中的发送端对应的步骤或流程。
图16是本申请实施例提供的通信装置的示意性框图。如图16所示，该装置600可以包括通信单元610和处理单元620。通信单元610可以与外部进行通信，处理单元620用于进行数据处理。通信单元610还可以称为通信接口或收发单元。
在一种可能的设计中，该装置600可实现对应于上文方法实施例中的发送端设备(例如，设备#A1、设备#B1、设备#C1、设备#D1、设备#E1)执行的步骤或者流程，其中， 处理单元620用于执行上文方法实施例中发送端设备的处理相关的操作，通信单元610用于执行上文方法实施例中发送端设备的发送相关的操作。
在又一种可能的设计中，该装置600可实现对应于上文方法实施例中的接收端设备(例如，设备#A2、设备#B2、设备#C2、设备#D2、设备#E2)执行的步骤或者流程，其中，通信单元610用于执行上文方法实施例中接收端设备的接收相关的操作，处理单元620用于执行上文方法实施例中接收端设备的处理相关的操作。
应理解，这里的装置600以功能单元的形式体现。这里的术语“单元”可以指应用特有集成电路(application specific integrated circuit，ASIC)、电子电路、用于执行一个或多个软件或固件程序的处理器(例如共享处理器、专有处理器或组处理器等)和存储器、合并逻辑电路和/或其它支持所描述的功能的合适组件。在一个可选例子中，本领域技术人员可以理解，装置600可以具体为上述实施例中的发送端设备，可以用于执行上述方法实施例中与发送端设备对应的各个流程和/或步骤，或者，装置600可以具体为上述实施例中的接收端设备，可以用于执行上述方法实施例中与接收端设备对应的各个流程和/或步骤，为避免重复，在此不再赘述。
上述各个方案的装置600具有实现上述方法中发送端设备所执行的相应步骤的功能，或者，上述各个方案的装置600具有实现上述方法中接收端设备所执行的相应步骤的功能。所述功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的模块；例如通信单元可以由收发机替代(例如，通信单元中的发送单元可以由发送机替代，通信单元中的接收单元可以由接收机替代)，其它单元，如处理单元等可以由处理器替代，分别执行各个方法实施例中的收发操作以及相关的处理操作。
此外，上述通信单元还可以是收发电路(例如可以包括接收电路和发送电路)，处理单元可以是处理电路。在本申请的实施例，图16中的装置可以是前述实施例中的AP或STA，也可以是芯片或者芯片系统，例如：片上系统(system on chip，SoC)。其中，通信单元可以是输入输出电路、通信接口；处理单元为该芯片上集成的处理器或者微处理器或者集成电路。在此不做限定。
图17示出了本申请实施例提供的通信装置700。该装置700包括处理器710和收发器720。其中，处理器710和收发器720通过内部连接通路互相通信，该处理器710用于执行指令，以控制该收发器720发送信号和/或接收信号。
可选地，该装置700还可以包括存储器730，该存储器730与处理器710、收发器720通过内部连接通路互相通信。该存储器730用于存储指令，该处理器710可以执行该存储器730中存储的指令。在一种可能的实现方式中，装置700用于实现上述方法实施例中的发送端设备(例如，设备#A1、设备#B1、设备#C1、设备#D1、设备#E1)对应的各个流程和步骤。在另一种可能的实现方式中，装置700用于实现上述方法实施例中的接收端设备(例如，设备#A2、设备#B2、设备#C2、设备#D2、设备#E2)对应的各个流程和步骤。
应理解，装置700可以具体为上述实施例中的AP或STA，也可以是芯片或者芯片系统。对应的，该收发器720可以是该芯片的收发电路，在此不做限定。具体地，该装置700可以用于执行上述方法实施例中与发送端或接收端对应的各个步骤和/或流程。可选地，该存储器730可以包括只读存储器和随机存取存储器，并向处理器提供指令和数据。存储 器的一部分还可以包括非易失性随机存取存储器。例如，存储器还可以存储设备类型的信息。该处理器710可以用于执行存储器中存储的指令，并且当该处理器710执行存储器中存储的指令时，该处理器710用于执行上述与AP或STA对应的方法实施例的各个步骤和/或流程。
在实现过程中，上述方法的各步骤可以通过处理器中的硬件的集成逻辑电路或者软件形式的指令完成。结合本申请实施例所公开的方法的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器，处理器读取存储器中的信息，结合其硬件完成上述方法的步骤。为避免重复，这里不再详细描述。
应注意，本申请实施例中的处理器可以是一种集成电路芯片，具有信号的处理能力。在实现过程中，上述方法实施例的各步骤可以通过处理器中的硬件的集成逻辑电路或者软件形式的指令完成。上述的处理器可以是通用处理器、数字信号处理器(DSP)、专用集成电路(ASIC)、现场可编程门阵列(FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。本申请实施例中的处理器可以实现或者执行本申请实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。结合本申请实施例所公开的方法的步骤可以直接体现为硬件译码处理器执行完成，或者用译码处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器，处理器读取存储器中的信息，结合其硬件完成上述方法的步骤。
可以理解，本申请实施例中的存储器可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(read-only memory，ROM)、可编程只读存储器(programmable ROM，PROM)、可擦除可编程只读存储器(erasable PROM，EPROM)、电可擦除可编程只读存储器(electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(random access memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(static RAM，SRAM)、动态随机存取存储器(dynamic RAM，DRAM)、同步动态随机存取存储器(synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(double data rate SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(synchlink DRAM，SLDRAM)和直接内存总线随机存取存储器(direct rambus RAM，DR RAM)。应注意，本文描述的系统和方法的存储器旨在包括但不限于这些和任意其它适合类型的存储器。
图18示出了本申请实施例提供的通信装置800。该装置800包括处理电路810和收发电路820。其中，处理电路810和收发电路820通过内部连接通路互相通信，该处理电路810用于执行指令，以控制该收发电路820发送信号和/或接收信号。
可选地，该装置800还可以包括存储介质830，该存储介质830与处理电路810、收发电路820通过内部连接通路互相通信。该存储介质830用于存储指令，该处理电路810可以执行该存储介质830中存储的指令。在一种可能的实现方式中，装置800用于实现上 述方法实施例中的发送端设备(例如，设备#A1、设备#B1、设备#C1、设备#D1、设备#E1)对应的各个流程和步骤。在另一种可能的实现方式中，装置800用于实现上述方法实施例中的接收端设备(例如，设备#A2、设备#B2、设备#C2、设备#D2、设备#E2)对应的各个流程和步骤。
图19示出了AP产品的内部结构图，其中，AP可以是多天线的，也可以是单天线的。图19中，AP包括物理层(physical layer，PHY)处理电路和媒体接入控制(media access control，MAC)层处理电路，物理层处理电路可以用于处理物理层信号，MAC层处理电路可以用于处理MAC层信号。
图20示出了STA产品的内部结构图，其中，STA产品通常为支持802.11系列标准的终端产品，如手机、笔记本电脑等，图20示出了单个天线的STA结构图，实际场景中，STA也可以是多天线的，并且可以是两个以上天线的设备。图20中，STA可以包括PHY层处理电路和MAC层处理电路，物理层处理电路可以用于处理物理层信号，MAC层处理电路可以用于处理MAC层信号。
根据本申请实施例提供的方法，本申请还提供一种计算机程序产品，该计算机程序产品包括：计算机程序代码，当该计算机程序代码在计算机上运行时，使得该计算机执行图7至图15中所示任一实施方式中的方法。
根据本申请实施例提供的方法，本申请还提供一种计算机可读介质，该计算机可读介质存储有程序代码，当该程序代码在计算机上运行时，使得该计算机执行图7至图15中所示任一实施方式中的方法。
根据本申请实施例提供的方法，本申请还提供一种系统，其包括前述的一个或多个站点以及一个或多个接入点。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(read-only memory，ROM)、随机存取存储器(random access memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (36)

  1. 一种发送数据帧的方法，其特征在于，在信道划分为N个子信道的通信系统中执行，N≥2，所述方法包括：
    发送端设备基于第一编码器对第一信息进行编码，以生成第一码片和第二码片，所述第一编码器包括1/2卷积码编码器，所述第一信息包括数据帧的前导码字段对应的部分或全部信息；
    基于M个交织器，对所述第一信息进行交织处理，生成M个信息，其中，所述M个信息与所述M个交织器一一对应，其中，所述M个信息中的第m信息是基于所述M个交织器中的第m交织器的交织处理生成的，所述第m信息与所述第m交织器对应，m∈[2，M+1]，M≥1；
    基于所述第一编码器对所述M个信息进行编码处理，以生成2M个码片，其中，所述2M个码片中的第2m+1码片和第2(m+1)码片是所述第m信息经过编码处理后生成的；
    生成数据帧，所述数据帧包括N个码片，所述N个码片与所述N个子信道一一对应，每个子信道用于承载所对应的码片，所述N个码片包括所述第一码片、所述第二码片和所述2M个码片中的全部或部分码片；
    通过所述N个子信道中的至少两个子信道发送所述数据帧。
  2. 根据权利要求1所述的方法，其特征在于，M＝1。
  3. 根据权利要求1所述的方法，其特征在于，M的值为N/2向上取整后减1的结果。
  4. 根据权利要求1至3中任一项所述的方法，其特征在于，所述方法还包括：
    根据第一映射关系，确定所述M个交织器，其中，所述第一映射关系包括所述N个子信道中的每个子信道的交织器对应信息，其中，所述第m交织器是第2m+1子信道和第2(m+1)子信道对应的交织器，所述第2m+1子信道用于传输所述第2m+1码片，所述第2(m+1)子信道用于传输所述第2(m+1)码片。
  5. 一种发送数据帧的方法，其特征在于，在信道划分为N个子信道的通信系统中执行，N≥2，所述方法包括：
    发送端设备根据第一信息，生成第一码片，所述第一信息包括数据帧的前导码字段对应的部分或全部信息；
    基于M个交织器，对所述第一信息进行交织处理，生成M个信息，其中，所述M个信息与所述M个交织器一一对应，其中，所述M个信息中的第m信息是基于所述M个交织器中的第m交织器的交织处理生成的，所述第m信息与所述第m交织器对应，m∈[2，M+1]，M≥1；
    基于第一编码器对所述M个信息进行编码，以生成M个码片，所述第一编码器包括递归系统卷积码编码器；
    生成数据帧，所述数据帧包括N个码片，所述N个码片与所述N个子信道一一对应，每个子信道用于承载所对应的码片，所述N个码片包括所述第一码片和所述M个码片中的全部或部分码片；
    通过所述N个子信道中的至少两个子信道发送所述数据帧。
  6. 根据权利要求5所述的方法，其特征在于，M＝3。
  7. 根据权利要求5所述的方法，其特征在于，M＝N-1。
  8. 根据权利要求5至7中任一项所述的方法，其特征在于，所述方法还包括：
    根据第一映射关系，确定所述M个交织器，其中，所述第一映射关系包括所述N个信道中的每个信道的交织器对应信息，其中，所述第m交织器是第m子信道对应的交织器，所述第m子信道用于传输所述第m码片，所述第m码片是所述第m信息经过编码后生成的码片。
  9. 一种接收数据帧的方法，其特征在于，在信道划分为N个子信道的通信系统中执行，N≥2，所述方法包括：
    接收端设备通过所述N个子信道中的K个子信道接收数据帧，N≥K≥2；
    根据所述K个子信道中的每个子信道的交织器对应信息和第一译码器，对所述至少两个子信道中的每个子信道中承载的码片进行译码，以获取第一信息，所述第一信息包括数据帧的前导码字段对应的部分或全部信息，其中，所述K个子信道中的第k子信道承载的码片是所述第一信息经过第k交织器的交织处理和第一编码器的编码处理后生成的，或者，所述K个子信道中的第k子信道承载的码片是所述第一信息经过所述第一编码器的编码处理后生成的，所述第k交织器是所述第k子信道对应的交织器，所述第一译码器与所述第一编码器对应，所述第一编码器包括1/2卷积码编码器或递归系统卷积码编码器，k∈[1，K]。
  10. 根据权利要求9所述的方法，其特征在于，所述根据所述K个子信道中的每个子信道的交织器对应信息和第一译码器，包括：
    将所述N个子信道中除所述K个子信道以外的子信道承载的码片的对数似然比置零。
  11. 根据权利要求9或10所述的方法，其特征在于，所述第一解码器包括维特比译码器。
  12. 根据权利要求9至11中任一项所述的方法，其特征在于，所述方法还包括：
    根据第一映射关系，确定所述K个子信道中的每个子信道的交织器对应信息，其中，所述第一映射关系包括所述N个信道中的每个信道的交织器对应信息。
  13. 一种接收数据帧的方法，其特征在于，在信道划分为N个子信道的通信系统中执行，N≥2，所述方法包括：
    根据预编码矩阵对第一信息进行预编码处理，生成第一信息矩阵，所述信息矩阵包括N行，所述预编码矩阵包括N行，所述预编码矩阵的N行与所述N个信道一一对应，所述预编码矩阵中的任意T行之间线性无关，T≥2；
    根据第一编码器对所述第一信息矩阵的每一行进行编码，以生成N个码片，其中，所述N个码片中的第n码片是所述第一矩阵中的第n行经过编码后生成的，n∈[1,N]；
    生成数据帧，所述数据帧包括N个码片，所述N个码片与所述N个子信道一一对应，每个子信道用于承载所对应的码片；
    通过所述2N个信道中的至少两个信道发送所述数据帧。
  14. 根据权利要求13所述的方法，其特征在于，所述根据预编码矩阵对第一信息进行预编码处理，包括：
    将所述第一信息划分为T个信息分段；
    根据所述T个信息分段生成第二信息矩阵，所述第二信息矩阵包括T行，每行对应一个信息分段；
    将所述预编码矩阵与所述第二信息矩阵相乘，获得所述第一信息矩阵，其中，所述预编码矩阵包括T列。
  15. 根据权利要求14所述的方法，其特征在于，所述第二矩信息阵中的每个元素对应为第一有限域上的一个数字，所述第一有限域的大小为2 q，且所述第二信息矩阵中的第t行中的每个元素对应所述T个信息分段中的第t个信息分段的q个比特，所述第t行与所述第t个信息分段对应，t∈[1，T]，且所述第二矩信息阵中的每个元素是所对应的q个比特转换后获得的，以及
    所述预编码矩阵中的任意T行之间在所述第一有限域上线性无关。
  16. 根据权利要求15所述的方法，其特征在于，当q＝2，T＝2时，所述预编码矩阵包括下述P矩阵的全部或部分行：
    Figure PCTCN2021098776-appb-100001
  17. 根据权利要求13至16中任一项所述的方法，其特征在于，在根据第一编码器对所述第一信息矩阵的每一行进行编码之前，所述方法还包括：
    在所述第一信息矩阵的每一行添加奇偶校验比特。
  18. 根据权利要求13至17中任一项所述的方法，其特征在于，所述发送端设备中保存有第一映射关系，所述第一映射关系用于指示所述预编码矩阵中的N行与所述N个信道之间的一一对应关系。
  19. 一种发送信息的方法，其特征在于，在信道划分为N个子信道的通信系统中执行，N≥2，所述方法包括：
    接收端设备通过所述N个子信道中的K个子信道接收数据帧，N≥K≥2；
    根据第一译码器和所述K个子信道中的每个子信道对应的预编码矩阵中的行，对所述至少两个子信道中的每个子信道中承载的码片进行译码，以获取第一信息，所述第一信息包括数据帧的前导码字段对应的部分或全部信息，其中，所述K个子信道中的第k个子信道承载的码片是第一信息矩阵中的第k行元素经过第一编码器的编码后生成的，所述第一信息矩阵是所述第一信息经过所述预编码矩阵的预编码处理生成的，所述预编码矩阵中的任意T行之间线性无关，T≥2，所述第一译码器与所述第一编码器对应。
  20. 根据权利要求19所述的方法，其特征在于，当q＝2，T＝2时，所述预编码矩阵包括：
    Figure PCTCN2021098776-appb-100002
  21. 根据权利要求19或20所述的方法，其特征在于，所述方法还包括
    根据第一映射关系，确定所述K个子信道中的每个子信道对应的预编码矩阵中的行，所述第一映射关系用于指示所述预编码矩阵中的N行与所述N个信道之间的一一对应关系。
  22. 一种发送数据帧的方法，其特征在于，在信道划分为N个子信道的通信系统中执行，N≥2，所述方法包括：
    发送端设备对第一信息进行划分，以生成第一码片和第二码片；
    根据M个交织器组，对所述第一码片和所述第二码片进行处理，以获得M个码片，所述M个码片与所述M个交织器组一一对应，每个码片是基于所对应的交织器组获得的，其中，每个交织器组包括两个交织器，所述M个码片中的第m码片是第m_1序列与第m_2序列相加后获得的，所述第m_1序列是所述第一码片经过所述M个交织器组中的第m交织器组中的一个交织器的交织后获得的，所述第m_2序列是所述第二码片经过所述第m交织器组中的另一个交织器的交织后获得的，所述第m码片与所述第m交织器组对应，m∈[3，M+2]，M≥1；
    生成数据帧，所述数据帧包括N个码片，所述N个码片与所述N个子信道一一对应，每个子信道用于承载所对应的码片，所述N个码片包括所述第一码片、所述第二码片和所述M个码片中的全部或部分码片；
    通过所述N个子信道中的至少两个子信道发送所述数据帧。
  23. 根据权利要求22所述的方法，其特征在于，M＝2。
  24. 根据权利要求22所述的方法，其特征在于，M＝N-2。
  25. 根据权利要求22至24中任一项所述的方法，其特征在于，所述第m_1序列与所述第一码片相同，所述第m_2序列是所述第二码片中的比特循环移位至少一个比特后形成的序列。
  26. 根据权利要求22至25中任一项所述的方法，其特征在于，所述方法还包括：
    根据第一映射关系，确定所述M个交织器组，其中，所述第一映射关系包括所述N个信道中的每个信道的交织器组对应信息，其中，所述第m交织器是第m子信道对应的交织器，所述第m子信道用于传输所述第m码片。
  27. 一种接收数据帧的方法，其特征在于，在信道划分为N个子信道的通信系统中执行，N≥2，所述方法包括：
    接收端设备通过所述N个子信道中的K个子信道接收数据帧，N≥K≥2；
    根据第一译码器和所述K个子信道中的每个子信道的交织器组对应信息，对所述至少两个子信道中的每个子信道中承载的码片进行译码，以获取第一信息，所述第一信息包括 数据帧的前导码字段对应的部分或全部信息，其中，所述K个子信道中的第k子信道承载的第k码片是所述第一信息进行划分后获得的第一码片或第二码片，或者，所述第k码片是所述第一码片和所述第二码片经过所第k子信道对应的第k交织器组进行处理后获得的，其中，每个交织器组包括两个交织器，第k码片是第k_1序列与第k_2序列相加后获得的，所述第k_1序列是所述第一码片经过第k交织器组中的一个交织器的交织后获得的，所述第k_2序列是所述第二码片经过所述第k交织器组中的另一个交织器的交织后获得的，k∈[1，K]。
  28. 根据权利要求27所述的方法，其特征在于，所述第k_1序列与所述第一码片相同，所述第k_2序列是所述第二码片中的比特循环移位至少一个比特后形成的序列。
  29. 根据权利要求27或28所述的方法，其特征在于，所述方法还包括：
    根据第一映射关系，确定所述K个子信道中的每个子信道的交织器组对应信息，其中，所述第一映射关系包括所述N个信道中的每个信道的交织器组对应信息。
  30. 一种无线通信的装置，其特征在于，包括：
    用于实现权利要求1至4中任一项所述的方法的单元；或者
    用于实现权利要求5至8中任一项所述的方法的单元；或者
    用于实现权利要求9至12中任一项所述的方法的单元；或者
    用于实现权利要求13至18中任一项所述的方法的单元；或者
    用于实现权利要求19至21中任一项所述的方法的单元；或者
    用于实现权利要求22至26中任一项所述的方法的单元；或者
    用于实现权利要求27至29中任一项所述的方法的单元。
  31. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质上存储有计算机程序，当所述计算机程序运行时，
    使得装置执行如权利要求1至4中任意一项所述的方法，或者
    使得装置执行如权利要求5至8中任意一项所述的方法，或者
    使得装置执行如权利要求9至12中任意一项所述的方法，或者
    使得装置执行如权利要求13至18中任意一项所述的方法，或者
    使得装置执行如权利要求19至21中任意一项所述的方法，或者
    使得装置执行如权利要求22至26中任意一项所述的方法，或者
    使得装置执行如权利要求27至29中任意一项所述的方法。
  32. 一种芯片系统，其特征在于，包括：处理器，用于从存储器中调用并运行计算机程序，
    使得安装有所述芯片系统的通信装置执行如权利要求1至4中任意一项所述的方法；或者
    使得安装有所述芯片系统的通信装置执行如权利要求5至8中任意一项所述的方法；或者
    使得安装有所述芯片系统的通信装置执行如权利要求9至12中任意一项所述的方法；或者
    使得安装有所述芯片系统的通信装置执行如权利要求13至18中任意一项所述的方法；或者
    使得安装有所述芯片系统的通信装置执行如权利要求19至21中任意一项所述的方法；或者
    使得安装有所述芯片系统的通信装置执行如权利要求22至26中任意一项所述的方法；或者
    使得安装有所述芯片系统的通信装置执行如权利要求27至29中任意一项所述的方法。
  33. 一种通信系统，其特征在于，包括：
    发送端设备，用于执行如权利要求1至4中任意一项所述的方法，或者
    用于执行如权利要求5至8中任意一项所述的方法；
    接收端设备，用于执行如权利要求9至12中任意一项所述的方法。
  34. 一种通信系统，其特征在于，包括：
    发送端设备，用于执行如权利要求13至18中任意一项所述的方法，
    接收端设备，用于执行如权利要求19至21中任意一项所述的方法。
  35. 一种通信系统，其特征在于，包括：
    发送端设备，用于执行如权利要求22至26中任意一项所述的方法，
    接收端设备，用于执行如权利要求27至29中任意一项所述的方法。
  36. 根据权利要求33至35中任一项所述的通信系统，其特征在于，
    所述发送端设备包括接入点AP，所述接收端设备包括站点STA；或者
    所述发送端设备包括STA，所述接收端设备包括AP；或者
    所述发送端设备包括STA，所述接收端设备包括STA。
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