WO2016173032A1 - 通信方法和装置 - Google Patents

通信方法和装置 Download PDF

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Publication number
WO2016173032A1
WO2016173032A1 PCT/CN2015/079865 CN2015079865W WO2016173032A1 WO 2016173032 A1 WO2016173032 A1 WO 2016173032A1 CN 2015079865 W CN2015079865 W CN 2015079865W WO 2016173032 A1 WO2016173032 A1 WO 2016173032A1
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bits
bit sequence
soft
soft bit
module
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PCT/CN2015/079865
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English (en)
French (fr)
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刘晟
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华为技术有限公司
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Publication of WO2016173032A1 publication Critical patent/WO2016173032A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J11/00—Orthogonal multiplex systems, e.g. using WALSH codes

Definitions

  • Embodiments of the present invention relate to the field of communications and, more particularly, to a communication method and apparatus.
  • the multipath propagation of the wireless signal causes the fading of the frequency domain channel, that is, the channel coefficients on different subcarriers are different.
  • the multipath delay spread is large, and the frequency domain channel coefficients vary on different subcarriers. severe.
  • the existing coded modulation scheme cannot effectively overcome the influence of frequency domain channel fading, and thus the transmission performance is poor.
  • the present invention provides a communication method comprising: acquiring a first bit sequence, the first bit sequence comprising K bits; copying the K bits to obtain 2K bits; for the 2K bits Interleaving processing is performed on a bit sequence formed by at least K bits, the at least K bits including K bits in the first bit sequence; the at least K bits after the interleaving process and the 2K
  • the performing, by the interleaving, the bit sequence formed by the at least K bits of the 2K bits including: the first bit sequence Performing an interleaving process; the modulating the at least K bits after the interleaving process and other bits of the 2K bits, including: the K pieces of the first bit sequence after the interleaving process
  • the bits and the other K bits of the 2K bits are modulated.
  • the 2K bits form a second bit sequence
  • the at least K bits of the 2K bits form Performing interleaving processing on the bit sequence includes: performing interleaving processing on the second bit sequence; and modulating the at least K bits after the interleaving process and other bits in the 2K bits, including: The 2K ratios of the second bit sequence after the interleaving process Special modulation.
  • the method further includes: performing channel coding on the M information bits to be sent to obtain the first bit sequence The K bits, wherein the coding rate of the channel coding is M/K.
  • the method further includes: performing an interleaving process on a third bit sequence to be sent to obtain the first bit sequence,
  • the third bit sequence includes K bits, and the K bits included in the third bit sequence are bits obtained by channel coding the M information bits to be transmitted, wherein the coding rate of the channel coding is M/K.
  • the performing the interleaving process comprises: performing the first bit sequence or the second bit sequence in reverse order.
  • the bit sequence respectively includes K soft bits; combining the second soft bit sequence and the third soft bit sequence to obtain a fourth soft bit sequence; and performing channel decoding on the fourth soft bit sequence to obtain M pieces of information Bit, the coding rate of the channel coding corresponding to the channel decoding is M/K.
  • the obtaining the second soft bit sequence and the third soft bit sequence according to the first soft bit sequence including: the first soft bit sequence
  • the soft bit sequence formed by the K soft bits is deinterleaved to obtain the third soft bit sequence, and the K soft bits correspond to the remaining K bits of the 2K bits transmitted by the L modulation symbols .
  • the obtaining the second soft bit sequence and the third soft bit sequence according to the first soft bit sequence includes: Decoding the first soft bit sequence; decomposing the first soft bit sequence after the deinterleaving process to obtain the second soft bit sequence and the third soft bit sequence.
  • the interleaving module is configured to perform interleaving processing on the first bit sequence
  • the modulating module is specifically configured to perform processing on the interleaving
  • the K bits of the first bit sequence and the other K bits of the 2K bits are modulated.
  • the interleaving module is configured to perform interleaving processing on the second bit sequence;
  • the 2K bits of the second bit sequence after the interleaving process are modulated.
  • the apparatus further includes an encoding module, where the encoding module is configured to perform channel coding according to the M information bits to be sent.
  • the interleaving module is specifically configured to: perform interleaving processing on a third bit sequence to be sent to obtain the first bit sequence,
  • the third bit sequence includes K bits, and the K bits included in the third bit sequence are bits obtained by channel coding the M information bits to be transmitted, where the coding rate of the channel coding is M/K .
  • the interleaving module is specifically configured to perform the reverse ordering of the first bit sequence or the second bit sequence.
  • the processing module is specifically configured to: perform deinterleaving a soft bit sequence formed by K soft bits in the first soft bit sequence Processing the third soft bit sequence, the K soft bits corresponding to the remaining K bits of the 2K bits transmitted by the L modulation symbols.
  • the processing module is specifically configured to: perform deinterleaving processing on the first soft bit sequence; and decompose the deinterleaving The processed first soft bit sequence results in the second soft bit sequence and the third soft bit sequence.
  • the processing module is specifically configured to: perform deinterleaving processing on the fourth soft bit sequence.
  • the embodiments of the present invention can reduce the impact of frequency domain channel fading, and can obtain higher transmission performance under the same channel resource and transmission rate, and can make the packet error rate (PER) smaller under the same SNR.
  • PER packet error rate
  • FIG. 1 is a flow chart of a communication method according to an embodiment of the present invention.
  • FIG. 2 is a flow chart of a communication method according to another embodiment of the present invention.
  • FIG. 3 is a flow chart of a communication method according to another embodiment of the present invention.
  • FIG. 4 is a flow chart of a communication method according to another embodiment of the present invention.
  • FIG. 5 is a schematic block diagram of an apparatus in accordance with an embodiment of the present invention.
  • Figure 6 is a schematic block diagram of an apparatus in accordance with another embodiment of the present invention.
  • FIG. 7 is a schematic block diagram of an apparatus in accordance with another embodiment of the present invention.
  • Figure 8 is a schematic block diagram of an apparatus in accordance with another embodiment of the present invention.
  • FIG. 9 is a schematic block diagram of an apparatus in accordance with another embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram of a physical layer grouping of 802.11ax according to an embodiment of the present invention.
  • 1 is a method 100 of communication in accordance with an embodiment of the present invention, the method 100 being performed by a transmitting end.
  • n is a positive integer greater than equal to 1.
  • the embodiment of the present invention can reduce the impact caused by frequency domain channel fading, and can obtain higher transmission performance under the same channel resource and transmission rate, and can make the packet error rate (PER) in the same SNR more. small.
  • PER packet error rate
  • performing the interleaving process on the bit sequence formed by the at least K bits of the 2K bits including: performing interleaving processing on the first bit sequence; Modulating at least K bits and other bits of the 2K bits, including: the K bits of the first bit sequence after the interleaving process and other of the 2K bits K bits are modulated.
  • the 2K bits form a second bit sequence
  • performing, by the interleaving process on the bit sequence formed by at least K bits of the 2K bits includes: performing interleaving processing on the second bit sequence;
  • the modulating the at least K bits after the interleaving process and the other bits of the 2K bits include: modulating the 2K bits of the second bit sequence after the interleaving process.
  • the method further includes: performing, by channel coding, the K bits included in the first bit sequence according to the M information bits to be sent, where the coding rate of the channel coding is M/K.
  • the method further includes performing an interleaving process on the third bit sequence to be sent to obtain the first bit sequence, where the third bit sequence includes K bits, and the third bit sequence includes K bits.
  • the interleaving process includes: performing the first bit sequence or the second bit sequence in reverse order.
  • the impact caused by frequency domain channel fading can be reduced, and higher transmission performance can be obtained under the same channel resource and transmission rate, and the packet error rate (PER) can be made under the same SNR. smaller.
  • the method 200 is a flow chart of a communication method according to another embodiment of the present invention. This method is performed by the receiving end.
  • the method 200 includes:
  • the embodiment of the present invention can reduce the impact caused by frequency domain channel fading, and can obtain higher transmission performance under the same channel resource and transmission rate, and can make the packet error rate (PER) in the same SNR more. small.
  • PER packet error rate
  • the obtaining the second soft bit sequence and the third soft bit sequence according to the first soft bit sequence includes: deinterleaving the soft bit sequence formed by the K soft bits in the first soft bit sequence Obtaining the third soft bit sequence, the K soft bits corresponding to the remaining K bits of the 2K bits transmitted by the L modulation symbols.
  • the obtaining the second soft bit sequence and the third soft bit sequence according to the first soft bit sequence comprising: performing deinterleave processing on the first soft bit sequence; and decomposing the first after the deinterleaving process
  • the soft bit sequence results in the second soft bit sequence and the third soft bit sequence.
  • the method further includes: performing deinterleaving processing on the fourth soft bit sequence.
  • the embodiment of the present invention can reduce the impact caused by frequency domain channel fading, and can obtain higher transmission performance under the same channel resource and transmission rate, and can make the packet error rate (PER) in the same SNR more. small.
  • PER packet error rate
  • the obtaining the second soft bit sequence and the third soft bit sequence according to the first soft bit sequence comprising: K soft bits in the first soft bit sequence constituting the second soft bit sequence, where The K soft bits correspond to the K bits of the 2K bits transmitted by the L modulation symbols, and the soft bit sequences formed by the other K soft bits in the first soft bit sequence are deinterleaved.
  • the third soft bit sequence comprising: K soft bits in the first soft bit sequence constituting the second soft bit sequence, where The K soft bits correspond to the K bits of the 2K bits transmitted by the L modulation symbols, and the soft bit sequences formed by the other K soft bits in the first soft bit sequence are deinterleaved.
  • the obtaining the second soft bit sequence and the third soft bit sequence according to the first soft bit sequence comprising: performing deinterleave processing on the first soft bit sequence; and performing first according to the deinterleaving process a soft bit sequence obtained by the second soft bit sequence and a third soft bit sequence, the second soft bit sequence being composed of K soft bits in the de-interleaved first soft bit sequence, the second K soft bits of the soft bit sequence corresponding to the K bits of the 2K bits transmitted by the L modulation symbols, the third soft bit sequence being processed by the de-interleaved first soft bit sequence
  • the other K soft bits are formed.
  • a communication method 100 in accordance with an embodiment of the present invention is described in detail below with reference to FIGS. 3 through 5.
  • WLAN Wireless Local Access Network
  • OFDMA Orthogonal Frequency-Division Multiple Access
  • MIMO Multiple Input Multiple Output
  • Figure 10 shows the physical layer packet structure of 802.11ax.
  • the initial part is also the traditional preamble, that is, the Legacy Short Training Field (L-STF) and the Legacy Long Training Field (Legacy Long Training Field).
  • L-STF Legacy Short Training Field
  • L-SIG Legacy Signal Field
  • the traditional preamble and data field are 802.11ax protocol-specific preambles, ie, HEW preambles.
  • the HEW preamble includes Repeated Legacy Signal Field (RL-SIG), High Efficiency Signal-A field (HE-SIG-A), High Efficiency Signal B field (High Efficiency Signal) -B field (referred to as HE-SIG-B), High Efficiency Short Training Field (HE-STF) and High Efficiency Long Training Field (HE-LTF).
  • the data field is used for data transmission, and the fields such as L-SIG, RL-SIG, HE-SIG-A and HE-SIG-B are respectively used to transmit different types of physical layer signaling, L-STF, L-LTF, Fields such as HE-STF and HE-LTF are mainly used for receiving timing and frequency synchronization, automatic gain control and channel estimation.
  • the basic constituent units of 802.11ax physical layer packets are OFDM symbols, and each OFDM symbol contains a certain length of Cyclic Prefix (CP), for example Both L-SIG and RL-SIG contain an OFDM symbol of length 4 microseconds, where the length of the CP is 0.8 microseconds. As shown in FIG.
  • MCS Modulation Coding Scheme
  • SNR Signal to Noise Ratio
  • MCS serial number Modulation Coding rate 0 BPSK 1/2 1 QPSK 1/2 2 QPSK 3/4 3 16QAM 1/2 4 16QAM 3/4
  • L-SIG, RL-SIG and HE-SIG-A use MCS0, ie binary phase shift key, for the purpose of reliable transmission of physical layer signaling and automatic identification of WLAN physical layer packets of different protocol versions.
  • MCS0 binary phase shift key
  • BPSK Binary Phase Shift Keying
  • the HE-SIG-B is mainly used for transmitting scheduling control information of a scheduled user, such as an identifier of each STA that performs data transmission in the physical layer packet, and a channel resource used for transmitting data of each STA (for example, a frequency domain) Subcarrier resources), the number of spatial streams and corresponding spatial stream identifiers, and the coded modulation scheme used to transmit the corresponding spatial streams.
  • scheduling control information of a scheduled user such as an identifier of each STA that performs data transmission in the physical layer packet, and a channel resource used for transmitting data of each STA (for example, a frequency domain) Subcarrier resources), the number of spatial streams and corresponding spatial stream identifiers, and the coded modulation scheme used to transmit the corresponding spatial streams.
  • HE-SIG-B can transmit using MCS0 when the SNR is low, at SNR.
  • High-time HE-SIG-B can use MCS1, Quadrature Phase Shift Keying (QPSK) modulation and convolutional coding with a coding rate of 1/2, or MCS2, QPSK modulation and coding rate of 3/.
  • the convolutional code of 4 is transmitted.
  • the data field is also transmitted using a lower-order coding modulation scheme such as MCS0, MCS1, and MCS2.
  • the present invention proposes an improved scheme of a low-order MCS scheme in a WLAN system, which can effectively overcome the influence of frequency domain channel fading, and can obtain higher transmission performance under the same channel resources and transmission rates, that is, the same SNR.
  • the Packet Error Rate (PER) is smaller.
  • Figure 3 (a) shows the OFDM signal generation process at the transmitting end.
  • K bits b K-1 , . . . , b 1 , b 0 are obtained, and two sets of identical bit sequences are obtained by repetition, wherein one set is interleaved by an interleaver 2 with a depth of K bits to obtain K bits b.
  • the interleaver 1 is the interleaver shown in FIG. 2 in the existing MCS scheme.
  • the present invention uses a 16-Quadrature Amplitude Modulation (16QAM) with constellation points of 16, which is about to Map to a 16QAM constellation point.
  • 16QAM 16-Quadrature Amplitude Modulation
  • the embodiment shown in FIG. 3(b) is a process in which the receiving end processes the received OFDM signal.
  • the received OFDM signal is first processed by removing CP, FFT, and channel equalization, and then demodulated by the higher order modulation to obtain two sets of soft bit sequences, respectively, and the original bit sequence before modulation at the transmitting end.
  • the bit sequence after interleaving by the interleaver 2 corresponds to a bit sequence, which is usually represented by a log-likelihood ratio (LLR), and is interleaved by the interleaver 2 before modulation at the transmitting end.
  • LLR log-likelihood ratio
  • the soft bit sequence corresponding to the sequence is deinterleaved by the deinterleaver 2
  • the soft bit sequences corresponding to the original bit sequence before the modulation of the transmitting end are merged one by one, and the processing of the combined soft bit sequence is the same as the prior art, that is, After the deinterleaver 1 performs deinterleaving, the transmitted information bits are obtained through channel decoding processing.
  • the deinterleaver 1 is the deinterleaver shown in FIG. 2 in the existing MCS scheme, and if the interleaver 2 is implemented in the bit reverse order, the deinterleaver 2 is also in the reverse order of bits.
  • the impact caused by frequency domain channel fading can be reduced, and higher transmission performance can be obtained under the same channel resource and transmission rate, and the packet error rate (PER) can be made under the same SNR. smaller.
  • FIG. 4 shows an OFDM signal transceiving process according to an embodiment of the present invention.
  • the scheme differs from the embodiment shown in FIG. 3 in that the existing interleaver 1 (ie, the interleaver in the existing MCS scheme) is directly used.
  • the K coded bits a K-1 , . . . , a 1 , a 0 after channel coding are directly repeated to obtain two sets of identical bit sequences, one of which is interleaved by the interleaver 1 to obtain K bits b K-1 , . . . , b 1 , b 0 , then the original bit sequence a K-1 , . . .
  • the existing deinterleaver 1 (ie the deinterleaver shown in FIG. 2 in the existing MCS scheme) is also directly utilized at the receiving end without adding the deinterleaver 2, in particular, the solution of the higher order modulation.
  • the impact caused by frequency domain channel fading can be reduced, and higher transmission performance can be obtained under the same channel resource and transmission rate, and the packet error rate (PER) can be made under the same SNR. smaller.
  • FIG. 5 shows an OFDM signal transceiving process according to an embodiment of the present invention.
  • the channel-coded K coded bits a K-1 , . . . , a 1 , a 0 are respectively repeated to obtain a set of bit sequences including 2K bits, wherein the arrangement of the repeated bits and the original bits is not
  • the bit sequence of length 2K may be arranged by a K-1 a K-1 , . . . , a 1 a 1 , a 0 a 0 , or may be a K-1 , . . .
  • the bit sequence of length 2K is interleaved by the interleaver 3 with a depth of 2K bits to obtain 2K bits, and then L modulation symbols are obtained by higher order modulation.
  • the number of carriers is the same as the existing MCS. Specifically, if the existing MCS adopts BPSK modulation, Then, the present invention adopts QPSK modulation. If the existing MCS adopts QPSK modulation, the present invention adopts 16QAM modulation. Thus, for MCS0, Embodiment 3 of the present invention employs QPSK modulation, while for MCS1 and MCS2, the embodiment shown in FIG. 5 employs 16QAM modulation.
  • the received OFDM signal is subjected to processing such as removing CP, FFT, and channel equalization, and then performing demodulation processing corresponding to the higher-order modulation to obtain a soft bit sequence, and then deinterleaving.
  • processing such as removing CP, FFT, and channel equalization, and then performing demodulation processing corresponding to the higher-order modulation to obtain a soft bit sequence, and then deinterleaving.
  • two sets of soft bit sequences are separated according to the arrangement corresponding to the transmitting end, respectively corresponding to the sequence of the original bit sequence and the repeated bits after the channel encoding of the transmitting end, and then the two groups are soft.
  • the bit sequences are merged one by one, and the combined soft bit sequence is finally subjected to channel decoding processing to obtain the transmitted information bits.
  • the interleaver 3 and the deinterleaver 3 can still use the interleaver and deinterleaver shown in the existing MCS scheme, but use the bits whose coding rate is also r but transmitted by each modulation symbol.
  • the interleaver and deinterleaver used in the MCS scheme of 2n for example, for MCS0, MCS1, and MCS2,
  • Embodiment 3 of the present invention can employ an interleaver and a deinterleaver of MCS1, MCS3, and MCS4, respectively.
  • the impact caused by frequency domain channel fading can be reduced, and higher transmission performance can be obtained under the same channel resource and transmission rate, and the packet error rate (PER) can be made under the same SNR. smaller.
  • FIG. 6 is a schematic block diagram of an apparatus in accordance with an embodiment of the present invention.
  • the device 600 includes:
  • An obtaining module 610 configured to acquire a first bit sequence, where the first bit sequence includes K bits;
  • the copying module is configured to copy the K bits to obtain 2K bits;
  • the interleaving module 630 is configured to perform interleaving processing on a bit sequence formed by at least K bits of the 2K bits, where the at least K bits include K bits in the first bit sequence;
  • the mapping module 650 is configured to map the L modulation symbols to L subcarriers to generate orthogonal frequency division multiplexing OFDM symbols.
  • the impact caused by frequency domain channel fading can be reduced, and higher transmission performance can be obtained under the same channel resource and transmission rate, and packets can be grouped under the same SNR.
  • the Packet Error Rate (PER) is smaller.
  • the modulating module 640 is configured to perform interleaving processing on the first bit sequence; the modulating module is specifically configured to use the K bits of the first bit sequence after the interleaving process and the 2K The other K bits of the bits are modulated.
  • the modulating module 640 is configured to perform interleaving processing on the second bit sequence, where the modulating module is specifically configured to modulate the 2K bits of the second bit sequence after the interleaving process.
  • the apparatus further includes an encoding module, where the encoding module is configured to obtain, according to the M information bits to be sent, the K bits included in the first bit sequence, where the channel coding
  • the encoding rate is M/K.
  • the interleaving module 630 is specifically configured to perform interleaving processing on a third bit sequence to be sent to obtain the first bit sequence, where the third bit sequence includes K bits, and the third bit sequence includes The K bits are bits obtained by channel coding the M information bits to be transmitted, wherein the coding rate of the channel coding is M/K.
  • the interleaving module 630 is specifically configured to perform the reverse ordering of the first bit sequence or the second bit sequence.
  • the impact caused by frequency domain channel fading can be reduced, and higher transmission performance can be obtained under the same channel resource and transmission rate, and the packet error rate (PER) can be made under the same SNR. smaller.
  • FIG. 7 is a schematic block diagram of an apparatus in accordance with another embodiment of the present invention.
  • the device 700 includes:
  • a communication device comprising:
  • An obtaining module 710 configured to acquire signals on L subcarriers of the received OFDM symbol, where the signals on the L subcarriers respectively correspond to L modulation symbols, and each of the modulation symbols is transmitted.
  • the number of bits is 2n
  • the L modulation symbols transmit 2K bits
  • a demodulation module 720 configured to demodulate signals on the L subcarriers to obtain a first soft bit sequence including 2K soft bits;
  • the processing module 730 is configured to obtain a second soft bit sequence and a third soft bit sequence according to the first soft bit sequence, where the second soft bit sequence and the third soft bit sequence respectively comprise K soft bits Bit
  • the processing module 730 is further configured to use the second soft bit sequence and the third soft bit sequence Merging to obtain a fourth soft bit sequence
  • the decoding module 740 is configured to perform channel decoding on the fourth soft bit sequence to obtain M information bits, where the channel coding corresponding to the channel decoding has an encoding rate of M/K.
  • the processing module 730 is specifically configured to: perform deinterleaving processing on a soft bit sequence formed by K soft bits in the first soft bit sequence to obtain the third soft bit sequence, where the K soft bits are The bits correspond to the remaining K bits of the 2K bits transmitted by the L modulation symbols.
  • the processing module 730 is specifically configured to: perform deinterleave processing on the first soft bit sequence; and decompose the first soft bit sequence after the deinterleaving process to obtain the second soft bit sequence and third Soft bit sequence.
  • the processing module 740 is specifically configured to: perform deinterleave processing on the fourth soft bit sequence.
  • the impact caused by frequency domain channel fading can be reduced, and higher transmission performance can be obtained under the same channel resource and transmission rate, and the packet error rate (PER) can be made under the same SNR. smaller.
  • an embodiment of the present invention further provides a communication device 10, which includes a processor 11, a memory 12, a bus system 13, and a receiver 14.
  • the processor 11, the memory 12 and the receiver 14 are connected by a bus system 13 for storing instructions for executing instructions stored in the memory 12 and controlling the receiver 14 to receive information.
  • the receiver 14 is configured to: acquire the first bit sequence, where the first bit sequence includes K bits; and the processor 11 is configured to: the copy module is configured to copy the K bits Obtaining 2K bits; performing interleaving processing on a bit sequence formed by at least K bits of the 2K bits, the at least K bits including K bits in the first bit sequence; processing the interleaving
  • the modulation symbols are respectively mapped with L subcarriers to generate orthogonal frequency division multiplexing OFDM symbols.
  • the mobility management network element of the embodiment of the present invention obtains a classification attribute of the downlink data to be transmitted, and determines whether to send a paging message to the access network device according to the classification attribute of the downlink data to be transmitted to determine whether to establish
  • the bearer between the access network device and the serving gateway and the bearer between the access network device and the user equipment thereby being able to control the establishment of the bearer on the access network side during the transmission of the downlink data, thereby avoiding blind connection establishment.
  • the bearer on the network side can save signaling overhead. And can alleviate data transmission congestion.
  • the processor 11 may be a central processing unit (“CPU"), and the processor 11 may also be other general-purpose processors, digital signal processors (DSPs). , an application specific integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, and the like.
  • the general purpose processor may be a microprocessor or the processor or any conventional processor or the like.
  • the memory 12 can include read only memory and random access memory and provides instructions and data to the processor 11.
  • a portion of the memory 12 may also include a non-volatile random access memory.
  • the memory 820 can also store information of the device type.
  • the bus system 13 may include a power bus, a control bus, a status signal bus, and the like in addition to the data bus. However, for the sake of clarity, various buses are labeled as the bus system 13 in the figure.
  • each step of the foregoing method may be completed by an integrated logic circuit of hardware in the processor 11 or an instruction in a form of software.
  • the steps of the method disclosed in the embodiments of the present invention may be directly implemented as a hardware processor, or may be performed by a combination of hardware and software modules in the processor.
  • the software module can be located in a conventional storage medium such as random access memory, flash memory, read only memory, programmable read only memory or electrically erasable programmable memory, registers, and the like.
  • the storage medium is located in the memory 12, and the processor 11 reads the information in the memory 820 and performs the steps of the above method in combination with its hardware. To avoid repetition, it will not be described in detail here.
  • the processor 11 is further configured to: perform interleaving processing on the first bit sequence; the modulation module is specifically configured to use the first bit sequence after the interleaving process The K bits and the other K bits of the 2K bits are modulated.
  • the processor 11 is further configured to: perform interleaving processing on the second bit sequence; and the modulation module is specifically configured to use the 2K of the second bit sequence after the interleaving process The bits are modulated.
  • the processor 11 is further configured to: perform channel coding, according to the M information bits to be sent, the K bits included in the first bit sequence, where the channel coding The coding rate is M/K.
  • the processor 11 is further configured to perform interleaving processing on the third bit sequence to be sent to obtain the first bit sequence, where the third bit sequence includes K bits, and the third The K bits contained in the bit sequence are M information bits to be transmitted and are channel-coded. A bit obtained by the code, wherein the coding rate of the channel coding is M/K.
  • the processor 11 is further configured to: perform the reverse ordering of the first bit sequence or the second bit sequence.
  • the mobility management network element 10 may correspond to an execution body of the communication method of the embodiment of the present invention, and the above-described and other operations and/or functions of the respective modules in the mobility management network element 10 are respectively In order to implement the various methods in FIG. 1 to FIG. 5 , for brevity, no further details are provided herein.
  • the impact caused by frequency domain channel fading can be reduced, and higher transmission performance can be obtained under the same channel resource and transmission rate, and the packet error rate (PER) can be made under the same SNR. smaller.
  • an embodiment of the present invention further provides an access network device 20, which includes a processor 21, a memory 22, a bus system 23, and a receiver 24.
  • the processor 21, the memory 22 and the receiver 24 are connected by a bus system 23 for storing instructions for executing instructions stored by the memory 22 and for controlling the receiver 24 to receive information.
  • the receiver 24 is configured to: acquire signals on L subcarriers of the received OFDM symbol, where the signals on the L subcarriers respectively correspond to L modulation symbols, and each of the modulation symbols is transmitted.
  • the impact caused by frequency domain channel fading can be reduced, and higher transmission performance can be obtained under the same channel resource and transmission rate, and the packet error rate (PER) can be made under the same SNR. smaller.
  • the processor 21 may be a central processing unit (“CPU"), and the processor 21 may also be other general-purpose processors and digital signal processors (DSPs). , an application specific integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, and the like.
  • the general purpose processor may be a microprocessor or the processor or any conventional processor or the like.
  • the memory 22 can include read only memory and random access memory and provides instructions and data to the processor 21. A portion of the memory 22 may also include a non-volatile random access memory. For example, the memory 22 can also store information of the device type.
  • the bus system 23 may include a power bus, a control bus, a status signal bus, and the like in addition to the data bus. However, for clarity of description, various buses are labeled as the bus system 23 in the figure.
  • each step of the above method may be completed by an integrated logic circuit of hardware in the processor 21 or an instruction in the form of software.
  • the steps of the method disclosed in the embodiments of the present invention may be directly implemented as a hardware processor, or may be performed by a combination of hardware and software modules in the processor.
  • the software module can be located in a conventional storage medium such as random access memory, flash memory, read only memory, programmable read only memory or electrically erasable programmable memory, registers, and the like.
  • the storage medium is located in the memory 22, and the processor 21 reads the information in the memory 22 and combines the hardware to perform the steps of the above method. To avoid repetition, it will not be described in detail here.
  • the processor 21 is configured to: perform deinterleaving processing on a soft bit sequence formed by K soft bits in the first soft bit sequence to obtain the third soft bit sequence, where The K soft bits correspond to the remaining K bits of the 2K bits transmitted by the L modulation symbols.
  • the access network device 20 may correspond to an execution body of the method of communication according to the embodiment of the present invention, and may correspond to the access network device 700 according to the embodiment of the present invention, and the access network device
  • the above and other operations and/or functions of the respective modules in the 700 are respectively implemented in order to implement the respective processes of the respective methods in FIG. 1 and FIG. 5, and are not described herein again for brevity.
  • the impact caused by frequency domain channel fading can be reduced, and higher transmission performance can be obtained under the same channel resource and transmission rate, and the packet error rate (PER) can be made under the same SNR. smaller.
  • the processor 31 may be a central processing unit (“CPU"), and the processor 31 may also be other general-purpose processors, digital signal processors (DSPs). , an application specific integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, and the like.
  • the general purpose processor may be a microprocessor or the processor or any conventional processor or the like.
  • the memory 32 can include a read only memory and a random access memory, and provides the processor 31 with For instructions and data. A portion of the memory 32 may also include a non-volatile random access memory. For example, the memory 32 can also store information of the device type.
  • the bus system 33 may include a power bus, a control bus, a status signal bus, and the like in addition to the data bus. However, for clarity of description, various buses are labeled as the bus system 33 in the figure.
  • each step of the above method may be completed by an integrated logic circuit of hardware in the processor 31 or an instruction in a form of software.
  • the steps of the method disclosed in the embodiments of the present invention may be directly implemented as a hardware processor, or may be performed by a combination of hardware and software modules in the processor.
  • the software module can be located in a conventional storage medium such as random access memory, flash memory, read only memory, programmable read only memory or electrically erasable programmable memory, registers, and the like.
  • the storage medium is located in the memory 32, and the processor 31 reads the information in the memory 32 and, in conjunction with its hardware, performs the steps of the above method. To avoid repetition, it will not be described in detail here.
  • the processor 31 determines, according to the classification attribute of the second downlink data to be transmitted and the downlink data control policy, whether to send a downlink data notification message to the mobility management network element, including:
  • Determining when determining that the classification attribute of the second downlink data to be transmitted belongs to the classification attribute set of the downlink data that is allowed to be transmitted indicated by the downlink data control policy, or determining that the classification attribute of the second downlink data to be transmitted does not belong to the downlink data control
  • the policy indicates a set of classification attributes of the downlink data that is prohibited from being transmitted, it is determined that the downlink data notification message is sent to the mobility management network element.
  • the classification attribute of the second to-be-transmitted downlink data includes at least one of the following information: service type information of the second to-be-transmitted downlink data, and priority of the second to-be-transmitted downlink data. Level information and quality of service information of the second downlink data to be transmitted.
  • the serving gateway 30 may correspond to an execution body of a method for transmitting downlink data according to an embodiment of the present invention, and may correspond to the serving gateway 900 according to an embodiment of the present invention, and in the serving gateway 30.
  • the above and other operations and/or functions of the respective modules are respectively implemented in order to implement the respective processes of the respective methods in FIG. 1 to FIG. 5, and are not described herein again for brevity.
  • the disclosed system, apparatus, and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be electrical, mechanical or otherwise.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the functions may be stored in a computer readable storage medium if implemented in the form of a software functional unit and sold or used as a standalone product.
  • the technical solution of the present invention which is essential or contributes to the prior art, or a part of the technical solution, may be embodied in the form of a software product, which is stored in a storage medium, including
  • the instructions are used to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .
  • bit sequence formed by at least K bits of 2K bits in step 130 is Line interleaving also includes the following methods:
  • Step 1 Split the bit sequence formed by the at least K bits into two sub-sequences of the same number of bits.
  • Step 2 Exchange the positions of the two sub-sequences to obtain a bit sequence composed of at least K bits after interleaving.
  • Step 1 divides the sequence into subsequences 101 and subsequences 110.
  • step 2 the positions of the two subsequences are exchanged to obtain 110101.

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Abstract

本发明公开了一种通信方法，该方法包括：获取第一比特序列，第一比特序列包含K个比特；复制K个比特，得到2K个比特；对2K个比特中的至少K个比特构成的比特序列进行交织处理，该至少K个比特包括第一比特序列中的K个比特；对交织处理后的至少K个比特和2K个比特中的其它比特进行调制，得到L＝K/n个调制符号，每个所述调制符号传输的比特数为2n；将L个调制符号分别与L个子载波映射，生成正交频分复用OFDM符号。本发明实施例能够降低频域信道衰落造成的影响，在相同的信道资源和传输速率下可以获得更高的传输性能。

Description

通信方法和装置
本申请要求于2015年04月30日提交中国专利局、申请号为PCT/CN2015/078153、发明名称为“通信方法和装置”的PCT专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明实施例涉及通信领域，并且更具体地，涉及通信方法和装置。
背景技术
无线信号的多径传播造成频域信道的衰落，即不同子载波上的信道系数均不相同，特别在室外应用场景中，多径时延扩展较大，频域信道系数在不同子载波上变化剧烈。但是，现有的编码调制方案并不能有效克服频域信道衰落造成的影响，因此传输性能较差。
发明内容
第一方面，本发明提供了一种通信方法，包括：获取第一比特序列，所述第一比特序列包含K个比特；复制所述K个比特，得到2K个比特；对所述2K个比特中的至少K个比特构成的比特序列进行交织处理，所述至少K个比特包括所述第一比特序列中的K个比特；对所述交织处理后的所述至少K个比特和所述2K个比特中的其它比特进行调制，得到L＝K/n个调制符号，每个所述调制符号传输的比特数为2n；将所述L个调制符号分别与L个子载波映射，生成正交频分复用OFDM符号。
结合第一方面，在第一方面的第一种可能的实现方式中，所述对所述2K个比特中的至少K个比特构成的比特序列进行交织处理，包括：对所述第一比特序列进行交织处理；所述对所述交织处理后的所述至少K个比特和所述2K个比特中的其它比特进行调制，包括：对所述交织处理后的第一比特序列的所述K个比特和所述2K个比特中的其它K个比特进行调制。
结合第一方面及其上述实现方式，在第一方面的第二种可能的实现方式中，所述2K个比特构成第二比特序列，所述对所述2K个比特中的至少K个比特构成的比特序列进行交织处理，包括：对所述第二比特序列进行交织处理；所述对所述交织处理后的所述至少K个比特和所述2K个比特中的其它比特进行调制，包括：对所述交织处理后的第二比特序列的所述2K个比 特进行调制。
结合第一方面及其上述实现方式，在第一方面的第三种可能的实现方式中，所述方法还包括：根据待发送的M个信息比特经信道编码得所述第一比特序列包含的所述K个比特，其中，所述信道编码的编码速率为M/K。
结合第一方面及其上述实现方式，在第一方面的第四种可能的实现方式中，所述方法还包括：对待发送的第三比特序列进行交织处理得到所述第一比特序列，所述第三比特序列包含K个比特，所述第三比特序列包含的K个比特为待发送的M个信息比特经信道编码得到的比特，其中，所述信道编码的编码速率为M/K。
结合第一方面及其上述实现方式，在第一方面的第四种可能的实现方式中，所述交织处理包括：将所述第一比特序列或第二比特序列进行反序排列。
第二方面，提供一种通信的方法，所述方法包括：获取接收到的OFDM符号的L个子载波上的信号，其中，所述L个子载波上的信号分别L个调制符号对应，每个所述调制符号传输的比特数为2n，所述L个调制符号传输2K个比特，所述2K个比特中的K个比特分别与其余K个比特相同，L＝K/n；解调所述L个子载波上信号，得到包括2K个软比特的第一软比特序列；根据第一软比特序列得到第二软比特序列和第三软比特序列，所述第二软比特序列和所述第三软比特序列分别包含K个软比特；将所述第二软比特序列和所述第三软比特序列进行合并，得到第四软比特序列；对所述第四软比特序列进行信道解码获得M个信息比特，所述信道解码所对应的信道编码的编码速率为M/K。
结合第二方面，在第二方面的第一种可能的实现方式中，所述根据第一软比特序列得到第二软比特序列和第三软比特序列，包括：对所述第一软比特序列中的K个软比特构成的软比特序列进行解交织处理得到所述第三软比特序列，所述K个软比特对应所述L个调制符号传输的2K个比特中的所述其余K个比特。
结合第二方面及其上述实现方式，在第二方面的第三种可能的实现方式中，所述根据第一软比特序列得到第二软比特序列和第三软比特序列，包括：对所述第一软比特序列进行解交织处理；分解所述解交织处理后的第一软比特序列得到所述第二软比特序列和第三软比特序列。
结合第二方面及其上述实现方式，在第二方面的第四种可能的实现方式 中，对所述第四软比特序列进行解交织处理。
第三方面，提供了一种通信装置，包括：获取模块，所述获取模块用于获取第一比特序列，所述第一比特序列包含K个比特；复制模块，所述复制模块用于复制所述K个比特，得到2K个比特；交织模块，所述交织模块用于对所述2K个比特中的至少K个比特构成的比特序列进行交织处理，所述至少K个比特包括所述第一比特序列中的K个比特；调制模块，所述调制模块用于对所述交织处理后的所述至少K个比特和所述2K个比特中的其它比特进行调制，得到L＝K/n个调制符号，每个所述调制符号传输的比特数为2n；映射模块，所述映射模块用于将所述L个调制符号分别与L个子载波映射，生成正交频分复用OFDM符号。
结合第三方面，在第三方面的第一种可能的实现方式中，所述交织模块用于对所述第一比特序列进行交织处理；所述调制模块具体用于对所述交织处理后的第一比特序列的所述K个比特和所述2K个比特中的其它K个比特进行调制。
结合第三方面及其上述实现方式，在第三方面的第二种可能的实现方式中，所述交织模块用于对所述第二比特序列进行交织处理；所述调制模块具体用于对所述交织处理后的第二比特序列的所述2K个比特进行调制。
结合第三方面及其上述实现方式，在第三方面的第三种可能的实现方式中，所述装置还包括编码模块，所述编码模块用于根据待发送的M个信息比特经信道编码得所述第一比特序列包含的所述K个比特，其中，所述信道编码的编码速率为M/K。
结合第三方面及其上述实现方式，在第三方面的第四种可能的实现方式中，所述交织模块具体用于：对待发送的第三比特序列进行交织处理得到所述第一比特序列，所述第三比特序列包含K个比特，所述第三比特序列包含的K个比特为待发送的M个信息比特经信道编码得到的比特，其中，所述信道编码的编码速率为M/K。
结合第三方面及其上述实现方式，在第三方面的第五种可能的实现方式中，所述交织模块具体用于将所述第一比特序列或第二比特序列进行反序排列。
第四方面，提供了一种通信装置，包括：获取模块，所述获取模块用于获取接收到的OFDM符号的L个子载波上的信号，其中，所述L个子载波 上的信号分别L个调制符号对应，每个所述调制符号传输的比特数为2n，所述L个调制符号传输2K个比特，所述2K个比特中的K个比特分别与其余K个比特相同，L＝K/n；解调模块，所述解调模块用于解调所述L个子载波上信号，得到包括2K个软比特的第一软比特序列；处理模块，所述处理模块用于根据第一软比特序列得到第二软比特序列和第三软比特序列，所述第二软比特序列和所述第三软比特序列分别包含K个软比特；所述处理模块还用于将所述第二软比特序列和所述第三软比特序列进行合并，得到第四软比特序列；解码模块，所述解码模块用于对所述第四软比特序列进行信道解码获得M个信息比特，所述信道解码所对应的信道编码的编码速率为M/K。
结合第四方面，在第四方面的第一种可能的实现方式中，，所述处理模块具体用于：对所述第一软比特序列中的K个软比特构成的软比特序列进行解交织处理得到所述第三软比特序列，所述K个软比特对应所述L个调制符号传输的2K个比特中的所述其余K个比特。
结合第四方面及其上述实现方式，在第四方面的第二种可能的实现方式中，所述处理模块具体用于：对所述第一软比特序列进行解交织处理；分解所述解交织处理后的第一软比特序列得到所述第二软比特序列和第三软比特序列。
结合第四方面及其上述实现方式，在第四方面的第三种可能的实现方式中，所述处理模块具体用于：对所述第四软比特序列进行解交织处理。
本发明实施例能够降低频域信道衰落造成的影响，在相同的信道资源和传输速率下可以获得更高的传输性能，能够使得相同SNR下分组错误率(Packet Error Rate，简称PER)更小。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例的通信方法的流程图。
图2是本发明另一实施例的通信方法的流程图。
图3是本发明另一实施例的通信方法的流程图。
图4是本发明另一实施例的通信方法的流程图。
图5是本发明实施例的装置的示意性框图。
图6是本发明另一实施例的装置的示意性框图。
图7是本发明另一实施例的装置的示意性框图。
图8是本发明另一实施例的装置的示意性框图。
图9是本发明另一实施例的装置的示意性框图。
图10是本发明实施例的802.11ax的物理层分组结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
图1是本发明实施例的通信的方法100，该方法100由发射端执行。
110，获取第一比特序列，第一比特序列包含K个比特；
120，复制K个比特，得到2K个比特；
130，对2K个比特中的至少K个比特构成的比特序列进行交织处理，该至少K个比特包括第一比特序列中的K个比特；
140，对交织处理后的至少K个比特和2K个比特中的其它比特进行调制，得到L＝K/n个调制符号，每个所述调制符号传输的比特数为2n；
150，将L个调制符号分别与L个子载波映射，生成正交频分复用OFDM符号。
应理解，现有K个比特采用的调整符号，每个调制符号传输的比特数为n，n为大于等与1的正整数。
因此，本发明实施例能够降低频域信道衰落造成的影响，在相同的信道资源和传输速率下可以获得更高的传输性能，能够使得相同SNR下分组错误率(Packet Error Rate，简称PER)更小。
可选地，所述对所述2K个比特中的至少K个比特构成的比特序列进行交织处理，包括：对所述第一比特序列进行交织处理；所述对所述交织处理后的所述至少K个比特和所述2K个比特中的其它比特进行调制，包括：对所述交织处理后的第一比特序列的所述K个比特和所述2K个比特中的其它 K个比特进行调制。
可选地，所述2K个比特构成第二比特序列，所述对所述2K个比特中的至少K个比特构成的比特序列进行交织处理，包括：对所述第二比特序列进行交织处理；所述对所述交织处理后的所述至少K个比特和所述2K个比特中的其它比特进行调制，包括：对所述交织处理后的第二比特序列的所述2K个比特进行调制。
可选地，所述方法还包括：根据待发送的M个信息比特经信道编码得所述第一比特序列包含的所述K个比特，其中，所述信道编码的编码速率为M/K。
可选地，所述方法还包括：对待发送的第三比特序列进行交织处理得到所述第一比特序列，所述第三比特序列包含K个比特，所述第三比特序列包含的K个比特为待发送的M个信息比特经信道编码得到的比特，其中，所述信道编码的编码速率为M/K。
可选地，所述交织处理包括：将所述第一比特序列或第二比特序列进行反序排列。
因此，本发明实施例，能够降低频域信道衰落造成的影响，在相同的信道资源和传输速率下可以获得更高的传输性能，能够使得相同SNR下分组错误率(Packet Error Rate，简称PER)更小。
图2是本发明另一实施例的通信方法的流程图。该方法由接收端执行。该方法200包括：
210，获取接收到的OFDM符号的L个子载波上的信号，其中，所述L个子载波上的信号分别L个调制符号对应，每个所述调制符号传输的比特数为2n，所述L个调制符号传输2K个比特，所述2K个比特中的K个比特分别与其余K个比特相同，L＝K/n；
220，解调所述L个子载波上信号，得到包括2K个软比特的第一软比特序列；
230，根据第一软比特序列得到第二软比特序列和第三软比特序列，所述第二软比特序列和所述第三软比特序列分别包含K个软比特；
240，将所述第二软比特序列和所述第三软比特序列进行合并，得到第四软比特序列；
250，对所述第四软比特序列进行信道解码获得M个信息比特，所述信 道解码所对应的信道编码的编码速率为M/K。
因此，本发明实施例能够降低频域信道衰落造成的影响，在相同的信道资源和传输速率下可以获得更高的传输性能，能够使得相同SNR下分组错误率(Packet Error Rate，简称PER)更小。
可选地，所述根据第一软比特序列得到第二软比特序列和第三软比特序列，包括：对所述第一软比特序列中的K个软比特构成的软比特序列进行解交织处理得到所述第三软比特序列，所述K个软比特对应所述L个调制符号传输的2K个比特中的所述其余K个比特。
可选地，所述根据第一软比特序列得到第二软比特序列和第三软比特序列，包括：对所述第一软比特序列进行解交织处理；分解所述解交织处理后的第一软比特序列得到所述第二软比特序列和第三软比特序列。
可选地，所述方法还包括：对所述第四软比特序列进行解交织处理。
因此，本发明实施例能够降低频域信道衰落造成的影响，在相同的信道资源和传输速率下可以获得更高的传输性能，能够使得相同SNR下分组错误率(Packet Error Rate，简称PER)更小。
可选地，所述根据第一软比特序列得到第二软比特序列和第三软比特序列，包括：所述第一软比特序列中的K个软比特构成所述第二软比特序列，所述K个软比特对应所述L个调制符号传输的2K个比特中的所述K个比特，对所述第一软比特序列中的其它K个软比特构成的软比特序列进行解交织处理得到所述第三软比特序列。
可选地，所述根据第一软比特序列得到第二软比特序列和第三软比特序列，包括：对所述第一软比特序列进行解交织处理；根据所述解交织处理后的第一软比特序列得到所述第二软比特序列和第三软比特序列，所述第二软比特序列由所述解交织处理后的第一软比特序列中的K个软比特构成，所述第二软比特序列的K个软比特对应所述L个调制符号传输的2K个比特中的所述K个比特，所述第三软比特序列由所述解交织处理后的第一软比特序列中的其它K个软比特构成。
下面结合图3至图5详细描述根据本发明实施例的通信方法100。
现有基于OFDM(Orthogonal Frequency-Division Multiplexing，正交频分复用)技术的无线局域网(Wireless local Access Network，简称WLAN) 标准由逐步演进的802.11a、802.11n、802.11ac等版本组成，目前IEEE 802.11标准组织已启动了称之为HEW(High Efficiency WLAN，高效率无线局域网)的新一代WLAN标准即802.11ax的标准化工作，该标准支持OFDMA(Orthogonal Frequency-Division Multiple Access，正交频分复用多址)和MIMO(Multiple Input Multiple Output，多输入多输出)技术，其中，OFDMA有效降低了随机信道竞争造成的冲突，从而提高密集用户场景下的传输效率，MIMO则通过空间复用的方式使用同一信道资源传输多个并行的空间流，从而提高系统的频谱效率。
图10示出了802.11ax的物理层分组结构，其最开始的部分也是传统前导，即由传统短训练字段(Legacy Short Training field，简称L-STF)、传统长训练字段(Legacy Long Training field，简称L-LTF)和传统信令字段(Legacy Signal field，简称L-SIG)组成的字段，最后为数据字段，传统前导和数据字段之间为802.11ax协议特定的前导即HEW前导，HEW前导包括重复的传统信令字段(Repeated Legacy Signal field，简称RL-SIG)、高效率信令A字段(High Efficiency Signal-A field，简称HE-SIG-A)、高效率信令B字段(High Efficiency Signal-B field，简称HE-SIG-B)、高效率短训练字段(High Efficiency Short Training field，简称HE-STF)和高效率长训练字段(High Efficiency Long Training field，简称HE-LTF)等字段。其中，数据字段用于数据传输，L-SIG、RL-SIG、HE-SIG-A和HE-SIG-B等字段分别用于传输不同类型的物理层信令，L-STF、L-LTF、HE-STF和HE-LTF等字段则主要用于接收端定时和频率同步、自动增益控制与信道估计等目的。
与802.11a、802.11n、802.11ac等基于OFDM技术的WLAN标准相同，802.11ax物理层分组的基本构成单位为OFDM符号，每个OFDM符号包含一定长度的循环前缀(Cyclic Prefix,简称CP)，例如，L-SIG和RL-SIG均包含一个长度为4微秒的OFDM符号，其中CP的长度为0.8微秒。如图10，发射端在将一定长度的信息比特经过信道编码、交织、调制(即星座映射)等操作之后，通过快速傅立叶反变换(Inverse Fast Fourier transform，简称IFFT)变换到时域，然后添加CP形成OFDM符号；接收端则对收到的每个OFDM符号先去除CP，然后通过快速傅立叶变换(Fast Fourier transform，简称FFT)变换到频域，在经过信道均衡、解调、解交织和信道解码等处理后，获得所传输的信息比特。现有WLAN中定义了一套调制编码方案 (Modulation Coding Scheme，简称MCS)，以适应不同信号噪声功率比(Signal to Noise Ratio，简称SNR)下的传输需求，其中，SNR较低时采用较低阶的MCS，SNR较高时则采用较高阶的MCS，图3示出了现有WLAN中较低阶的MCS列表。
MCS序号 调制方式 编码速率
0 BPSK 1/2
1 QPSK 1/2
2 QPSK 3/4
3 16QAM 1/2
4 16QAM 3/4
表1现有WLAN中的较低阶MCS
在802.11ax系统中，基于物理层信令的可靠传输和不同协议版本WLAN物理层分组的自动识别等目的，L-SIG、RL-SIG和HE-SIG-A均采用MCS0，即二进制相移键控(Binary Phase Shift Keying，简称BPSK)调制和编码速率为1/2的卷积编码。HE-SIG-B主要用于传输被调度用户的调度控制信息，如在该物理层分组中进行数据传输的各STA的标识、传输所述各STA的数据所使用的信道资源(例如频域的子载波资源)、空间流数与相应空间流标识、以及传输相应空间流所使用的编码调制方案等信息，典型地，在SNR较低时HE-SIG-B可以采用MCS0进行传输，在SNR较高时HE-SIG-B可以采用MCS1即正交相移键控(Quadrature Phase Shift Keying，简称QPSK)调制和编码速率为1/2的卷积编码，或者MCS2即QPSK调制和编码速率为3/4的卷积编码进行传输。同时，当SNR较低时，数据字段也采用MCS0、MCS1、MCS2等较低阶的编码调制方案等进行传输。
众所周知，无线信号的多径传播造成频域信道的衰落，即不同子载波上的信道系数均不相同，特别在室外应用场景中，多径时延扩展较大，频域信道系数在不同子载波上变化剧烈。但是，现有的编码调制方案并不能有效克服频域信道衰落造成的影响，因此传输性能较差。为此，本发明提出了一种WLAN系统中低阶MCS方案的改进方案，能有效克服频域信道衰落造成的影响，相同的信道资源和传输速率下可以获得更高的传输性能，即相同SNR下分组错误率(Packet Error Rate，简称PER)更小。
图3(a)所示为发射端OFDM信号产生过程。首先P个信息比特经过编 码速率为r的信道编码器后，得到K个已编码比特aK-1,…,a1,a0，其中K＝P/r，经过深度为K比特的交织器1交织后，得到K个比特bK-1,…,b1,b0，经过重复得到两组相同的比特序列，其中一组经过深度为K比特的交织器2交织后得到K个比特b′K-1,…,b′1,b′0，然后原比特序列bK-1,…,b1,b0和该交织后的比特序列b′K-1,…,b′1,b′0一起进行较高阶的调制得到L个调制符号，其中每个较高阶的调制符号传输的比特数为2n，因此L＝(2K)/(2n)＝K/n，这L个调制符号分别对应L个子载波，经IFFT并添加CP后形成OFDM信号。其中，交织器1即为现有MCS方案中图2所示交织器，交织器2典型地可以采用比特反序的方式简单实现，即将原比特序列前后顺序反转，即有b′K-1,…,b′1,b′0＝b0,b1,…,bK-1。
可以看到，相比编码速率为r、每个调制符号所传输的比特数为n的现有MCS，尽管图3所示的实施例中因为比特重复使得总的比特数增加了一倍，但是由于所采用的较高阶的调制符号所传输的比特数为2n，因此总的调制符号数(L＝K/n)不变，因此所使用的信道资源(OFDM系统中即为子载波数)与现有MCS相同。具体地，若现有MCS采用BPSK调制，本发明采用QPSK调制，即将bkb′k(k＝0,1,…,K-1)映射为一个QPSK星座点；若现有MCS采用QPSK调制，则本发明采用星座点数为16的正交幅度调制(16-Quadrature Amplitude Modulation，简称16QAM)，即将
Figure PCTCN2015079865-appb-000001
映射为一个16QAM星座点。这样，对于MCS0，本发明实施方案1采用QPSK调制，而对于MCS1和MCS2，本发明实施方案1则采用16QAM调制。
图3(b)所示的实施例为接收端对接收的OFDM信号的处理过程。与现有技术相同，接收的OFDM信号首先经过去除CP、FFT和信道均衡等处理，然后经该较高阶调制的解调得到两组软比特序列，分别与发射端调制前的原比特序列和经交织器2交织后的比特序列相对应，其中，所述软比特通常用对数似然比(Log-likelihood ratio，简称LLR)来表示，与发射端调制前经交织器2交织后的比特序列对应的软比特序列经过解交织器2进行解交织后，与发射端调制前的原比特序列对应的软比特序列逐一进行合并，对合并后的软比特序列的处理与现有技术相同，即经解交织器1进行解交织后经过信道解码处理得到所传输的信息比特。其中，解交织器1即为现有MCS方案中图2所示解交织器，交织器2若采用比特反序的方式实现，则解交织器2同样为比特反序操作。
因此，本发明实施例，能够降低频域信道衰落造成的影响，在相同的信道资源和传输速率下可以获得更高的传输性能，能够使得相同SNR下分组错误率(Packet Error Rate，简称PER)更小。
图4所示为本发明实施方案的OFDM信号收发过程，在发射端，该方案与图3所示实施方案的区别在于直接利用已有的交织器1(即现有MCS方案中的交织器)而不增加交织器2，具体地，信道编码后K个已编码比特aK-1,…,a1,a0直接重复得到两组相同的比特序列，其中一组经过交织器1交织后得到K个比特bK-1,…,b1,b0，然后原比特序列aK-1,…,a1,a0和该交织后的比特序列bK-1,…,b1,b0一起进行较高阶的调制得到L个调制符号。相应地，在接收端也直接利用已有的解交织器1(即现有MCS方案中图2所示解交织器)而不增加解交织器2，具体地，经该较高阶调制的解调得到的两组软比特序列，其中与发射端调制前经交织器1交织后的比特序列对应的软比特序列经过解交织器1进行解交织后，与发射端调制前的原比特序列对应的软比特序列逐一进行合并，合并后的软比特序列后直接经过信道解码处理得到所传输的信息比特。
因此，本发明实施例，能够降低频域信道衰落造成的影响，在相同的信道资源和传输速率下可以获得更高的传输性能，能够使得相同SNR下分组错误率(Packet Error Rate，简称PER)更小。
图5所示为本发明实施方案的OFDM信号收发过程。在发射端，信道编码后的K个已编码比特aK-1,…,a1,a0分别重复，得到一组包含2K个比特的比特序列，其中，重复比特与原比特的排列方式不限定，例如，该长度2K的比特序列可以按aK-1aK-1,…,a1a1,a0a0排列，也可以按aK-1,…,a1,a0,aK-1,…,a1,a0排列，该长度2K的比特序列再经过深度为2K比特的交织器3交织后得到2K个比特，然后，经较高阶的调制得到L个调制符号，其中每个较高阶的调制符号传输的比特数为2n，因此L＝(2K)/(2n)＝K/n，这L个调制符号分别对应L个子载波，经IFFT并添加CP后形成OFDM信号。
同样地，相比编码速率为r、每个调制符号所传输的比特数为n的现有MCS，尽管图5所示的本发明实施方案中信道编码后比特重复使得总的比特数增加了一倍，但是由于所采用的较高阶的调制符号所传输的比特数为2n，因此总的调制符号数(L＝K/n)不变，因此所使用的信道资源(OFDM系统中即为子载波数)与现有MCS相同。具体地，若现有MCS采用BPSK调制， 则本发明采用QPSK调制，若现有MCS采用QPSK调制，则本发明采用16QAM调制。因此对于MCS0，本发明实施方案3采用QPSK调制，而对于MCS1和MCS2，图5所示的实施例则采用16QAM调制。
如图5(b)所示，在接收端，接收的OFDM信号经去除CP、FFT和信道均衡等处理，然后进行所述较高阶调制相应的解调处理得到软比特序列，再经过解交织器3的解交织后，按照与发射端相应的排列方式，分离出两组软比特序列，分别与发射端信道编码后的原比特序列和重复比特构成的序列相对应，然后将该两组软比特序列逐一进行合并，合并后的软比特序列后最后经过信道解码处理得到所传输的信息比特。
在图5所示的实施方案，交织器3和解交织器3仍可以沿用现有MCS方案中示交织器和解交织器，但使用的是编码速率同样为r、但每个调制符号所传输的比特数为2n的MCS方案中所使用的交织器和解交织器，例如，对于MCS0、MCS1和MCS2，本发明实施方案3可以分别采用MCS1、MCS3、MCS4的交织器和解交织器。
因此，本发明实施例，能够降低频域信道衰落造成的影响，在相同的信道资源和传输速率下可以获得更高的传输性能，能够使得相同SNR下分组错误率(Packet Error Rate，简称PER)更小。
图6是本发明实施例的装置的示意性框图。该装置600包括：
获取模块610，所述获取模块用于获取第一比特序列，所述第一比特序列包含K个比特；
复制模块620，所述复制模块用于复制所述K个比特，得到2K个比特；
交织模块630，所述交织模块用于对所述2K个比特中的至少K个比特构成的比特序列进行交织处理，所述至少K个比特包括所述第一比特序列中的K个比特；
调制模块640，所述调制模块用于对所述交织处理后的所述至少K个比特和所述2K个比特中的其它比特进行调制，得到L＝K/n个调制符号，每个所述调制符号传输的比特数为2n；
映射模块650，所述映射模块用于将所述L个调制符号分别与L个子载波映射，生成正交频分复用OFDM符号。
因此，本发明实施例，能够降低频域信道衰落造成的影响，在相同的信道资源和传输速率下可以获得更高的传输性能，能够使得相同SNR下分组 错误率(Packet Error Rate，简称PER)更小。
可选地，所述调制模块640用于对所述第一比特序列进行交织处理；所述调制模块具体用于对所述交织处理后的第一比特序列的所述K个比特和所述2K个比特中的其它K个比特进行调制。
可选地，所述调制模块640用于对所述第二比特序列进行交织处理；所述调制模块具体用于对所述交织处理后的第二比特序列的所述2K个比特进行调制。
可选地，所述装置还包括编码模块，所述编码模块用于根据待发送的M个信息比特经信道编码得所述第一比特序列包含的所述K个比特，其中，所述信道编码的编码速率为M/K。
可选地，所述交织模块630具体用于：对待发送的第三比特序列进行交织处理得到所述第一比特序列，所述第三比特序列包含K个比特，所述第三比特序列包含的K个比特为待发送的M个信息比特经信道编码得到的比特，其中，所述信道编码的编码速率为M/K。
可选地，所述交织模块630具体用于将所述第一比特序列或第二比特序列进行反序排列。
因此，本发明实施例，能够降低频域信道衰落造成的影响，在相同的信道资源和传输速率下可以获得更高的传输性能，能够使得相同SNR下分组错误率(Packet Error Rate，简称PER)更小。
图7是本发明另一实施例的装置的示意性框图。该装置700包括：
一种通信装置，其特征在于，包括：
获取模块710，所述获取模块710用于获取接收到的OFDM符号的L个子载波上的信号，其中，所述L个子载波上的信号分别L个调制符号对应，每个所述调制符号传输的比特数为2n，所述L个调制符号传输2K个比特，所述2K个比特中的K个比特分别与其余K个比特相同，L＝K/n；
解调模块720，所述解调模块720用于解调所述L个子载波上信号，得到包括2K个软比特的第一软比特序列；
处理模块730，所述处理模块730用于根据第一软比特序列得到第二软比特序列和第三软比特序列，所述第二软比特序列和所述第三软比特序列分别包含K个软比特；
所述处理模块730还用于将所述第二软比特序列和所述第三软比特序列 进行合并，得到第四软比特序列；
解码模块740，所述解码模块用于对所述第四软比特序列进行信道解码获得M个信息比特，所述信道解码所对应的信道编码的编码速率为M/K。
可选地，所述处理模块730具体用于：对所述第一软比特序列中的K个软比特构成的软比特序列进行解交织处理得到所述第三软比特序列，所述K个软比特对应所述L个调制符号传输的2K个比特中的所述其余K个比特。
可选地，所述处理模块730具体用于：对所述第一软比特序列进行解交织处理；分解所述解交织处理后的第一软比特序列得到所述第二软比特序列和第三软比特序列。
可选地，所述处理模块740具体用于：对所述第四软比特序列进行解交织处理。
因此，本发明实施例，能够降低频域信道衰落造成的影响，在相同的信道资源和传输速率下可以获得更高的传输性能，能够使得相同SNR下分组错误率(Packet Error Rate，简称PER)更小。
如图8所示，本发明实施例还提供了一种通信装置10，该通信装置10包括处理器11、存储器12、总线系统13和接收器14。其中，处理器11、存储器12和接收器14通过总线系统13相连，该存储器12用于存储指令，该处理器11用于执行该存储器12存储的指令，并控制该接收器14接收信息。其中，该接收器14用于：所述获取模块用于获取第一比特序列，所述第一比特序列包含K个比特；处理器11用于：所述复制模块用于复制所述K个比特，得到2K个比特；对所述2K个比特中的至少K个比特构成的比特序列进行交织处理，所述至少K个比特包括所述第一比特序列中的K个比特；对所述交织处理后的所述至少K个比特和所述2K个比特中的其它比特进行调制，得到L＝K/n个调制符号，每个所述调制符号传输的比特数为2n；用于将所述L个调制符号分别与L个子载波映射，生成正交频分复用OFDM符号。
因此，本发明实施例的移动性管理网元，通过获取待传输下行数据的分类属性，并根据该待传输下行数据的分类属性，确定是否向接入网设备发送寻呼消息，以确定是否建立接入网设备与服务网关之间的承载以及接入网设备与用户设备之间的承载，由此能够在下行数据的传输过程中，对接入网侧承载的建立进行控制，避免盲目建立接入网侧承载，从而能够节省信令开销， 并能够缓解数据传输拥塞。
应理解，在本发明实施例中，该处理器11可以是中央处理单元(Central Processing Unit，简称为“CPU”)，该处理器11还可以是其他通用处理器、数字信号处理器(DSP)、专用集成电路(ASIC)、现成可编程门阵列(FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
该存储器12可以包括只读存储器和随机存取存储器，并向处理器11提供指令和数据。存储器12的一部分还可以包括非易失性随机存取存储器。例如，存储器820还可以存储设备类型的信息。
该总线系统13除包括数据总线之外，还可以包括电源总线、控制总线和状态信号总线等。但是为了清楚说明起见，在图中将各种总线都标为总线系统13。
在实现过程中，上述方法的各步骤可以通过处理器11中的硬件的集成逻辑电路或者软件形式的指令完成。结合本发明实施例所公开的方法的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器12，处理器11读取存储器820中的信息，结合其硬件完成上述方法的步骤。为避免重复，这里不再详细描述。
可选地，作为一个实施例，该处理器11还用于：用于对所述第一比特序列进行交织处理；所述调制模块具体用于对所述交织处理后的第一比特序列的所述K个比特和所述2K个比特中的其它K个比特进行调制。
可选地，作为一个实施例，该处理器11还用于：对所述第二比特序列进行交织处理；所述调制模块具体用于对所述交织处理后的第二比特序列的所述2K个比特进行调制。
可选地，作为一个实施例，该处理器11还用于：根据待发送的M个信息比特经信道编码得所述第一比特序列包含的所述K个比特，其中，所述信道编码的编码速率为M/K。
可选地，作为一个实施例，该处理器11还用于：对待发送的第三比特序列进行交织处理得到所述第一比特序列，所述第三比特序列包含K个比特，所述第三比特序列包含的K个比特为待发送的M个信息比特经信道编 码得到的比特，其中，所述信道编码的编码速率为M/K。
可选地，作为一个实施例，该处理器11还用于：将所述第一比特序列或第二比特序列进行反序排列。
应理解，根据本发明实施例的移动性管理网元10可对应于本发明实施例的通信方法的执行主体，并且移动性管理网元10中的各个模块的上述和其它操作和/或功能分别为了实现图1至图5中的各个方法，为了简洁，在此不再赘述。
因此，本发明实施例，能够降低频域信道衰落造成的影响，在相同的信道资源和传输速率下可以获得更高的传输性能，能够使得相同SNR下分组错误率(Packet Error Rate，简称PER)更小。
如图9所示，本发明实施例还提供了一种接入网设备20，该网络设备20包括处理器21、存储器22、总线系统23和接收器24。其中，处理器21、存储器22和接收器24通过总线系统23相连，该存储器22用于存储指令，该处理器21用于执行该存储器22存储的指令，并控制接收器24接收信息。其中，该接收器24用于：用于获取接收到的OFDM符号的L个子载波上的信号，其中，所述L个子载波上的信号分别L个调制符号对应，每个所述调制符号传输的比特数为2n，所述L个调制符号传输2K个比特，所述2K个比特中的K个比特分别与其余K个比特相同，L＝K/n；该处理器21用于：解调所述L个子载波上信号，得到包括2K个软比特的第一软比特序列；根据第一软比特序列得到第二软比特序列和第三软比特序列，所述第二软比特序列和所述第三软比特序列分别包含K个软比特；将所述第二软比特序列和所述第三软比特序列进行合并，得到第四软比特序列；对所述第四软比特序列进行信道解码获得M个信息比特，所述信道解码所对应的信道编码的编码速率为M/K。
因此，本发明实施例，能够降低频域信道衰落造成的影响，在相同的信道资源和传输速率下可以获得更高的传输性能，能够使得相同SNR下分组错误率(Packet Error Rate，简称PER)更小。
应理解，在本发明实施例中，该处理器21可以是中央处理单元(Central Processing Unit，简称为“CPU”)，该处理器21还可以是其他通用处理器、数字信号处理器(DSP)、专用集成电路(ASIC)、现成可编程门阵列(FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。 通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
该存储器22可以包括只读存储器和随机存取存储器，并向处理器21提供指令和数据。存储器22的一部分还可以包括非易失性随机存取存储器。例如，存储器22还可以存储设备类型的信息。
该总线系统23除包括数据总线之外，还可以包括电源总线、控制总线和状态信号总线等。但是为了清楚说明起见，在图中将各种总线都标为总线系统23。
在实现过程中，上述方法的各步骤可以通过处理器21中的硬件的集成逻辑电路或者软件形式的指令完成。结合本发明实施例所公开的方法的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器22，处理器21读取存储器22中的信息，结合其硬件完成上述方法的步骤。为避免重复，这里不再详细描述。
可选地，作为一个实施例，该处理器21用于：对所述第一软比特序列中的K个软比特构成的软比特序列进行解交织处理得到所述第三软比特序列，所述K个软比特对应所述L个调制符号传输的2K个比特中的所述其余K个比特。
应理解，根据本发明实施例的接入网设备20可对应于本发明实施例的通信的方法的执行主体，并可以对应于根据本发明实施例的接入网设备700，并且接入网设备700中的各个模块的上述和其它操作和/或功能分别为了实现图1和图5中的各个方法的相应流程，为了简洁，在此不再赘述。
因此，本发明实施例，能够降低频域信道衰落造成的影响，在相同的信道资源和传输速率下可以获得更高的传输性能，能够使得相同SNR下分组错误率(Packet Error Rate，简称PER)更小。
应理解，在本发明实施例中，该处理器31可以是中央处理单元(Central Processing Unit，简称为“CPU”)，该处理器31还可以是其他通用处理器、数字信号处理器(DSP)、专用集成电路(ASIC)、现成可编程门阵列(FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
该存储器32可以包括只读存储器和随机存取存储器，并向处理器31提 供指令和数据。存储器32的一部分还可以包括非易失性随机存取存储器。例如，存储器32还可以存储设备类型的信息。
该总线系统33除包括数据总线之外，还可以包括电源总线、控制总线和状态信号总线等。但是为了清楚说明起见，在图中将各种总线都标为总线系统33。
在实现过程中，上述方法的各步骤可以通过处理器31中的硬件的集成逻辑电路或者软件形式的指令完成。结合本发明实施例所公开的方法的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器32，处理器31读取存储器32中的信息，结合其硬件完成上述方法的步骤。为避免重复，这里不再详细描述。
可选地，作为一个实施例，该处理器31根据该第二待传输下行数据的分类属性和该下行数据控制策略，确定是否向该移动性管理网元发送下行数据通知消息，包括：
在确定该第二待传输下行数据的分类属性属于该下行数据控制策略指示的允许传输的下行数据的分类属性集合时，或在确定该第二待传输下行数据的分类属性不属于该下行数据控制策略指示的禁止传输的下行数据的分类属性集合时，确定向该移动性管理网元发送该下行数据通知消息。
可选地，作为一个实施例，该第二待传输下行数据的分类属性包括下列信息中的至少一种信息：该第二待传输下行数据的业务类型信息、该第二待传输下行数据的优先级信息和该第二待传输下行数据的服务质量信息。
应理解，根据本发明实施例的服务网关30可对应于本发明实施例的用于传输下行数据的方法的执行主体，并可以对应于根据本发明实施例的服务网关900，并且服务网关30中的各个模块的上述和其它操作和/或功能分别为了实现图1至图5中的各个方法的相应流程，为了简洁，在此不再赘述。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其他的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其他的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本发明各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应所述以权利要求的保护范围为准。
可选地，对步骤130中2K个比特中的至少K个比特构成的比特序列进 行交织处理，还包括以下方法：
步骤1：将所述至少K个比特构成的比特序列分成两个相同比特数目的子序列。
步骤2、交换两个子序列的位置，得到交织后的至少K个比特构成的比特序列。
举例说明，所述至少K个比特序列中，K＝6，该序列为101110。步骤1将序列分为子序列101和子序列110，步骤2中交换两个子序列的位置，得到110101。

Claims (20)

  1. 一种通信的方法，其特征在于，所述方法包括：
    获取第一比特序列，所述第一比特序列包含K个比特；
    复制所述K个比特，得到2K个比特；
    对所述2K个比特中的至少K个比特构成的比特序列进行交织处理，所述至少K个比特包括所述第一比特序列中的K个比特；
    对所述交织处理后的所述至少K个比特和所述2K个比特中的其它比特进行调制，得到L＝K/n个调制符号，每个所述调制符号传输的比特数为2n；
    将所述L个调制符号分别与L个子载波映射，生成正交频分复用OFDM符号。
  2. 根据权利要求1所述的方法，其特征在于，所述对所述2K个比特中的至少K个比特构成的比特序列进行交织处理，包括：
    对所述第一比特序列进行交织处理；
    所述对所述交织处理后的所述至少K个比特和所述2K个比特中的其它比特进行调制，包括：
    对所述交织处理后的第一比特序列的所述K个比特和所述2K个比特中的其它K个比特进行调制。
  3. 根据权利要求1所述的方法，其特征在于，所述2K个比特构成第二比特序列，所述对所述2K个比特中的至少K个比特构成的比特序列进行交织处理，包括：
    对所述第二比特序列进行交织处理；
    所述对所述交织处理后的所述至少K个比特和所述2K个比特中的其它比特进行调制，包括：
    对所述交织处理后的第二比特序列的所述2K个比特进行调制。
  4. 根据权利要求1至3中任一项所述的方法，其特征在于，所述方法还包括：
    根据待发送的M个信息比特经信道编码得所述第一比特序列包含的所述K个比特，其中，所述信道编码的编码速率为M/K。
  5. 根据权利要求1至4中任一项所述的方法，其特征在于，所述方法还包括：
    对待发送的第三比特序列进行交织处理得到所述第一比特序列，所述第三比特序列包含K个比特，所述第三比特序列包含的K个比特为待发送的M个信息比特经信道编码得到的比特，其中，所述信道编码的编码速率为M/K。
  6. 根据权利要求1至5中任一项所述的方法，其特征在于，所述交织处理包括：
    将所述第一比特序列或第二比特序列进行反序排列。
  7. 一种通信的方法，其特征在于，所述方法包括：
    获取接收到的OFDM符号的L个子载波上的信号，其中，所述L个子载波上的信号分别与L个调制符号对应，每个所述调制符号传输的比特数为2n，所述L个调制符号传输2K个比特，所述2K个比特中的K个比特分别与其余K个比特相同，L＝K/n；
    解调所述L个子载波上信号，得到包括2K个软比特的第一软比特序列；
    根据第一软比特序列得到第二软比特序列和第三软比特序列，所述第二软比特序列和所述第三软比特序列分别包含K个软比特；
    将所述第二软比特序列和所述第三软比特序列进行合并，得到第四软比特序列；
    对所述第四软比特序列进行信道解码获得M个信息比特，所述信道解码所对应的信道编码的编码速率为M/K。
  8. 根据权利要求7所述的方法，其特征在于，所述根据第一软比特序列得到第二软比特序列和第三软比特序列，包括：
    对所述第一软比特序列中的K个软比特构成的软比特序列进行解交织处理得到所述第三软比特序列，所述K个软比特对应所述L个调制符号传输的2K个比特中的所述其余K个比特。
  9. 根据权利要求6所述的方法，其特征在于，所述根据第一软比特序列得到第二软比特序列和第三软比特序列，包括：
    对所述第一软比特序列进行解交织处理；
    分解所述解交织处理后的第一软比特序列得到所述第二软比特序列和第三软比特序列。
  10. 根据权利要求6或7所述的方法，其特征在于，所述方法还包括：
    对所述第四软比特序列进行解交织处理。
  11. 一种通信装置，其特征在于，包括：
    获取模块，所述获取模块用于获取第一比特序列，所述第一比特序列包含K个比特；
    复制模块，所述复制模块用于复制所述K个比特，得到2K个比特；
    交织模块，所述交织模块用于对所述2K个比特中的至少K个比特构成的比特序列进行交织处理，所述至少K个比特包括所述第一比特序列中的K个比特；
    调制模块，所述调制模块用于对所述交织处理后的所述至少K个比特和所述2K个比特中的其它比特进行调制，得到L＝K/n个调制符号，每个所述调制符号传输的比特数为2n；
    映射模块，所述映射模块用于将所述L个调制符号分别与L个子载波映射，生成正交频分复用OFDM符号。
  12. 根据权利要求11所述的装置，其特征在于，所述交织模块用于对所述第一比特序列进行交织处理；所述调制模块具体用于对所述交织处理后的第一比特序列的所述K个比特和所述2K个比特中的其它K个比特进行调制。
  13. 根据权利要求11所述的装置，其特征在于，所述交织模块用于对所述第二比特序列进行交织处理；所述调制模块具体用于对所述交织处理后的第二比特序列的所述2K个比特进行调制。
  14. 根据权利要求11至13中任一项所述的装置，其特征在于，所述装置还包括编码模块，所述编码模块用于根据待发送的M个信息比特经信道编码得所述第一比特序列包含的所述K个比特，其中，所述信道编码的编码速率为M/K。
  15. 根据权利要求11至14中任一项所述的装置，其特征在于，所述交织模块具体用于：对待发送的第三比特序列进行交织处理得到所述第一比特序列，所述第三比特序列包含K个比特，所述第三比特序列包含的K个比特为待发送的M个信息比特经信道编码得到的比特，其中，所述信道编码的编码速率为M/K。
  16. 根据权利要求11至15中任一项所述的装置，其特征在于，所述交织模块具体用于将所述第一比特序列或第二比特序列进行反序排列。
  17. 一种通信装置，其特征在于，包括：
    获取模块，所述获取模块用于获取接收到的OFDM符号的L个子载波上的信号，其中，所述L个子载波上的信号分别L个调制符号对应，每个所述调制符号传输的比特数为2n，所述L个调制符号传输2K个比特，所述2K个比特中的K个比特分别与其余K个比特相同，L＝K/n；
    解调模块，所述解调模块用于解调所述L个子载波上信号，得到包括2K个软比特的第一软比特序列；
    处理模块，所述处理模块用于根据第一软比特序列得到第二软比特序列和第三软比特序列，所述第二软比特序列和所述第三软比特序列分别包含K个软比特；
    所述处理模块还用于将所述第二软比特序列和所述第三软比特序列进行合并，得到第四软比特序列；
    解码模块，所述解码模块用于对所述第四软比特序列进行信道解码获得M个信息比特，所述信道解码所对应的信道编码的编码速率为M/K。
  18. 根据权利要求17所述的装置，其特征在于，所述处理模块具体用于：
    对所述第一软比特序列中的K个软比特构成的软比特序列进行解交织处理得到所述第三软比特序列，所述K个软比特对应所述L个调制符号传输的2K个比特中的所述其余K个比特。
  19. 根据权利要求17所述的方法，其特征在于，所述处理模块具体用于：
    对所述第一软比特序列进行解交织处理；
    分解所述解交织处理后的第一软比特序列得到所述第二软比特序列和第三软比特序列。
  20. 根据权利要求17至19任一项所述的方法，其特征在于，所述处理模块具体用于：
    对所述第四软比特序列进行解交织处理。
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CN1516935A (zh) * 2002-02-28 2004-07-28 ���µ�����ҵ��ʽ���� 无线电通信方法、无线电发射装置和无线电接收装置
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