WO2021254052A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2021254052A1
WO2021254052A1 PCT/CN2021/093671 CN2021093671W WO2021254052A1 WO 2021254052 A1 WO2021254052 A1 WO 2021254052A1 CN 2021093671 W CN2021093671 W CN 2021093671W WO 2021254052 A1 WO2021254052 A1 WO 2021254052A1
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WIPO (PCT)
Prior art keywords
sub
pixel
distance
display
line
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Ceased
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PCT/CN2021/093671
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English (en)
French (fr)
Chinese (zh)
Inventor
陈玉琼
刘晓那
王孟杰
张瑞
孙玉家
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Application filed by BOE Technology Group Co Ltd, Beijing BOE Display Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to EP21826654.2A priority Critical patent/EP4043950B1/en
Priority to US17/763,657 priority patent/US12313928B2/en
Priority to KR1020227014494A priority patent/KR102875593B1/ko
Priority to JP2022525422A priority patent/JP7739277B2/ja
Publication of WO2021254052A1 publication Critical patent/WO2021254052A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
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    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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Definitions

  • the present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display panel and a display device.
  • Liquid crystal display (Liquid Crystal Display, LCD for short) has the characteristics of small size, low power consumption, and no radiation, and has been developed rapidly.
  • the liquid crystal display panel includes a thin film transistor array (TFT) substrate of a cell (CELL) and a color filter (CF) substrate, and liquid crystal (Liquid Crystal, LC) molecules are arranged on the array substrate and the color film Between the substrates, the common electrode and the pixel electrode are controlled to form an electric field that drives the deflection of the liquid crystal to achieve grayscale display.
  • TFT thin film transistor array
  • CF color filter
  • the present disclosure provides a display panel, including a first substrate and a second substrate that are arranged oppositely;
  • the first substrate includes M*N sub-pixels defined by the intersection of M gate lines and N pairs of data lines, each pair of data lines includes a first data line and a second data line, and the sub-pixels include thin film transistors and pixels. Electrodes; in the m-th display row, the thin film transistors of all sub-pixels are connected to the m-th gate line; in the n-th display column, the thin-film transistors of the sub-pixels in the odd-numbered display row are connected to the first data line of the n-th pair of data lines, The thin film transistor of the sub-pixel in the even-numbered display row is connected to the second data line of the n-th pair of data lines; or, in the n-th display column, the thin-film transistor of the sub-pixel in the even-numbered display row and the first data line of the n-th pair of data lines Connected, the thin film transistors of the sub-pixels in the odd-numbered display rows are connected to the second data lines of the n-th pair of data lines
  • the second substrate includes M*N filter units corresponding to the sub-pixels in a one-to-one manner, a black matrix is arranged between adjacent filter units, and the black matrix includes shields located between adjacent display rows. Rows and occluded columns between adjacent display columns;
  • the shielding row located between the kth display row and the k+1th display row has a first width
  • the shielding row located between the k+1th display row and the k+2th display row It has a second width, and the first width is not equal to the second width.
  • the multiple sub-pixels in the m-th display row include a first sub-pixel, a second sub-pixel, and a third sub-pixel that are periodically arranged; they are located in the k-th display row and the k+1-th display row.
  • the occlusion row includes an upper edge located in the k-th display row and a lower edge located in the k+1-th display row;
  • the upper edge includes the first sub-pixel located in the k-th display row
  • the occlusion line located between the k+1th display line and the k+2th display line
  • the occlusion line includes an upper edge in the k+1th display line and a lower edge in the k+2th display line
  • the upper edge includes the fourth upper edge located in the first sub-pixel of the k+1 display row, the fifth
  • the sixth upper edge in the three sub-pixels, the lower edge includes the fourth lower edge in the first sub-pixel of the k+2 display row, and the fifth edge in the second sub-pixel of the k+2 display row.
  • the first width is not equal to the second width includes any one or more of the following: the first distance is less than the fourth distance, the second distance is less than the fifth distance, and the third distance is greater than the sixth distance.
  • the difference between the first distance and the fourth distance is 10 ⁇ m to 20 ⁇ m
  • the difference between the second distance and the fifth distance is 10 ⁇ m to 20 ⁇ m
  • the difference between the third distance and the sixth distance The difference is 1 ⁇ m to 5 ⁇ m.
  • the third distance is greater than the first distance, and the third distance is greater than the second distance.
  • the difference between the third distance and the first distance is 10 ⁇ m to 35 ⁇ m
  • the difference between the third distance and the second distance is 10 ⁇ m to 35 ⁇ m
  • the sixth distance is greater than the fourth distance, and the sixth distance is greater than the fifth distance.
  • the difference between the sixth distance and the fourth distance is 10 ⁇ m-20 ⁇ m
  • the difference between the sixth distance and the fifth distance is 10 ⁇ m-20 ⁇ m
  • the shielding row located in the first sub-pixel of the k-th display row is provided with first protrusions, and the first protrusions are provided on the first upper edge along the distance away from the The first lower edge extends in the direction;
  • the shielding row located in the second sub-pixel of the k-th display row is provided with second protrusions, the second protrusions are provided on the second upper edge, and the second protrusions It extends along a direction away from the second lower edge.
  • the first bump is located on the side where the thin film transistor is provided in the first sub-pixel, and the second bump is located on the second sub-pixel. The side where the thin film transistor is arranged in the pixel.
  • the shape of the first protrusion and the second protrusion includes a rectangle or a trapezoid.
  • the first protrusion in the extension direction of the data line, includes a first protrusion upper edge, the second protrusion includes a second protrusion upper edge, and the first protrusion
  • the distance between the upper edge and the first upper edge is 10 ⁇ m-20 ⁇ m, and the distance between the upper edge of the second protrusion and the second upper edge is 10 ⁇ m-20 ⁇ m.
  • the distance between the third upper edge and the first upper edge is greater than the first protrusion upper edge and the first upper edge
  • the distance between the third upper edge and the second upper edge is greater than the distance between the second protrusion upper edge and the second upper edge.
  • the first lower edge, the second lower edge, and the third lower edge are all straight edges extending along the extension direction of the grid line;
  • the fourth upper edge, the fifth upper edge Both the edge and the sixth upper edge are straight edges extending along the extension direction of the grid line;
  • the fourth lower edge, the fifth lower edge and the sixth lower edge are all provided with bumps, and the bumps are respectively It is arranged at the positions of the fourth lower edge, the fifth lower edge and the sixth lower edge adjacent to the shielding columns on both sides.
  • the bump includes a right-angled triangle
  • the first right-angled side of the right-angled triangle is respectively disposed on the fourth lower edge, the fifth lower edge, and the sixth lower edge
  • the right-angled triangle The second right-angled edges of are respectively arranged on the shielding rows on both sides of the fourth lower edge, the fifth lower edge and the sixth lower edge.
  • the first substrate includes a first conductive layer, a first metal layer, a first insulating layer, a semiconductor layer, a second metal layer, a second insulating layer, and a second conductive layer that are stacked;
  • the first conductive layer includes a common electrode provided in each sub-pixel;
  • the first metal layer includes a gate line and a common electrode line, a gate electrode provided in each sub-pixel, and a gate electrode provided in the third sub-pixel
  • the gate line is connected to the gate electrode in each sub-pixel, the common electrode line is connected to the common electrode in each sub-pixel, and the first connection electrode is connected to the common electrode of the third sub-pixel.
  • the semiconductor layer includes an active layer provided in each sub-pixel;
  • the second metal layer includes a first data line, a second data line, and a source electrode and a drain electrode provided in each sub-pixel.
  • the source electrode of each sub-pixel is connected to the first data line
  • the source electrode of each sub-pixel is connected to the second data line
  • the source electrode is connected to the drain electrode.
  • a conductive channel is formed therebetween;
  • the second conductive layer includes a pixel electrode arranged in each sub-pixel and a second connecting electrode arranged in the third sub-pixel, and the pixel electrode is connected to the sub-pixel through the via hole.
  • the second connection electrode is connected to the first connection electrode and the common electrode line through the via hole, respectively.
  • the common electrodes in the first sub-pixel, the second sub-pixel, and the third sub-pixel are provided with first common electrode bumps, and the first common electrode of each sub-pixel is The electrode protrusion is located on the side of the common electrode adjacent to the k-1th display line; the common electrode in the third sub-pixel is provided with a second common electrode protrusion, and the second common electrode protrusion is located on the common electrode Adjacent to one side of the next display row, the first connection electrode is disposed on the second common electrode bump.
  • the common electrode line in the first interval area between adjacent common electrode lines, has a third width, and in the second interval area between adjacent first interval areas, the common The electrode line has a fourth width, the third width is smaller than the fourth width; in the first interval area, the gate line has a fifth width, and in the second interval area, the gate line has a Six widths, the fifth width is smaller than the sixth width.
  • the gate electrodes in the first sub-pixel, the second sub-pixel, and the third sub-pixel are all rectangular, and the long edges of the gate electrodes in the first sub-pixel and the second sub-pixel are Extending in the display row direction, the long side of the gate electrode in the third sub-pixel extends in the display column direction.
  • one end of the second connection electrode is connected to the first connection electrode through a via hole opened in the first insulating layer and the second insulating layer, and the other end of the second connection electrode passes through The via holes opened on the first insulating layer and the second insulating layer are connected to the common electrode line of the next display row.
  • connection area between the pixel electrode and the drain electrode overlaps the black matrix
  • edge area of the pixel electrode overlaps the black matrix
  • the multiple filter units in the k-th display row include a first filter unit, a second filter unit, and a third filter unit that are periodically arranged, and the first filter unit Corresponding to the first sub-pixel, the second filter unit corresponds to the second sub-pixel, and the third filter unit corresponds to the third sub-pixel; the first filter unit includes a red filter unit , The second filter unit includes a green filter unit, and the third filter unit includes a blue filter unit.
  • the present disclosure provides a display device including the above-mentioned display panel.
  • FIG. 1 is a schematic structural diagram of a display panel according to an exemplary embodiment of the present disclosure
  • Fig. 2 is an equivalent circuit diagram of a first substrate according to an exemplary embodiment of the present disclosure
  • FIG. 3 is a top view of a display panel according to an exemplary embodiment of the present disclosure.
  • FIG. 4A is a schematic diagram of an exemplary embodiment of the present disclosure after a first conductive layer pattern is formed
  • Figure 4B is a cross-sectional view taken along the line A-A in Figure 4A;
  • Figure 4C is a cross-sectional view taken along the line B-B in Figure 4A;
  • 5A is a schematic diagram of an exemplary embodiment of the present disclosure after a first metal layer pattern is formed
  • Figure 5B is a cross-sectional view taken along the line A-A in Figure 5A;
  • Figure 5C is a cross-sectional view taken along the line B-B in Figure 5A;
  • 6A is a schematic diagram of an exemplary embodiment of the present disclosure after a semiconductor layer pattern is formed
  • Fig. 6B is a cross-sectional view taken along the line A-A in Fig. 6A;
  • Figure 6C is a cross-sectional view taken along the line B-B in Figure 6A;
  • FIG. 7A is a schematic diagram of an exemplary embodiment of the present disclosure after a second metal layer pattern is formed
  • Fig. 7B is a cross-sectional view taken along the line A-A in Fig. 7A;
  • Figure 7C is a cross-sectional view taken along the line B-B in Figure 7A;
  • FIG. 8A is a schematic diagram of an exemplary embodiment of the present disclosure after a second insulating layer pattern is formed;
  • Figure 8B is a cross-sectional view taken along the line A-A in Figure 8A;
  • Figure 8C is a cross-sectional view taken along the line B-B in Figure 8A;
  • FIG. 9A is a schematic diagram of an exemplary embodiment of the present disclosure after a second conductive layer pattern is formed;
  • Figure 9B is a cross-sectional view taken along the line A-A in Figure 9A;
  • Figure 9C is a cross-sectional view taken along the line B-B in Figure 9A;
  • FIG. 10A is a schematic diagram of an exemplary embodiment of the present disclosure after a black matrix pattern is formed
  • Figure 10B is a cross-sectional view taken along the line C-C in Figure 10A;
  • Figure 10C is a cross-sectional view taken along the line D-D in Figure 10A;
  • FIG. 11A is a schematic diagram of an exemplary embodiment of the present disclosure after a pattern of a light filter unit is formed
  • Figure 11B is a cross-sectional view taken along the line C-C in Figure 11A;
  • Figure 11C is a cross-sectional view taken along the line D-D in Figure 11A;
  • FIG. 12 is a schematic diagram of forming a display panel according to an exemplary embodiment of the present disclosure.
  • FIG. 13 is an equivalent circuit diagram of another first substrate according to an exemplary embodiment of the present disclosure.
  • the terms “installed”, “connected”, and “connected” should be interpreted broadly unless otherwise clearly defined and limited. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate piece, or a connection between two components.
  • installed can be a fixed connection, or a detachable connection, or an integral connection
  • it can be a mechanical connection or an electrical connection
  • it can be a direct connection, or an indirect connection through an intermediate piece, or a connection between two components.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between the drain electrode (or drain electrode terminal, drain region, or drain electrode) and the source electrode (or source electrode terminal, source region, or source electrode), and current can flow through the drain electrode and channel Area and source electrode.
  • the channel region refers to the region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may sometimes be interchanged. Therefore, in this article, the "source electrode” and the “drain electrode” can be interchanged.
  • electrical connection includes the case where constituent elements are connected together by elements having a certain electrical function.
  • An element having a certain electrical function is not particularly limited as long as it can transmit and receive electrical signals between connected constituent elements.
  • An element having a certain electrical function may be, for example, an electrode or a wiring, or a switching element such as a transistor, or other functional elements such as a resistor, inductor, or capacitor.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore, it also includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore also includes a state where an angle of 85° or more and 95° or less is included.
  • film and “layer” can be interchanged.
  • conductive layer can be replaced with “conductive film”.
  • insulating film may sometimes be replaced with an “insulating layer.”
  • a liquid crystal display device scans row by row, and a timing control circuit (T-CON) controls the sub-pixels of the display device to turn on row by row and column by row in the order from left to right and top to bottom.
  • T-CON timing control circuit
  • the length of the gate lines and data lines also increases.
  • the effective charging time of the sub-pixels is greatly shortened.
  • a pixel structure adopts a gate line double-side drive and a double data line structure, which is called 2G2D drive.
  • the thin film transistors of one display row are arranged on the right side of the first data line, and the thin film transistors of another adjacent display row are arranged on the left side of the second data line. It is found through research that the positions of thin film transistors in two adjacent display rows are different, which makes the sub-pixels of two adjacent display rows have different pixel aperture ratios. The difference in pixel aperture ratio not only leads to poor horizontal stripes, but also misalignment between the array substrate and the color film substrate. It will cause poor light leakage in the dark state.
  • Exemplary embodiments of the present disclosure provide a display panel, including a first substrate and a second substrate that are opposed to each other; the first substrate includes M*N sub-pixels defined by the intersection of M gate lines and N pairs of data lines , Each pair of data lines includes a first data line and a second data line, and the sub-pixels include thin film transistors and pixel electrodes; in the m-th display row, the thin-film transistors of all sub-pixels are connected to the m-th gate line; the n-th display In the column, the thin film transistors of the sub-pixels in the odd-numbered display rows are connected to the first data line of the n-th pair of data lines, and the thin-film transistors of the sub-pixels in the even-numbered display rows are connected to the second data line of the n-th pair of data lines; or In the n display column, the thin film transistors of the sub-pixels in the even-numbered display rows are connected to the first data line of the n-th pair of data lines, and
  • the second substrate includes M*N filter units corresponding to the sub-pixels in a one-to-one manner, a black matrix is arranged between adjacent filter units, and the black matrix includes shields located between adjacent display rows. Rows and occluded columns between adjacent display columns;
  • the shielding row located between the kth display row and the k+1th display row has a first width
  • the shielding row located between the k+1th display row and the k+2th display row It has a second width, and the first width is not equal to the second width.
  • FIG. 1 is a schematic structural diagram of a display panel according to an exemplary embodiment of the present disclosure.
  • the display panel includes a first substrate 1 and a second substrate 2 disposed opposite to each other, and a liquid crystal layer (not shown) disposed between the first substrate 1 and the second substrate 2.
  • the first substrate 1 includes at least a thin film transistor 3 and a pixel electrode 8 disposed on a first substrate 10
  • a second substrate 2 includes at least a black matrix 21 and a filter unit 22 disposed on a second substrate 20.
  • the black matrix 21 is configured to block at least the thin film transistor 3 of the first substrate 1.
  • FIG. 2 is an equivalent circuit diagram of a first substrate according to an exemplary embodiment of the present disclosure.
  • the first substrate 1 includes M gate lines 4, M common electrode lines 5, and N pairs of data lines.
  • Each pair of data lines includes a first data line 6 and a second data line 7, which extend in a horizontal direction.
  • each sub-pixel includes a thin film transistor 3, a pixel electrode 8 and a common electrode 9.
  • the source electrode of the thin film transistor 3 is connected to the first data line 6 or the second data line 7, and the drain electrode of the thin film transistor 3 is connected to the pixel electrode 8 of the sub-pixel.
  • the common electrode 9 is connected to the common electrode line 5.
  • the gate line 4 is arranged on the side adjacent to the next display row
  • the common electrode line 5 is arranged on the side adjacent to the previous display row, that is, the gate line 4 is arranged on the lower side of the sub-pixels of the current display row.
  • the common electrode line 5 is arranged on the upper side of the sub-pixels of the current display row.
  • the first data line 6 is arranged on the side adjacent to the previous display column (in this example, the left display column is the previous display column), and the second data line 7 is arranged adjacent to the next display column (this In the example, the right display column is the next display column), that is, the first data line 6 is set on the left side of the sub-pixels of this display column, between this display column and the left display column, and the second data line 7 is set On the right side of the sub-pixels in the current display column, it is located between the current display column and the right display column.
  • the M display lines include M/2 odd-numbered display lines and M/2 even-numbered display lines.
  • the thin film transistors 3 of the sub-pixels in the M/2 odd-numbered display rows are connected to the first data line 6, and the thin film transistors 3 of the sub-pixels in the M/2 even-numbered display rows are connected to the second data line 7.
  • the second substrate 2 includes M*N filter units 22 arranged in an array, and the positions of the M*N filter units 22 and M*N sub-pixels are in one-to-one correspondence.
  • a black matrix 21 is provided between the filter units 22.
  • FIG. 3 is a top view of a display panel according to an exemplary embodiment of the present disclosure, illustrating the black matrix 21 and the filter unit 22 with 2 display rows and 3 display columns in the display panel.
  • the two display lines are the k-th display line and the k+1-th display line, respectively, the k-th display line and the k+2-th display line are odd-numbered display lines, and the k+1-th display line is even-numbered display lines.
  • each display row of the first substrate 1 includes first sub-pixels, second sub-pixels, and third sub-pixels periodically arranged along the display row direction, and each of the second substrate 2
  • the display line includes a first filter unit, a second filter unit, and a third filter unit periodically arranged along the display row direction.
  • the position of the first filter unit corresponds to the position of the first sub-pixel.
  • the position of the second filter unit corresponds to the position of the second sub-pixel, and the position of the third filter unit corresponds to the position of the third sub-pixel.
  • the filter unit of the second substrate 2 corresponds to the sub-pixels of the first substrate 1 one-to-one, in the subsequent description of the present disclosure, the sub-pixels of the first substrate 1 and the filter unit of the second substrate 2 are uniformly adopted as sub-pixels. To illustrate.
  • a black matrix 21 is located between two adjacent sub-pixels (filter units), and the black matrix 21 includes a shielding row 211 and a shielding row located between the sub-pixels of adjacent display rows.
  • the shielding row 211 is configured to shield the gate line, the common electrode line and the thin film transistor of the first substrate 1, and the shielding column 212 is configured to shield the first substrate 1 A data line and a second data line.
  • the shielding row 211 located between the sub-pixels of the k-th display row and the sub-pixels of the k+1-th display row has a first width and is located in the k+1-th display row.
  • the blocking row 211 between the sub-pixels of the row and the sub-pixels of the k+2th display row has a second width, and the first width is not equal to the second width.
  • the thin film transistors of the sub-pixels in the kth display row and the k+2th display row are connected to the first data line, and the thin film transistors of the sub-pixels in the k+1th display row are connected to the second data line .
  • the shielding line between the kth (odd) display line and the k+1 (even) display line is set to have the first width
  • the k+1 (even) display line is set to have the first width. +2 (odd number)
  • the occlusion line between the display lines has a second width, and the first width is not equal to the second width.
  • the extension direction Y of the data line refers to a direction parallel to the data line.
  • the shielding row 211 between the sub-pixels of the kth display row and the sub-pixels of the k+1th display row includes an upper edge located in the kth display row and a lower edge located in the k+1th display row. edge.
  • the upper edge located in the k-th display row includes a first upper edge 101 located in the first sub-pixel of the k-th display row, a second upper edge 201 located in the second sub-pixel of the k-th display row, and a second upper edge 201 located in the k-th display row.
  • the lower edge located in the k+1 display row includes a first lower edge 102 located in the first sub-pixel of the k+1 display row, and a second lower edge 202 located in the second sub-pixel of the k+1 display row. And the third lower edge 302 located in the third sub-pixel of the k+1 display row.
  • the distance between the first upper edge 101 and the first lower edge 102 is a first distance L1
  • the distance between the second upper edge 201 and the second lower edge 202 is a second distance L2
  • the distance between the third upper edge 301 and the third lower edge 302 is a third distance L3.
  • the blocking row 211 between the sub-pixels of the k+1th display row and the k+2th display row includes an upper edge located in the k+1th display row and an upper edge located in the k+2th display row. Show the bottom edge of the line.
  • the upper edge located in the k+1 display row includes a fourth upper edge 401 located in the first sub-pixel of the k+1 display row, and a fifth upper edge 501 located in the second sub-pixel of the k+1 display row.
  • the lower edge located in the k+2th display row includes a fourth lower edge 402 located in the first sub-pixel of the k+2 display row, and a fifth lower edge 502 located in the second sub-pixel of the k+2 display row. And the sixth lower edge 602 in the third sub-pixel of the k+2 display row.
  • the distance between the fourth upper edge 401 and the fourth lower edge 402 is the fourth distance L4
  • the distance between the fifth upper edge 501 and the fifth lower edge 502 is the fifth distance L5
  • the distance between the sixth upper edge 601 and the sixth lower edge 602 is a sixth distance L6.
  • the first width is not equal to the second width includes any one or more of the following: the first distance L1 is less than the fourth distance L4, the second distance L2 is less than the fifth distance L5, and the third distance L3 is greater than the fourth distance L5.
  • the difference between the first distance L1 and the fourth distance L4 is approximately 10 ⁇ m-20 ⁇ m
  • the difference between the second distance L2 and the fifth distance L5 is approximately 10 ⁇ m-20 ⁇ m
  • the third distance L3 and the sixth distance L6 The difference is about 1 ⁇ m to 5 ⁇ m.
  • the difference between the first distance L1 and the fourth distance L4 is about 13 ⁇ m to 15 ⁇ m
  • the difference between the second distance L2 and the fifth distance L5 is about 13 ⁇ m to 15 ⁇ m
  • the difference of L6 is about 2.5 ⁇ m ⁇ 3.5 ⁇ m.
  • the third distance L3 is greater than the first distance L1
  • the third distance L3 is greater than the second distance L2
  • the first distance L1 is equal to the second distance L2.
  • the difference between the third distance L3 and the first distance L1 is about 10 ⁇ m to 35 ⁇ m, and the difference between the third distance L3 and the second distance L2 is about 10 ⁇ m to 35 ⁇ m.
  • the sixth distance L6 is greater than the fourth distance L4, the sixth distance L6 is greater than the fifth distance L5, and the fourth distance L4 is equal to the fifth distance L5.
  • the difference between the sixth distance L6 and the fourth distance L4 is about 10 ⁇ m-20 ⁇ m
  • the difference between the sixth distance L6 and the fifth distance L5 is about 10 ⁇ m-20 ⁇ m.
  • the shielding row located in the first sub-pixel of the k-th display row is provided with first protrusions 103
  • the shielding row located in the second sub-pixel of the k-th display row is provided with second protrusions 203 .
  • the first protrusion 103 is arranged on the first upper edge 101 and extends in a direction away from the first lower edge 102
  • the second protrusion 203 is arranged on the second upper edge 201 and extends in a direction away from the second lower edge 202.
  • the first bump 103 is located on the side where the thin film transistor is provided in the first sub-pixel
  • the second bump 203 is located on the side where the thin film transistor is provided in the second sub-pixel.
  • the first protrusion 103 is located on the left side of the first sub-pixel, and the second protrusion 203 is located on the left side of the second sub-pixel.
  • the extending direction X of the gate line refers to a direction parallel to the gate line.
  • the shape of the first protrusion 103 and the second protrusion 203 may include a rectangle or a trapezoid.
  • the shape of the first protrusion 103 and the second protrusion 203 is rectangular or trapezoidal, the first protrusion 103 includes the upper edge of the first protrusion, and the second protrusion 203 includes the upper edge of the second protrusion.
  • the distance L7 between the upper edge of the first protrusion and the first upper edge 101 is about 10 ⁇ m-20 ⁇ m, and the distance L8 between the upper edge of the second protrusion and the second upper edge 201 is about It is 10 ⁇ m ⁇ 20 ⁇ m.
  • the distance between the third upper edge 301 and the first upper edge 101 is greater than the distance L7 between the first protrusion upper edge and the first upper edge 101
  • the distance between the third upper edge 301 and the second upper edge 201 is greater than the distance L8 between the second protrusion upper edge and the second upper edge 201.
  • the first lower edge, the second lower edge, and the third lower edge are all straight edges extending along the extension direction of the grid line; the fourth upper edge and the fifth upper edge Both the upper edge and the sixth upper edge are straight edges extending along the extension direction of the gate line; the fourth lower edge, the fifth lower edge and the sixth lower edge are all provided with bumps, and the bumps are respectively provided.
  • the fourth lower edge, the fifth lower edge, and the sixth lower edge are adjacent to the positions of the shielding rows on both sides.
  • the bump includes a right-angled triangle, and the first right-angled side of the right-angled triangle is respectively disposed on the fourth lower edge, the fifth lower edge, and the sixth lower edge.
  • the second right-angled edges are respectively arranged on the shielding rows on both sides of the fourth lower edge, the fifth lower edge and the sixth lower edge.
  • the first substrate includes a first conductive layer, a first metal layer, a first insulating layer, a semiconductor layer, a second metal layer, a second insulating layer, and a second conductive layer that are stacked;
  • the first conductive layer includes a common electrode provided in each sub-pixel;
  • the first metal layer includes a gate line and a common electrode line, a gate electrode provided in each sub-pixel, and a gate electrode provided in the third sub-pixel.
  • the first connection electrode, the gate line is connected to the gate electrode in each sub-pixel, the common electrode line is connected to the common electrode in each sub-pixel, and the first connection electrode is connected to the common electrode of the third sub-pixel Connection;
  • the semiconductor layer includes an active layer provided in each sub-pixel;
  • the second metal layer includes a first data line, a second data line, and a source electrode and a drain electrode provided in each sub-pixel, the kth In the display row, the source electrode of each sub-pixel is connected to the first data line. In the k+1 display row, the source electrode of each sub-pixel is connected to the second data line.
  • a conductive channel is formed between the second conductive layer; the second conductive layer includes a pixel electrode arranged in each sub-pixel and a second connecting electrode arranged in the third sub-pixel, and the pixel electrode is connected to the sub-pixel through a via hole.
  • the drain electrode is connected, and the second connection electrode is respectively connected to the first connection electrode and the common electrode line through the via hole.
  • the common electrodes in the first sub-pixel, the second sub-pixel, and the third sub-pixel are provided with first common electrode bumps, and the first common electrode of each sub-pixel is The protrusion is located on the side of the common electrode adjacent to the k-1th display row; the common electrode in the third sub-pixel is provided with a second common electrode protrusion, and the second common electrode protrusion is located adjacent to the common electrode On one side of the next display line, the first connection electrode is arranged on the second common electrode bump.
  • the common electrode line in a first interval area between adjacent common electrode lines, has a third width, and in a second interval area between adjacent first interval areas, the common electrode The line has a fourth width, the third width is smaller than the fourth width; in the first interval area, the gate line has a fifth width, and in the second interval area, the gate line has a sixth width Width, the fifth width is smaller than the sixth width.
  • the gate electrodes in the first sub-pixel, the second sub-pixel, and the third sub-pixel are all rectangular, and the long side of the gate electrode in the first sub-pixel and the second sub-pixel is along The display row direction extends, and the long side of the gate electrode in the third sub-pixel extends along the display column direction.
  • one end of the second connection electrode is connected to the first connection electrode through a via hole opened in the first insulating layer and the second insulating layer, and the other end of the second connection electrode passes through the The via holes opened on the first insulating layer and the second insulating layer are connected to the common electrode line of the next display row.
  • connection area between the pixel electrode and the drain electrode overlaps the black matrix
  • edge area of the pixel electrode overlaps the black matrix
  • the first sub-pixel is a red sub-pixel (red filter unit)
  • the second sub-pixel is a green sub-pixel (green filter unit)
  • the third sub-pixel is a blue sub-pixel (blue filter unit).
  • the "patterning process” referred to in the present disclosure includes film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping treatments.
  • the deposition can be any one or more of sputtering, evaporation and chemical vapor deposition
  • the coating can be any one or more of spraying and spin coating
  • the etching can be any of dry etching and wet etching.
  • Thin film refers to a layer of film made by depositing or coating a certain material on a substrate. If the "film” does not require a patterning process during the entire production process, the "film” can also be referred to as a "layer".
  • the "thin film” requires a patterning process during the entire production process, it is called a "thin film” before the patterning process and a “layer” after the patterning process.
  • the "layer” after the patterning process contains at least one "pattern”.
  • “A and B are arranged in the same layer” means that A and B are formed at the same time through the same patterning process.
  • “the orthographic projection of A includes the orthographic projection of B” means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A and the orthographic projection of B The projected boundaries overlap completely.
  • the preparation process of the display panel may include two parts, the first part includes substrate preparation, and the second part includes alignment pressing (box alignment).
  • the preparation of the substrate includes the preparation of the first substrate and the preparation of the second substrate, both of which are not required in order and can be carried out at the same time.
  • the first substrate may be an array substrate, and the second substrate may be a color filter substrate. The two parts of the process are described below.
  • the array substrate illustrates the structure of 6 sub-pixels in two display rows and three display columns.
  • the kth display line and the k+2th display line may be odd-numbered lines
  • the k+1th display line may be an even-numbered line.
  • Each display row may include a first sub-pixel, a second sub-pixel, and a third sub-pixel, which correspond to the first filter unit, the second filter unit, and the third filter unit of the color filter substrate, respectively.
  • forming the first conductive layer pattern may include: depositing a first transparent conductive film on a first substrate, patterning the first transparent conductive film through a patterning process, and forming a first conductive film on the first substrate 10.
  • the first conductive layer pattern includes at least a common electrode 9 arranged in each sub-pixel, as shown in FIGS. 4A, 4B, and 4C.
  • FIG. 4B is a cross-sectional view in the AA direction in FIG. Sectional view in BB direction.
  • the common electrode 9 is a plate-shaped electrode, the shape and size of the common electrode 9 of the first sub-pixel and the second sub-pixel are the same, and the common electrode 9 of the third sub-pixel has the same shape and size.
  • the shape and size are different from the first sub-pixel and the second sub-pixel.
  • the shape and size of the common electrode 9 of the first sub-pixel of the k-th display row and the first sub-pixel of the k+1-th display row are different.
  • the shape and size of the common electrode 9 of the second sub-pixel of the display line and the second sub-pixel of the k+1-th display line are different.
  • the shape and size of the common electrode 9 of the two sub-pixels are different.
  • the common electrode 9 in the first sub-pixel, the second sub-pixel, and the third sub-pixel of the k-th display row is provided with a first common electrode protrusion, and the first common electrode of each sub-pixel is located at The common electrode 9 is adjacent to the side of the k-1th display row, and the first common electrode bump of each sub-pixel is configured to be connected to the subsequent common electrode line to realize the mutual connection of the common electrode 9 of each sub-pixel in the display row direction.
  • the common electrode 9 in the third sub-pixel of the k-th display row and the third sub-pixel of the k+1-th display row is provided with a second common electrode bump, and the third sub-pixel of the k-th display row
  • the second common electrode protrusion of the pixel is located on the side of the common electrode 9 adjacent to the k+1th display row
  • the second common electrode protrusion of the third sub-pixel of the k+1th display row is located on the common electrode 9 adjacent to the k+2th display row.
  • the second common electrode bump is configured to display the common electrode 9 in the third sub-pixel of the kth display row and the k+1 th
  • the common electrodes 9 in the third sub-pixels of the row are connected to realize the mutual connection of the common electrodes 9 of the third sub-pixels in the display column direction. Since the common electrodes 9 in the sub-pixels in the display row direction are connected to each other through the common electrode line 5, the third sub-pixels in the display column direction pass through the second common electrode bump, the first connection electrode, the second connection electrode, and the common electrode line. 5 are connected to each other, so that the common electrodes 9 of all sub-pixels are connected to each other, so that the common electrodes 9 of all sub-pixels have the same potential, which improves the display effect of the display panel.
  • a partial area of the orthographic projection of the common electrode line 5 on the substrate 10 overlaps a partial area of the orthographic projection of the common electrode 9 on the substrate 10. That is, a part of the common electrode line 5 is provided on the common electrode 9 and the other part is provided on the substrate 10.
  • all areas of the orthographic projection of the common electrode line 5 on the substrate 10 overlap with a partial area of the orthographic projection of the common electrode 9 on the substrate 10. That is, the common electrode line 5 is provided on the common electrode 9.
  • forming the first metal layer pattern may include: depositing a first metal film on the first substrate formed with the aforementioned pattern, patterning the first metal film through a patterning process, and forming on the first substrate 10.
  • a first metal pattern, the first metal pattern includes at least a gate line 4 and a common electrode line 5 extending in the horizontal direction, a gate electrode 11 provided in each sub-pixel, and a first connection electrode 31 provided in the third sub-pixel, As shown in FIG. 5A, FIG. 5B and FIG. 5C, FIG. 5B is a cross-sectional view in the AA direction in FIG. 5A, and FIG. 5C is a cross-sectional view in the BB direction in FIG. 5A.
  • the gate line 4 of each display row is arranged on the lower side of the current display row, and is spaced a certain distance from the common electrode 9 of each sub-pixel in the current display row, and the common electrode line 5 parallel to the gate line 4 It is arranged on the upper side of the current display row, and is placed on the common electrode 9 of each sub-pixel in the current display row to realize the connection between the common electrode line 5 in the display row direction and the common electrode 9 of each sub-pixel.
  • the gate electrode 11 is an integral structure connected to the gate line 4.
  • the first connection electrode 31 located in the third sub-pixel is arranged on the second common electrode bump of the common electrode 9 in the third sub-pixel to realize the connection between the first connection electrode 31 and the common electrode 9 of the third sub-pixel.
  • the first connecting electrode 31 is arranged on the right side of the gate electrode 11 of the third sub-pixel, and in the k+1-th display row, the first connecting electrode 31 is arranged on the left side of the gate electrode 11 of the third sub-pixel. side.
  • the common electrode lines 5 arranged in the horizontal direction may be arranged with unequal widths.
  • the common electrode line 5 In the first interval area between adjacent common electrode lines 5, the common electrode line 5 has a third width, and in the second interval area between adjacent first interval areas, the common electrode line 5 has a fourth width, and the third The width is smaller than the fourth width.
  • the wider common electrode line 5 In the second separation area, since the common electrode line 5 is connected to the common electrode 9, the wider common electrode line 5 can ensure a reliable connection between the common electrode line 5 and the common electrode 9. Since in the subsequent process, data lines are arranged in the first space between adjacent common electrode lines 5, the narrower common electrode lines 5 can make the common electrode lines 5 and the subsequently formed data lines have a smaller overlap area.
  • the common electrode line 5 is designed to be widened in the overlapping area with the data line, so the parasitic capacitance between the common electrode line 5 and the data line can be reduced, and the electrical performance of the display panel can be improved.
  • the width of the common electrode line refers to the size of the common electrode line in a direction perpendicular to the common electrode line.
  • the gate lines 4 arranged in the horizontal direction may be arranged with unequal widths.
  • the gate line 4 In the first interval area between adjacent common electrode lines 5, the gate line 4 has a fifth width, and in the second interval area between adjacent first interval areas, the gate line 4 has a sixth width, and the fifth width is smaller than the fifth width. Six widths.
  • the wider gate line 4 can increase the area of the gate electrode 11 and improve the electrical performance of the thin film transistor.
  • the narrower gate lines 4 can make the gate lines 4 and the subsequently formed data lines have a smaller overlap area, which is equivalent to
  • the gate line 4 is designed to be widened in the overlapping area with the data line, so that the parasitic capacitance between the gate line 4 and the data line can be reduced, and the electrical performance of the display panel can be improved.
  • the width of the gate line refers to the size of the gate line in a direction perpendicular to the gate line.
  • the gate electrodes 11 in the first sub-pixel, the second sub-pixel, and the third sub-pixel are all rectangular, and the long side of the gate electrode 11 in the first sub-pixel and the second sub-pixel is along the display line.
  • the long side of the gate electrode 11 in the third sub-pixel extends along the display column direction. In the direction perpendicular to the gate line, the distance between the upper edge of the gate electrode 11 and the gate line 4 in the third sub-pixel is greater than the distance between the upper edge of the gate electrode 11 and the gate line 4 in the first and second sub-pixels. distance.
  • the distance between the two edges of the gate electrode 11 in the third sub-pixel is smaller than the distance between the two edges of the gate electrode 11 in the first and second sub-pixels. Since the common electrode 9 in the third sub-pixel is provided with a second common electrode protrusion extending toward the gate line 4, the gate electrode 11 in the third sub-pixel is designed to have a rectangular shape extending toward the common electrode 9 to ensure the third The area of the gate electrode 11 in the sub-pixel.
  • forming the semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor layer film on the first substrate formed with the aforementioned pattern, and patterning the semiconductor layer film through a patterning process to form a covering first metal Layer pattern and the first conductive layer pattern of the first insulating layer 12, and the semiconductor layer pattern disposed on the first insulating layer 12, the semiconductor layer pattern includes at least the active layer 13 disposed in each sub-pixel, each active layer The position of the layer 13 corresponds to the position of the gate electrode 11 in the sub-pixel where it is, as shown in FIGS. 6A, 6B, and 6C.
  • FIG. 6B is a cross-sectional view in the AA direction in FIG. 6A
  • FIG. 6C is a cross-sectional view in the BB direction in FIG. 6A .
  • the shape of the active layer 13 in each sub-pixel may be the same, and the position of the active layer 13 in each sub-pixel in the k-th display row is different from that in each sub-pixel in the k+1-th display row.
  • the thin film transistors in the first sub-pixel, the second sub-pixel, and the third sub-pixel are connected to the first data line located on the left side of the sub-pixel, so the k-th display
  • the active layer 13 in the row is located on the side close to the first data line (left side), which can simplify the structure of the source electrode in the thin film transistor, reduce the parasitic capacitance between the source electrode and the gate electrode, and improve the electrical performance of the thin film transistor .
  • the thin film transistors in the first sub-pixel, the second sub-pixel, and the third sub-pixel are connected to the second data line located on the right side of the sub-pixel, so the k+1 display row
  • the active layer 13 is located on the side (right side) close to the second data line, which can simplify the structure of the source electrode in the thin film transistor, reduce the parasitic capacitance between the source electrode and the gate electrode, and improve the electrical performance of the thin film transistor.
  • forming the first metal layer pattern may include: depositing a second metal film on the first substrate formed with the aforementioned pattern, and patterning the second metal film through a patterning process to form the first insulating layer
  • the second metal pattern on 12 the second metal pattern includes at least a first data line 6 and a second data line 7 extending in a vertical direction, a source electrode 14 and a drain electrode 15 provided in each sub-pixel, as shown in FIG. 7A 7B and 7C
  • FIG. 7B is a cross-sectional view in the AA direction in FIG. 7A
  • FIG. 7C is a cross-sectional view in the BB direction in FIG. 7A.
  • the first data line 6 and the second data line 7 in each display column form a double data line
  • the first data line 6 is arranged on the left side of each display column for displaying to the kth
  • the sub-pixels in rows provide data signals
  • the second data line 7 is arranged on the right side of each display column for providing data signals to the sub-pixels in the k+1th display row (even-numbered rows).
  • the source electrode 14 of each sub-pixel is an integrated structure connected to the first data line 6, and in the k+1-th display row, the source electrode 14 of each sub-pixel is an integrated structure connected to the second data line 7. structure.
  • one end of the source electrode 14 and one end of the drain electrode 15 are respectively disposed on the active layer 13, and a conductive channel is formed between the source electrode 14 and the drain electrode 15.
  • the shape, size, and position of the source electrode 14 and the drain electrode 15 of the first and second subpixels are the same, and the third subpixel is the same as the first and second subpixels.
  • the shape, size, and position of the source electrode 14 and the drain electrode 15 of the two sub-pixels are different.
  • the shape and size of the source electrode 14 and the drain electrode 15 of the first sub-pixel in the k-th display row and the first sub-pixel in the k+1-th display row are the same, and the positions are mirror-symmetrical with respect to the vertical center line.
  • the shape and size of the source electrode 14 and the drain electrode 15 of the second sub-pixel in the k-th display row and the second sub-pixel in the k+1-th display row are the same, and the positions are mirror-symmetrical with respect to the vertical center line.
  • the shape and size of the source electrode 14 and the drain electrode 15 of the third sub-pixel in the k-th display row and the third sub-pixel in the k+1-th display row are the same, and the positions are mirror-symmetrical with respect to the vertical center line.
  • the vertical center line is the center line of the first data line 6 and the second data line 7 in each display column.
  • the patterning of the semiconductor layer and the patterning of the second metal layer can be formed in a single patterning process.
  • Forming a second insulating layer pattern may include: depositing a second insulating film on the first substrate formed with the aforementioned pattern, and patterning the second insulating film through a patterning process to form a pattern covering the second metal
  • the second insulating layer 16 pattern, the second insulating layer 16 pattern includes at least a plurality of via holes, as shown in FIG. 8A, FIG. 8B and FIG. 8C, FIG. 8B is a cross-sectional view of FIG. Sectional view in BB direction.
  • the via hole may include: a first via hole K1 provided at the location of the drain electrode 15 in each sub-pixel, a second via hole provided at the location of the first connection electrode 31 in the third sub-pixel K2 and the third via hole K3 arranged at the position of the common electrode line 5 in the third sub-pixel, the second insulating layer 16 in the first via hole K1 is etched away, exposing the surface of the drain electrode 15, and the second pass
  • the second insulating layer 16 and the first insulating layer 12 in the hole K2 are etched away, exposing the surface of the first connection electrode 31, and the second insulating layer 16 and the first insulating layer 12 in the third via K3 are etched It is etched away, exposing the surface of the common electrode line 5.
  • the position of the third via hole K3 in the third sub-pixel of the k-th display row is different from the position of the third via hole K3 in the third sub-pixel of the k+1-th display row.
  • forming the second conductive layer pattern may include: depositing a second transparent conductive film on the first substrate formed with the aforementioned pattern, and patterning the second transparent conductive film through a patterning process to form the second conductive layer
  • the second conductive layer pattern includes at least a pixel electrode 8 arranged in each sub-pixel and a second connecting electrode 32 arranged in the third sub-pixel, as shown in FIGS. 9A, 9B, and 9C, and FIG. 9B is a diagram 9A is a cross-sectional view in the direction of AA, and FIG. 9C is a cross-sectional view in the direction of BB in FIG. 9A.
  • the pixel electrode 8 in each sub-pixel, is a slit electrode, and is connected to the drain electrode 15 of the sub-pixel where it is located through the first via hole K1.
  • one end of the second connection electrode 32 is connected to the first connection electrode 31 through the second via K2, and the other end is connected to the common electrode line 5 of the next display row through the third via K3 to realize display
  • the common electrodes 9 in each third sub-pixel in the column direction are connected to each other.
  • the shape and size of the pixel electrode 8 of the first sub-pixel and the second sub-pixel are the same, and the shape and size of the pixel electrode 8 of the third sub-pixel are different from those of the first sub-pixel.
  • Pixels and second sub-pixels are different.
  • the shape and size of the pixel electrodes 8 of the two second sub-pixels are different, and the shape and size of the pixel electrodes 8 of the third sub-pixel of the k-th display row and the third sub-pixel of the k+1-th display row are different.
  • the common electrode 9 of each third sub-pixel in the display column direction is connected to each other through the second common electrode bump, the first connection electrode 31, the second connection electrode 32, and the common electrode line 5, the display row
  • the common electrodes 9 in each sub-pixel are connected to each other through the common electrode line 5, so that the common electrodes 9 of all sub-pixels are connected to each other, so that the common electrodes 9 of all sub-pixels have the same potential, which improves the display effect of the display panel.
  • the first substrate may use a glass substrate, a quartz substrate, or a plastic substrate.
  • the first metal film and the second metal film can be made of metal materials and deposited by a magnetron sputtering method (Sputter).
  • the metal materials can include silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum Any one or more of (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be a single-layer structure or a multilayer composite structure, such as Ti/Al /Ti etc.
  • the first insulating film and the second insulating film can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single-layer structure or a multilayer composite
  • the structure is deposited by chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD).
  • the first insulating layer is called a gate insulating (GI) layer
  • the second insulating layer is called a passivation (PVX) layer.
  • the first transparent conductive film and the second transparent conductive film may be indium tin oxide (ITO) or indium zinc oxide (IZO).
  • the semiconductor layer film can use amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polysilicon (p-Si), Materials such as hexathiophene or polythiophene, that is, the embodiments of the present disclosure are applicable to transistors manufactured based on oxide technology, silicon technology, or organic technology.
  • a-IGZO amorphous indium gallium zinc oxide
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polysilicon
  • the gate electrode 11, the active layer 13, the source electrode 14 and the drain electrode 15 in each sub-pixel constitute a thin film transistor
  • the common electrode 9 in each sub-pixel is a plate electrode
  • the pixel voltage 8 is The slit electrode
  • the common electrode 9 is configured to provide a common voltage
  • the pixel electrode 8 is configured to provide a pixel voltage for display
  • the multi-dimensional electric field generated between the slit electrode and the plate electrode drives the liquid crystal to deflect.
  • the common electrodes 9 in the first sub-pixel, the second sub-pixel, and the third sub-pixel are connected to each other through the same common electrode line 5.
  • the common electrode 9 in the k-th display row is connected to the The common electrodes 9 in the k+1 display row are connected to each other through the first connection electrode 31 and the second connection electrode 32.
  • the first conductive layer pattern may include a pixel electrode
  • the second conductive layer pattern may include a common electrode
  • the pixel electrode is a plate electrode
  • the common electrode is a slit electrode.
  • the preparation method of the array substrate may further include processing such as forming a flat layer, an alignment film, and aligning the alignment film.
  • the color filter substrate illustrates the structure of 6 filter units in two display rows and three display columns.
  • the k-th display line may be an odd-numbered line
  • the k+1-th display line may be an even-numbered line.
  • Each display row includes a first filter unit, a second filter unit and a third filter unit, which respectively correspond to the first sub-pixel, the second sub-pixel and the third sub-pixel of the array substrate.
  • the first filter unit may be a red filter unit
  • the second filter unit may be a green filter unit
  • the third filter unit may be a blue filter unit.
  • forming the black matrix pattern may include: coating a black matrix film on the second substrate 20, exposing the black matrix film using a mask, and forming a black matrix 21 pattern on the second substrate 20 after development.
  • FIGS. 10A, 10B and 10C FIG. 10B is a cross-sectional view in the CC direction in FIG. 10A
  • FIG. 10C is a cross-sectional view in the DD direction in FIG. 10A.
  • the black matrix 21 pattern on the color filter substrate includes a shielding row 211 extending in the gate line extension direction X and a shielding column 212 extending in the data line extension direction Y.
  • a plurality of shielding rows 211 and shielding columns 212 are mutually connected. Cross to form a plurality of opening regions, and the plurality of opening regions correspond to the positions of the plurality of pixel electrodes 8 on the array substrate.
  • the position of the shielding row 211 corresponds to the positions of the gate line 4, the common voltage line 5, and the thin film transistor on the array substrate.
  • the shielding row 211 is configured to shield the gate line, the common electrode line and the thin film transistor on the array substrate, and the shielding column 212
  • the position of is corresponding to the position of the first data line and the second data line on the array substrate, and the shielding column 212 is configured to shield the first data line and the second data line on the array substrate.
  • the shielding row 211 between the filter unit located in the kth display row and the filter unit of the k+1 display row has a first width and is located in the k+1 display row.
  • the blocking row 211 between the filter unit of the row and the filter unit of the k+2 display row has a second width, and the first width is not equal to the second width.
  • the vertical direction Y is a direction parallel to the data line.
  • the blocking row 211 between the filter unit located in the kth display row and the filter unit in the k+1 display row includes an upper edge located in the kth display row and an upper edge located in the k+1 display row.
  • the upper edge located in the k-th display row includes a first upper edge 101 located in the first filter unit of the k-th display row, a second upper edge 201 located in the second filter unit of the k-th display row, and a second upper edge 201 located in the second filter unit of the k-th display row.
  • the third upper edge 301 in the third filter unit of the display line includes a first upper edge 101 located in the first filter unit of the k-th display row, a second upper edge 201 located in the second filter unit of the k-th display row, and a second upper edge 201 located in the second filter unit of the k-th display row.
  • the lower edge located in the k+1 display row includes the first lower edge 102 located in the first filter unit of the k+1 display row, and the second filter located in the k+1 display row.
  • the distance between the first upper edge 101 and the first lower edge 102 is the first distance L1
  • the distance between the second upper edge 201 and the second lower edge 202 is the second distance L2
  • the distance between the lower edges 302 is the third distance L3.
  • the blocking row 211 between the filter unit located in the k+1th display row and the filter unit in the k+2th display row includes an upper edge located in the k+1th display row and an upper edge located in the k+1th display row. +2 shows the bottom edge of the line.
  • the upper edge located in the k+1 display row includes the fourth upper edge 401 located in the first filter unit of the k+1 display row, and the fifth upper edge located in the second filter unit of the k+1 display row.
  • the lower edge located in the k+2th display row includes the fourth lower edge 402 located in the first filter unit of the k+2 display row, and the fifth lower edge located in the second filter unit of the k+2 display row.
  • the distance between the fourth upper edge 401 and the fourth lower edge 402 is the fourth distance L4
  • the distance between the fifth upper edge 501 and the fifth lower edge 502 is the fifth distance L5
  • the distance between the lower edges 602 is the sixth distance L6.
  • the first width is not equal to the second width includes any one or more of the following: the first distance L1 is less than the fourth distance L4, the second distance L2 is less than the fifth distance L5, and the third distance L3 is greater than the fourth distance L5.
  • the difference between the first distance L1 and the fourth distance L4 is approximately 10 ⁇ m-20 ⁇ m
  • the difference between the second distance L2 and the fifth distance L5 is approximately 10 ⁇ m-20 ⁇ m
  • the third distance L3 and the sixth distance L6 The difference is about 1 ⁇ m to 5 ⁇ m.
  • the difference between the first distance L1 and the fourth distance L4 is about 13 ⁇ m to 15 ⁇ m
  • the difference between the second distance L2 and the fifth distance L5 is about 13 ⁇ m to 15 ⁇ m
  • the difference of L6 is about 2.5 ⁇ m ⁇ 3.5 ⁇ m.
  • the third distance L3 is greater than the first distance L1
  • the third distance L3 is greater than the second distance L2
  • the first distance L1 is equal to the second distance L2.
  • the difference between the third distance L3 and the first distance L1 is about 10 ⁇ m to 35 ⁇ m, and the difference between the third distance L3 and the second distance L2 is about 10 ⁇ m to 35 ⁇ m.
  • the sixth distance L6 is greater than the fourth distance L4, the sixth distance L6 is greater than the fifth distance L5, and the fourth distance L4 is equal to the fifth distance L5.
  • the difference between the sixth distance L6 and the fourth distance L4 is about 10 ⁇ m-20 ⁇ m
  • the difference between the sixth distance L6 and the fifth distance L5 is about 10 ⁇ m-20 ⁇ m.
  • the shielding row located in the first filter unit of the k-th display row is provided with first protrusions 103
  • the shielding row located in the second filter unit of the k-th display row is provided with second protrusions.
  • the first protrusion 103 is arranged on the first upper edge 101 and extends in a direction away from the first lower edge 102
  • the second protrusion 203 is arranged on the second upper edge 201 and extends in a direction away from the second lower edge 202.
  • the position of the first bump 103 corresponds to the position of the thin film transistor on the array substrate.
  • the horizontal direction X is a direction parallel to the gate line.
  • the shape of the first protrusion 103 and the second protrusion 203 may include a rectangle or a trapezoid.
  • the first protrusion 103 includes a first protrusion upper edge
  • the second protrusion 203 includes a second protrusion upper edge.
  • the first protrusion upper edge and the first upper edge The distance L7 between 101 is about 10 ⁇ m-20 ⁇ m
  • the distance L8 between the upper edge of the second protrusion and the second upper edge 201 is about 10 ⁇ m-20 ⁇ m.
  • the widths of the first protrusion 103 and the second protrusion 203 are 1/3 to 1/2 of the width of the filter unit where they are located.
  • the shielding line located between the first filter unit of the k-th display row and the first filter unit of the k+1-th display row includes a first upper edge 101 provided with a first protrusion 103
  • the first lower edge 102, the first upper edge 101 and the first lower edge 102 extend along the horizontal direction X, which are flat and straight.
  • the shielding line located between the first filter unit on the k+1 display row and the first filter unit on the k+2 display row includes a straight fourth upper edge 401 and a fourth On the lower edge 402, two bumps are respectively arranged at the positions of the fourth lower edge 402 adjacent to the blocking rows on both sides.
  • the bump may be a right-angled triangle, the first right-angled side of the two right-angled triangles are respectively arranged on the fourth lower edge 402, and the second right-angled side of the two right-angled triangles are respectively arranged on the fourth lower edge 402 On the occluded columns on both sides.
  • the blocking line located between the second filter unit of the k-th display row and the second filter unit of the k+1-th display row includes a second upper edge 201 provided with a second protrusion 203
  • the flat second lower edge 202, the second upper edge 201 and the flat second lower edge 202 extend along the horizontal direction X.
  • the shading line located between the second filter unit on the k+1 display row and the second filter unit on the k+2 display row includes a straight fifth upper edge 501 and a fifth On the lower edge 502, two bumps are respectively arranged at positions of the fifth lower edge 502 adjacent to the blocking rows on both sides.
  • the bump may be a right-angled triangle, the first right-angled side of the two right-angled triangles are respectively arranged on the fifth lower edge 502, and the second right-angled side of the two right-angled triangles are respectively arranged on the fifth lower edge 502 On the occluded columns on both sides.
  • the blocking line located between the third filter unit of the k-th display row and the third filter unit of the k+1-th display row includes a flat third upper edge 301 and a flat third The lower edge 302, the third upper edge 301 and the third lower edge 302 extend along the horizontal direction X.
  • the shading line located between the third filter unit on the k+1 display row and the third filter unit on the k+2 display row includes a straight sixth upper edge 601 and a sixth row provided with two bumps. On the lower edge 602, two bumps are arranged at the position of the sixth lower edge 602 adjacent to the blocking rows on both sides.
  • the bump may be a right-angled triangle, the first right-angled side of the two right-angled triangles are respectively arranged on the sixth lower edge 602, and the second right-angled side of the two right-angled triangles are respectively arranged on the sixth lower edge 602 On the occluded columns on both sides.
  • the bump at the fourth lower edge when the bump includes a right-angled triangle, the first right-angled side of the right-angled triangle is set close to the fourth lower edge, and the second right-angled side of the right-angled triangle is set close to the first The position of the shielding column on one side (left or right) of the lower edge.
  • the first right-angled side of the first right-angled triangle is set close to the fourth lower edge
  • the second right-angled side of the first right-angled triangle is set close to the left side of the fourth lower edge ( (Or right) of the shielding column position
  • the first right-angled side of the second right-angled triangle is set close to the fourth lower edge position
  • the second right-angled side of the second right-angled triangle is set close to the right side of the fourth lower edge (or (Left) at the position of the occluded column.
  • the distance between the third upper edge 301 and the first upper edge 101 is greater than the distance L7 between the first protrusion upper edge and the first upper edge 101, and the third upper edge
  • the distance between the edge 301 and the second upper edge 201 is greater than the distance L8 between the second protrusion upper edge and the second upper edge 201.
  • the distance between the upper edge of the first protrusion 103 and the first center line is greater than that of the first upper edge 101 and the first center.
  • the distance between the upper edge of the second protrusion 203 and the first centerline is greater than the distance between the second upper edge 201 and the first centerline, and the distance between the third upper edge 301 and the first centerline is greater than that of the first protrusion.
  • the distance between the upper edge of 103 and the first centerline, and the distance between the third upper edge 301 and the first centerline is greater than the distance between the upper edge of the second protrusion 203 and the first centerline.
  • the distance between the third lower edge 302 and the first centerline is greater than the distance between the first lower edge 102 and the first centerline, and the distance between the third lower edge 302 and the first centerline is greater than the distance between the second lower edge 202 and the first centerline distance.
  • the first center line is a center line extending in the horizontal direction X between the upper edge in the k-th display row and the lower edge in the k+1-th display row.
  • the distance between the upper edge of the first protrusion 103 and the first center line is equal to the distance between the upper edge of the second protrusion 203 and the first center line, and the first upper edge 101 is relative to the first center line.
  • the distance of is equal to the distance between the second upper edge 201 and the first centerline, and the distance between the first lower edge 102 and the first centerline is equal to the distance between the second lower edge 202 and the first centerline.
  • the distance between the sixth upper edge 601 and the second centerline is greater than that of the fourth upper edge 401 and the second centerline.
  • the distance between the sixth upper edge 601 and the second centerline is greater than the distance between the fifth upper edge 501 and the second centerline, and the distance between the sixth lower edge 602 and the second centerline is equal to the distance between the fourth lower edge 402 and the second centerline.
  • the distance from the center line, the distance between the sixth lower edge 602 and the second center line is equal to the distance between the fifth lower edge 502 and the second center line.
  • the second centerline is a centerline extending in the horizontal direction X between the upper edge in the k+1th display row and the lower edge in the k+2th display row.
  • the distance between the fourth upper edge 401 and the second center line is equal to the distance between the fifth upper edge 501 and the second center line.
  • forming the filter unit pattern may include: sequentially forming three filter unit patterns on the second substrate 20 formed with the black matrix 21 pattern, the three filter unit patterns including the red filter unit 23, The green filter unit 24 and the blue filter unit 25, the three filter units are respectively arranged between the black matrix 21, and are arranged periodically according to the set law, as shown in FIG. 11A, FIG. 11B and FIG. 11C, and FIG. 11B It is a cross-sectional view in the direction of CC in FIG. 11A, and FIG. 11C is a cross-sectional view in the direction of DD in FIG. 11A.
  • the box matching process may include: first, turning the color filter substrate over so that the color filter layer on the color filter substrate faces the array substrate. Subsequently, the sealing body is coated on the non-display area of the array substrate, and liquid crystal is dripped on the display area of the array substrate. Under vacuum conditions, the color filter substrate and the array substrate are relatively close to each other for positioning and pressing, and then UV curing and/or Heat curing to cure the frame sealant, complete the box alignment process, and form a display panel, as shown in FIG. 12.
  • the shielding rows of the black matrix achieve shielding of multiple gate lines, multiple common electrode lines, and a plurality of thin film transistors on the first substrate
  • the shielding columns of the black matrix achieve shielding of multiple first substrates on the first substrate.
  • a data line and a plurality of second data lines are shielded, and a plurality of opening regions formed by a plurality of shielding rows and shielding columns intersecting each other exposes a plurality of pixel electrodes on the first substrate.
  • connection area between the pixel electrode and the drain electrode overlaps the black matrix, so that the black matrix can block the first via hole, which can ensure good display quality .
  • the edge area of the pixel electrode overlaps the black matrix, so that the black matrix can block the edge area, which can ensure good display quality.
  • the array substrate can be turned over, the frame sealant can be coated on the array substrate, or can be coated on the color film substrate, the liquid crystal can be dripped on the array substrate, or it can be dripped on the array substrate.
  • the disclosure is not limited here.
  • the array substrate and the color filter substrate may also be prepared in other ways, and other film layers may be formed on the array substrate and the color filter substrate, which is not limited in this disclosure.
  • the electrode shapes of the sub-pixels in the odd rows and the even rows are different, As a result, a difference in pixel aperture ratio occurs.
  • the odd-numbered display rows and the even-numbered display rows are set to different widths to make the pixel aperture ratios of the first sub-pixels in the odd-numbered rows and even-numbered rows be the same.
  • the pixel aperture ratio of the second sub-pixel is the same, and the pixel aperture ratio of the third sub-pixel in odd-numbered rows and even-numbered rows is the same, which reduces the difference between the pixel aperture ratio of odd-numbered display rows and even-numbered display rows, which is effective Avoid bad horizontal stripes and bad light leakage in dark state.
  • the shielding row adjacent to the thin film transistor is widened, effectively avoiding the formation of the array substrate and the color filter substrate.
  • the poor light leakage in the dark state caused by the misalignment improves the product quality.
  • FIG. 13 is an equivalent circuit diagram of another first substrate according to an exemplary embodiment of the present disclosure.
  • the first substrate includes M gate lines 4, M common electrode lines 5, and N pairs of data lines.
  • Each pair of data lines includes a first data line 6 and a second data line 7, which extend in the horizontal direction and
  • the plurality of gate lines 4 and the plurality of common electrode lines 5 arranged in parallel define M display rows, and the plurality of first data lines 6 and the plurality of second data lines 7 arranged in parallel and extending in the vertical direction define N Display columns, therefore M gate lines 4, M common electrode lines 5, N first data lines 6 and N second data lines 7 perpendicularly intersect to define M*N sub-pixels arranged in an array, M and N Is a positive integer greater than or equal to 1.
  • Each sub-pixel includes a thin film transistor 3 and a pixel electrode 8.
  • the source electrode of the thin film transistor 3 is connected to the first data line 6 or the second data line 7, and the drain electrode of the thin film transistor 3 is connected to the pixel electrode 8 of the sub-pixel.
  • the gate line 4 is arranged on the side adjacent to the next display row
  • the common electrode line 5 is arranged on the side adjacent to the previous display row, that is, the gate line 4 is arranged on the lower side of the sub-pixels in the current display row.
  • the common electrode line 5 is arranged on the upper side of the sub-pixels in the current display row.
  • the first data line 6 is arranged on the side adjacent to the previous display column
  • the second data line 7 is arranged on the side adjacent to the next display column, that is, the first data line 6 is arranged on the sub-pixels of the current display column.
  • the left side of is located between the present display column and the left display column
  • the second data line 7 is arranged on the right side of the sub-pixels of the present display column, between the present display column and the right display column.
  • the M display lines include M/2 odd-numbered display lines and M/2 even-numbered display lines.
  • the thin film transistors 3 of the sub-pixels in the M/2 odd-numbered display rows are connected to the second data line 7, and the thin film transistors 3 of the sub-pixels in the M/2 even-numbered display rows are connected to the first data line 6.
  • the second substrate 2 includes M*N filter units arranged in an array, and the positions of the M*N filter units 22 correspond to the positions of the M*N sub-pixels in a one-to-one relationship.
  • a black matrix 21 is provided between the light units 22. Since the thin film transistors of the sub-pixels in the even-numbered display rows are connected to the first data line, and the thin-film transistors of the sub-pixels in the odd-numbered display rows are connected to the second data line, it is possible to set the kth (even) display row and the k+1 (odd number) display row.
  • the shielding line between the display lines has a first width
  • the shielding line between the k+1 (odd) display line and the k+2 (even) display line has a second width
  • the first width is not equal to all Mentioned second width
  • the first width not equal to the second width includes any one or more of the following: the first distance is less than the fourth distance, the second distance is less than the fifth distance, and the third distance is greater than the sixth distance.
  • the first distance is the distance between the first upper edge in the first sub-pixel of the k-th display row and the first lower edge in the first sub-pixel of the k+1-th display row
  • the second distance is the distance between the The distance between the second upper edge in the second sub-pixel of the k display line and the second lower edge in the second sub-pixel of the k+1 display line.
  • the third distance is the third distance in the k-th display line.
  • the distance between the third upper edge in the sub-pixel and the third lower edge in the third sub-pixel in the k+1 display row, and the fourth distance is the distance in the first sub-pixel in the k+1 display row
  • the distance between the fourth upper edge and the fourth lower edge in the first sub-pixel of the k+2 display row, and the fifth distance is the fifth upper edge in the second sub-pixel of the k+1 display row
  • the distance from the fifth lower edge in the second sub-pixel in the k+2 display row, the sixth distance is the sixth upper edge in the third sub-pixel in the k+1 display row and the sixth upper edge in the k+th display row +2
  • the embodiment of the present disclosure also provides a display device including the aforementioned display panel.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

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KR1020227014494A KR102875593B1 (ko) 2020-06-18 2021-05-13 디스플레이 패널 및 디스플레이 장치
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KR20230025651A (ko) 2023-02-22
JP7739277B2 (ja) 2025-09-16
EP4043950B1 (en) 2024-07-31
EP4043950A4 (en) 2022-12-21
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JP2023531573A (ja) 2023-07-25
US20220334430A1 (en) 2022-10-20

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